| PART |
Description |
Maker |
| AD808 AD808-622BR AD808-622BRRL AD808-622BRRL7 AD6 |
622 Mbps, Low Power, Post-Amp/Clock and Data Recovery IC
Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming RECEIVER, PDSO16
Ic = 500 mA; Package: PG-SOT223-4; Polarity: NPN; VCEO (max): 60.0 V; Ptot (max): 2,000.0 mW; hFE (min): 100.0 - 250.0; IC: 1,000.0 mA;
16-Bit, 250ksps, Single Supply ADC; Package: SSOP; No of Pins: 28; Temperature Range: -40°C to 85°C
|
Analog Devices, Inc.
|
| MC100EP16VA MC100EP17 MC100EP29 MC100EP35 MC100EP4 |
3.3V / 5V ECL Differential Receiver/Driver with High Gain
3.3V / 5V ECL Quad Differential Driver/Receiver
3.3V / 5V ECL Dual Differential Data and Clock D Flip?Flop With Set and Reset
3.3V / 5V ECL JK Flip?Flop
3.3V/5V ECL 8?Bit Serial/Parallel Converter
3.3V / 5V ECL Differential Data and Clock D Flip?Flop
3.3V / 5V ECL 4:1 Differential Multiplexer
3.3V / 5V ECL 2:1 Multiplexer
9?Bit TTL to ECL Translator
3.3V / 5V ECL 8?Bit Synchronous Binary Up Counter
3.3V / 5V ECL 2?Input Differential AND/NAND
3.3V / 5V ECL Quad 4?Input OR/NOR
3.3V / 5V ECL Quad 2?Input Differential AND/NAND
3.3 V / 5 V Hex Differential Line Receiver/Driver
3.3V / 5V ECL 1:2 Differential Fanout Buffer
3.3V / 5V ECL 卤2/4, 卤4/5/6 Clock Generation Chip
3.3V / 5V ECL Differential Receiver/Driver with Internal Termination
3.3V ECL Programmable Delay Chip
3.3V / 5V ECL D Flip?Flop with Set and Reset
3.3V / 5V ECL 卤2 Divider
3.3V / 5V ECL 卤4 Divider
3.3 V/5 V 8-Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter
3.3V / 5V ECL 6?Bit Differential Register with Master Reset
3.3V / 5V ECL D Flip?Flop with Reset and Differential Clock
3.3V / 5V ECL Dual Differential 2:1 Multiplexer
3.3V / 5V ECL Coaxial Cable Driver
?3.3V / ?5V Triple ECL Input to LVPECL/PECL Output Translator
3.3V LVTTL/LVCMOS to Differential LVPECL Translator
|
ONSEMI[ON Semiconductor]
|
| NB4L16MMNEVB |
2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver/Receiver/Buffer/ Translator with Internal Termination
|
ON Semiconductor
|
| NB7L216MNR2 NB7L216MNR2G NB7L216MNG NB7L216 NB7L21 |
2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination
|
ONSEMI[ON Semiconductor]
|
| NBSG16M |
2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer(2.5V/3.3V多级输入到CML时钟/数据接收驱动转换缓冲 2.5V/3.3V的多级白血病的输入时钟/数据接收驱动翻译缓冲区（2.5V/3.3V的多级输入到白血病时数据接收驱动转换缓冲器）
|
ON Semiconductor
|
| CY2935011 CY29350AXIT |
2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver Nine Clock outputs: Drive up to 18 clock lines
|
Cypress Semiconductor
|
| SL6649-1 SL6649-KG SL6649-I SL6649-MPEF SL6649-MPE |
200MHz Direct Conversion Downstream Keying (DSK) Data Receiver
200MHz DIRECT CONVERSION FSK DATA RECEIVER 200MHz的直接转换接收FSK数据
|
Zarlink Semiconductor Inc.
Zarlink Semiconductor, Inc.
|
| R2705E |
27.195MHz FSK Radio Data Receiver for Manchester Data Format
|
List of Unclassifed Manufacturers
|
| IDT5T9050PGI IDT5T9050 |
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFERJR 2.5V的单数据传输速率1:5时钟缓冲器TERABUFFER⑩JR
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER⑩ JR
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer Jr.
|
Integrated Device Technology, Inc.
IDT[Integrated Device Technology]
|
| CY2PP3220AI CY2PP3220AIT CY2PP3220 |
Dual 1:10 Differential Clock/Data Fanout Buffer
Dual 1:10 Differential Clock / Data Fanout Buffer 2PP SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
|
CYPRESS[Cypress Semiconductor]
Cypress Semiconductor, Corp.
|
| M14D2561616A-2E |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
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