| PART |
Description |
Maker |
| HYS72D128320 HYS72D128320GBR-6-C HYS72D128320GBR-7 |
184-Pin Registered Double Data Rate SDRAM Module
|
Qimonda AG
|
| HYS72D64320GBR-7-B |
184 - Pin Registered Double Data Rate SDRAM Modules
|
http://
|
| HYS72D64300HU-5-C |
184-Pin Unbuffered Double Data Rate SDRAM
|
Qimonda
|
| HYS64D32301HU-5-C HYS64D32301HU HYS64D32301HU-6-C |
184-Pin Unbuffered Double Data Rate SDRAM
|
Qimonda AG
|
| K4D26323AA-GL |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Data Sheet
|
Samsung Electronic
|
| 3TB41-15 |
TB Series Basic Switch, Double Pole Double Throw Double Break Circuitry, 10 A at 250 Vac, Pin Plunger Actuator, Silver Contacts, Screw Termination
|
Honeywell
|
| EM423M3284LBA-8FE EM424M3284LBA-75FE EM424M3284LBA |
512Mb (4MBank2) Double DATA RATE SDRAM
512Mb (4MBank32) Double DATA RATE SDRAM
512Mb (4M4Bank2) Double DATA RATE SDRAM
|
Electronic Theatre Controls, Inc.
|
| GS8170DD36C-333 GS8170DD36C-250 GS8170DD36C-300 GS |
18Mb x2Lp CMOS I/O Double Data Rate SigmaRAM 512K X 36 STANDARD SRAM, 2.1 ns, PBGA209
18Mb 1x2Lp CMOS I/O Double Data Rate SigmaRAM 35.71x2Lp的CMOS的I / O双数据速率SigmaRAM
|
GSI Technology, Inc.
|
| W631GG6KB-15 W631GG6KB12A W631GG6KB12I W631GG6KB12 |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| M13S2561616A-2S |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M14D5121632A-2K |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
