| PART |
Description |
Maker |
| SY87702LHG |
3.3V 28Mbps-2.5Gbps AnyRate CLOCK AND DATA RECOVERY
|
Micrel Semiconductor,Inc.
|
| SY877021 |
3.3V 28Mbps-2.5Gbps AnyRate Clock and Data Recovery(用于数据传输速率8Mbps.5Gbps的时钟恢复和数据重定时电
|
Micrel Semiconductor,Inc.
|
| MAX3875A MAX3875AEHJ MAX3875AE_D MAX3875AE/D |
"2.5Gbps, Low-Power, 3.3V Clock Recovery and Data Retiming IC"
From old datasheet system
|
Maxim Integrated Products
|
| SY87700V SY87700VHC SY87700VZC |
5V/3.3V 32-175Mbps AnyRate??CLOCK AND DATA RECOVERY
5V/3.3V 32-175Mbps AnyRateCLOCK AND DATA RECOVERY CLOCK RECOVERY CIRCUIT, PDSO28
Isolation Transformer
5V/3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY
5V/3.3V 32-175Mbps AnyRate⑩ CLOCK AND DATA RECOVERY
|
Micrel Semiconductor, Inc.
Micrel Semiconductor,Inc.
MICREL[Micrel Semiconductor]
|
| MAX3831 MAX3831UCB MAX3832UCB |
3.3V / 2.5Gbps / SDH/SONET / 4-Channel Interconnect Mux/Demux ICs with Clock Generator
3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator
|
MAXIM - Dallas Semiconductor
MAXIM[Maxim Integrated Products]
|
| ORLI10G ORLI10G-1BM680C ORLI10G-1BM680I ORLI10G-1B |
Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC
|
Lattice Semiconductor
|
| IDT5T9050PGI IDT5T9050 |
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFERJR 2.5V的单数据传输速率1:5时钟缓冲器TERABUFFER⑩JR
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER⑩ JR
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer Jr.
|
Integrated Device Technology, Inc.
IDT[Integrated Device Technology]
|
| SY87700L SY87700LHITR |
3.3V 32-175Mbps AnyRate??CLOCK AND DATA RECOVERY
3.3V 32-175Mbps AnyRateCLOCK AND DATA RECOVERY
3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY Use lower-power SY87700AL for new designs
|
Micrel Semiconductor,Inc.
MICREL[Micrel Semiconductor]
|
| W9725G6JB25I |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| W9751G6KB-18 W9751G6KB-25 W9751G6KB-3 W9751G6KB25A |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| M13S128324A-2M |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
