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Maxim Integrated Products
Lattice Semiconductor, Corp.
LATTICE SEMICONDUCTOR CORP
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| Part No. |
DS1020S-25 LC4064ZC-5M132C LC4064ZC-75M132C LC4032ZC-75T48E LC4128ZC-42M132C LC4064ZC-75M132I LC4064ZC-5M132I LC4256V-5FT256AI LC4256V-5F256AC LC4256V-3FT256BC LC4128ZC-75M132C LC4256B-75T100C LC4384V-35T176C LC4384V-10T176I LC4032V-75T48C LC4512V-10FT256I LC4512V-35F256C LC4512V-5FT256I LC4512V-75FT256C LC4512V-75T176C LC4032C-5T44C LC4512C-75F256C LC4384C-5FT256I LC4512C-75T176C LC4032B-75T48I LC4128V-75T100I LC4032C-75T48C LC4384V-75FT256I LC4064ZC-75T48I LC4256V-3FT256AC LC4256C-3FT256AC LC4256B-3FT256AC LC4256C-75FT256AC LC4256C-75FT256BC LC4256C-5FT256AC LC4256C-5FT256BC LC4256B-3T100C LC4256V-75T176C LC4128B-75T100C LC4256V-5FT256AC LC4384B-10FT256I LC4384C-10F256I LC4032V-75T44I LC4384B-5FT256I LC4032B-25T44C
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| OCR Text |
...duct terms forms a product term cluster starting with pt0. there is one product term cluster for every macrocell in the glb. figure 3 is a graphical representation of the and array. logic allocator 36 inputs from grp 16 macrocells to orp t... |
| Description |
EE PLD, 5 ns, PBGA132 CSBGA-132
EE PLD, 7.5 ns, PBGA132 CSBGA-132
EE PLD, 7.5 ns, PQFP48 1 MM HEIGHT, TQFP-48
EE PLD, 4.2 ns, PBGA132 CSBGA-132
EE PLD, 5 ns, PBGA256 FTBGA-256
EE PLD, 5 ns, PBGA256 FPBGA-256
EE PLD, 3 ns, PBGA256 FTBGA-256
EE PLD, 7.5 ns, PQFP100 TQFP-100
EE PLD, 3.5 ns, CQFP176 TQFP-176
EE PLD, 10 ns, CQFP176 TQFP-176
EE PLD, 10 ns, PBGA256 FTBGA-256
EE PLD, 3.5 ns, PBGA256 FPBGA-256
EE PLD, 7.5 ns, PBGA256 FTBGA-256
EE PLD, 7.5 ns, CQFP176 TQFP-176
EE PLD, 5 ns, PQFP44 1 MM HEIGHT, TQFP-44
EE PLD, 7.5 ns, PBGA256 FPBGA-256
EE PLD, 3 ns, PQFP100
EE PLD, 7.5 ns, PQFP44
EE PLD, 2.5 ns, PQFP44
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| File Size |
482.50K /
99 Page |
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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY39050Z208-83NTC CY3930V388-83NTC CY39050V484-83NTC CY39050V208-83NTC CY3930V676-83NTC CY3930V484-83NTC CY3930V256-83NTC CY3930Z208-83NTC CY39050V676-83NTC CY39030Z484-83NTC CY39050Z388-83NTC CY39030Z256-83NTC CY39050Z256-83NTC CY39050Z484-83NTC CY39030Z388-83NTC CY3930V484-125MGI CY39030Z484-125MBI CY39030Z484-125MGC CY39050V256-83NTC CY39050V484-125MGC CY3930V484-125MGC CY39030Z484-125MGI CY39050Z676-83NTC CY3930V208-83NTC CY39050V484-125MBC CY39050V388-83NTC CY39030Z676-83NTC CY39050V484-125MBI CY39030Z484-125MBC CY3930V208-83NI CY3930Z208-83NI CY39030Z676-233NTC CY39030Z676-200NTC CY39030Z676-200NTI CY39030Z676-233NTI CY39165Z676-200NTI CY39165Z676-233NTI CY39050V208-200MGI CY39050V208-200MGC CY39050Z208-125MGC CY39050V208-233MGC CY39050V208-233MGI CY39050V208-83MGC CY39050V208-83MGI CY39050V208-233BBC CY39050V208-233BBI CY39050V208-233BGC CY39050V208-233MBI CY39050V388-125BBC CY39050V208-233BGI CY39050V208-233MBC CY39050V208-233NC CY39050V388-125BBI CY39050V388-125BGC CY39050V388-125BGI CY39030Z388-233NI CY39050V388-233NI CY39050V484-233NI CY39030Z484-200MBI CY3930V388-233NI CY39030Z484-200MGI CY39050Z388-233NI CY39050Z676-233NI CY39030Z484-200MGC CY39030Z676-233NI CY39050Z48
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| OCR Text |
...e typical gates [1] macrocells cluster memory (kbits) channel memory (kbits) maximum i/o pins f max2 (mhz) speed-t pd pin-to-pin (ns) standby i cc [2] t a = 25 c 3.3/2.5v 39k30 16k ? 48k 512 64 16 174 233 7.2 5 ma 39k50 23k ? 72... |
| Description |
Evaluation Board for ADXL346 - 3-Axis, ±2 g/±4 g/±8 g/±16 g Ultralow Power Digital Accelerometer
50 MHz to 4.0 GHz RF/IF Gain Block; Package: 3-pin; Temperature Range: -40°C to 125°C
Triple Skew-Compensating Video Delay Line with Analog and Digital Control; Package: 32-LFCSP (5x5mm w/3.5mm exposed pad); Temperature Range: -40°C to 125°C
3-Axis, ±2 g/±4 g/±8 g/±16 g Ultralow Power Digital Accelerometer; Package: 16-LGA; Temperature Range: -40°C to 125°C
CPLDs at FPGA Densities CPLD器件在FPGA的密
CPLDs at FPGA Densities LOADABLE PLD, 8.5 ns, PBGA676
CPLDs at FPGA Densities LOADABLE PLD, 7.2 ns, PQFP208
CPLDs at FPGA Densities LOADABLE PLD, 7.2 ns, PBGA256
CPLDs at FPGA Densities LOADABLE PLD, 10 ns, PBGA388
CPLDs at FPGA Densities LOADABLE PLD, 15 ns, PQFP208
CPLDs at FPGA Densities LOADABLE PLD, 15 ns, PBGA256
CPLDs at FPGA Densities LOADABLE PLD, 15 ns, PBGA484
CPLDs at FPGA Densities LOADABLE PLD, 15 ns, PBGA676
CPLDs at FPGA Densities LOADABLE PLD, 10 ns, PBGA676
CPLDs at FPGA Densities LOADABLE PLD, 10 ns, PBGA256
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| File Size |
1,243.04K /
86 Page |
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it Online |
Download Datasheet |
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