View AN641_9088769.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

application note an overview of the serial digital interface AN641/1293 summary page i revolution or evolution ? ......................................... 1 i.1 the digital island . . . . . . . . . . . ....................................... 2 i.2 serial interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................... 3 ii audio developments ............................................... 3 ii.1 other data. . . . . . . . . ............................. ................... 3 iii a practical serial interface ...................................... 4 iv. the serial interface . . . . . . . . ....................... ................ 4 iv.1 the digital data stream . . . . . . . . . . . . . . . ............................. 4 iv.2 data resolution . . . . . . . . . . ......................................... 4 iv.3 identifying the inserted data . . . . . . . . . . . . . . . . . . . ................... 6 iv.4 data serialisation . ................................................ 6 iv.5 transmission. . . . . . . . . . . . . . . . ....................... ................ 6 v at the destination ................................................. 8 v.1 clock recovery. . . . ............................. ................... 8 v.2 de-serialisation ........... ......................................... 8 v.3 data separation . . . . . . . . . . . . . . . . . . . . . . ............................. 9 vi signal routing ..................................................... 9 appendix 1 : digital concepts . . . . . . . . . . . . ....................................... 10 appendix 2 : serial interface - technical details . . . . . . . ............................. 16 i - revolution or evolution ? revolutions in the technological world are rare, most developments are the result of evolutionary changes rather than instantaneous ones. the im- pact of new technologies in the programme making environment has followed a similar course - valves gave way to semiconductors, discrete logic to mi- crocomputers to name but two, not to mention 405 and 625, monochrome and colour and many, many more. the changing technologies co-existed quite happily, as indeed many still do today, if for no other reason than the fact that, whilst they might change completely what goes on inside a piece of equip- ment, its input and output requirements remained largely unchanged. and then came digits ! whereas the traditional new technology product could be simply 'slotted-in' to the existing environ- ment, generally with an immediate improvement in productivity or performance, and most likely both, digital implementation brought with it the possibility, and indeed probability, of a need to change the world outside as well as that within. some digital developments, of which the d-2 composite digital vtr is a good example, followed the traditional approach of interfacing directly with the existing analogue environment. many others however, even if able to do so, could only be used to their fullest capabilities in an alldigital environment. 1/28
dtoa digital sources (e.g. graphics) analogue sources (e.g. cameras) vision switcher digital effects atod dtoa digital vtr's atod dtoa analogue interconnection digital sources (e.g. graphics) analogue sources (e.g. cameras) vision switcher digital effects digital vtr's digital interconnection atod betacam sp tbc AN641-01.eps figure 1 : comparison of analog and digital interconnection i.1 - the digital island nowhere has the impact of digital technologybeen felt more fully than in the world of video post production. the demand for graphics, animations and related sequencesof ever increasing complex- ity has brought with it rigorous demands of the equipment, of which that most frequentlydiscussed is the need for transparency. a typical animation, such as a programme title sequence, is the result of many video signals superimposed on top of one another, the concept of layering. rarely is it possi- ble to bring all the layers together in one pass, consequently many generations of re-recording are needed to build up the final sequence. four different types of equipment will generally be used : graphics origination (a paint system), a vision switcher, a digital effects device and, of course, several vtr' s. whereas the individual components of the system offer transparent signal processing internally there remains the problem of how they interconnect. analogueinterconnection, whilst a relatively simple process, introduces degradation at every transition from analogue to digital and back again. of course there has not always been much choice, as the digital vision switcher is only now becoming com- monplace. figure 1 shows a comparison between two nominally identical post production suites, one using an analogue switcher and the other digital. notice the number of analogue/digital transitions involved in just one pass through the analogue based system, not to mention the number of a-to-d converters needed were the digital vision switcher to be used with analogue interfacing. of course the example of figure 1 overleaf only takes into account two possibilities of what is, in fact, a four way situation. not only is there the option of digital or analogue, but also composite or component. as many digital effects devices must operate with component signals there may well be additional sources of degradation in the coder/de- coder combinations needed with composite inter- facing. once all the equipment is implemented digitally it might seem foolish not to ensure that all interfacing remains digital as well. on the surface this would appear to be straightforward, surely less demand- ing than returning to analogue. the requirements for interconnectingdigital equipments are bothsim- pler, and yet more difficult, than the equivalent analogue . whilst the problems traditionally asso- ciated with analogue signals, such as frequency response and non-linearity are less of a problem the rangeof frequenciesis generally rather greater, as is the number of interconnections. this latter point arises, of course, because the digital signal is typically a parallel one, having at least 8 bits plus a clock. an overview of the serial digital interface 2/28
with many post-production suites operating with component signals (a digital effects device must process the signal in component or primary form) three digital signals are involved. even if some form of multiplexing is introduced to combine all on to one link, as with ccir 656, there are still eight interconnections, as well as clocking information. interconnectionis no longer simple, the single coax with its associated bnc or musa connectors is replaced by a multicore cable and multiway data connector. the implementation of even a simple patch panel is a task not undertaken lightly, and limits are imposed on the separation of equipment, owing to such problems as degradation of the data streams, and bit-slipping, caused by propagation differences between the different data bits such that all the bits of a data word do not arrive at the destination together. as a result of these difficulties the use of digital equipment in an all-digital environment has gener- ally remained in small, largely self contained units, and gave rise to the concept of a digital island in an otherwise analogue world. increasingly however the programme maker sought ways of intercon- necting the islands and, importantly, ways in which he could take advantage of the existing infra-struc- ture represented by conventional cable routes. the only answer was serial data transmission, but how could this be achieved with a transmission require- ment well in excess of 200 mbits/second? i.2 - serial interfacing the idea of a serial interface for digital equipment has been with us for many years. for a long time however the only possible solution appeared to involve the use of fibre optic links. whilst advanta- geous in many respects such a solution was hardly likely to appeal to the programme maker with a considerable investment in conventional distribu- tion systems, not to mention the problems involved in developing an optical routing crosspoint. even- tually a more conventional solution emerged in the form of ccir-656, the serial implementation of ccir-601. not serial in the true sense of the word, in that the 8 bits were carried on separate conduc- tors, but the y, c r and c b components were inter- leaved. other problems arose when some of the funda- mental concepts of serial data transmission were contemplated. ideally such signals should be 'self- clocking', that is no external reference to identify the timing of the data bits is needed. the range and occurrence of the serial data patterns has to be carefully controlled in order to optimize the fre- quency distribution of the serial signal, and mini- mise any dc component. many conventional tech- niques used are difficult, if not impossible, to imple- ment using existing technology at the data rates involved. ii - audio developments one other development which greatly affects the question of signal routing is that of digital audio. the growth of digital audio applications is well charted, spurred on not only by the capabilities of the technologyavailable but also, as always, by the ever increasingdemands of the programme maker. in much the same way as with video, many of the demands are associated with post production work. multi-track dubbing, track bouncing and audio sweetening all call for the highest possible quality, something which was often severely re- stricted with the limited signal-to-noise ratio and dynamic range of the analogue vtr. post-produc- tion invariably meant transferring to dedicated audio machines for that part of the work. the digital vtr has removed many of these diffi- culties, with a typical complement of four tracks of cd quality audio many users need look no further. however to take full advantage of such machines a digital mixing console is needed. such consoles are becoming available, but once more the ques- tion is raised - how are the vtr's to be routed to the console? of course much work has already been done in this area, with the developmentin particular of the aes/ ebu interface. as well as offering all the usual advantagesof digital transmission it eliminates one of those problems that has long plagued the pro- gramme maker - channel phasing. because left and right signals share the same transmission path differential propagation delays, with their associ- ated problems of image shifting and compatibility, are avoided. there would be considerable benefits to be gained were any serial interface able to support the audio data as well as just the video, may be a form of digital osound in syncso. ii.1 - other data video and audio signals are not quite all the infor- mation involved, one other signal is generally re- quired as well - timecode. a post-production suite without timecode is virtually unthinkable, the infor- mation it provides is as important as the basic video synchronizing signal itself. it would be a pity if an interface that provided simultaneous connection of audio and video was unable to handle the timecode as well. an overview of the serial digital interface 3/28
iii - a practical serial interface a practical solution to the problems of serial inter- facing is now available. developed by sony, and based on a number of specially designed lgi chips the interface deals with all the points raised in the preceding paragraphs. the interface combines digital video - component or composite, 525 or 625, ntsc or pal - with four channels of aes/ebu audio together with vertical interval timecode in the video, as well as the possibility of user data as well. in spite of a bit rate of 270 mbits/second for 625 line component working the interface offers separation distances in excess of 300 m using standard studio co-ax and connectors such as bnc's and musa's. unlike many other systems the bit rate is not in- creased over that represented by the digital video signal itself, however for reasons that will emerge later the interface offers a video signal resolution of 10 bits, rather than the 8 to which most systems are currently restricted. the next section offers an overview of the interface in very general terms, however those needing a more detailed description, or perhaps a gentle reminder of some of the terms and concepts asso- ciated with it, are directed to the appendices which follow. iv - the serial interface as shown in figure 2 the serial interface comprises four main components. at the source digital video and auxiliary data - which includes the aes/ebu audio - are combined, after which data serialisation takes place. these functions are matched at the destination by their complements - de-serialisation and data separation. each of the four functions is implemented in a dedicated vlsi chip. in order to see just how the interface is imple- mented two distinct aspects must be considered - the hardware involved and the nature of the digital signal. the latter aspect is considered first. iv.1 - the digital data stream as may be seen from figure 2 the first task of the interface is to combine the various data streams: video and auxiliary data. the process of combining is dictated by the video information, the other data being 'slotted into' gaps in the video signal. but just where are those gaps? if we take a look at figure 3 we can see that a digital component (ccir-60 1 ) signal appears to have quite a large amount of unused data capacity. in fact between the end of active video (eav) and start of active video (sav) words some 280 unused words exist (268 - 525/60), with rather more during the vertical blanking interval. the d-2 composite signal represents a very differ- ent state of affairs. in order to retain an accurate picture of the sc/h relationship the sync reference edges are encoded together with the burst. this means that for a 625 line pal signal only some 70 samples, during the sync bottom interval, are avail- able. for 525 line ntsc the figure is even lower (about 60), this is because the sample rate (4 x fsc) is rather lower (14.3mhz as opposed to 17.7mhz) and the sample period correspondingly longer. iv.2 - data resolution in recent years much discussion has taken place on the subject of the resolution required of a digital video signal. whilst 8 bits may well be satisfactory for display purposes there are advantages to be gained through the use of a greater number of bits at intermediate stages. one reason stems from the processing of the digital signal, in a switcher or linear keyer for example. typically the signal will be multiplied by a constant, for fading, or a second signal for keying purposes. when two 8 bit values are multiplied the result is one of 16 bits, just as two, two digit, decimal numbers yield a four digit product (99 x 99 = 9801) the video effect desired can be described by the 8 most significant bits - but what should be done about the least significant data? simply discarding it is likely to result in noticeable errors, however even data rounding to the nearest 8 bit value can also result in imperfections, particu- larly if several functions are cascaded. by increas- ing the data resolution such imperfections have a lesser significance, consequently preserving a greater number of bits at least through the signal processing stages offers considerable benefits. this would allow future digital effects devices, for example, to pass an anti-aliassed key to the switcher without any of the artifacts associated with 8-bit rounding.only after processing in the switcher might the 8-bit value be re-established. there is, of course, a second key point to consider. with the ccir-601 signal some 220 quantizing levels are available to the luminance signal, as shown in figure 5 overleaf. this contrasts strongly with the situation for d-2composite signals. be- cause the range of quantizing levels has to encom- pass not only the chrominance component but the sync pulse as well the number of luminance levels is considerably reduced at 147. there is thus a much greater susceptibility to contouring effects, something that could be largely avoided if a greater number of bits were to be used. an overview of the serial digital interface 4/28
receiver co-processor serial decoder line driver serial encoder transmitter co-processor data outputs video data auxiliary data AN641-02.eps figure 2 : overview of the serial interface - 70 samples (pal) - 60 samples (ntsc) digital blanking : 187 samples (pal) 142 samples (ntsc) (b) (a) digital active line (1440 words) 4 words (eav) 4 words (sav) AN641-03.eps figure 3 : horizontal timing relationships for : (a) component and (b) composite digital video signals an overview of the serial digital interface 5/28
iv.3 - identifying the inserted data figure 3 showed those periods which might be used for inserting non-video data. the next step is to see how these periods are flagged, so that a receiving device can extract this information cor- rectly. the process of data identification is shown in figure 4, where it will be seen that a number of different data words are used. the primary data identifier is the trs - timing reference signal - a sequence of 3 consecutive data words with the specific values of 3ff, 000, 000 (values are in hex with a word size of 10 bits). these data values should not occur during normal video data, figure 5 shows the range of data values for both component and composite signals. in fact four data values are reserved : 000, 001, 002 and 003. these allow the interface to be used with either 10 bit video inputs, or 8 bit values with 'dummy' lsb's. after the trs comes a single data word - the line id. this provides timing information - two, four or eight field sequence information, together with in- formation about the location of the current line within the field. the next word is the auxiliary data flag, which indicates the presence of non-video data, it is followed in its turn by the data id, another single word used to indicate the type of data - aes/ebu formatted audio data for example. the remaining data words comprise the data itself, formatted in blocks having a maximum length of 255 words, together with a checksum for validity checking. a full description of the block format, and the way in which aes/ebu data is processed, is given in appendix 2. iv.4 - data serialisation the output of the combiner is a 10 bit parallel signal comprising video data with embedded ancillary information. this signal is converted to serial form for transmission, two processes being involved. as explained in appendix 2 there are many different ways of serializing a data signal. that chosen is usually the one that best matches the resulting signal to the characteristics of the transmission path. there is also the requirement that any clock information needed to decode the signal can be extracted from the signal itself. the ideal signal in this case is one in which the energy content is well distributed across the fre- quency spectrum represented by the data rate, which in this case has a maximum value of 270mhz (13.5mhz y sample rate + 6.75mhz c r + 6.75mhz c b x 10 bits) for ccir-601 signals. furthermore to avoid signal distortions, particularly those which might affect the shape of the data bits, the signal should be dc free with little energy at the lower frequencies. dc free conditions are achieved if the signal has an equal number of 0's and 1's, whilst the low frequency content is minimized if long 'runs' of all 1's or all 0's is avoided. in fact there is a maximum length of all 0's in this case because an all zero parallel word is reserved for trs use only. in order to break up long sequences of 1's and to better distribute the energy spectrum the data sig- nal is randomized, or 'scrambled', following which logic 1's are converted to transitions (+ve to -ve and vice versa). this results in a signal with a large number of transitions, a feature essential to clock recovery. it should be apparent that a clock signal is needed to allow the receiver to determine whether a transition, and hence a logic 1, has been received. figure 6 shows the process of serialisa- tion in graphical form, a fuller description will be found in appendix 2. iv.5 - transmission whilst the signal produced by the serialiser ic can be used for direct transmission over short transmis- sion lines, within equipment for example, co-ax cable will generally be used. for these applications another ic is available offering cable driver and distribution amplifier functions. timing reference signal line id aux data flag data id data block no. data count check sum user data 255 words maximum AN641-04.eps figure 4 : identifiyng the inserted data an overview of the serial digital interface 6/28
147 levels 224 levels 220 levels white level blanking level peak positive level peak negative level chroma peak white level blanking level sync level not digitised luminance colour difference composite 40 hex 01 hex d3 ff hex hex 10 hex 80 hex f0 hex hex 10 hex eb 10-bit interface levels 8-bit signal values 3ac hex 040 hex 3c0 hex 200 hex 040 hex 3fc 34c hex hex 100 004 hex hex AN641-05.eps figure 5 : range of data values for digital video signals an overview of the serial digital interface 7/28
logic 1 encode as transition data scrambling 1001010111 1001 1 1 101 0 1001 1 1 101 0 serial data output serial data input data values are for example only AN641-06.eps figure 6 : data serialisation serial data serial clock reclocked data delay edge pulse generator phase detector vco data recovery AN641-07.eps figure 7 : obtaining the clock information v - at the destination not surprisingly the processes involved at the des- tination are largely the reverse of those undergone at the source, namely de-serialisation and data separation. before any action can take place how- ever it is essential that a clock signal is derived, in order that the individual data bits can be identified, and the best possible data signal obtained. the de-serialiser chip has a built in cable equalizer, offering adjustment free equalization for cable runs up to at least 300m. for longer runs the de-serial- iser can be used as a signal regenerator, the data signal is detected and re-clocked, but with no change in the serial pattern. v.1 - clock recovery as explained in section 4.5 on data serialisation one of the requirements was to ensure sufficient data transitions to permit the clock information to be recovered. this is largely achieved through the encoding of low tic 1's as transitions. a voltage controlled oscillator (vco) is synchronized to the data transitions and thus the clock information can be extracted. figure 7 shows this. one of the features of the serial interface that has already been described is its ability to operate with both ccir-601 and d-2 format signals, 525 ntsc and 625 pal. this is a demanding requirement for the vco, which hasto operate over a 2:1 frequency range, from the 143mhz clock for ntsc composite to the 270mhz needed for ccir-601 signals. v.2 - de-serialisation de-serialisation sounds a simple enough process, each sequence of 10 bits is clocked into a shift register, whereupon the resulting parallel word can be clocked out at one tenth the rate. however there remains the small problem of identifying just which sequence of 10 bits constitutes a complete word, not five from one word and five from the next. also, of course, the data signal was scrambled at the source. the first step in the de-serialisation process therefore is to unscramble the data signal. this is achieved through the use of an identical logic ar- rangement to that used by the scrambler, again appendix 2 has more details. identificationof the data words is achieved through the use of the trs information which, we may recall, is a unique data pattern which cannot occur during normal data. the trs occupies 3 consecu- tive words, 30 bits in all. the de-serialiser therefore employs a 30 stage shift register in order to store three consecutivewords of data, or at least a period equal to three words. the shift register outputs are compared with the data pattern corresponding to the trs, as soon as a match is detected a synchronization signal is produced, which in turn controls the timing of the output, parallel, clock. an overview of the serial digital interface 8/28
v.3 - data separation the remainder of the destination process is con- cern with extracting the auxiliary data from the combined data stream, and restoring the video component to its correct blanking or sync bottom values. the process of data separation is fully explained in appendix 2, however it is perhaps worth mention- ing the fact that a number of different outputs are provided, including auxiliary data presence and error information. the error information is quite comprehensive, and reports the result of parity checks performed on the various timing signals and id's, as well as the data itself and its checksum. video timing information, derived from the line id, is also provided. vi - signal routing whilst this article is mainly concerned with the characteristics of the serial signal itself and its hardware it would be incomplete without a mention of the requirements of signal routing. as explained earlier the serial signal can be distributed using conventional co-ax cable over distances of at least 300 m without additional equalization. this means that existing analogue circuits can be used for the serial digital signal. the data rate, up to 270 mbits/ second, is rather higher than that which conven- tional routing systems, or indeed technologies, are likely to handle. here again the power of large scale integration is revealed. in addition to developing chips to imple- ment the interface sony has also developed a crosspoint chip in order to facilitate the construction of the digital routing system. a single crosspoint chip offers a 16 source x 16 destination matrix - 256 crosspoints in all. four such chips arranged on a single printed board make up a 32 x 32 router, whilst an arrangement of four cards yields 64 x 64 and so on up to a possible 256 x 256. figure 8 shows a typical arrangement. by associating other matrices a total routing sys- tem, including separate audio, tally and control signals, can be assembled. as the serial crosspoint can handle the full bandwidth of the data signal ccir-601 and d-2 signals can be mixed in any combination. the router control logic must know however which sources are composite and which component, and similarly for the destinations, as it would be inappropriate to route a ccir-601 source to a d-2 destination, although a number of data converters, which essentially offer coding or decod- ing in the all digital environment, are under devel- opment. cross- point matrix cross- point matrix cross- point matrix cross- point matrix cross- point matrix 32 inputs 32 outputs 16 inputs 16 outputs AN641-08.eps figure 8 : rounting matrix configurations an overview of the serial digital interface 9/28
analogue signal voltage samples AN641-09.eps figure 9 : sampling of an analogue signal quatized samples quatising levels AN641-10.eps figure 10 : the effect of quantising appendix 1 : digital interconnection concepts this appendix offers a reminder of the basic concepts associated with the processing of signals in digital form, together with a number of those associated with serial data transmission 1 - obtaining the digital signal 1.1 - sampling sampling is the first step in any digital process. the continuouslyvarying analogue signal is sampled at discrete time intervals, as shown in figure 9 the result is a sequence of voltage samples which, if occurring sufficiently rapidly, allow the analogue signal to be reconstructed. the rules which govern the sampling process are very well known, and generally require the sam- pling frequency to be at least twice the highest analogue frequency (the so-called nyquist limit), and in practice a little above this, owing to the limitations of the pass filter needed to recover the original analogue component from the sampled version. 1.2 - quantising the sampling process converts the timescale from one of infinite resolution to a series of discrete intervals. although constrained to particular time periods the analogue samples are not restricted in terms of amplitude resolution. this is the task of quantization. closely associated with the concept of signal coding quantizationdoes for the amplitude domain what sampling did for time. the signal is only permitted to exist at certain fixed levels as shown in figure 10. the number of !evels is, of course, determined by the resolution required, and in turn depends on the way in which the recovered pictures or sound are perceived by the viewer or listener. put simply the change in brightness or sound intensity repre- sented by a single step should not be discernible. in practice around 250 levels are used for video, with several thousand for audio. there are many issues which govern the number of quantizing levels required, not merely the fact that the eye, or ear, may not be able to distinguish the change between one step and the next. if the steps are too coarse, i.e. too few levels, visible or audible defects will be noticed. in video the defect shows up as 'contouring' of the picture, whereas with audio signals the effect takes the form of quantizing noise, a granular type of noise which is only noticeable in the presence of a signal. increasing the number of levels increases the reso- lution and decreases the undesirable effects of contouring and quantizing noise. particularly for audio a greater number of bits also increases the maximum dynamic range. in fact increasing the number of levels is not the only way in which quantizing effects can be reduced, other tech- niques can be used, of which the two most popular are nonlinear encoding and the use of dither. when non-linear encoding isused the total number of levels is unchanged, instead the distribution of levels is altered. more levels are assigned to small amplitude signals with fewer for the large signal peaks. the technique reduces the subjective effect of the noise for the low level signal, however the dynamic range is restricted. non-linear encoding is illustrated in figure 11 overleaf. an overview of the serial digital interface 10/28
quantising levels (a) (b) AN641-11eps figure 11 : comparison of : (a) linear and (b) non-linear quantising dither signal quantising levels AN641-12.eps figure 12 : using a dither component 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 10110 10101 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00100 decimal binary coded sample values AN641-13.eps figure 13 : sample coding a different approach is through the use of a 'dither' component. this is a low-level, typically white noise of 1 quantizinglevel peak-to-peakamplitude, which is added to the analogue signal prior to sampling. the dither component ensures that even the small- est signal must cross at least one sample level - adjacent sample periods will typically correspond to adjacent sample levels. the filtering action of the decoding process will smooth out the effect of the dither and provide a more accurate picture of the original signal. figure 12 shows the concept of dither. one interesting point to note is that much of the contouring that would normally be seen on a com- posite digital signal, which has only some 157 quantizing levels between black and white, is masked by the effective dithering action of the chrominance component. 1.3 - coding coding is the final stage in the digitizing process. the result of sampling and quantizing is still a series of voltage levels, albeit constrained to dis- crete amplitude levels and time intervals. coding represents each voltage level as a number, gener- ally expressed in binary form, as shown in fig- ure 13. once binary representation is considered the link between coding and quantizing is obvious. the 8-bit coding typically used for video describes 256 brightness levels. audio uses as many as 16 to 20 bits, the latter corresponding to over 1 million discrete levels. 2 - parallel signals we now have a parallel digital signal, that is one in which all the bits describing the value of a sample are present simultaneouslyand is the form in which many digital equipments process the signal. when it is desired to connect one unit to another parallel interfacing may be less than satisfactory, particu- larly in terms of the inconvenience of having to separately interconnect each bit. another problem when connecting one digital unit to another is the need to provide clock information. the signal is in the form of a sequence of samples, each represented by, say, an 8-bit number. at the destinationthe decoder must be able to identify the separate sample periods in order to recreate the analogue samples from their binary repre- sentations. parallel interfacing generally includes an additional connection in the form of a clock signal. the clock signal is derived from the master oscillator used to control the sampling and coding process. parallel interfacing therefore involves multiple in- terconnections. for relatively short distances this might be the most practical arrangement, however for longerdistances and particularly if signal routing is contemplated, serial transmission is really the only practical solution. even if all other points are an overview of the serial digital interface 11/28
set aside the need for relatively complex cabling and connectors makes parallel interconnection rather impracticable. 3 - serial transmission at first glance serial transmission is nothing more than sending the signal 'a bit at a time'. only one link is required, however the data rate is increased by a factor at least equal to the number of bits. for example an 8-bit system is sampled at 1mhz, i.e. one sample every 1 m s. when transmitted serially all 8 bits have to be accommodated in the sample period. thus the data rate increases to 8 mbits/s. not only has the bit rate increased but there is the problem of synchronization. the decoder must be able to identify not just each bit as it arrives but also which bit is which. the correct sequence of 8 bits must be reassembled, not some from one sample period and the rest from the next. this requirement can generally be achieved through the inclusion of particular bit patterns which are not allowed during normal data. logic associ- ated with the decoder 'watches out' for the synchro- nizing bit pattern - often called the sync word - and is thus able to identify correctly the transmitted sequence. successful identification of the sync word enables the decoder to identify only the start of a particular data sequence. correct decoding of the data which follows depends on the ability of the decoder to keep track of the bits as they are transmitted. once again clock information is necessary, however as one of the reasons for adopting a serial transmis- sion standard was to minimise the number of con- nections a separate clock connection should be avoided. if clock information cannot be provided separately it must feature as an integral part of the signal, that is it should be 'self clocking'. a self clocking signal is one which guarantees to provide a number of transitions in a given period, a voltage controlled oscillator - vco - in the decoder can lock to the transition information and thus regenerate the missing clock. the production of a self clocking data signal is one of the functions associated with the concept of channel coding, and is discussed in the next sec- tion. 4 - channel coding channel coding basically describes the way in which the 1's and 0's of the data stream are repre- sented on the transmission path. many different channel coding standards exist, all are geared to optimize some aspect of the serial signal : dc content, spectral distribution and clock recovery are generally the key factors. 4.1 - nrz the simplest channel code is the one known as nrz, or non return to zero. simple, combinational logic, signals are a good example of nrz, where a logic 1 is coded as one dc level and logic 0 as another. figure 14 shows an example of an nrz signal. figure 14 also identifies the periods associ- ated with each bit, known as bit cells their duration corresponds to the period of the transmission clock. nrz is a simple code and is used within equipment. for serial transmission it has a number of draw- backs however, these are : (a) it is not self clocking, a long string of all l's or all 0's has no transitions (b) its dc content varies with the nature of the data stream the low frequency content tends to dominate. for these reasons nrz is rarely used for serial transmission, except for relatively low speed opera- tions such as those associated with modem trans- fers. bit cell data clock 10 10 101 0 100 10 AN641-14.eps figure 14 : nrz code 4.2 - nrzi nrzi is a derivative of nrz, non return to zero inverse. nrzi codes logic 0's as a dc level, logic 1's however are coded as a transition. figure 15 shows the data signal of figure 13 encoded as nrzi, together with a typical method for producing it. this data signal is now self clocking, at least so long as a practical limit is placed on the maximum number of zeros. this will generally be achieved by reserving the parallel all-zero word for sync pur- poses only. nrzi still has a relatively dominant lf content and is not dc free. an overview of the serial digital interface 12/28
nrzi nrz data data clock 1011000100101 AN641-15.eps figure 15 : nrzi code 4.3 - bi-phase mark bi-phase mark, or manchester code, is a code well known to many broadcast equipment users as it is the form of channel coding associated with time- code. with this code all bits are identified by a transition at the cell boundary, however logic 1's have an additional transition at the mid cell point. figure 16 shows this. because there is a transition for every bit the clock information can be recovered directly from the bitstream without the need for a vco. this means that the signal can be decoded over a wide range of transmission rates, a situation similar to that of timecode recovery when machines are shuttling at high speed. also because it is fundamentally the time between transitions which indicates a one or a zero the signal can be recovered irrespective of waveform polarity. 4.4 - miller coding miller coding, or modified frequency modulation (mfm), like bi-phase mark, provides a transition for every bit. in this code a one is encoded as a transition occurring at the centre of the bit cell, whilst consecutive zeros have a transition at the cell boundary between them (this means that a pattern such as 10101 has no transitions at the cell boundaries). figure 16 shows an example of miller coding, together with a derivative, miller squared coding. miller coding is self clocking and has a relatively low l.f. content. it is not dc free however, and this can cause problems particularly with recording, and long cable runs. miller squared coding (so called because it was the result of a modification of miller coding by a second, quite separate miller!) has one additional rule. this states that the final transition of an even number of ones occurring between two zeros is omitted i.e. 01110 occupies five cells and has three transitions 011110 occupies six cells but also has three transi- tions. as shown in figure 16 this makes the code dc free. the d-2 composite digital video-tape recorder uses miller squared coding as the form in which the signal is recorded on the tape. amongs other bene- fits the fact that no erase head is required permits such techniques as read before write, where a signal can be taken off tape, combined with exter- nal information, and re-recorded over the original. 1011000100101 original inverted version 1011000100101 miller coding miller coding 2 6 cells 'hi' 7 cells 'lo' - d.c. content 6.5 cells 'hi' 6.5 cells 'lo' - d.c. free (a) bi-phase mark coding (b) miller and miller coding 2 AN641-16.eps figure 16 an overview of the serial digital interface 13/28
look-up table e.g. rom 8-bit data input 9-bit data output AN641-17.eps figure 17 : example of 8/9 code implementation 4.5 - bit mapping this represents a very different approach in which an input parallel word is encoded as one having more bits. a typical code for video might be an 8/9 code where each 8-bit video word is represented by one of 9 bits, a word size which has twice the number of states as one of 9 bits. the coding process therefore maps each of the combinations of the 8-bit word to one of 9 bits. through an appropriate choice of mapping - which 9 bit codes are used and which ignored for example - the channel code desired can be achieved. coding is typically achieved through the use of look-up ta- bles, such as that of figure 17. whilst a considerable flexibility exists the data rate is increased over the minimum necessary and often results in a frequency spectrum with pro- nounced peaks. the l.f. content is generally re- duced however. whilst a data serialiser has been implemented using an 8/9 coding technique it has not proved possible to develop it in single chip form. also the data rate is already increased over that of the basic signal, which makes it difficult to contemplateeither an increase in data resolution, for improved per- formance, or the inclusion of non-video information such as audio. 4.6 - scrambled codes an alternative to the codes described above is the concept of the scrambled, or randomized, code. when scrambled the sequence of the data bits is changed, according to either a pre-determined se- quence or one having a pseudo-random nature. scrambling is of little value with streams of already random data, however it can be used to advantage with data that exhibits a high degree of correlation, such as that associated with video waveforms. in such cases scrambling can produce a better spec- tral distribution than many of the other codes. as the scrambled code aims to provide an equal num- ber of 1's and 0's clock recovery is relatively straightforward. scrambling can be on a word basis, where the parallel data is scrambled before serializing, or on a bit-by-bit basis in its serial form. the ccir-601 recorder uses code scrambling, according to a set of predetermined look-up tables, whilst the serial digital interface described next uses a pseudo-ran- dom sequence. bit scrambling systems are based on the produc- tion of a pseudo-random binary sequence (prbs), which in turn is combined with the trans- mitted data. such a sequencecan be generated by means of a shift register with associated feedback, as shown in figure 18 generally such diagrams show the feedback signals as being combined by an adder. in fact modulo-2 addition is used, where : 0+0=0, 1 + 0 = 1, and 1+1=0. this will be instantly recognized as an exclusive-or function. such a generator produces what is known as a maximum length shift register sequence, or more simply an m-sequence. a shift register having n stages has 2 n states, however as the all zero condition effectively 'locks-up' the sequence the number of valid states is 2 n-1 . the sequence gen- erator of figure 18 therefore has 15 differentstates, as shown in figure 19a. notice how the sequence contains eight l's and seven 0's, in other words there is a more or less equal probability of the generator producing a 0 or a 1. as the length of the register increases so does the probabilityfactor tendto one half. also of course the sequence becomes longer, an 8 stage gener- ator would have 255 states, 9 stages 511 and so on. as was explained earlier the prbs is combined with the transmitted data in order to randomize it. figure 19b shows such an arrangement. because the same random sequence is added to the signal for transmission, and then subtracted at the decoder, the recovered data is identical with the original. in practice of course the use of a separate channel is undesirable. this has led to the devel- opment of the so-called self synchronizing scram- bler, as shown in figure 20 where a nine stage generator is used. notice in this example how a feedback connection is used for the scrambling generator, whereas a feed forward implementation is used by the de-scrambler. in both cases the same stage outputs are used. before leaving the subject of data scrambling it is worth mentioning the way in which the m-sequence generator is classified. length is an obvious factor but there is also a 'shorthand'method of describing the feedback connections. this is by means of its so called characteristic polynomial. for the nine stage registers illustrated in figure 20 this is: f(x)=x 9 +x 4 +1 an overview of the serial digital interface 14/28
clock q1 q2 q3 q4 AN641-18.eps figure 18 : pseudo-random binary sequence generator q1 q2 q3 q4 1 1 1 1 1 1 1 1 1 00 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 00 1 0 1 1 1 0 0 10 0 1 1 1 1 0 1 1 0 1 1 1 0 1 1 after this the pattern repeats AN641-19.eps figure 19a : states of the 4 stage m-sequence generator data for transmission recovered data scrambled data clock m-sequence generator AN641-20.eps figure 19b : using the m-sequence generator to randomize a data signal 159 data for transmission recovered data scrambled data 9 stage register 159 9 stage register scrambler de-scrambler AN641-21.eps figure 20 : self-synchronising scrambler an overview of the serial digital interface 15/28
appendix 2 : serial interface - technical details this appendix looks at the details of the hardware associated with the serial digital interface, in particular the vlsi chips developed to support it. whilst correct at the time of writing it is possible that certain details might be changed as a result of development. 1 - the serial data format 1.1 - what is carried as mentioned in the introduction one of the main sources-of impetus for the digital interface is the development of digital vtrs and the digital video switcher and its audio equivalent. it seems only natural therefore that the interfacing should best deal with interconnecting these equipments. the serial digital interface offers one video channel, either to d-l or d-2 standard, both 525 and 625, together with a maximum of four channels of digital audio data plus vertical interval time code (vitc). 1.2 - the basic interface two distinct areas of signal processing can be identified when the operation of the interface is considered, data combining and serializing. data combining takes place at source and relates to the bringing together of video, timecode, and audio digital data into one common signal. the signals are combined as parallel data, the combination which results is then serialized for transmission. at the decoder the processes are reversed, de-serial- isation is followed by data separation. 1.3 - data transmission as we have already seen the serial interface is designed to handle signals in either d-1 component or d-2 composite forms, to either 525/60 or 625/50 standards. although component operation is the most demanding case from the transmission point of view, the composite situation is complicated by the relatively short periods available for the auxil- iary data. this is because the d-2 video interface, unlike its d-1 counterpart, includes a digital speci- fication of video synchronizing information - the sync edges and the colour burst. throughout this appendix the timing diagrams refer to composite operation, as typified by the pal d-2 blanking interval shown in figure 21. two other data signals, in addition to the video, are carried by the serial interface, synchronization and auxiliary data, of which audio is a good example. 1.3.1 - serial data synchronization synchronization of the serial data is by means of a sequence of trs (timing reference signal) words. three such words are used, corresponding to the 10 bit values 3ff hex ,000 hex , 000 hex , i.e. the same data pattern as the d-i eav and sav signals. note that as the value 000 hex is reserved for synchronizationit ensures that a long sequence of 0's cannot occur during actual data. in fact, as the interface is designed to cope with both 8 and 10 bit data four values are reserved. corresponding to 000 hex ,001 hex ,002 hex and 003 hex . this allows an 8 bit word (reserved value 00 hex ) to be transmitted as a 10 bit word with two 'dummy' lsb's. the trs data is transmitted on three samples following the sync leading edge. i.e. samples 790 792 in the ntsc example of figure 22 overleaf. immediately following the trs is a line id. this id indicates the field number (within a four field se- quence for ntsc, eight field for pal), as well as an indication of the position of the line within the field. up to line 30 the line number is given explicitly, above this no indication other than the fact that the line number is greater than 30 is provided. fig- ure 23 shows this. the sync level samples which follow the line id, up to the trailing edge of sync, can be used for auxiliary data. figure 24 shows which samples may be used, again the figures are for ntsc. sample 948 (100h) possible data period sample 958 (069h) sample 957 (09bh) (17eh) (082h) sync level (004h) sample 1134 (100h) sample 0 AN641-22.eps figure 21 : d-2 blanking interval showing data sample periods (pal signal) an overview of the serial digital interface 16/28
sample 850 sample 787 sample 785 sample 784 sample 768 samples 790 - 792 trs AN641-23.eps figure 22 : position of trs data sample 850 sample 787 sample 785 sample 784 sample 768 sample793 - line id not used line 1 line 2 line 3 line x line 29 line 30 line < 30 0 0 0 0 n 1 1 1 0 0 0 0 n 1 1 1 0 0 0 0 n 1 1 1 0 0 1 1 n 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 0 1 filed 1 field 2 field 3 field 4 field 5 field 6 field 7 field 8 b7 b6 b0 b1 b2 b3 b5 b4 0 1 0 1 n 1 0 1 AN641-24.eps figure 23 : line id sample 850 sample 787 sample 785 sample 784 sample 768 samples 794 - 849 AN641-25.eps figure 24 : data sample periods an overview of the serial digital interface 17/28
1.3.2 - auxiliary data auxiliary data is transmitted with the block format illustrated in figure 25. the maximum length of a block is 260 words (10 bits), which corresponds to 255 words of actual data. the breakdown of the block is as follows : - auxiliary data flag (l word) this flag must be present if the auxiliary data is to be recognized. the flag has the value 3fc hex . - data id this indicates the type of data, and could have one of 256 states, determined by the state of the 8 lsb's. the remaining bits are used for parity checking - b 8 is an even parity bit for b 7 -b o , whilst by is the inverse of b 8 . although capable of distinguishing 256 different types of data only two are currently identified : aes/ebu format digital audio, and unformatted data. a data id of ff hex indicates audio, 00 hex unformatted. - data block number this is used to distinguish different blocks of data which all share the same data id. it increments by one over the range 1 to 255 as consecutive blocks are transmitted. in this way a string of data longer than 255 words can be transmitted and reassembled in the correct sequence. for data that is not continuous, or identified in some other way, the block number is set to zero. as with the data id the value is conveyed by the 8 lsb's, with the two msb's providing a parity check. - data count the data count word indicates the number of data words included in this block. it can have any value from 1 to 255, and is encoded in precisely the same way as the other control words. - checksum this is a single 9 bit word and is used to check the validity of the data id and user data. it is calculated as the sum, ignoring carry, of the 9 lsb's of the user data and data id words. 1.3.3 - aes/ebu formatted audio data when the data id is set to ff the auxiliary data is interpreted as audio signals corresponding to the aes/ebu format. up to four channels of audio can be included, with a maximum of 27 bits per data sample, spread over three words. 20 of the 27 bits are used for the audio sample itself, the remainder are used for channel identification (2 bits) and the aes/ebu flags. table 1 overleaf shows the distri- bution of data between the three words. table 1 : distribution of aes/ebu format audio data bit 1st word 2nd word 3rd word b9 b8 b8 b8 b8 d5 d14 p b7 d4 d13 c b6 d3 d12 u b5 d2 d11 v b4 d1 d10 d19 b3 d0 d9 d18 b2 ch msb d8 d17 b1 ch 1sb d7 d16 b0 z d6 d15 1.3.4 - unformatted data unformatted data can be transmitted in one of two forms, either 8-bit data with b 8 providing an even parity check, or-9 bit data with no parity checking. in either case b 9 is not used unless as the inverse of b 8 . aux data flag data id data block no. data count check sum user data 255 words maximum AN641-26.eps figure 25 : auxiliary data format an overview of the serial digital interface 18/28
receiver co-processor serial decoder line driver serial encoder transmitter co-processor data outputs video data auxiliary data AN641-27.eps figure 26 : transmitter co-processor bloc diagram data combiner trs & line id adder auxiliary data processing data insertion control timing generation data output timing error indication trs timing v timing pulse data insertion enable composite video data 4 x fsc clock auxiliary data aes/ebu mode data block number data start data insert composite sync colour framing AN641-28.eps figure 27 : transmitter co-processor block diagram 2 - hardware details sony has developed a number of vlsi chips with which the serial interface is implemented. some, the co-processors, are concerned with combining parallel data such as audio and video and its sub- sequent separation. other chips implement the serial link itself. adiagram showing the key features of the transmission system is shown in figure 26. 2.1 - transmitter co-processor the transmitter (and receiver) co-processor is only available for composite signal processing at pre- sent. essentially the co-processor performs two tasks : it combines video and auxiliary data signals prior to serialisation, and it generates the trs and line id data. a block diagram of the co-processor will be found in figure 27. 2.1.1 - main data path composite digital data is first combined with the trs and line id signals (see section 1.3.1). the co-processor assumes 10-bit data throughout the main path, if the input is only 8-bit then the two input lsb's are merely dummies. the trs and line id signals are produced by the main timing block, which is itself controlled by reference video timing information. the timing block ensures that the trs and line id insertion timing is correct (see fig- ure 22). a sync phase adjustment allows timing discrepancies of up to 3 clock periods between the video data and sync reference to be accommo- dated. an overview of the serial digital interface 19/28
2.1.2 - auxiliary data path a number of functions are associated with the auxiliary path, principally mode control and inser- tion timing. mode control governs the way in which the auxiliary data is handled and formatted. with the aes/ebu mode input held high the processor assumes that the incoming data is formatted according to the aes/ ebu standard. the processor internally sets the data id word to ff hex , and the data block number to the value present at the data block number input (see 1.3.2 for description of data id etc.). the auxiliary data flag is also internally set (to 3fc hex ) to indicate the presence of auxiliary data. the information taken from the auxiliary data input is restricted to the data count and audio data words only. the checksum word is ignored and a new checksum calculated internally according to the rules outlined in section 1.3.2. when non aes/ebu formatted data is input (mode control held low) the data id and day block num- ber words are also derived from the incoming data. the auxiliary data flag and checksum continue to be generated internally figure 29 shows the way in which such data fields are combined. 2.1.3 - data insertion control insertion timing control ensures that the incoming auxiliary data is presented by the external device at the appropriate time. figure 24 showed that 55 words were available during the ntsc horizontal sync period for the transmission of auxiliary data. because of the different 4 times fsc clock rates the figure for pal is somewhat higher at 61 words. to enable the external device to match its data to the transmission sequence the co-processor gener- ates a data insertion enable (die) pulse which can have three durations depending on the precise point in the field. there is, of course, less time for data during an equalizing pulse and rather more during a broad pulse. figure 28 shows the timing of the three die pulse durations. the apparent one word discrepancy with figure 24 is due to the fact that the die pulse does not include the checksum word. in order to provide the external device with 'ad- vance warning' of the different insertion periodstwo vertical rate output pulses are also provided. des- ignated enmod0 and enmodl respectively. both are normally low, however enmod0 goes high during the vertical sync period (3 lines ntsc, 21/2 lines pal) whilst enmodi has two high periods, corresponding to the pre- and post- equalizing pulses. 375 words ntsc 465 words pal 20 words nysc 22 words pal 54 words nysc 63 words pal line syncs equalising pulse broad pulse AN641-29.eps figure 28 : die pulse durations an overview of the serial digital interface 20/28
data id aux data flag data block no. data count check sum user data 255 words maximum aux data flag data id check sum data block no. data count user data 255 words maximum data block number input auxiliary data input internally generated aes/ebu formatted data data id aux data flag data block no. data count check sum user data 255 words maximum aux data flag data id check sum data block no. data count user data 255 words maximum auxiliary data input internally generated unormatted data AN641-30.eps figure 29 : auxiliary data formatting once the external device has prepared its data it signals this by means of two control signals, data start pulse (dsp) and data insert pulse (dip). these pulses indicate the start of the user data (defined as the timing of the auxiliary data flag), and the period of actual data. which is, of course, different for formatted and unformatted data. fig- ure 30 overleaf shows the timing relationship of these signals for both cases. of the two pulses the timing of dip is perhaps more important than that of dsp, the processor allows some leeway in the case of the latter. in terms of their relationship with the processorgenerated die signal both must start at least one clock periodlater. in terms of their relative timing dsp can occur up to 3 clock periods early, or 1 clock period late, with respect to dip. this basically means that dsp can be permanently set for either formatted or unfor- matted data, and data of either type transmitted. the dip timing is then changed to suit the data. an error indication is provided if these conditions are not met. figure 31 illustrates these points. 2.1.4 - timing generator the timing generator derives control timing infor- mation from the composite sync signal, in particular a vertical reference pulse which flags the start of each field. all insertion timings are derived from the sync signal, clocked by 4fsc as appropriate. one of the processor inputs is a pal/ntsc mode control which is used to modify the timings of signals such as enmod and die in order to reflect the different system parameters. colour framing information (four field ntsc, eight field pal) is also input. this is used to determine the state of the three lsb's of the line id, see figure 23. a timing signal to indicate the position of the trs information is also provided. an overview of the serial digital interface 21/28
aux data flag data id data block no. data count check sum user data 255 words maximum period defined by die data start (dsp) data insert (dip) aes/ebu format data shaded blocks show data words determined internally aux data flag data id data block no. data count check sum user data 255 words maximum period defined by die data start (dsp) data insert (dip) shaded blocks show data words determined internally unormatted data AN641-21.eps figure 30 : timing of dsp and dip signal aux data flag data id data block no. data count check sum user data 255 words maximum period defined by die dsp dip dsp dip one clock period minimum die AN641-32.eps figure 31 : timing requirements for dip and dsp an overview of the serial digital interface 22/28
serial clock data input (nrz) scrambled output (nrzi) nrz to nrzi data scrambler AN641-33.eps figure 32 : form of data scrambler 2.2 - serial encoder the encoder contains all the circuitry for parallel to serial conversionof the data signal, channel coding and transmission line driving. whilst the internal transmission line driver is suitable for board to board interfacing the external cable driver will nor- mally be used as well. whilst features such as parallel-to-serial conver- sion itself and clock generation are, perhaps, obvi- ous two features are worthy of explanation. 2.2.1 - sync identification whilst the responsibility for generating the trs (3ff hex . 000 hex , 000 hex ) rests with the external parallel data processing the encoder includes cir- cuitry to trap the presence of multiple all-zero words. if three consecutive all-zero words are de- tected at the input the two lsb's are set to one (003 hex ). 2.2..2 - data scrambling the channel coding is described as scrambled nrzi (see sections 4.4.2 and 4.4.6 in appendix 1). in fact more accurate description would be (scram- bled nrz), as the input nrz data is first random- ized, and the result converted to nrzi. figure 32 shows the form of the so-called scrambler. note that this as no effect on logic 0's, however the possibility of a long run occurring is limited because of the data restrictions associated with the sync word. in fact the maximum number of zeros recur- ring at the scrambler output has been calculated as 38 after the sync word, but only 20 with normal data. although a long run of ones could be produced these are converted to transitions by the nrz to nrzi conversion, which helps to reduce the if content of the signal. 2.2.3 - logic level the parallel inputs are pin selectable for either balanced ecl levels, or single ended ttl drives. 2.3 - decoder the key features of the decoder are cable equali- zation, clock recovery, de-scrambling and serial to parallel conversion, as shown in the overview of figure 33. clock recovery timing generator serial to parallel cable equalizer de-scrambling serial data input parallel output AN641-34.eps figure 33 : serial decoder overview an overview of the serial digital interface 23/28
slicing level data signal AN641-35.eps figure 34 : optimum slicing level peak detector buffer amplifier hf amplifier variable gain amplifier variable gain amplifier buffer amplifier hf amplifier buffer amplifier equalizer output equalizer input AN641-36.eps figure 35 : cable equalizer 2.3.1 - cable equalization although line driving is carried out by a separate ic associated with the encoder cable equalization is an integral part of the decoder. in fact the decoder has two selectable data inputs, a 'digital' input intended for use with a balanced ecl transmission line, and an analogue input for single ended co-ax- ial transmission. the analogue input includes a cable equalizer capable of correcting both the h.f. and l.f. re- sponses of the circuit. the hf equalizer is designed to correct a loss of some 30db at 135mhz, and is shown in figure 35. rather than passing the input signal through some form of reactive correction circuit variable gain amplifiers in a side chain are used. with no hf loss, as determined by peak detection, the side chain amplifiers are just cut off. as the h.f. content falls the peak detector increases the gain of the ampli- fiers in order to boost the hf response. the equal- izer is capable of maintaining a constant signal level, within +2db, for cables of up to 300m. note that as the equalizer responds to the peak signal level it is vital that the signal level at the encoder output is set correctly. the decoder also corrects the lf response, which in this case is taken as frequencies below 8mhz. fundamentally the lf equalizer aims to keep the data signal at the dc level that results in half-ampli- tude sampling, see figure 34. obasically the equalizer integrates the output of the data slicer, and uses the resulting dc to offset the slicer input bias. figure 36 shows this. 2.3.2 - clock recovery clock recovery relies on the fact that the nrzi data stream contains a large number of transitions. an edge detector circuit identifies the transitions and passes them to a phase detector. this compares the local vco output with the incoming data tran- sitions and so regenerates the serial clock, see figure 37. 2.3.3 - de-scrambling de-scrambling follows the same procedure as scrambling in reverse. first the nrzi signal is converted back to nrz, and then descrambled. figure 38 shows this. an overview of the serial digital interface 24/28
buffer amplifier 8mhz l.p.f. 8mhz h.p.f. zero crossing detector buffer amplifier data output from hf equalizer AN641-37.eps figure 36 : dc compensation serial data serial clock reclocked data delay edge pulse generator phase detector vco data recovery AN641-38.eps figure 37 : serial clock regeneration serial clock nrz to nrzi data scrambler data input (scrambled nrz) serial output (nrz) AN641-39.eps figure 38 : data de-scrambling 2.3.4 - serial-to-parallel conversion 10-bit parallel data words have to be re-assembled from the de-scrambled serial data. this means storing the data until a complete group is available and latching the result. how does the decoder identify the bit groups? the answer is by looking for the trs - the timing reference signal. as described in section 1.3.1 . the trs is a reserved combination of three ten bit data words - 3ff hex , 000 hex , 000 hex , the order of transmission being 3ff, followed by 000, 000, lsb's first. the decoder therefore stores a se- quence of 30 bits in a shift register. the parallel outputs are continuously examined for the trs data pattern, and, when identified, a sync signal is generated. the sync signal is used to control the timing generatorused to produce the parallel clock, which in turn is used to latch the 10-bit data words to the decoder output. figure 39 shows these functions. an overview of the serial digital interface 25/28
serial data serial clock parallel output 30-bit shift register 10-bit data latch timing generation trs identifier 10 bits 30 bits AN641-40.eps figure 39 : serial-to-parallel conversion 2.4 - receiver co-processor the receiver co-processor caries out the reverse functions to those of the transmitter, at separates the video, audio and ancillary data for their respec- tive destinationsas well as providing control signals and error indication. a block diagram of the co-processor is shown in figure 40. 2.4.1 - sync data replacement this block is responsible for returning the sync intervals of the video data to normal. it therefore replaces all the non-video data words (trs, line id, aux data, etc.) with the appropriate blanking or sync interval value. for d-2 pal this is 004 hex , 010 hex for ntsc. the timing of this process is achieved from the line id information, which in- cludes information about the line timing within the field and hence allows a replica of the transmitter die signal to be reconstructed. if a line id error is detected for three or more lines the id error output goes high to flag the condition. 2.4.2 - auxiliary data recovery the recovery of auxiliary data is initiated by correct identification of the auxiliary data flag in the data stream. an output (user data exists) is provided as one of the control signals. the nature of data recovery depends on whether the data is formatted or not. this is achieved through detection of the data id and data count words. the auxiliary data block is, in fact, output in its entirety (aux data flag to checksum inclusive), however timing signals are provided to enable external equipment to identify the component parts of the data. figure 41 shows this information 2.4.3 - error information in addition to the line id error output described in section 2.4.1 a composite error flag is provided. the signal is the result of parity checks performed on individual data words. by combining the error flag with the timing control signals shown in fig- ure 41 specific errors can be identified - e.g. data id error, checksum, etc. an example error flag output is also shown in figure 41. an overview of the serial digital interface 26/28
aes/ebu mode detector data count detector id error detector data id detector id detector sync data replace timing control trs detector aux data flag detector auxiliary data recovery and error detection auxiliary data output error flag timing and control signals audio mode id error line number colour framing video data output trs timing v pulse auxiliary data block composite video data AN641-41.eps figure 40 : the receiver co-processor an overview of the serial digital interface 27/28
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. timing reference signal line id aux data flag data id data block no. data count check sum user data 255 words maximum trs timing adf timing did timing dbn timing dc timing user data exists cs timing error flag dc error aux data error cs error adf error AN641-42.eps figure 41 : timing control signals an overview of the serial digital interface 28/28

▲Up To Search▲

Price & Availability of AN641

	To Download AN641 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .