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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. TPSM831D31 slusdc9 ? august 2018 TPSM831D31 8-v to 14-v input, 0.25-v to 1.52-v dual output, 120-a + 40-a pmbus ? power module 1 1 features 1 ? input voltage range: 8 v to 14 v ? dual output: 120 a (3-phase) + 40 a (1-phase) ? output voltage range: 0.25 v to 1.52 v ? programmable in 5-mv steps ? differential remote sense ? 0.5% vref accuracy with remote sense ? pmbus interface ? programmable v out , uvlo, fault limits ? vin, vout, iout, temperature telemetry ? supports up to 1-mhz bus speed ? on-chip non-volatile configuration memory ? ultra-fast transient response ? switching frequency range: 350 khz to 700 khz ? 15-mm 48-mm footprint and 12-mm height ? efficiencies up to 95% ? dual power good outputs ? overcurrent, overvoltage, overtemperature protection ? operating ic junction range: ? 40 c to 125 c ? operating ambient range: ? 40 c to 105 c 2 applications ? high-performance processor / asic with dual power rails ? networking processor power ( broadcom ? , cavium ? , marvell ? , nxp ? ) ? high-current fpga power ( intel ? , xilinx ? ) ? high-performance arm processor power 3 description the TPSM831D31 is a pmbus ? -controlled, dual- output, 4-phase power module that combines a high- performance d-cap+ ? controller with four high- efficiency smart power stages, and low-loss inductors, into a rugged, thermally enhanced surface- mount package. the user supplies the input and output capacitors and a few passive components to complete the system. the first output is configured as a 3-phase power stage that can deliver up to 120 a of continuous output current. the second output is a single phase power stage that can deliver up to 40 a of output current. the pmbus interface provides for converter configuration of each vout, uvlo, soft start, overcurrent, and thermal shutdown parameters. the interface provides support for telemetry that can report the actual input voltage, output voltage, output current, and device temperature. the computed input and output power can also be reported. standard pmbus warning and fault functions are also supported. the device supports pmbus communication speeds up to 1 mhz, with 1.8-v or 3.3-v logic levels, as detailed in section 4.3 of smbus specification v3.0. the module supports a subset of the commands in the pmbus 1.3 specification. device information (1) part number package body size (nom) TPSM831D31 moa (28) 48.00 mm 15.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified application pmbus v in : 8 v to 14 v asic core asic i/o voutb 40 a vouta 120 a advance information tools & software technical documents ordernow productfolder support &community
2 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 6 6.5 electrical characteristics ........................................... 6 6.6 references: dac ...................................................... 8 6.7 telemetry .................................................................. 8 6.8 current sense and calibration .................................. 8 6.9 logic interface pins: a_en, a_pgood, b_en, b_pgood,reset .................................................... 9 6.10 protections: ovp and uvp ..................................... 9 6.11 typical characteristics (v in = 12 v) ...................... 10 7 detailed description ............................................ 12 7.1 overview ................................................................. 12 7.2 functional block diagram ....................................... 12 7.3 feature description ................................................. 13 7.4 device functional modes ........................................ 17 7.5 programming ........................................................... 17 8 application and implementation ........................ 71 8.1 application information ............................................ 71 8.2 typical application .................................................. 71 9 power supply recommendations ...................... 73 10 layout ................................................................... 73 10.1 layout guidelines ................................................. 73 10.2 layout examples ................................................... 73 11 device and documentation support ................. 75 11.1 receiving notification of documentation updates 75 11.2 community resources .......................................... 75 11.3 trademarks ........................................................... 75 11.4 electrostatic discharge caution ............................ 75 11.5 glossary ................................................................ 75 12 mechanical, packaging, and orderable information ........................................................... 76 4 revision history date revision notes august 2018 * initial release advance information
3 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) g = ground, i = input, o = output 5 pin configuration and functions moa package 28-pin qfm top view pin functions pin i/o (1) description name no. addr 23 i connect a resistor from this pin to gnd to set the desired pmbus address. do not leave this pin floating. see pmbus address section. a_en 10 i active high enable input for vout_a. asserting this pin high enables power conversion on the vout_a channel. a_pgood 9 o open drain power good signal of the vout_a channel. this pin requires a pullup resistor. this pin is pulled low when a shutdown fault occurs. avsn 12 i negative input of the remote voltage sense of channel a. connect this pin to ground at the vout_a load for best voltage regulation. do not let this pin float. avsp 11 i positive input of the remote voltage sense of channel a. connect this pin to vout_a at the load for best voltage regulation. do not let this pin float. b_en 21 i active high enable input for vout_b. asserting this pin high enables power conversion on the vout_b channel. b_pgood 22 o open drain power good signal of the vout_b channel. this pin requires a pullup resistor. this pin is pulled low when a shutdown fault occurs. advance information 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 5 6 7 8 9 10 11 12 4 3 2 1 vout_a vout_a vout_a vout_b vin gnd vin gnd vin gnd vin gnd pmbdat pmbclk pmbalert reset a_pgood a_en avsp avsn gnd gnd dnc addr b_pgood b_en bvsp bvsn
4 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions (continued) pin i/o (1) description name no. bvsn 19 i negative input of the remote voltage sense of channel b. connect this pin to ground at the vout_b load for best voltage regulation. do not let this pin float. bvsp 20 i positive input of the remote voltage sense of channel b. connect this pin to vout_a at the load for best voltage regulation. do not let this pin float. dnc 24 ? do not connect. this pin is connected to internal circuitry. do not connect this pin to other signal or voltage source. connecting the pin to gnd is recommended. gnd 1 g power ground of the device. connect pins 1, 3, 13, and 15 to the bypass caps associated with vin. connect pads 1, 3, 13, 15 to the pcb ground planes using multiple vias for optimal thermal performance. 3 13 15 25 26 pmbclk 6 i pmbus serial clock interface. (open drain) pmbdat 5 i/o pmbus bi-directional serial data interface. (open drain) pmbalert 7 i/o pmbus bi-directional alert pin interface. (open drain) reset 8 i active low reset input that resets the output voltage to its programmed boot voltage. this pin requires a pullup resistor. vin 2 i input voltage. these pins provide voltage to the power conversion stages of the module. connect these pins to the pcb vin planes using multiple vias for optimal thermal performance. 4 14 16 vout_a 18 o output voltage of channel a. connect these pins to the output a load. connect external bypass capacitors between these pins and gnd pins 1, 3, and 13. 27 28 vout_b 17 o output voltage of channel b. connect this pin to the output b load. connect external bypass capacitors between this pin and gnd pin 15. advance information
5 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolutemaximum ratings may cause permanent damage to the device. these are stress ratings onlyand functional operation of the device at these or any other conditions beyond those indicatedunder " recommended operating conditions " is not implied. exposure to absolute-maximum-ratedconditions for extended periods may affect device reliability. (2) all voltage values are with respect to the network ground terminalgnd unless otherwise noted. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit input voltage (2) vin ? 0.3 19 v addr, avsp, bvsp, reset, pmbclk, pmbdat ? 0.3 3.6 v agnd, avsn, bvsn ? 0.3 0.3 v output voltage (1) (2) vout_a, vout_b, a_pgood, b_pgood, pmbalert ? 0.3 3.6 v mechanical shock mil-std-883d, method 2002.3, 1 msec, 1/2 sine, mounted tbd g mechanical vibration mil-std-883d, method 2007.2, 20 to 2000 hz tbd g operating junction temperature, t j ? 40 150 c storage temperature, t stg ? 55 150 c (1) jedec document jep155 states that 500-v hbm allows safemanufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safemanufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) tbd v charged-device model (cdm), per jedec specification jesd22-c101 (2) tbd 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit vin 8 12 14 v vout_a, vout_b, avsp, bvsp 0.25 1.52 v iouta 0 120 a ioutb 0 40 a pmbclk, pmbdat, reset pullup, a_pgood pullup, b_pgood pullup, pmbalert pullup 3.3 3.5 v switching frequency 350 400 700 khz operating junction temperature, t j ? 40 125 c operating ambient temperature, t a ? 40 105 c external input capacitance, c in ceramic 500 f non-ceramic 1000 f external output capacitance, c out_a ceramic 600 1200 f non-ceramic 2750 5500 f external output capacitance, c out_b ceramic 200 400 f non-ceramic 900 1800 f advance information
6 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for more information about thermal metrics, see the semiconductor and ic package thermalmetrics application report . (2) the junction-to-ambient thermal resistance applies to devicessoldered directly to a 100 mm x 150 mm, 8-layer pcb with 2 oz. copper. (3) the junction-to-top board characterization parameter, jt , estimates the junction temperature, t j , of adevice in a real system, using a procedure described in jesd51-2a (section 6 and 7).t j = jt pdis + t t ; wherepdis is the power dissipated in the device and t t is the temperature of thetop of the inductor. (4) the junction-to-board characterization parameter, jb , estimates the junction temperature, t j , of adevice in a real system, using a procedure described in jesd51-2a (sections 6 and 7).t j = jb pdis + t b ; wherepdis is the power dissipated in the device and t b is the temperature of theboard 1mm from the device. 6.4 thermal information thermal metric (1) TPSM831D31 unit moa (qfn) 28 pins r ja junction-to-ambient thermal resistance (2) natural convection 5.5 c/w 200 lfm 3.4 c/w 400 lfm 2.8 c/w jt junction-to-top characterization parameter (3) 0.3 c/w jb junction-to-board characterization parameter (4) 1.6 c/w t sd thermal shutdown temperature (default setting) 135 c 6.5 electrical characteristics t a = ? 40 c to +105 c , v in = 12 v,v outa = v avsp = 1 v, v outb =v bvsp = 1 v, v avsn = v bvsn = 0v, i outa = i outb = 0 a, f sw =400 khz, c in1 = 24 22- f, 25-v, 1210 ceramic, c in2 = 2 470 f, electrolytic bulk, c outa1 = 12 100- f, 6.3-v, 1210 ceramic,c outa2 = 12 470 f, 6.3 v, c outb1 = 4 100- f,6.3-v, 1210 ceramic, c outb2 = 4 470- f, 6.3-v polymer bulk. minimum andmaximum limits are specified through production test or by design. typical values represent themost likely parametric norm and are provided for reference only.(unless otherwisenoted). parameter test conditions min typ max unit input voltage v in input voltage range 8 14 v uvlo v in undervoltage lockout v in increasing (default setting) 7.25 v v in decreasing (default setting) 6.5 v i in(stby) input standby current a_en = b_en = gnd 8 12 ma output voltage v out_a boot voltage 5-mv dac (default setting) 0.492 0.5 0.508 v programmable range 5-mv dac 0.25 1.52 v programmable step size 5-mv dac 5 mv set-point voltage tolerance 5-mv dac, 0.8 v vout 1 v ? 5% 5% line regulation 8 v v in 14 v 0.1% load regulation 0 a i out 120 a 0.1% output voltage ripple 20-mhz bandwidth 10 mv v out_b boot voltage 5-mv dac (default setting) 0.492 0.5 0.508 v programmable range 5-mv dac 0.25 1.52 v programmable step size 5-mv dac 5 mv set-point voltage tolerance 5-mv dac, 0.8 v vout 1 v ? 5% 5% line regulation 8 v v in 14 v, 0.1% load regulation 0 a i out 120 a 0.1% output voltage ripple 20-mhz bandwidth 30 mv advance information
7 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) t a = ? 40 c to +105 c , v in = 12 v,v outa = v avsp = 1 v, v outb =v bvsp = 1 v, v avsn = v bvsn = 0v, i outa = i outb = 0 a, f sw =400 khz, c in1 = 24 22- f, 25-v, 1210 ceramic, c in2 = 2 470 f, electrolytic bulk, c outa1 = 12 100- f, 6.3-v, 1210 ceramic,c outa2 = 12 470 f, 6.3 v, c outb1 = 4 100- f,6.3-v, 1210 ceramic, c outb2 = 4 470- f, 6.3-v polymer bulk. minimum andmaximum limits are specified through production test or by design. typical values represent themost likely parametric norm and are provided for reference only.(unless otherwisenoted). parameter test conditions min typ max unit (1) see soa graph for derating over temperature. (2) phase shedding disabled. (3) applies to both vouta and voutb. output current i out_a output current natural convection (1) 0 120 a overcurrent fault threshold factory default setting (150% of i out max) 180 a per phase ocl level (default setting) 54 a overcurrent warning threshold factory default setting (100% of i out max) 120 a i out_b output current natural convection (1) 0 40 a overcurrent fault threshold factory default setting (150% of i out max) 60 a per phase ocl level (default setting) 54 a overcurrent warning threshold factory default setting (100% of i out max) 40 a performance efficiency (2) i out_a = 90 a, v out_b disabled 93% i out_b = 30 a, v out_a = disabled 92% timing t startupa vouta start-up time v vboot > 0 v, no faults, ton_delay = 0xb1ec (page 0) (default setting) 0.38 0.48 0.58 ms t startupb voutb start-up time v vboot > 0 v, no faults, ton_delay = 0xb396 (page 1) (default setting) 0.8 0.9 1 ms t vccvid vid change to vsp change ack of setvid_x command to start of voltage ramp 500 ns t on_blank rising-edge blanking time (3) mfr_spec_09 < 8:6 > = 110b (default setting) 53 72 92 ns sl set slew rate setting (3) vout_transition_rate = 0xe028 (default setting) 2.5 mv/ s sl ss avsp and bvsp slew rate soft-start (3) mfr_spec_13 < 8 > = 0b (default setting) sl set /4 mv/ s switching frequency f sw switching frequency (3) frequency_switch = 0x0190 (default setting) 360 400 440 khz range (3) 350 700 khz advance information
8 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) applies to both vouta and voutb. 6.6 references: dac over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit v vidstp vid step size (1) 5 mv dac: change vid0 hi to lo to hi 5 mv k ratio voltage divider ratio (1) vout_scale_loop = 0xe808, vout_scale_monitor = 0xe808 1.000 v out_triml v out offset lsb (1) mfr_specific_05 = 0x01 0 1.25 2.5 mv v out_trimr v out offset range mfr_specific_05 = 0x1f 37.5 38.75 40 mv mfr_specific_05 = 0xa0 ? 43.25 ? 40 ? 37.75 mfr_specific_05 = 0x5f 56.25 58.75 61.25 mfr_specific_05 = 0xe0 ? 63 ? 60 ? 57 6.7 telemetry over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit v read_vout mfr_read_vout accuracy 5-mv dac : 0.25 v v vsp 1.52 v ? 12 12 mv v read_vin read_vin accuracy 8 v v in 14 v ? 2.25% 2.25% i mon_acc_a digital current monitor accuracy, rail a (read_iout) i out = 120 a ? 3% 3% i mon_acc_b digital current monitor accuracy, rail b (read_iout) i out = 40 a ? 3% 3% temp read_temp1 0.28 v ( ? 40 c) tsen 1.8 v (150 c) ? 2 0 2 c 6.8 current sense and calibration over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit i mon_cal_of1 current monitor calibration offset lsb (per-phase) iout_cal_offset resolution (per-phase) 0.125 a i mon_cal_of2 current monitor calibration offset range (per-phase) iout_cal_offset = 0xe808 (per-phase) 1 a iout_cal_offset = 0xeff9 (per-phase) ? 0.875 a i mon_cal_of3 current monitor calibration offset lsb (total) iout_cal_offset resolution (total) 0.25 a i mon_cal_of4 current monitor calibration offset range (total) iout_cal_offset = 0xe820 (total) 4 a iout_cal_offset = 0xefe2 (total) ? 3.75 a i mon_cal_lsb current monitor calibration gain lsb iout_cal_gain resolution 0.3125% i mon_cal_gain current monitor calibration gain range iout_cal_gain = 0xd131 4.7656 m iout_cal_gain = 0xd150 5.25 m advance information
9 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) specified by design. not production tested. 6.9 logic interface pins: a_en, a_pgood, b_en, b_pgood,reset over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit r rpgdl open-drain pulldown resistance v a_pgood = v b_pgood = 0.45 v 36 50 i vrttlk open-drain leakage current sdio, a_pgood, b_pgood, hi z leakage, 3.3-v applied in off state ? 2 0.2 2 a v aenl channel a enable logic low 0.7 v v aenh channel a enable logic high 0.8 v v aenhys channel a enable hysteresis 0.028 0.05 0.07 v t aendig channel a enable deglitch (1) 0.2 s i aenh channel a i/o 1.1-v leakage v a_en = 1.1 v 25 a v benl channel b enable logic low 0.7 v v benh channel b enable logic high 0.8 v v benhys channel b enable hysteresis 0.028 0.05 0.07 v t bendig channel b enable deglitch (1) 0.2 s t aenvrrdyf channel a enable low to a_pgood low from a_en low to a_pgood low 1.5 s i benh channel b i/o 1.1-v leakage v benh = 1.1 v 25 a v rstl reset logic low 0.8 v v rsth reset logic high (1) 1.09 v t rsttdly reset delay time 1 s (1) time from vsp out of 200-mv or 400-mv vdac boundary to vr_rdylow. (2) can be programmed with different configurations. 6.10 protections: ovp and uvp over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit v rdyh5 tracking ovp measured at the vsp pin wrt vid code. device latches off. 330 400 mv v rdyh0 measured at the vsp pin wrt vid code. device latches off. 140 200 mv t rdydglto vr_rdy deglitch time see (1) 2.5 s t rdydgltu vr_rdy deglitch time f sw = 500 khz 4 s v rdyl undervoltage protection (2) (v vsp + v droop ) with respect to vid 370 400 430 mv v ovpa fixed overvoltage protection, channel a (2) v avsp > v ovp for 1 s, enable = hi or lo, pwm to lo 2.75 2.75 2.86 v v ovpb fixed overvoltage protection, channel b (2) v bvsp > v ovp for 1 s, enable = hi or lo, pwm to lo 1.85 1.9 1.95 v advance information
10 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.11 typical characteristics (v in = 12 v) figure 1. vouta efficiency figure 2. voutb efficiency figure 3. vouta power dissipation figure 4. voutb power dissipation figure 5. vouta load regulation figure 6. voutb load regulation output current (a) efficiency (%) 0 5 10 15 20 25 30 35 40 70 75 80 85 90 95 100 d007 v out 1.5 v 1.2 v 1.0 v 0.85 v output current (a) power dissipation (w) 0 5 10 15 20 25 30 35 40 0 1 2 3 4 5 6 7 8 d008 v out 1.5 v 1.2 v 1.0 v 0.85 v output current (a) efficiency (%) 0 10 20 30 40 50 60 70 80 90 100 110 120 70 75 80 85 90 95 100 d001 v out 1.5 v 1.2 v 1.0 v 0.85 v output current (a) load regulation (v) 0 5 10 15 20 25 30 35 40 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 1.004 d010 v out 1.0 v output current (a) power dissipation (w) 0 10 20 30 40 50 60 70 80 90 100 110 120 0 2 4 6 8 10 12 14 16 d002 v out 1.5 v 1.2 v 1.0 v 0.85 v advance information output current (a) load regulation (v) 0 10 20 30 40 50 60 70 80 90 100 110 120 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 1.004 d004 v out 1.0 v
11 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (v in = 12 v) (continued) v in = 12 v v outa = v outb = 1.0 v f sw = 400 khz all phases evenly loaded figure 7. thermal safe operating area v in = 12 v v outa = v outb = 0.8 v f sw = 400 khz all phases evenly loaded figure 8. thermal safe operating area output current (a) ambient temperature (c) 0 20 40 60 80 100 120 140 160 25 35 45 55 65 75 85 95 105 115 d021 airflow 400lfm 200lfm 100lfm nat conv advance information output current (a) ambient temperature (c) 0 20 40 60 80 100 120 140 160 25 35 45 55 65 75 85 95 105 115 d022 airflow 400lfm 200lfm 100lfm nat conv
12 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the TPSM831D31 is a pmbus-controlled, dual output 4-phase power module. both outputs have a programmable output voltage range of 0.25 v to 1.52 v. the first output is configured as a 3-phase power stage that can deliver up to 120 a of output current. the second output is a single phase power stage that can deliver up to 40 a of output current 7.2 functional block diagram advance information vin gnd vouta TPSM831D31 cpu logic, protection, status circuitry adaptive on-time control and current share circutry internal regultors (5v/3.3v) i 2 c interface pmbclk pmbdata nvm pmbalert addr afe adc dac a_pgood b_pgood avsp avsn remote sense amplifier ramp generator copyright ? 2018, texas instruments incorporated bvsp bvsn loadline control programmable loop mode control, phase manager, fet drivers voutb vin vin vin reset b_en a_en
13 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3 feature description 7.3.1 dcap+ control for high current applications, d-cap+ control architecture, combines the benefits of d-cap constant on-time control with those of multiphase converters. d-cap+ control ensures that inductor currents of individual phases are fed back so the system has accurate droop control and good current-sharing performance as well an error amplifier is utilized to improve dc accuracy over load and line. figure 9 illustrates the operational waveforms of d-cap+ control architecture with 3 phases in steady state. by using the adaptive on-time control concept, a pseudo fixed switching frequency of sw_clk is generated by comparing the summed inductor currents, isum, and the error amplifier output, ea, signal. by distributing the switching signal to different phases, all phases can be perfectly interleaved in steady state. during load transients, the switching frequency is varied to improve the transient performance as shown in figure 10 . variable switching frequencies of different phases can be observed. one important feature of a multiphase converter is the capability to dynamically add or drop the number of operational phases based on load conditions. the goal is to optimize efficiency while maintaining good load transient performance. figure 9. 3-phase steady state switching figure 10. 3-phase transient operation advance information
14 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 7.3.2 setting the load-line (droop) figure 11. load line the loadline can be set with vout_droop register via pmbus. the programmable range for channel a is between 0 m ? and 3.125 m ? with 64 options, and the range for channel b is between 0 m ? and 0.875 m ? with 16 options to fulfill the requirements for different applications. see table 27 for the dc load line settings. 7.3.3 start-up timing the start-up time is the time from when a start condition is received (as programmed by the on_off_config command) until the output voltage starts to rise. the start-up time for both outputs can be programmed using the ton_delay command as shown in table 1 . (1) channel a (page 0); channel b (page 1) table 1. start-up time (1) start-up time (ms) min typ max ton_delay = 0xb1ec 0.38 0.48 0.58 ton_delay = 0xb396 0.8 0.9 1 ton_delay = 0xbad1 1.308 1.408 1.508 ton_delay = 0xc26e 2.28 2.432 2.584 ton_delay = others invalid 7.3.4 load transitions the TPSM831D31 achieves fast load transient performance using the inherent variable switching frequency characteristics. when there is a sudden load increase, the output voltage rapidly drops, which forces the pwm pulses to switch sooner and more frequently which causes the inductor current to rapidly increase. as the inductor current reaches the new load current, the device reaches a steady-state operating condition and the pwm switching resumes the steady-state frequency. when there is a sudden load release, the output voltage rapidly rises, which forces the pwm pulses to be delayed until the inductor current reaches the new load current. at that point, the switching resumes and steady- state switching continues. v droop v dac v droop = r ll x i out slope of loadline r ll i out advance information
15 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.5 switching frequency the TPSM831D31 switching frequency can be selected from several values between 350 khz to 700 khz as shown in table 2 . the frequency_switch command is used to select the desired switching frequency. table 2. switching frequency select frequency select (khz) command 350 frequency_switch = 0x015e 400 frequency_switch = 0x0190 (factory default setting) 450 frequency_switch = 0x01c2 500 frequency_switch = 0x01f4 550 frequency_switch = 0x0226 600 frequency_switch = 0x0258 650 frequency_switch = 0x028a 700 frequency_switch = 0x02bc 7.3.6 reset function during adaptive voltage scaling (avs) operation, the voltage may become falsely adjusted to be out of asic operating range. the reset function returns the voltage to the vboot voltage. when the voltage is out of asic operating range, the asic issues a reset signal to the TPSM831D31 device. the device senses this signal and after a delay of greater than 1 s, it sets an internal reset_fault signal and sets vout_command to vboot. the device pulls the output voltage to the vboot level with the slew rate set by vout_transition_rate command. when the reset pin signal goes high, the internal reset_fault signal goes low. table 3. vboot boot voltage setting (5-mv dac) boot voltage (v) mfr_spec_11 < 7:0 > = 00h 0.000 mfr_spec_11 < 7:0 > = 33h 0.500 mfr_spec_11 < 7:0 > = 83h 0.900 mfr_spec_11 < 7:0 > = 97h 1.000 mfr_spec_11 < 7:0 > = bfh 1.200 advance information
16 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.7 vid table the dac voltage vdac can be changed via pmbus according to table 4 . table 4. vid table (5 mv dac) vid hex value dac step vid hex value dac step vid hex value dac step vid hex value dac step vid hex value dac step vid hex value dac step 00 0.000 2b 0.460 56 0.675 81 0.890 ac 1.105 d7 1.320 01 0.250 2c 0.465 57 0.680 82 0.895 ad 1.110 d8 1.325 02 0.255 2d 0.470 58 0.685 83 0.900 ae 1.115 d9 1.330 03 0.260 2e 0.475 59 0.690 84 0.905 af 1.120 da 1.335 04 0.265 2f 0.480 5a 0.695 85 0.910 b0 1.125 db 1.340 05 0.270 30 0.485 5b 0.700 86 0.915 b1 1.130 dc 1.345 06 0.275 31 0.490 5c 0.705 87 0.920 b2 1.135 dd 1.350 07 0.280 32 0.495 5d 0.710 88 0.925 b3 1.140 de 1.355 08 0.285 33 0.500 5e 0.715 89 0.930 b4 1.145 df 1.360 09 0.290 34 0.505 5f 0.720 8a 0.935 b5 1.150 e0 1.365 0a 0.295 35 0.510 60 0.725 8b 0.940 b6 1.155 e1 1.370 0b 0.300 36 0.515 61 0.730 8c 0.945 b7 1.160 e2 1.375 0c 0.305 37 0.520 62 0.735 8d 0.950 b8 1.165 e3 1.380 0d 0.310 38 0.525 63 0.740 8e 0.955 b9 1.170 e4 1.385 0e 0.315 39 0.530 64 0.745 8f 0.960 ba 1.175 e5 1.390 0f 0.320 3a 0.535 65 0.750 90 0.965 bb 1.180 e6 1.395 10 0.325 3b 0.540 66 0.755 91 0.970 bc 1.185 e7 1.400 11 0.330 3c 0.545 67 0.760 92 0.975 bd 1.190 e8 1.405 12 0.335 3d 0.550 68 0.765 93 0.980 be 1.195 e9 1.410 13 0.340 3e 0.555 69 0.770 94 0.985 bf 1.200 ea 1.415 14 0.345 3f 0.560 6a 0.775 95 0.990 c0 1.205 eb 1.420 15 0.350 40 0.565 6b 0.780 96 0.995 c1 1.210 ec 1.425 16 0.355 41 0.570 6c 0.785 97 1.000 c2 1.215 ed 1.430 17 0.360 42 0.575 6d 0.790 98 1.005 c3 1.220 ee 1.435 18 0.365 43 0.580 6e 0.795 99 1.010 c4 1.225 ef 1.440 19 0.370 44 0.585 6f 0.800 9a 1.015 c5 1.230 f0 1.445 1a 0.375 45 0.590 70 0.805 9b 1.020 c6 1.235 f1 1.450 1b 0.380 46 0.595 71 0.810 9c 1.025 c7 1.240 f2 1.455 1c 0.385 47 0.600 72 0.815 9d 1.030 c8 1.245 f3 1.460 1d 0.390 48 0.605 73 0.820 9e 1.035 c9 1.250 f4 1.465 1e 0.395 49 0.610 74 0.825 9f 1.040 ca 1.255 f5 1.470 1f 0.400 4a 0.615 75 0.830 a0 1.045 cb 1.260 f6 1.475 20 0.405 4b 0.620 76 0.835 a1 1.050 cc 1.265 f7 1.480 21 0.410 4c 0.625 77 0.840 a2 1.055 cd 1.270 f8 1.485 22 0.415 4d 0.630 78 0.845 a3 1.060 ce 1.275 f9 1.490 23 0.420 4e 0.635 79 0.850 a4 1.065 cf 1.280 fa 1.495 24 0.425 4f 0.640 7a 0.855 a5 1.070 d0 1.285 fb 1.500 25 0.430 50 0.645 7b 0.860 a6 1.075 d1 1.290 fc 1.505 26 0.435 51 0.650 7c 0.865 a7 1.080 d2 1.295 fd 1.510 27 0.440 52 0.655 7d 0.870 a8 1.085 d3 1.300 fe 1.515 28 0.445 53 0.660 7e 0.875 a9 1.090 d4 1.305 ff 1.520 29 0.450 54 0.665 7f 0.880 aa 1.095 d5 1.310 2a 0.455 55 0.670 80 0.885 ab 1.100 d6 1.315 advance information
17 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4 device functional modes 7.4.1 continuous conduction mode the TPSM831D31 device operates in continuous conduction mode (ccm) at a fixed frequency. as programmed from the factory, phase shedding is disabled and can be enabled with a pmbus command. to begin power conversion, the en signal and/or operation command must be asserted high. following a fault that stops power conversion, the enable contol must be pulled low and then re-asserted high to resume power conversion. 7.4.2 operation with en signal control according to a bit value in the on_off_config register, the TPSM831D31 device can be commanded to use the en pin to enable or disable power conversion, regardless of the state of the operation command. the TPSM831D31 is factory programmed to use the en pin only. when the en pin is pulled low, power conversion stops immediately without first waiting for a turn-off delay or actively ramping down the output voltage. 7.4.3 operation with operation control according to a bit value in the on_off_config register, the TPSM831D31 device can be commanded to use the operation command to enable or disable conversion, regardless of the state of the en signal. 7.4.4 operation with en and operation control according to a bit value in the on_off_config register, the TPSM831D31 device can be commanded to require both the assertion of the en pin, and the operation command to enable or disable conversion. 7.5 programming 7.5.1 pmbus connections the TPSM831D31 device can support either 100-khz class, 400-khz class or 1-mhz class operation, with 1.8-v or 3.3-v logic levels. connection for the pmbus interface should follow the dc specifications given in section 4.3 of the system management bus (smbus) specification v3.0 . the complete smbus specification is available from the smbus website, smbus.org . 7.5.2 pmbus address selection the pmbus slave address is set by the voltage on the addr pin and is selected with a resistor from the addr pin to gnd. refer to table 5 . note that TPSM831D31 uses 7 bit addressing, per the smbus specification. users communicating to the device using generic i 2 c drivers should be aware that these 7 bits occupy the most significant bits of the first byte in each transaction, with the least significant bit being the data direction bit (0 for write operations, 1 for read operations). that is, for read transactions, the address byte is a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 and for write operations the address byte is a 6 a 5 a 4 a 3 a 2 a 1 a 0 0. refer to the smbus specification for more information. table 5. pmbus slave address selection v addr (v) pmbus address (7 bit binary) a 6 a 5 a 4 a 3 a 2 a 1 a 0 pmbus address (7 bit decimal) r addrl (k ) i 2 c address byte (write operation) i 2 c address byte (read operation) 0.039 v 1011000b 88d 0 b0h b1h 0.073 v 15 mv 1011001b 89d 0.453 b2h b3h 0.122 v 15 mv 1011010b 90d 0.768 b4h b5h 0.171 v 15 mv 1011011b 91d 1.13 b6h b7h 0.219 v 15 mv 1011100b 92d 1.47 b8h b9h 0.268 v 15 mv 1011101b 93d 1.87 bah bbh 0.317 v 15 mv 1011110b 94d 2.32 bch bdh 0.366 v 15 mv 1011111b 95d 2.74 beh bfh 0.415 v 15 mv 1100000b 96d 3.24 c0h c1h 0.464 v 15 mv 1100001b 97d 3.74 c2h c3h advance information
18 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 5. pmbus slave address selection (continued) v addr (v) pmbus address (7 bit binary) a 6 a 5 a 4 a 3 a 2 a 1 a 0 pmbus address (7 bit decimal) r addrl (k ) i 2 c address byte (write operation) i 2 c address byte (read operation) 0.513 v 15 mv 1100010b 98d 4.32 c4h c5h 0.562 v 15 mv 1100011b 99d 4.99 c6h c7h 0.610 v 15 mv 1100100b 100d 5.62 c8h c9h 0.660 v 15 mv 1100101b 101d 6.34 cah cbh 0.708 v 15 mv 1100110b 102d 7.15 cch cdh 0.757 v 15 mv 1100111b 103d 8.06 ceh cfh 0.806 v 15 mv 1101000b 104d 9.09 d0h d1h 0.854 v 15 mv 1101001b 105d 10.0 d2h d3h 0.903 v 15 mv 1101010b 106d 11.3 d4h d5h 0.952 v 15 mv 1101011b 107d 12.7 d6h d7h 1.000 v 15 mv 1101100b 108d 14.3 d8h d9h 1.050 v 15 mv 1101101b 109d 16.2 dah dbh 1.098 v 15 mv 1101110b 110d 18.2 dch ddh 1.147 v 15 mv 1101111b 111d 20.5 deh dfh 1.196 v 15 mv 1110000b 112d 23.7 e0h e1h 1.245 v 15 mv 1110001b 113d 27.4 e2h e3h 1.294 v 15 mv 1110010b 114d 31.6 e4h e5h 1.343 v 15 mv 1110011b 115d 37.4 e6h e7h 1.392 v 15 mv 1110100b 116d 45.3 e8h e9h 1.440 v 15 mv 1110101b 117d 54.9 eah ebh 1.489 v 15 mv 1110110b 118d 69.8 ech edh 1.540 v 15 mv 1110111b 119d 95.3 eeh efh advance information
19 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) nvm-backed bits in the mfr_specific or user_data commands affect the reset value of these commands. refer to the individual register maps for more detail. 7.5.3 supported commands the table below summarizes the pmbus commands supported by the TPSM831D31. only selected commands, which are most commonly used during device configuration and usage are reproduced in this document. for a full set of register maps for this device, refer to the accompanying technical reference manual . cmd command name description r/w, nvm default behavior default value ch. a page 0 ch. b page 1 00h page selects which channel subsequent pmbus commands address rw all commands address channel a n/a 01h operation enable or disable each channel, enter or exit margin. rw conversion disabled. margin none. 00h 00h 02h on_off_config configure the combination of operation, and enable pin required to enable power conversion for each channel. rw, nvm avr_en/ben pins only. 17h 17h 03h clear_fault clears all fault status registers to 00h and releases pmb_alert w write-only n/a 04h phase selects which phase of the active channel subsequent pmbus commands address rw commands address all phases. ffh ffh 10h write_protect used to control writing to the volatile operating memory (pmbus and restore from nvm). rw writes to all commands are allowed 00h 11h store_default_all stores all current storable register settings into nvm as new defaults. w write-only n/a 12h restore_default_all restores all storable register settings from nvm. w write-only n/a 19h capability provides a way for a host system to determine key pmbus capabilities of the device. r 1 mhz, pec, pmb_alert supported d0h 1bh smbalert_mask (status_vout) selects which faults/status bits may to assert pmb_alert rw, nvm all bits may assert pmb_alert 00h 00h 1bh smbalert_mask (status_iout) selects which faults/status bits may to assert pmb_alert rw, nvm all bits may assert pmb_alert 00h 00h 1bh smbalert_mask (status_input) selects which faults/status bits may to assert pmb_alert rw, nvm low_vin does not assert pmb_alert 08h 08h 1bh smbalert_mask (status_temperature) selects which faults/status bits may to assert pmb_alert rw, nvm all bits may assert pmb_alert 00h 00h 1bh smbalert_mask (status_cml) selects which faults/status bits may to assert pmb_alert rw, nvm all bits may assert pmb_alert 00h 00h 1bh smbalert_mask (status_mfr_specific) selects which faults/status bits may to assert pmb_alert rw, nvm all bits may assert pmb_alert 00h 00h 20h vout_mode read-only output mode indicator r (1) vid mode. 5 mv step (ch a), 5 mv step (ch b) 27h 27h 21h vout_command output voltage target rw, nvm 0.500 v (ch a) 0.500 v (ch b) 0033h 0033h 24h vout_max sets the maximum output voltage rw, nvm 1.520 v (ch a) 1.520 v (ch b) 00ffh 00ffh 25h vout_margin_high load the unit with the voltage to which the output is to be changed when operation command is set to ? margin high ? . rw 0.000 v (ch a) 0.000 v (ch b) 0000h 0000h 26h vout_margin_low load the unit with the voltage to which the output is to be changed when operation command is set to ? margin low ? . rw 0.000 v (ch a) 0.000 v (ch b) 0000h 0000h advance information
20 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated cmd command name description r/w, nvm default behavior default value ch. a page 0 ch. b page 1 27h vout_transition_rate used to set slew rate settings for output voltage updates rw, nvm 2.5 mv/ s (ch a) 2.5 mv/ s (ch b) e028h e028h 28h vout_droop the vout_droop sets the rate, in mv/a (m ) at which the output voltage decreases (or increases) with increasing (or decreasing) output current for use with adaptive voltage positioning rw, nvm 0.000 m (ch a) 0.000 m (ch b) d000h d000h 29h vout_scale_loop used for scaling the vid code rw, nvm 1.000 (ch a) 1.000 (ch b) e808h e808h 2ah vout_scale_monitor used for scaling output voltage telemetry rw, nvm 1.000 (ch a) 1.000 (ch b) e808h e808h 2bh vout_min sets the minimum output voltage rw, nvm 0.000 v (ch a) 0.000 v (ch b) 0000h 0000h 33h frequency_switch sets the switching frequency rw, nvm 400 khz (ch a) 400 khz (ch b) 0190h 0190h 35h vin_on sets value of input voltage at which the device should start power conversion. rw, nvm 7.25 v f01dh 38h iout_cal_gain sets the ratio of voltage at the current sense pins to the sensed current. rw, nvm 5.0625 m (ch a) 5.0625 m (ch b) d144h d144h 39h iout_cal_offset used to null offsets in the output current sensing circuit rw, nvm 0.000 a (ch a) 0.000 a (ch b) (all phases) e800h e800h 40h vout_ov_fault_limit sets the value of the sensed output voltage which triggers an output overvoltage fault r 1.520 v (ch a) 1.520 v (ch b) 00ffh 00ffh 41h vout_ov_fault_response sets the converter response to an output overvoltage event r shutdown, do not restart 80h 80h 44h vout_uv_fault_limit sets the value of the sensed output voltage which triggers an output undervoltage fault r 0.000 v (ch a) 0.000 v (ch b) 0000h 0000h 45h vout_uv_fault_response sets the converter response to an output undervoltage event rw, nvm shutdown, do not restart 80h 80h 46h iout_oc_fault_limit sets the output overcurrent fault limit, in amperes rw, nvm (1) 180 a (ch a) 60 a (ch b) 00b4h 003ch 47h iout_oc_fault_response defines the overcurrent fault response rw, nvm shutdown, do not restart c0h c0h 4ah iout_oc_warn_limit sets the output overcurrent warning limit, in amperes rw, nvm (1) 120 a (ch a) 40 a (ch b) 0078h 0028h 4fh ot_fault_limit sets the output overtemperature fault limit, in degrees celsius. rw, nvm (1) 135 c (ch a) 135 c (ch b) 0087h 0087h 50h ot_fault_response defines the overtemperature fault response rw, nvm shutdown, do not restart 80h 80h 51h ot_warn_limit sets the output overtemperature warning limit, in degrees celsius. rw 105 c (ch a) 105 c (ch b) 0069h 0069h 55h vin_ov_fault_limit sets the vin overvoltage fault limit, in volts rw, nvm 17.000 v 0011h 56h vin_ov_fault_response defines the vin overvoltage fault response r continue uninterrupted 00h 59h vin_uv_fault_limit sets the vin undervoltage fault limit, in volts rw, nvm 6.500 v f80dh 5ah vin_uv_fault_response defines the vin undervoltage fault response r shutdown, do not restart c0h 5bh iin_oc_fault_limit sets the input current overcurrent fault limit, in amperes rw, nvm 40.0 a f850h 5ch iin_oc_fault_response defines the input overcurrent fault response r shutdown, do not restart c0h 5dh iin_oc_warn_limit sets the input current overcurrent warning limit, in amperes rw, nvm 32.0 a f840h advance information
21 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated cmd command name description r/w, nvm default behavior default value ch. a page 0 ch. b page 1 60h ton_delay sets the time, in milliseconds, from when a start condition is received (as programmed by the on_off_config command) until the output voltage starts to rise rw, nvm 0.480 ms (ch a) 0.896 ms (ch b) b1ech b396h 6bh pin_op_warn_limit the pin_op_warn_limit command sets the value of the input power, in watts, that causes a warning that the input power is high rw 450 w 08e1h 78h status_byte pmbus read-only status and flag bits. rw current status n/a n/a 79h status_word pmbus read-only status and flag bits. rw current status n/a n/a 7ah status_vout pmbus read-only status and flag bits. rw current status n/a n/a 7bh status_iout pmbus read-only status and flag bits. rw current status n/a n/a 7ch status_input pmbus read-only status and flag bits. rw current status n/a 7dh status_temperature pmbus read-only status and flag bits. rw current status n/a n/a 7eh status_cml pmbus read-only status and flag bits. rw current status n/a 80h status_mfr_specific pmbus read-only status and flag bits. rw current status n/a n/a 88h read_vin returns the input voltage in volts r current status n/a 89h read_iin returns the input current in amperes r current status n/a 8bh read_vout returns the output voltage in vid format r current status n/a n/a 8ch read_iout returns the output current in amperes r current status n/a n/a 8dh read_temperature_1 returns the highest power stage temperature in c r current status n/a n/a 96h read_pout returns the output power in watts r current status n/a n/a 97h read_pin returns the input power in watts r current status n/a 98h pmbus_revision returns the version of the pmbus specification to which this device complies r pmbus 1.3 part i, part ii 33h 99h mfr_id loads the unit with bits that contain the manufacturer ? s id rw, nvm ti 5449h 9ah mfr_model loads the unit with bits that contain the manufacturer ? s model number rw, nvm 3+1 phase configuration 4331h 9bh mfr_revision loads the unit with bits that contain the manufacturer ? s model revision rw, nvm rev 1.0 0001h 9dh mfr_date loads the unit with bits that contain the manufacture date rw, nvm july 2018 1207h 9eh mfr_serial nvm checksum r nvm checksum 679e8b7dh adh ic_device_id returns a number indicating the part number of the device r TPSM831D31 81h aeh ic_device_rev returns a number indicating the device revision r rev 1.0 00h b0h user_data_00 used for batch nvm programming. rw nvm current configuration factory default settings b1h user_data_01 used for batch nvm programming. rw nvm current configuration factory default settings b2h user_data_02 used for batch nvm programming. rw nvm current configuration factory default settings b3h user_data_03 used for batch nvm programming. rw nvm current configuration factory default settings b4h user_data_04 used for batch nvm programming. rw nvm current configuration factory default settings b5h user_data_05 used for batch nvm programming. rw nvm current configuration factory default settings b6h user_data_06 used for batch nvm programming. rw nvm current configuration factory default settings advance information
22 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated cmd command name description r/w, nvm default behavior default value ch. a page 0 ch. b page 1 b7h user_data_07 used for batch nvm programming. rw nvm current configuration factory default settings b8h user_data_08 used for batch nvm programming. rw nvm current configuration factory default settings b9h user_data_09 used for batch nvm programming. rw nvm current configuration factory default settings bah user_data_10 used for batch nvm programming. rw nvm current configuration factory default settings bbh user_data_11 used for batch nvm programming. rw nvm current configuration factory default settings bch user_data_12 used for batch nvm programming. rw nvm current configuration factory default settings d0h mfr_specific_00 configures per-phase overcurrent levels, current share thresholds, and other miscellaneous settings. rw nvm misc. configuration, see register maps 003eh 203dh d3h mfr_specific_03 returns information regarding current imbalance warnings for each phase r current status n/a n/a d4h mfr_specific_04 returns the output voltage for the active channel, in linear format r current status n/a n/a d5h mfr_specific_05 used to trim the output voltage of the active channel, by applying an offset to the currently selected vid code. rw nvm 1.25 mv offset (ch a and ch b) 01h 01h d6h mfr_specific_06 configures dynamic load line options for both channels, and selects auto-dcm operation. rw nvm misc. configuration, see register maps 0605h 1000h d7h mfr_specific_07 configures the internal loop compensation for both channels. rw nvm misc. configuration, see to register maps 0946h 01c6h d8h mfr_specific_08 used to identify catastrophic faults which occur first, and store this information to nvm rw nvm current status 00h 00h d9h mfr_specific_09 used to configure non-linear transient performance enhancements such as undershoot reduction (usr) rw nvm misc. configuration, see register maps 46c5h 06c7h dah mfr_specific_10 used to configure input current sensing, and set the maximum output current rw nvm misc. configuration, see register maps c878h 0028h dbh mfr_specific_11 boot-up vid code for each channel rw nvm vid 051d (ch a) vid 051d (ch b) 33h 33h dch mfr_specific_12 used to configure input current sensing and other miscellaneous settings rw nvm misc. configuration, see register maps c570h 07f0 ddh mfr_specific_13 used to configure output voltage slew rates, dac stepsize, and other miscellaneous settings. rw nvm misc. configuration, see register maps 9ce5h 00e5h deh mfr_specific_14 used to configure dynamic phase shedding, and compensation ramp amplitude, and dynamic ramp amplitude during usr, and different power states rw nvm misc. configuration, see register maps 0007h 0007h dfh mfr_specific_15 used to configure dynamic phase shedding. rw nvm misc. configuration, see register maps 1ffah 0000h e4h mfr_specific_20 used to set the maximum operational phase number, on-the-fly. rw nvm misc. configuration, see register maps hardware configured f0h mfr_specific_32 used to set the input over-power warning rw 450 w 00e1h fah mfr_specific_42 nvm security rw nvm nvm security key 0000h advance information
23 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.4 commonly used pmbus commands the following sections describe the most commonly used pmbus commands and their usage in the configuration, operation and testing of TPSM831D31 power solutions: ? voltage, current, power, and temperature readings ? output current sense and calibration ? output voltage margin testing ? loop compensation ? converter protection and response ? dynamic phase shedding ? nvm programming ? nvm security ? black box fault recording ? board identification and inventory tracking ? status reporting 7.5.5 voltage, current, power, and temperature readings using an internal adc, the TPSM831D31 provides a full set of telemetry capabilities, allowing the user to read back critical information about the converter's input voltage, input current, input power, output voltage, output current, output power and temperature. the table below summarizes the available commands and their formats. register maps for each command are included. table 6. telemetry functions command description format units channel/phase read_vin input voltage telemetry linear v shared, channel a and b read_iin input current telemetry linear a shared, channel a and b read_vout output voltage telemetry (vid format) vid vid code per channel read_iout output current telemetry linear a per channel and per phase read_temperature_1 power stage temperature telemetry linear c per channel, highest phase temperature only read_pout output power telemetry linear w per channel read_pin input power telemetry linear w shared, channel a and b mfr_specific_04 output voltage telemetry (linear format) linear v per channel 7.5.5.1 (88h) read_vin the read_vin command returns the input voltage in volts. the two data bytes are formatted in the linear data format. the refresh rate is 1200 s. this command should be accessed through read word transactions, and is shared between channel a and channel b. 15 14 13 12 11 10 9 8 r r r r r r r r read_vin_exp read_vin_man 7 6 5 4 3 2 1 0 r r r r r r r r read_vin_man legend: r/w = read/write; r = read only advance information
24 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated read_vin table 7. read_vin register field descriptions bit field type reset description 15:11 read_vin_exp r current status linear two's complement format exponent. 10:0 read_vin_man r current status linear two's complement format mantissa. 7.5.5.2 (89h) read_iin the read_iin command returns the input current in amperes. the refresh rate is 100 s. the two data bytes are formatted in the linear data format. this command should be accessed through read word transactions, and is shared between channel a and channel b. 15 14 13 12 11 10 9 8 r r r r r r r r read_iin_exp read_iin_man 7 6 5 4 3 2 1 0 r r r r r r r r read_iin_man legend: r/w = read/write; r = read only read_iin table 8. read_iin register field descriptions bit field type reset description 15:11 read_iin_exp r current status linear two's complement format exponent. 10:0 read_iin_man r current status linear two's complement format mantissa. 7.5.5.3 (8bh) read_vout the read_vout command returns the actual, measured output voltage. the two data bytes are formatted in the vid data format, and the refresh rate is 1200 us. this command should be accessed through read word transactions. read_vout is a paged register. in order to access read_vout command for channel a, page must be set to 00h. in order to access read_vout register for channel b, page must be set to 01h. 15 14 13 12 11 10 9 8 r r r r r r r r 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r r r r r r r r read_vout_vid legend: r/w = read/write; r = read only read_vout table 9. read_vout register field descriptions bit field type reset description 7:0 read_vout_vid r current status output voltage, vid format advance information
25 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.5.4 (8ch) read_iout the read_iout command returns the output current in amperes. read_iout is a linear format command. read_iout is a paged register. in order to access read_iout for channel a, page must be set to 00h. in order to access the read_iout register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. read_iout is also a phased register. depending on the configuration of the design, for channel a, phase must be set to 00h to access phase 1, 01h to access phase 2, etc... phase must be set to ffh to access all phases simultaneously. phase may also be set to 80h to readack the total phase current (sum of all active phase currents for the active channel) measurement, as described in output current sense and calibration . note that read_iout is only a phased command for channel a (page 0). the read_iout command must be accessed through read word transactions. 15 14 13 12 11 10 9 8 r r r r r r r r read_iout_exp read_iout_man 7 6 5 4 3 2 1 0 r r r r r r r r read_iout_man legend: r/w = read/write; r = read only read_iout table 10. read_iout register field descriptions bit field type reset description 15:11 read_iout_exp r current status linear two's complement format exponent. 10:0 read_iout_man r current status linear two's complement format mantissa. attempts to write to this command results in invalid transactions. the device ignores the invalid data, sets the appropriate flags in status_cml and status_word, and asserts the pmb_alert signal to notify the system host of an invalid transaction. 7.5.5.5 (8dh) read_temperature_1 the read_temperature_1 command returns the temperature in degree celsius. the two data bytes are formatted in the linear data format. the refresh rate is 1200 s. read_temperature_1 is a linear format command. read_temperature_1 is a paged register. in order to access operation command for channel a, read_temperature_1 must be set to 00h. in order to access read_temperature_1 register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. the read_temperature_1 command must be accessed through read word transactions. 15 14 13 12 11 10 9 8 r r r r r r r r read_temp_exp read_temp_man 7 6 5 4 3 2 1 0 r r r r r r r r read_temp_man legend: r/w = read/write; r = read only advance information
26 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated read_temperature_1 table 11. read_temperature_1 register field descriptions bit field type reset description 15:11 read_temp_exp r current status linear two's complement format exponent. 10:0 read_temp_man r current status linear two's complement format mantissa. attempts to write to this command results in invalid transactions. the device ignores the invalid data, sets the appropriate flags in status_cml and status_word, and asserts the pmb_alert signal to notify the system host of an invalid transaction 7.5.5.6 (96h) read_pout the read_pout command returns the calculated output power, in watts for the active channel. the refresh rate is 1200 s. read_pout is a linear format command. read_pout is a paged register. in order to access read_pout command for channel a, page must be set to 00h. in order to access read_pout register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. the read_pout command must be accessed through read word transactions. 15 14 13 12 11 10 9 8 r r r r r r r r read_pout_exp read_pout_man 7 6 5 4 3 2 1 0 r r r r r r r r read_pout_man legend: r/w = read/write; r = read only read_pout table 12. read_pout register field descriptions bit field type reset description 15:11 read_pout_exp r current status linear two's complement format exponent. 10:0 read_pout_man r current status linear two's complement format mantissa. attempts to write to this command results in invalid transactions. the device ignores the invalid data, sets the appropriate flags in status_cml and status_word, and asserts the pmb_alert signal to notify the system host of an invalid transaction 7.5.5.7 (97h) read_pin the read_pin command returns the calculated input power. the refresh rate is 1200 s. read_pin is a linear format command. the read_pin command must be accessed through read word transactions. the read_pin command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. advance information
27 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 15 14 13 12 11 10 9 8 r r r r r r r r read_pin_exp read_pin_man 7 6 5 4 3 2 1 0 r r r r r r r r read_pin_man legend: r/w = read/write; r = read only read_pin table 13. read_pin register field descriptions bit field type reset description 15:11 read_pin_exp r current status linear two's complement format exponent. 10:0 read_pin_man r current status linear two's complement format mantissa. 7.5.5.8 (d4h) mfr_specific_04 the mfr_specific_04 command is used to return the output voltage for the active channel, in the linear format (read_vout uses vid format). the mfr_specific_04 command must be accessed through read word transactions. mfr_specific_04 is a linear format command. mfr_specific_04 is a paged register. in order to access mfr_specific_04 command for channel a, page must be set to 00h. in order to access the mfr_specific_04 register for channel b, page must be set to 01h. 15 14 13 12 11 10 9 8 r r r r r r r r vout_lin_exp vout_lin_man 7 6 5 4 3 2 1 0 r r r r r r r r vout_lin_man legend: r/w = read/write; r = read only mfr_specific_04 table 14. mfr_specific_04 register field descriptions bit field type reset description 15:11 vout_lin_exp r current status linear format two's complement exponent. 10:0 vout_lin_man r current status linear format two's complement mantissa. advance information
28 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.6 output current sense and calibration the read_iout command may be used to read the individual phase currents, and the total channel current. 7.5.6.1 reading individual phase currents using the page and phase commands, the TPSM831D31 can be configured to return output current information for each individual phase. the examples below demonstrate this process: example #1: read back the output current of channel a, first phase 1. select channel a. write page to 00h 2. select first phase. write phase to 00h 3. read read_iout example #2: read back the output current of channel b, second phase 1. select channel b. write page to 01h 2. select second phase. write phase to 01h 3. read read_iout 7.5.6.1.1 reading total current when the phase command is set to 80h, the TPSM831D31 device is configured to return the total channel current (sum of individual phase currents) in response to the read_iout command. example: read the total output current of channel a 1. select channel a. write page to 00h 2. select total current measurement. write phase to 80h 3. read read_iout advance information
29 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.7 output voltage margin testing the TPSM831D31 provides several commands to enable voltage margin testing. the upper two margin bits in the operation command can be used to toggle the active channel between three states: 1. margin none (margin = 0000b). the output voltage target is equal to vout_command. 2. margin low (margin = 01xxb). the output voltage target is equal to vout_margin_low. 3. margin high (margin = 10xxb). the output voltage target is equal to vout_margin_high. in order to use operation, the active channel must be configured for to respect the operation command, via on_off_config. output voltage transitions will occur at the slew rate defined by vout_transition_rate. table 15. slew rate settings parameter test conditions min typ max unit sl set slew rate setting vout_transition_rate = 0xe050 5 6 7 mv/ s vout_transition_rate = 0xe0a0 10 12 14 mv/ s vout_transition_rate = 0xe0f0 15 18 mv/ s vout_transition_rate = 0xe140 20 24 mv/ s vout_transition_rate = 0xe190 25 30 mv/ s vout_transition_rate = 0xe1e0 30 36 mv/ s vout_transition_rate = 0xe230 35 42 mv/ s vout_transition_rate = 0xe280 40 48 mv/ s vout_transition_rate = 0xe005 0.3125 mv/ s vout_transition_rate = 0xe00a 0.625 mv/ s vout_transition_rate = 0xe00f 0.9375 mv/ s vout_transition_rate = 0xe014 1.25 mv/ s vout_transition_rate = 0xe019 1.5625 mv/ s vout_transition_rate = 0xe01e 1.875 mv/ s vout_transition_rate = 0xe023 2.1875 mv/ s vout_transition_rate = 0xe028 2.5 mv/ s vout_transition_rate = others invalid data mv/ s sl f avsp and bvsp slew rate setvid_fast sl set mv/ s sl s1 avsp and bvsp slew rate slow sl set / 4 mv/ s sl set / 2 mv/ s sl ss avsp and bvsp slew rate slew rate soft-start mfr_spec_13 < 8 > = 0b sl set / 4 mv/ s mfr_spec_13 < 8 > = 1b sl set / 16 mv/ s the lower two margin bits in the operation command select overvoltage/undervoltage fault handling during margin testing: 1. ignore faults (margin = xx01b) . overvoltage/undervoltage faults will not trigger during margin tests. 2. act on faults (margin = xx10b). overvoltage/undervoltage faults will trigger during margin tests. example: output voltage margin testing (ignore faults) 1. write to the page command to select the desired channel (e.g. page = 00h for channel a). 2. write vout_command to the desired vid code during margin none operation. 3. write vout_margin_low to the desired vid code during margin low operation. 4. write vout_margin_high to the desired vid code during margin high operation. 5. write mfr_specific_02 to 01h to ensure that the pmbus interface has control of the output voltage. 6. set the cmd bit in operation to 1b to ensure the device is configured to respect the operation command. 7. margin none. write operation to 80h. advance information
30 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 8. margin low. write operation to 94h. 9. margin high. write operation to a4h. 7.5.7.1 (01h) operation the operation command is used to turn the device output on or off in conjunction with the input from the avr_en pin for channel a, and ben pin for channel b, acc ording to the configuration of the on_off_config command. it is also used to set the output voltage to the upper or lower margin levels. operation is a paged register. in order to access operation command for channel a, page must be set to 00h. in order to access operation register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. the operation command must be accessed through read byte/write byte transactions. 7 6 5 4 3 2 1 0 rw r rw rw rw rw rw rw on 0 margin 0 0 legend: r/w = read/write; r = read only operation table 16. operation register field descriptions bit field type reset description 7 on rw 0b enable/disable power conversion for the currently selected channel(s) according to the page command, when the on_off_config command is configured to require input from the on bit for output control. note that there may be several other requirements that must be satisfied before the currently selected channel(s) can begin converting power (e.g. input voltages above uvlo thresholds, avr_en/ben pins high if required by on_off_config, etc...) 0b: disable power conversion 1b: enable power conversion 5:2 margin rw 0000b set the output voltage to either the value selected by the vout_margin_high or margin_low commands, for the currently selected channel(s), according to the page command. 0000b: margin off. output voltage is set to the value of vout_command 0101b: margin low (ignore fault). output voltage is set to the value of vout_margin_low. 0110b: margin low (act on fault). output voltage is set to the value of vout_margin_low. 1001b: margin high (ignore fault). output voltage is set to the value of vout_margin_high 1010b: margin high (act on fault). output voltage is set to the value of vout_margin_high. 1:0 0 rw 00b these bits are writeable but should always be set to 00b. note that the vout_max_warn bit in status_vout can be caused by a margin operation, if "act on fault" is selected, and the vout_margin_high/vout_margin_low value loaded by the margin operation exceeds the value of vout_command. 7.5.7.2 (26h) vout_margin_low the vout_margin_low command loads the unit with the voltage to which the output is to be changed when the operation command is set to ? margin low ? . vout_margin_low is a vid format command. the vout_margin_low command must be accessed through read word/write word transactions. advance information
31 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated vout_margin_low is a paged register. in order to access vout_margin_low for channel a, page must be set to 00h. in order to access the vout_margin_low register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. 15 14 13 12 11 10 9 8 r r r r r r r r 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw vout_margl_vid legend: r/w = read/write; r = read only vout_margin_low table 17. vout_margin_low register field descriptions bit field type reset description 7:0 vout_margl_vid rw 00h used to set the output voltage to be loaded when the active page is set to margin low, in vid format. 7.5.7.3 (25h) vout_margin_high the vout_margin_high command loads the unit with the voltage to which the output is to be changed when the operation command is set to ? margin high ? . vout_margin_high is a vid format command. the vout_margin_high command must be accessed through read word/write word transactions. vout_margin_high is a paged register. in order to access vout_margin_high for channel a, page must be set to 00h. in order to access the vout_margin_high register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. 15 14 13 12 11 10 9 8 r r r r r r r r 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw vout_margh_vid legend: r/w = read/write; r = read only vout_margin_high table 18. vout_margin_high register field descriptions bit field type reset description 7:0 vout_margh_vid rw 00h used to set the output voltage to be loaded when the active page is set to margin high, in vid format. advance information
32 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) specified by design. not production tested. 7.5.8 loop compensation the TPSM831D31 provides several options for tuning the output voltage feedback and response to transients. these may be configured by programming the mfr_specific_07 , vout_droop , and mfr_specific_14 . several such parameters may be configured through these commands: ? dc load line - selects the dc shift in output voltage corresponding to increased output current. the dc load line affects both the final value the output voltage settles to, as well as the settling time. use the vout_droop command to select the dc load line. ? integration time constant - in order to maintain dc accuracy, the control loop includes an integration stage. use mfr_specific_07 to select the integration time constant. ? integration path gain - the gain of the integration and ac paths may be selected independently. the ac and dc gains both affect the small-signal bandwidth of the converter. use mfr_specific_07 to select the integration path gain. ? ac load line - selects the ac response to output voltage error. the ac load line affects the settling and response time following a load transient event. mfr_specific_07 use the mfr_specific_07 command to select the ac load line. ? ac path gain - the gain of the integration and ac paths may be selected independently. the ac and dc gains both affect the small-signal bandwidth of the converter. use mfr_specific_07 to select the ac path gain. ? ramp amplitude - smaller ramp settings result in faster response, but may also lead to increased frequency jitter. likewise, large ramp settings result in lower frequency jitter, but may be slightly slower to respond to changing conditions. the ramp setting also affects the small-signal bandwidth of the converter. use mfr_specific_14 to select the ramp high setting. table 19. dynamic integration and undershoot reduction (t a = 25 c) parameter test conditions min typ max unit v dyn dynamic integration voltage setting mfr_spec_12 < 10:8 > = 000b; 90 100 116 mv mfr_spec_12 < 10:8 > = 001b; 135 150 175 mv mfr_spec_12 < 10:8 > = 010b; 175 200 230 mv mfr_spec_12 < 10:8 > = 011b; 225 250 285 mv mfr_spec_12 < 10:8 > = 100b; 270 300 345 mv mfr_spec_12 < 10:8 > = 101b; 315 350 400 mv mfr_spec_12 < 10:8 > = 110b; 360 400 455 mv mfr_spec_12 < 10:8 > = 111b; off mv t dint dynamic integration time constant (1) mfr_spec_12 < 7:4 > = 0000b; 1 s mfr_spec_12 < 7:4 > = 0001b; 2 s mfr_spec_12 < 7:4 > = 0010b; 3 s mfr_spec_12 < 7:4 > = 0011b; 4 s mfr_spec_12 < 7:4 > = 0100b; 5 s mfr_spec_12 < 7:4 > = 0101b; 6 s mfr_spec_12 < 7:4 > = 0110b; 7 s mfr_spec_12 < 7:4 > = 0111b; 8 s mfr_spec_12 < 7:4 > = 1000b; 12 s mfr_spec_12 < 7:4 > = 1001b; 13 s mfr_spec_12 < 7:4 > = 1010b; 14 s mfr_spec_12 < 7:4 > = 1011b; 15 s mfr_spec_12 < 7:4 > = 1100b; 16 s mfr_spec_12 < 7:4 > = 1101b; 17 s mfr_spec_12 < 7:4 > = 1110b; 18 s mfr_spec_12 < 7:4 > = 1111b; 19 s advance information
33 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 19. dynamic integration and undershoot reduction (t a = 25 c) (continued) parameter test conditions min typ max unit v usr2 usr level 2 voltage setting mfr_spec_09 < 14:12 > = 000b; 120 140 160 mv mfr_spec_09 < 14:12 > = 001b; 155 180 205 mv mfr_spec_09 < 14:12 > = 010b; 190 220 245 mv mfr_spec_09 < 14:12 > = 011b; 230 260 290 mv mfr_spec_09 < 14:12 > = 100b; 265 300 335 mv mfr_spec_09 < 14:12 > = 101b; 300 340 375 mv mfr_spec_09 < 14:12 > = 110b; 335 380 420 mv mfr_spec_09 < 14:12 > = 111b; off mv v usr1 usr level 1 voltage setting mfr_spec_09 < 2:0 > = 000b; 70 90 110 mv mfr_spec_09 < 2:0 > = 001b; 100 120 140 mv mfr_spec_09 < 2:0 > = 010b; 130 150 170 mv mfr_spec_09 < 2:0 > = 011b; 160 180 205 mv mfr_spec_09 < 2:0 > = 100b; 185 210 240 mv mfr_spec_09 < 2:0 > = 101b; 215 240 270 mv mfr_spec_09 < 2:0 > = 110b; 240 270 305 mv mfr_spec_09 < 2:0 > = 111b; off mv ph usr1 maximum phase added in usr level 1 (1) mfr_spec_09 < 5 > = 0b; 3 phases mfr_spec_09 < 5 > = 1b; 4 phases v ousrhys dynamic integration/usr voltage hysteresis mfr_spec_09 < 4:3 > = 00b; 2 5 9 mv mfr_spec_09 < 4:3 > = 01b; 5 10 15 mv mfr_spec_09 < 4:3 > = 10b; 10 15 20 mv mfr_spec_09 < 4:3 > = 11b; 15 20 25 mv table 20. ramp selections parameter test conditions min typ max unit v ramp ramp setting mfr_spec_14 < 2:0 > = 000b 30 40 55 mv mfr_spec_14 < 2:0 > = 001b 70 80 95 mv mfr_spec_14 < 2:0 > = 010b 110 120 135 mv mfr_spec_14 < 2:0 > = 011b 150 160 175 mv mfr_spec_14 < 2:0 > = 100b 190 200 215 mv mfr_spec_14 < 2:0 > = 101b 230 240 255 mv mfr_spec_14 < 2:0 > = 110b 270 280 300 mv mfr_spec_14 < 2:0 > = 111b 305 320 335 mv advance information
34 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.8.1 (d7h) mfr_specific_07 the mfr_specific_07 command is used to configure the internal loop compensation for both channels. the mfr_specific_07 command must be accessed through write word/read word transactions. mfr_specific_07 is a paged register. in order to access mfr_specific_07 command for channel a, page must be set to 00h. in order to access the mfr_specific_07 register for channel b, page must be set to 01h. 15 14 13 12 11 10 9 8 r r rw rw rw rw rw rw 0 0 int_gain int_tc 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw ac_gain acll legend: r/w = read/write; r = read only mfr_specific_07 table 21. mfr_specific_07 register field descriptions bit field type reset description 15:14 not used r 0 not used and set to 0. 13:12 int_gain rw nvm integration path gain. see table 22 . 11:8 int_tc rw nvm integration time constant. see table 23 . 7:6 ac_gain rw nvm ac path gain. see table 24 . 5:0 acll rw nvm ac load line. see table 25 . table 22. integration path gain settings int_gain (binary) integration path gain (v/v) 00b 2 ac_gain 01b 1 ac_gain 10b 0.66 ac_gain 11b 0.5 ac_gain table 23. integration time constant settings int_tc (binary) time constant ( s) 0000b 5 0001b 10 0010b 15 0011b 20 0100b 25 0101b 30 0110b 35 0111b 40 1000b 1 1001b 2 1010b 3 1011b 4 1100b 5 1101b 6 1110b 7 1111b 8 advance information
35 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 24. ac path gain settings ac_gain (binary) ac path gain (v/v) 00b 1 01b 1.5 10b 2 11b 0.5 table 25. ac load line settings bin acll (hex) ac load line (m ) bin acll (hex) ac load line (m ) 0 00h 0.0000 32 20h 1.6250 1 01h 0.1250 33 21h 1.7500 2 02h 0.2500 34 22h 1.8750 3 03h 0.3125 35 23h 1.9375 4 04h 0.3750 36 24h 2.000 5 05h 0.4375 37 25h 2.0625 6 06h 0.5000 38 26h 2.1250 7 07h 0.5625 39 27h 2.1875 8 08h 0.6250 40 28h 2.2500 9 09h 0.7500 41 29h 2.375 10 0ah 0.7969 42 2ah 2.4218 11 0bh 0.8125 43 2bh 2.4375 12 0ch 0.8281 44 2ch 2.4531 13 0dh 0.8438 45 2dh 2.4687 14 0eh 0.8594 46 2eh 2.4843 15 0fh 0.8750 47 2fh 2.5000 16 10h 0.8906 48 30h 2.5156 17 11h 0.9063 49 31h 2.5312 18 12h 0.9219 50 32h 2.5468 19 13h 0.9375 51 33h 2.5625 20 14h 0.9531 52 34h 2.5781 21 15h 0.9688 53 35h 2.5937 22 16h 0.9844 54 36h 2.609 23 17h 1.000 55 37h 2.625 24 18h 1.0156 56 38h 2.6406 25 19h 1.0313 57 39h 2.6562 26 1ah 1.0469 58 3ah 2.6718 27 1bh 1.0625 59 3bh 2.6875 28 1ch 1.1250 60 3ch 2.750 29 1dh 1.2500 61 3dh 2.875 30 1eh 1.3750 62 3eh 3.000 31 1fh 1.5000 63 3fh 3.125 advance information
36 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.8.2 (28h) vout_droop the vout_droop command sets the rate, in mv/a (m ) at which the output voltage decreases (or increases) with increasing (or decreasing) output current for use with adaptive voltage positioning. this is also referred to as the dc load line (dcll). vout_droop is a linear format command. the vout_droop command must be accessed through read word/write word transactions. vout_droop is a paged register. in order to access vout_droop for channel a, page must be set to 00h. in order to access the vout_droop register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. 15 14 13 12 11 10 9 8 r r r r r rw rw rw vdroop_exp vdroop_man 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw vdroop_man legend: r/w = read/write; r = read only vout_droop table 26. vout_droop register field descriptions bit field type reset description 15:11 vdroop_exp r 11010b linear two's complement fixed exponent, ? 6. lsb = 0.015625 m 10:0 vdroop_man rw nvm linear two's complement mantissa. see table of acceptable values below, note that channel a and channel b support different acceptable values of vout_droop. the table below summarizes the acceptable values of vout_droop for channel a and channel b. attempts to write any value other than those specified below will be treated as invalid data - invalid data will be ignored, the appropriate flags in status_cml and status_word will be set, and the pmb_alert will be asserted to notify the system host of an invalid transaction. table 27. acceptable vout_droop values bin vout_droop (hex) supported by channel a supported by channel b dc load line (m ) 0 d000h yes yes 0 1 d008h yes yes 0.125 2 d010h yes yes 0.25 3 d014h yes yes 0.3125 4 d018h yes yes 0.375 5 d01ch yes yes 0.4375 6 d020h yes yes 0.5 7 d024h yes yes 0.5625 8 d028h yes yes 0.625 9 d030h yes yes 0.7031 10 d033h yes yes 0.7969 11 d034h yes yes 0.8125 12 d035h yes yes 0.8281 13 d036h yes yes 0.8438 14 d037h yes yes 0.8594 15 d038h yes yes 0.875 16 d039h yes no 0.8906 advance information
37 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 27. acceptable vout_droop values (continued) bin vout_droop (hex) supported by channel a supported by channel b dc load line (m ) 17 d03ah yes no 0.9063 18 d03bh yes no 0.9219 19 d03ch yes no 0.9375 20 d03dh yes no 0.9531 21 d03eh yes no 0.9688 22 d03fh yes no 0.9844 23 d040h yes no 1 24 d041h yes no 1.0156 25 d042h yes no 1.0313 26 d043h yes no 1.0469 27 d044h yes no 1.0625 28 d048h yes no 1.125 29 d050h yes no 1.25 30 d058h yes no 1.375 31 d060h yes no 1.5 32 d068h yes no 1.625 33 d070h yes no 1.75 34 d078h yes no 1.875 35 d07ch yes no 1.9375 36 d080h yes no 2 37 d084h yes no 2.0625 38 d088h yes no 2.125 39 d08ch yes no 2.1875 40 d090h yes no 2.25 41 d098h yes no 2.328 42 d09bh yes no 2.4218 43 d09ch yes no 2.4375 44 d09dh yes no 2.4531 45 d09eh yes no 2.4687 46 d09fh yes no 2.4843 47 d0a0h yes no 2.5 48 d0a1h yes no 2.5156 49 d0a2h yes no 2.5312 50 d0a3h yes no 2.5468 51 d0a4h yes no 2.5625 52 d0a5h yes no 2.5781 53 d0a6h yes no 2.5937 54 d0a7h yes no 2.609 55 d0a8h yes no 2.625 56 d0a9h yes no 2.6406 57 d0aah yes no 2.6562 58 d0abh yes no 2.6718 59 d0ach yes no 2.6875 60 d0b0h yes no 2.75 61 d0b8h yes no 2.875 62 d0c0h yes no 3 63 d0c8h yes no 3.125 advance information
38 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.9 converter protection and response the TPSM831D31 supports a variety of power supply protection features. the table below summarizes these protection features, and their related pmbus registers. see the following sections for more details. table 28. TPSM831D31 protection and response threshold response command name default value command name default value output voltage over-voltage protection vout_ov_fault_limit 1.520 v (ch a) 1.520 v (ch b) vout_ov_fault_response shutdown, do not restart maximum allowed output voltage vout_max 1.520 v (ch a) 1.520 v (ch b) refer to register description under-voltage protection vout_uv_fault_limit 0.000 v (ch a) 0.000 v (ch b) vout_uv_fault_response shutdown, do not restart minimum allowed output voltage vout_min 0.000 v (ch a) 0.000 v (ch b) refer to register description output current over-current protection iout_oc_fault_limit 180 a (ch a) 60 a (ch b) iout_oc_fault_response shutdown, do not restart over-current warning iout_oc_warn_limit 120 a (ch a) 40 a (ch b) n/a. warning only. input voltage turn-on threshold vin_on 7.25 v n/a over-voltage protection vin_ov_fault_limit 17.000 v vin_ov_fault_response continue uninterrupted under-voltage protection vin_uv_fault_limit 6.50 v vin_uv_fault_response shutdown, do not restart input current over-current protection iin_oc_fault_limit 40.0 a iin_oc_fault_response shutdown, do not restart over-current warning iin_oc_warn_limit 32.0 a n/a. warning only temperature over-temperature protection ot_fault_limit 135 c (ch a) 135 c (ch b) ot_fault_response shutdown, do not restart over-temperature warning ot_warn_limit 105 c (ch a) 105 c (ch b) n/a. warning only. advance information
39 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.10 output overvoltage protection and response the output overvoltage thresholds track the configured maximum output voltage, vout_max, with a fixed offset, and may be read back in vid format via the read-only vout_ov_fault_limit command. the converter response to an overvoltage fault is configured by the read-only vout_ov_fault_response command. 7.5.10.1 (40h) vout_ov_fault_limit the vout_ov_fault_limit is used to read back the value of the output voltage measured at the sense or output pins that causes an output overvoltage fault in vid format. vout_ov_fault_limit is a vid format command, and must be accessed through read word/write word transactions. vout_ov_fault_limit is a paged register. in order to access vout_ov_fault_limit for channel a, page must be set to 00h. in order to access the vout_ov_fault_limit register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. 15 14 13 12 11 10 9 8 r r r r r r r r 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r r r r r r r r vo_ovf_vid legend: r/w = read/write; r = read only vout_ov_fault_limit table 29. vout_ov_fault_limit register field descriptions bit field type reset description 7:0 vo_ovf_vid r see below. read-only overvoltage fault limit, in vid format. when the 5-mv dac mode vid table is selected via mfr_specific_13, the vout_ov_fault_limit register will be set to ffh. when the 10-mv dac mode vid table is enabled, the vout_ov_fault_limit is determined according to the value of vout_max, with a fixed offset applied. 7.5.10.2 (41h) vout_ov_fault_response the vout_ov_fault_response instructs the device on what action to take in response to an output overvoltage fault. the vout_ov_fault_response command must be accessed through read byte transactions. the vout_ov_fault_response command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. upon triggering the over-voltage fault, the controller is latched off, and the following actions are taken: ? set the vout_ov_fault bit in the status_byte ? set the vout bit in the status_word ? set the vout_ov_fault bit in the status_vout register ? the device notifies the host (asserts pmb_alert, if the corresponding mask bit in smbalert_mask is not set) 7 6 5 4 3 2 1 0 r r r r r r r r vo_ov_resp legend: r/w = read/write; r = read only vout_ov_fault_response advance information
40 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 30. vout_ov_fault_response register field descriptions bit field type reset description 7:0 vo_ov_resp r 80h 80h: latch-off and do not restart. to clear a shutdown event due to a fault event, the user must toggle the avr_en/ben pin and/or the on bit in operation, per the settings in on_off_config, or power cycle the bias power to the v3p3 pin of the controller device. 7.5.11 maximum allowed output voltage setting the vout_max command sets an upper limit on the output voltage that the unit may be commanded to, regardless of an other commands or combinations. the intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructive level. 7.5.11.1 (24h) vout_max the vout_max command sets an upper limit on the output voltage that the unit may be commanded to, regardless of an other commands or combinations. the intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructive level. vout_max is a vid format command, and must be accessed through read word/write word transactions. vout_max is a paged register. in order to access vout_max for channel a, page must be set to 00h. in order to access the vout_command register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. the device detects that an attempt has been made to program the output to a voltage greater than the value set by the vout_max command. attempts to program the output voltage greater than vout_max can include vout_command attempts, and margin events while the vout_margin_high/vout_margin_low values exceed the value of vout_max. these events will be treated warning conditions and not as fault conditions. if an attempt is made to program the output voltage higher than the limit set by the vout_max command, the device will respond as follows: ? the commanded output voltage will be clamped to vout_max, ? the other bit will be set in the status_byte, ? the vout bit will be set in the status_word, ? the vout_max warning bit will be set in the status_vout register, and ? the device notifies the host (asserts pmb_alert, if the corresponding mask bit in smbalert_mask is not set). this register should be programmed by the user depending upon the maximum output voltage the converter can support. 15 14 13 12 11 10 9 8 r r r r r r r r 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw vout_max_vid legend: r/w = read/write; r = read only vout_max table 31. vout_max register field descriptions bit field type reset description 7:0 vout_max_vid rw nvm used to set the maximum vout of the device in vid format. advance information
41 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.12 output undervoltage protection and response the output undervoltage protection threshold is configured based on commanded output voltage, vout_command, including the shift due to the dc load line, and a fixed offset. the undervoltage threshold may be read back in vid format via the read-only vout_uv_fault_limit command. the converter response to an overvoltage fault is configured by the read-only vout_uv_fault_response command. 7.5.12.1 (44h) vout_uv_fault_limit the vout_uv_fault_limit is used to read back the value of the output voltage measured at the sense or output pins that causes an output undervoltage fault in vid format. vout_uv_fault_limit is a vid format command, and must be accessed through read word transactions. vout_uv_fault_limit is a paged register. in order to access vout_uv_fault_limit for channel a, page must be set to 00h. in order to access the vout_uv_fault_limit register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. 15 14 13 12 11 10 9 8 r r r r r r r r 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r r r r r r r r vo_uvf_vid legend: r/w = read/write; r = read only vout_uv_fault_limit table 32. vout_uv_fault_limit register field descriptions bit field type reset description 7:0 vo_uvf_vid r see below. read-only undervoltage fault limit, in vid format. 7.5.12.2 (45h) vout_uv_fault_response the vout_uv_fault_response instructs the device on what action to take in response to an output undervoltage fault. upon triggering the undervoltage fault, the following actions are taken: ? set the other bit in the status_byte ? set the vout bit in the status_word ? set the vout_uv_fault bit in the status_vout register ? the device notifies the host (asserts pmb_alert, if the corresponding mask bit in smbalert_mask is not set) the vout_uv_fault_response command must be accessed through read byte/write byte transactions. the vout_uv_fault_response command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw vo_uv_resp legend: r/w = read/write; r = read only vout_uv_fault_response advance information
42 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 33. vout_uv_fault_response register field descriptions bit field type reset description 7:0 vo_uv_resp rw nvm 00h: ignore. the controller will set the appropriate status bits, and alert the host, but continue converting power. bah: shutdown and restart. the controller will shutdown the channel on which the fault occurred, and attempt to restart 20ms later. this will occur continuously until the condition causing the fault has disappeared, or the controller has been disabled. 80h: latch-off and do not restart. to clear a shutdown event due to a fault event, the user must toggle the avr_en/ben pin and/or the on bit in operation, per the settings in on_off_config, or power cycle the bias power to the v3p3 pin of the controller device. 7.5.13 minimum allowed output voltage setting the vout_min command sets a lower bound on the output voltage to which the unit can be commanded, regardless of any other commands or combinations. the intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructive level rather than to be the primary output under voltage protection. 7.5.13.1 (2bh) vout_min the vout_ min command sets a lower bound on the output voltage to which the unit can be commanded, regardless of any other commands or combinations. the intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructive level rather than to be the primary output under voltage protection. vout_min is a vid format command, and must be accessed through read word/write word transactions. vout_min is a paged register. in order to access vout_min for channel a, page must be set to 00h. in order to access the vout_min register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. if an attempt is made to program the output voltage lower than the limit set by this command, the device will respond as follows: ? the commanded output voltage will be clamped to vout_min ? the other bit will be set in the status_byte ? the vout bit will be set in the status_word ? the vout_max_min warning bit will be set in the status_vout register ? the device notifies the host (asserts pmb_alert, if the corresponding mask bit in smbalert_mask is not set). 15 14 13 12 11 10 9 8 r r r r r r r r 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw vout_min_vid legend: r/w = read/write; r = read only vout_min table 34. vout_min register field descriptions bit field type reset description 7:0 vout_min_vid rw nvm used to set a lower bound for output voltage programming for the active page, is set to in vid format. advance information
43 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.14 output overcurrent protection and response overcurrent thresholds are configured using the iout_oc_fault_limit . when the overcurrent fault threshold is reached, the converter will respond according to the settings in iout_oc_fault_response . the iout_oc_warn_limit may also be used to configure an information-only overcurrent warning, which triggers prior to an overcurrent fault. note, that the mfr_specific_00 command, not listed below, also contains settings for per-phase overcurrent limits. refer to the device technical reference manual for more information. 7.5.14.1 (46h) iout_oc_fault_limit the iout_oc_fault_limit command sets the value of the total output current, in amperes, that causes the over-current detector to indicate an over-current fault condition. the command has two data bytes and the data format is linear as shown in the table below. the units are amperes. iout_oc_fault_limit is a linear format command, and must be accessed through read word/write word transactions. iout_oc_fault_limit is a paged register. in order to access iout_oc_fault_limit command for channel a, page must be set to 00h. in order to access iout_oc_fault_limit register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. 15 14 13 12 11 10 9 8 r r r r r rw rw rw ioocf_exp ioocf_man 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw ioocf_man legend: r/w = read/write; r = read only iout_oc_fault_limit table 35. iout_oc_fault_limit register field descriptions bit field type reset description 15:11 ioocf_exp r 00000b linear two's complement exponent, 0. lsb = 1.0 a 10:0 ioocf_man rw see below. linear two's complement mantissa at power-on, or after a restore_default_all operation, the iout_oc_fault_limit command will be loaded with the value of iout_max 1.50. the iout_max bits for each channel are stored in mfr_specific_10 (page 0 for channel a, page 1 for channel b). iout_oc_fault_limit may be changed during operation, but returns to this value on reset. 7.5.14.2 (4ah) iout_oc_warn_limit the iout_oc_warn_limit command sets the value of the output current, in amperes, that causes the over- current detector to indicate an over-current warning condition. iout_oc_warn_limit is a linear format command, and must be accessed through read word/write word transactions. iout_oc_warn_limit is a paged register. in order to access iout_oc_warn_limit command for channel a, page must be set to 00h. in order to access iout_oc_warn_limit register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. upon triggering the overcurrent warning, the following actions are taken: ? set the other bit in the status_byte ? set the iout bit in the status_word ? set the iout over current warning bit in the status_iout register ? the device notifies the host (asserts pmb_alert, if the corresponding mask bit in smbalert_mask is not set) advance information
44 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 15 14 13 12 11 10 9 8 r r r r r rw rw rw ioocw_exp ioocw_man 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw ioocw_man legend: r/w = read/write; r = read only iout_oc_warn_limit table 36. iout_oc_warn_limit register field descriptions bit field type reset description 15:11 ioocw_exp r 00000b linear two's complement exponent, 0. lsb = 1.0 a 10:0 ioocw_man rw see below. linear two's complement mantissa. at power-on, or after a restore_default_all operation, the iout_oc_warn_limit command will be loaded with the value of iout_max. the iout_max bits for each channel are stored in mfr_specific_10 (page 0 for channel a, page 1 for channel b). iout_oc_warn_limit may be changed during operation, but will return to this value on reset. 7.5.14.3 (47h) iout_oc_fault_response the iout_oc_fault_response instructs the device on what action to take in response to an output over- current fault. the iout_oc_fault_response command must be accessed through read byte/write byte transactions. the iout_oc_fault_response command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. note iout_oc_warn_limit maximum default value is 180a for vouta and 60a for voutb. if an application maximum load current is less than 180a, iout_oc_warn_limit needs to change as the default max load current value is restored each time after power-on or restore_default_all operation. upon triggering the over-current fault, the controller is latched off, and the following actions are taken: ? set the iout_oc_fault bit in the status_byte ? set the iout bit in the status_word ? set the iout_oc_fault bit in the status_iout register ? the device notifies the host (asserts pmb_alert, if the corresponding mask bit in smbalert_mask is not set) 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw io_oc_resp legend: r/w = read/write; r = read only iout_oc_fault_response advance information
45 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 37. iout_oc_fault_response register field descriptions bit field type reset description 7:0 io_oc_resp rw nvm c0h: latch-off and do not restart. to clear a shutdown event due to a fault event, the user must toggle the avr_en/ben pin and/or the on bit in operation, per the settings in on_off_config, or power cycle the bias power to the v3p3 pin of the controller device. fah: shutdown and restart. the controller will shutdown the channel on which the fault occurred, and attempt to restart 20ms later. this will occur continuously until the condition causing the fault has disappeared, or the controller has been disabled. 7.5.14.4 per phase overcurrent limit thresholds table 38. ocl parameter test conditions min typ max unit i oclax phase ocl levels for channel a (acspx-vref), valley current limit mfr_spec_00 < 3:0 > , (page0) = 0000b 12.5 14.5 16.5 a mfr_spec_00 < 3:0 > , (page0) = 0001b 16.5 18.5 20.5 a mfr_spec_00 < 3:0 > , (page0) = 0010b 20.5 22.5 24.5 a mfr_spec_00 < 3:0 > , (page0) = 0011b 24.5 26.5 28.5 a mfr_spec_00 < 3:0 > , (page0) = 0100b 28.5 30.5 32.5 a mfr_spec_00 < 3:0 > , (page0) = 0101b 32.5 34.5 36.5 a mfr_spec_00 < 3:0 > , (page0) = 0110b 36.5 38.5 40.5 a mfr_spec_00 < 3:0 > , (page0) = 0111b 40.5 42.5 44.5 a mfr_spec_00 < 3:0 > , (page0) = 1000b 44.5 46.5 48.5 a mfr_spec_00 < 3:0 > , (page0) = 1001b 48.5 50.5 52.5 a mfr_spec_00 < 3:0 > , (page0) = 1010b 52.5 54.5 56.5 a mfr_spec_00 < 3:0 > , (page0) = 1011b 56.5 58.5 60.5 a mfr_spec_00 < 3:0 > , (page0) = 1100b 60.5 62.5 64.5 a mfr_spec_00 < 3:0 > , (page0) = 1101b 64.5 66.5 68.5 a mfr_spec_00 < 3:0 > , (page0) = 1110b 68.5 70.5 72.5 a mfr_spec_00 < 3:0 > , (page0) = 1111b 72.5 74.5 76.5 a i oclbx phase ocl levels for channel b (bcspx-vref), valley current limit mfr_spec_00 < 3:0 > , (page1) = 0000b 12 14 16 a mfr_spec_00 < 3:0 > , (page1) = 0001b 16 18 20 a mfr_spec_00 < 3:0 > , (page1) = 0010b 20 22 24 a mfr_spec_00 < 3:0 > , (page1) = 0011b 24 26 28 a mfr_spec_00 < 3:0 > , (page1) = 0100b 28 30 32 a mfr_spec_00 < 3:0 > , (page1) = 0101b 32 34 36 a mfr_spec_00 < 3:0 > , (page1) = 0110b 36 38 40 a mfr_spec_00 < 3:0 > , (page1) = 0111b 40 42 44 a mfr_spec_00 < 3:0 > , (page1) = 1000b 44 46 48 a mfr_spec_00 < 3:0 > , (page1) = 1001b 48 50 52 a mfr_spec_00 < 3:0 > , (page1) = 1010b 52 54 56 a mfr_spec_00 < 3:0 > , (page1) = 1011b 56 58 60 a mfr_spec_00 < 3:0 > , (page1) = 1100b 60 62 64 a mfr_spec_00 < 3:0 > , (page1) = 1101b 64 66 68 a mfr_spec_00 < 3:0 > , (page1) = 1110b 68 70 72 a mfr_spec_00 < 3:0 > , (page1) = 1111b 72 74 76 a advance information
46 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.15 input under-voltage lockout (uvlo) the TPSM831D31 may not start converting power until the power stage input voltage reaches the level specified by vin_on . 7.5.15.1 (35h) vin_on the vin_on command sets the value of the input voltage, in volts, at which the unit should start power conversion. this command has two data bytes encoded in linear data format, and must be accessed through read word/write word transactions. the vin_on command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. the supported range for vin_on is from 4.0 v volts to 11.25 volts. 15 14 13 12 11 10 9 8 r r r r r rw rw rw vinon_exp vinon_man 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw vinon_man legend: r/w = read/write; r = read only vin_on table 39. vin_on register field descriptions bit field type reset description 15:11 vinon_exp r 11110b linear two's complement exponent, ? 2. lsb = 0.25 v 10:0 vinon_man rw nvm linear two's complement mantissa. see the table of acceptable values below. table 40. acceptable values of vin_on vin_on (hex) turn-on voltage (v) f01dh 7.25 f021h 8.25 f025h 9.25 f029h 10.25 f02dh 11.25 table 41. vin undervoltage fault limits vin_uv_fault_limit (hex) fault threshold (v) f80fh 7.5 f811h 8.5 f813h 9.5 f815h 10.5 f817h 11.5 7.5.16 input over-voltage protection and response the TPSM831D31 provides protection from input transients via the vin_ov_fault_limit and vin_ov_fault_response commands. 7.5.16.1 (55h) vin_ov_fault_limit the vin_ov_fault_limit command sets the value of the input voltage that causes an input overvoltage fault. vin_ov_fault_limit is a linear format command, and must be accessed through read word/write word transactions. the vin_ov_fault_limit command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. advance information
47 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 15 14 13 12 11 10 9 8 r r r r r rw rw rw vin_ovf_exp vin_ovf_man 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw vin_ovf_man legend: r/w = read/write; r = read only vin_ov_fault_limit table 42. vin_ov_fault_limit register field descriptions bit field type reset description 15:11 vin_ovf_exp r 00000b linear two's complement exponent, 0. lsb = 1 v 10:0 vin_ovf_man rw nvm linear two's complement mantissa. valid values of the mantissa range from 0d to 31d. 7.5.16.2 (56h) vin_ov_fault_response the vin_ov_fault_response command instructs the device on what action to take in response to an input overvoltage fault. the vin_ov_fault_response command must be accessed through read byte transactions. the vin_ov_fault_response command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. in response to the vin_ov_limit being exceeded, the device will: ? set the other bit in the status_byte ? set the input bit in the upper byte of the status_word ? sets the vin_ov_fault bit in the status_input register ? notify the host (assert the pmb_alert signal, if the corresponding mask bit in smbalert_mask is not set) 7 6 5 4 3 2 1 0 r r r r r r r r vi_ovf_resp legend: r/w = read/write; r = read only vin_ov_fault_response table 43. vin_ov_fault_response register field descriptions bit field type reset description 7:0 vi_ovf_resp r 00h 00h: ignore. the controller will set the appropriate status bits, and alert the host, but continue converting power. 7.5.17 input undervoltage protection and response the TPSM831D31 provides protection from input transients via the vin_uv_fault_limit and vin_uv_fault_response commands. 7.5.17.1 (59h) vin_uv_fault_limit the vin_uv_fault_limit command sets the value of the input voltage that causes an input under voltage fault. this fault is masked until the input exceeds the value set by the vin_on command for the first time, and the unit has been enabled. vin_uv_fault_limit is a linear format command, and must be accessed through read word/write word transactions. the vin_uv_fault_limit command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. advance information
48 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw vin_uvf_exp vin_uvf_man 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw vin_uvf_man legend: r/w = read/write; r = read only vin_uv_fault_limit table 44. vin_uv_fault_limit register field descriptions bit field type reset description 15:11 vin_uvf_exp rw nvm linear two's complement exponent. see the table of acceptable values below. 10:0 vin_uvf_man rw nvm linear two's complement mantissa. see the table of acceptable values below. table 45. acceptable values of vin_uv_fault_limit vin_uv_fault_limit (hex) vin uvf limit (v) f80dh 6.5 f80fh 7.5 f811h 8.5 f813h 9.5 f815h 10.5 f817h 11.5 7.5.17.2 (5ah) vin_uv_fault_response the vin_uv_fault_response command instructs the device on what action to take in response to an input overvoltage fault. the vin_uv_fault_response command must be accessed through read byte transactions. the vin_uv_fault_response command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. in response to the vin_uv_limit being exceeded, the device will: ? set the other bit in the status_byte ? set the input bit in the upper byte of the status_word ? set the vin_uv_fault bit in the status_input register ? the device notifies the host (asserts pmb_alert, if the corresponding mask bit in smbalert_mask is not set) 7 6 5 4 3 2 1 0 r r r r r r r r vi_uvf_resp legend: r/w = read/write; r = read only vin_uv_fault_response table 46. vin_uv_fault_response register field descriptions bit field type reset description 7:0 vi_uvf_resp r c0h c0h: shutdown and restart when the fault condition is no longer present. advance information
49 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.18 input overcurrent protection and response input overcurrent protection is configured via the iin_oc_fault_limit , iin_oc_warn_limit and iin_oc_fault_response commands. 7.5.18.1 (5bh) iin_oc_fault_limit the iin_oc_fault_limit command sets the value of the input current, in amperes, that causes the input over current fault condition. iin_oc_fault_limit is a linear format command, and must be accessed through read word/write word transactions. the iin_oc_fault_limit command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. 15 14 13 12 11 10 9 8 r r r r r rw rw rw iin_ocf_exp iin_ocf_man 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw iin_ocf_man legend: r/w = read/write; r = read only iin_oc_fault_limit table 47. iin_oc_fault_limit register field descriptions bit field type reset description 15:11 iin_ocf_exp r 11111b linear two's complement format exponent, ? 1. lsb = 0.5 a. 10:0 iin_ocf_man rw see below. linear two's complement format mantissa. acceptable values range from 0d (0 a) to 127d (63.5 a). during operation, the iin_oc_fault_limit may be changed to any valid value, as specified above. the iin_oc_fault_limit command has only limited nvm backup. the table below summarizes the values that iin_oc_fault_limit may be restored to following a reset, or restore_default_all operation. table 48. iin_oc_fault_limit reset values hex value iin_oc_fault_limit during nvm store operation iin_oc_fault_limit following reset/restore operation f810h 8 a 8 a f820h 16 a 16 a f830h 24 a 24 a f840h 32 a 32 a f850h 40 a 40 a f860h 48 a 48 a f870h 56 a 56 a f87fh 63.5 a 63.5 a any other valid data any other valid data 63.5 a 7.5.18.2 (5dh) iin_oc_warn_limit the iin_oc_warn_limit command sets the value of the input current, in amperes, that causes the input overcurrent warning condition. the iin_oc_warn_limit command must be accessed through read word/write word transactions. the iin_oc_warn_limit command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. upon triggering the over-current warning, the following actions are taken: ? set the other bit in the status_byte ? set the input bit in the status_word ? set the iin over-current warning bit in the status_input register ? the device notifies the host (asserts pmb_alert, if the corresponding mask bit in smbalert_mask is not advance information
50 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated set) 15 14 13 12 11 10 9 8 r r r r r r r r iin_ocw_exp iin_ocw_man 7 6 5 4 3 2 1 0 r rw rw rw rw rw rw rw iin_ocw_man legend: r/w = read/write; r = read only iin_oc_warn_limit table 49. iin_oc_fault_limit register field descriptions bit field type reset description 15:11 iin_ocw_exp r 11111b linear two's complement format exponent, ? 1. lsb = 0.5 a. 10:0 iin_ocw_man rw see below. linear two's complement format mantissa. acceptable values range from 0d (0 a) to 127d (63.5 a). during operation, the iin_oc_fault_limit may be changed to any valid value, as specified above. the iin_oc_fault_limit command has only limited nvm backup. the table below summarizes the values that iin_oc_fault_limit may be restored to following a reset, or restore_default_all operation. table 50. iin_oc_warn_limit reset values hex value iin_oc_warn_limit during nvm store operation iin_oc_warn_limit following reset/restore operation f810h 8 a 8 a f820h 16 a 16 a f830h 24 a 24 a f840h 32 a 32 a f850h 40 a 40 a f860h 48 a 48 a f870h 56 a 56 a f87fh 63.5 a 63.5 a any other valid data any other valid data 63.5 a 7.5.18.3 (5ch) iin_oc_fault_response the iin_oc_fault_response command instructs the device on what action to take in response to an input over-current fault. iin_oc_fault_response command must be accessed through read byte transactions. the iin_oc_fault_response command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. upon triggering the input over-current fault, the controller is latched off, and the following actions are taken: ? set the other bit in the status_byte ? set the input bit in the status_word ? set the iin_oc_fault bit in the status_input register ? the device notifies the host (asserts pmb_alert and vr_fault, if the corresponding mask bit in smbalert_mask is not set) 7 6 5 4 3 2 1 0 r r r r r r r r iin_oc_resp legend: r/w = read/write; r = read only advance information
51 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated iin_oc_fault_response table 51. iin_oc_fault_limit register field descriptions bit field type reset description 7:0 iin_oc_resp r c0h c0h: latch-off and do not restart. to clear a shutdown event due to a fault event, the user must toggle the avr_en/ben pin and/or the on bit in operation, per the settings in on_off_config, or power cycle the bias power to the v3p3 pin of the controller device. 7.5.19 overtemperature protection and response overtemperature protection is configured via the ot_fault_limit , ot_warn_limit and ot_fault_response commands. 7.5.19.1 (4fh) ot_fault_limit the ot_fault_limit command sets the value of the temperature limit, in degrees celsius, that causes an overtemperature fault condition when the sensed temperature from the external sensor exceeds this limit. the default value is selected inmfr_specific_13, using the otf_dflt bit. refer to the device technical reference manual for more information. ot_fault_limit is a linear format command, and must be accessed through read word/write word transactions. ot_fault_limit is a paged register. in order to access ot_fault_limit command for channel a, page must be set to 00h. in order to access ot_fault_limit register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. 15 14 13 12 11 10 9 8 r r r r r rw rw rw otf_exp otf_man 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw otf_man legend: r/w = read/write; r = read only ot_fault_limit table 52. ot_fault_limit register field descriptions bit field type reset description 15:11 otf_exp r 00000b linear two's complement exponent, 0. lsb = 1 o c 10:0 otf_man rw nvm linear two's complement mantissa. the default ot_fault_limit is set by the otf_dflt bit in mfr_specific_13. 7.5.19.2 (51h) ot_warn_limit the ot_warn_limit command sets the temperature, in degrees celsius, of the unit at which it should indicate an over-temperature warning event. ot_warn_limit is a linear format command, and must be accessed through read word/write word transactions. ot_warn_limit is a paged register. in order to access ot_warn_limit command for channel a, page must be set to 00h. in order to access ot_warn_limit register for channel b, page must be set to 01h. for simultaneous access of channels a and b, the page command must be set to ffh. in response to the ot_warn_limit being exceeded, the device will: ? set the temperature bit in the status_byte ? set the over-temperature warning bit in the status_temperature register ? notify the host (asserts pmb_alert, if the corresponding mask bit in smbalert_mask is not set) advance information
52 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 15 14 13 12 11 10 9 8 r r r r r rw rw rw otw_exp otw_man 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw otw_man legend: r/w = read/write; r = read only ot_warn_limit table 53. ot_warn_limit register field descriptions bit field type reset description 15:11 otf_exp r 00000b linear two's complement exponent, 0. lsb = 1 o c 10:0 otf_man rw 105d linear two's complement mantissa. default = 105 o c 7.5.19.3 (50h) ot_fault_response the ot_fault_response instructs the device on what action to take in response to an output over- temperature fault. the ot_fault_response command must be accessed through read byte/write byte transactions. the ot_fault_response command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. upon triggering the over-temperature fault, the controller is latched off, and the following actions are taken: ? set the temperature bit in the status_byte ? set the ot_fault bit in the status_temperature register ? the device notifies the host (asserts pmb_alert, if the corresponding mask bit in smbalert_mask is not set). 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw otf_resp legend: r/w = read/write; r = read only ot_fault_response table 54. ot_fault_response register field descriptions bit field type reset description 7:0 otf_resp rw nvm 80h: latch-off and do not restart. to clear a shutdown event due to a fault event, the user must toggle the avr_en/ben pin and/or the on bit in operation, per the settings in on_off_config, or power cycle the bias power to the v3p3 pin of the controller device. c0h: shutdown and restart when the fault condition is no longer present. 7.5.20 dynamic phase shedding (dps) the dynamic phase shedding (dps) feature allows the TPSM831D31 to dynamically select the number of operational phases for each channel, based on the total output current. this increases the total converter efficiency by reducing unnecessary switching losses when the output current is low enough to be supported by a fewer number of phases, than are available in hardware. the mfr_specific_14 and mfr_specific_15 commands may be used to configure dynamic phase shedding behavior and thresholds. the dps_en bit in mfr_specific_14 may be used to enable or disable dynamic phase shedding. un-setting (writing to 0b) this bit forces each channel to use the maximum number of available phases, regardless of the output current. dps is disabled as the factory default. advance information
53 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated the phase add/drop thresholds, at which phases are added or dropped are configured based on the peak efficiency point per phase. for a given switching frequency/duty cycle, the efficiency of an individual power stage has a "peak" point, at which switching losses become less significant and conduction losses begin to dominate. for a multiphase converter, the optimum efficiency is achieved when all of the power stages operate as close as possible to their peak efficiency point. for example, consider a 4-phase design, with power stages that have a peak efficiency point of 12 a per phase. when the total output current is 25 a, if all four phases were active, each phase would be supplying 6.25 a, and hence would be operating far away from their peak efficiency point. with only two phases active, however, each phase supplies 12.5a, meaning that each power stage is operating close to its peak efficiency point, therefore the total converter efficiency is higher overall. in order to maintain regulation during severe load transient events, phases may be added immediately whenever the total peak current reaches phase addition thresholds. to prevent chattering, phases are dropped when the total average current falls below phase drop thresholds, after a delay of 85 s typically. phases are always added/dropped, in numerical order. for example, phase 3 is added after phase 2, and dropped after phase 4. the dps_course_th bits in mfr_specific_15 select the peak efficiency point per phase. refer to the power stage datasheet to determine the peak efficiency point per phase. phase adding thresholds are configured based on the peak efficiency point per phase. each phase transition has a configurable threshold of 6 a to 12 a above the peak efficiency point. for example, the threshold at which the converter transitions from 2 phases to 3 phases is determined by the dps_2to3_fine_add bits in mfr_specific_15 . when 8 a is selected, the total peak current which causes the third phase to be added is 2 i eff(peak) + 8 a. see the register descriptions below for more detailed information. likewise, phase drop thresholds are configured based on the peak efficiency point per phase. each phase transition has a configurable threshold of 2a below a to 4 a above the peak efficiency point. for example, the threshold at which the converter transitions from 3 phases to 2 phases is determined by the dps_3to2_fine_drop bits in mfr_specific_14 . when 0 a is selected, the total average current which causes the third phase to be dropped is 2 i eff(peak) . see the register descriptions below for more detailed information. advance information
54 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 55. dynamic phase add and drop parameter test conditions min typ max unit v dpstha1 dynamic phase adding threshold, 1 to 2 phases (peak current) peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = 2 a; (mfr_specific_15 < 4:3 > = 00b); v ripple 18 a (estimation) 21 23 25 a peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = 4 a; (mfr_specific_15 < 4:3 > = 01b); v ripple 18 a (estimation) 23 25 27 a peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = 6 a; (mfr_specific_15 < 4:3 > = 10b); v ripple 18 a (estimation) 25 27 29 a peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = 8 a; (mfr_specific_15 < 4:3 > = 11b); v ripple 18 a (estimation) 27 29 31 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = 2 a; (mfr_specific_15 < 4:3 > = 00b); v ripple 18 a (estimation) 23 25 27 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = 4 a; (mfr_specific_15 < 4:3 > = 01b); v ripple 18 a (estimation) 25 27 29 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = 6 a; (mfr_specific_15 < 4:3 > = 10b); v ripple 18 a (estimation) 27 29 31 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = 8 a; (mfr_specific_15 < 4:3 > = 11b); v ripple 18 a (estimation) 29 31 33 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = 2 a; (mfr_specific_15 < 4:3 > = 00b); v ripple 18 a (estimation) 25 27 29 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = 4 a; (mfr_specific_15 < 4:3 > = 01b); v ripple 18 a (estimation) 27 29 31 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = 6 a; (mfr_specific_15 < 4:3 > = 10b); v ripple 18 a (estimation) 29 31 33 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = 8 a; (mfr_specific_15 < 4:3 > = 11b); v ripple 18 a (estimation) 31 33 35 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = 2 a; (mfr_specific_15 < 4:3 > = 00b); v ripple 18 a (estimation) 27 29 31 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = 4 a; (mfr_specific_15 < 4:3 > = 01b); v ripple 18 a (estimation) 29 31 33 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = 6 a; (mfr_specific_15 < 4:3 > = 10b); v ripple 18 a (estimation) 31 33 35 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = 8 a; (mfr_specific_15 < 4:3 > = 11b); v ripple 18 a (estimation) 33 35 37 a advance information
55 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 55. dynamic phase add and drop (continued) parameter test conditions min typ max unit v dpsths1 dynamic phase shedding threshold, 2 to 1 phase (average current) peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = -6 a; (mfr_specific_15 < 14:13 > = 00b) 4 6 8 a peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = -4 a; (mfr_specific_15 < 14:13 > = 01b) 6 8 10 a peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = -2 a; (mfr_specific_15 < 14:13 > = 10b) 8 10 12 a peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = 0 a; (mfr_specific_15 < 14:13 > = 11b) 10 12 14 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = -6 a; (mfr_specific_15 < 14:13 > = 00b) 6 8 10 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = -4 a; (mfr_specific_15 < 14:13 > = 01b) 8 10 12 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = -2 a; (mfr_specific_15 < 14:13 > = 10b) 10 12 14 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = 0 a; (mfr_specific_15 < 14:13 > = 11b) 12 14 16 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = -6 a; (mfr_specific_15 < 14:13 > = 00b) 8 10 12 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = -4 a; (mfr_specific_15 < 14:13 > = 01b) 10 12 14 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = -2 a; (mfr_specific_15 < 14:13 > = 10b) 12 14 16 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = 0 a; (mfr_specific_15 < 14:13 > = 11b) 14 16 18 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = -6 a; (mfr_specific_15 < 14:13 > = 00b) 10 12 14 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = -4 a; (mfr_specific_15 < 14:13 > = 01b) 12 14 16 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = -2 a; (mfr_specific_15 < 14:13 > = 10b) 14 16 18 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = 0 a; (mfr_specific_15 < 14:13 > = 11b) 16 18 20 a advance information
56 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 55. dynamic phase add and drop (continued) parameter test conditions min typ max unit v dpstha2 dynamic phase adding threshold, 2 to 3 phases (peak current) peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = 4 a; (mfr_specific_15 < 6:5 > = 00b); v ripple = 14 a (estimation) 32.5 35 37.5 a peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = 6 a; (mfr_specific_15 < 6:5 > = 01b); v ripple = 14 a (estimation) 34.5 37 39.5 a peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = 8 a; (mfr_specific_15 < 6:5 > = 10b); v ripple = 14 a (estimation) 36.5 39 41.5 a peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = 10 a; (mfr_specific_15 < 6:5 > = 11b); v ripple = 14 a (estimation) 38.5 41 43.5 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = 4 a; (mfr_specific_15 < 6:5 > = 00b); v ripple = 14 a (estimation) 36.5 39 41.5 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = 6 a; (mfr_specific_15 < 6:5 > = 01b); v ripple = 14 a (estimation) 38.5 41 43.5 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = 8 a; (mfr_specific_15 < 6:5 > = 10b); v ripple = 14 a (estimation) 40.5 43 45.5 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = 10 a; (mfr_specific_15 < 6:5 > = 11b); v ripple = 14 a (estimation) 42.5 45 47.5 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = 4 a; (mfr_specific_15 < 6:5 > = 00b); v ripple = 14 a (estimation) 40.5 43 45.5 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = 6 a; (mfr_specific_15 < 6:5 > = 01b); v ripple = 14 a (estimation) 42.5 45 47.5 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = 8 a; (mfr_specific_15 < 6:5 > = 10b); v ripple = 14 a (estimation) 44.5 47 49.5 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = 10 a; (mfr_specific_15 < 6:5 > = 11b); v ripple = 14 a (estimation) 46.5 49 51.5 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = 4 a; (mfr_specific_15 < 6:5 > = 00b); v ripple = 14 a (estimation) 44.5 47 49.5 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = 6 a; (mfr_specific_15 < 6:5 > = 01b); v ripple = 14 a (estimation) 46.5 49 51.5 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = 8 a; (mfr_specific_15 < 6:5 > = 10b); v ripple = 14 a (estimation) 48.5 51 53.5 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = 10 a; (mfr_specific_15 < 6:5 > = 11b); v ripple = 14 a (estimation) 50.5 53 55.5 a advance information
57 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 55. dynamic phase add and drop (continued) parameter test conditions min typ max unit v dpsths2 dynamic phase shedding threshold, 3 to 2 phases (average current) peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = -4 a; (mfr_specific_14 < 9:8 > = 00b) 17.5 20 22.5 a peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = -2 a; (mfr_specific_14 < 9:8 > = 01b) 19.5 22 24.5 a peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = 0 a; (mfr_specific_14 < 9:8 > = 10b) 21.5 24 26.5 a peak efficiency = 12 a; (mfr_specific_15 < 1:0 > = 00b); offset = 2 a; (mfr_specific_14 < 9:8 > = 11b) 23.5 26 28.5 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = -4 a; (mfr_specific_14 < 9:8 > = 00b) 21.5 24 26.5 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = -2 a; (mfr_specific_14 < 9:8 > = 01b) 23.5 26 28.5 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = 0 a; (mfr_specific_14 < 9:8 > = 10b) 25.5 28 30.5 a peak efficiency = 14 a; (mfr_specific_15 < 1:0 > = 01b); offset = 2 a; (mfr_specific_14 < 9:8 > = 11b) 27.5 30 32.5 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = -4 a; (mfr_specific_14 < 9:8 > = 00b) 25.5 28 30.5 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = -2 a; (mfr_specific_14 < 9:8 > = 01b) 27.5 30 32.5 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = 0 a; (mfr_specific_14 < 9:8 > = 10b) 29.5 32 34.5 a peak efficiency = 16 a; (mfr_specific_15 < 1:0 > = 10b); offset = 2 a; (mfr_specific_14 < 9:8 > = 11b) 31.5 34 36.5 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = -4 a; (mfr_specific_14 < 9:8 > = 00b) 29.5 32 34.5 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = -2 a; (mfr_specific_14 < 9:8 > = 01b) 31.5 34 36.5 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = 0 a; (mfr_specific_14 < 9:8 > = 10b) 33.5 36 38.5 a peak efficiency = 18 a; (mfr_specific_15 < 1:0 > = 11b); offset = 2 a; (mfr_specific_14 < 9:8 > = 11b) 35.5 38 40.5 a 7.5.20.1 (deh) mfr_specific_14 the mfr_specific_14 command is used to configure dynamic phase shedding, and compensation ramp amplitude, and dynamic ramp amplitude during usr, and different power states. the mfr_specific_14 command must be accessed through write word/read word transactions. mfr_specific_14 is a paged register. in order to access mfr_specific_14 command for channel a, page must be set to 00h. in order to access the mfr_specific_14 register for channel b, page must be set to 01h. 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw n/a n/a n/a n/a n/a n/a dps_3to2_fine_drop 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw dps_en dyn_ramp_usr dyn_ramp_2 ph dyn_ramp_1 ph ramp legend: r/w = read/write; r = read only mfr_specific_14 advance information
58 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 56. mfr_specific_14 register field descriptions bit field type reset description 15:10 n/a rw nvm n/a 9:8 dps_3to2_fine_drop rw nvm dynamic phase drop threshold, fine adjustment, 3 phases to 2 phases. set as an offset from peak efficiency point per phase in amperes. phases drop when average phase current reaches the stated threshold. i eff(peak) refers to the value selected by dps_course_th in mfr_specific_15 . 00b: threshold = 2 i eff(peak) ? 2 a 01b: threshold = 2 i eff(peak) 10b: threshold = 2 i eff(peak) + 2 a 11b: threshold = 2 i eff(peak) + 4 a 7 dps_en rw nvm enable or disable dynamic phase shedding 0b: disable dynamic phase shedding 1b: enable dynamic phase shedding 6:5 dyn_ramp_usr rw nvm dynamic ramp amplitude setting during usr operation. only applies to usr level 1. 00b: equal to the settings in the ramp bits 01b: 40 mv 10b: 80 mv 11b: 120 mv 4 dyn_ramp_2ph rw nvm dynamic ramp amplitude setting during 2 phase operation. 0b: equal to the settings in the ramp bits 1b: 120 mv 3 dyn_ramp_1ph rw nvm dynamic ramp amplitude setting during 1 phase operation. 0b: equal to the settings in the ramp bits 1b: 80 mv 2:0 ramp rw nvm ramp amplitude settings. see table 57 . table 57. ramp amplitude settings ramp (binary) ramp amplitude setting (mv) 000b 40 001b 80 010b 120 011b 160 100b 200 101b 240 110b 280 111b 320 7.5.20.2 (dfh) mfr_specific_15 the mfr_specific_15 command is used to configure dynamic phase shedding. the mfr_specific_15 command must be accessed through write word/read word transactions. mfr_specific_15 is a paged register. in order to access mfr_specific_15 command for channel a, page must be set to 00h. in order to access the mfr_specific_15 register for channel b, page must be set to 01h. advance information
59 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw dps_dcm dps_2to1_fine_drop n/a n/a n/a n/a n/a 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw n/a dps_2to3_fine_add dps_1to2_fine_add 2to1_ph_en dps_course_th legend: r/w = read/write; r = read only mfr_specific_15 table 58. mfr_specific_15 register field descriptions bit field type reset description 15 dps_dcm rw nvm enable dcm mode during 1 phase operation, when higher order phases are dropped due to dynamic phase shedding. 0b: disable dcm operation during 1 phase operation 1b: enable dcm operation during 1 phase operation 14:13 dps_2to1_fine_drop rw nvm dynamic phase drop threshold, fine adjustment, 2 phases to 1phase. set as an offset from peak efficiency point per phase in amperes. phases drop when average phase current reaches the stated threshold. i eff(peak) refers to the value selected by dps_course_th below. 00b: threshold = 1 i eff(peak) ? 2 a 01b: threshold = 1 i eff(peak) 10b: threshold = 1 i eff(peak) + 2 a 11b: threshold = 1 i eff(peak) + 4 a 12:7 n/a rw nvm n/a 6:5 dps_2to3_fine_add rw nvm dynamic phase add threshold, fine adjustment, 2 phases to 3 phases. set as an offset from peak efficiency point per phase in amperes. phases add when peak phase current reaches the stated threshold. i eff(peak) refers to the value selected by dps_course_th below 00b: threshold = 2 i eff(peak) + 6a 01b: threshold = 2 i eff(peak) + 8 a 10b: threshold = 2 i eff(peak) + 10 a 11b: threshold = 2 i eff(peak) + 12 a 5:4 dps_1to2_fine_add rw nvm dynamic phase add threshold, fine adjustment, 1 phase to 2 phases. set as an offset from peak efficiency point per phase in amperes. phases add when peak phase current reaches the stated threshold. i eff(peak) refers to the value selected by dps_course_th below 00b: threshold = 1 i eff(peak) + 6a 01b: threshold = 1 i eff(peak) + 8 a 10b: threshold = 1 i eff(peak) + 10 a 11b: threshold = 1 i eff(peak) + 12 a 3 2to1_ph_en rw nvm enable phase dropping from 2 phases to 1 phase operation. 0b: disable phase shedding to 1 phase 1b: enable phase shedding to 1 phase 2:0 dps_course_th rw nvm sets the peak efficiency point per phase. this is used to determine phase add/drop thresholds. 00b: i eff(peak) = 12 a 01b: i eff(peak) = 14 a 10b: i eff(peak) = 16 a 11b: i eff(peak) = 18 a advance information
60 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.21 nvm programming the user_data_00 - user_data_12 commands are provided to streamline nvm programming. these 6- byte block commands are mapped internally to all of the user-configurable parameters the TPSM831D31 supports. the mfr_serial command also provides a checksum, to streamline verification of desired programming values. the generalized procedure for programming the TPSM831D31 is summarized below. configure user-programmable parameters 1. first, configure all of the user-accessible parameters via the standard pmbus, and manufacturer specific commands. ti provides the fusion digital power designer graphical interface software to streamline this step. the user can also refer to the technical reference manual for a full set of register maps for these commands. 2. once the device is configured as desired, issue the store_default_all command to commit these values to nvm, and update the checksum value. wait approximately 100 ms after issuing store_default_all before communicating with the device again. 3. write page to 00h 4. read-back and record the value of ic_device_id and ic_device_rev commands 5. read-back and record the value of the user_data_00 through user_data_12 commands 6. read-back and record the value of the mfr_serial command 7. read-back and record the value of vout_max 8. write page to 01h 9. read-back and record the value of vout_max program and verify nvm (repeat for each device) 1. power the device by supplying +3.3v to the v3p3 pin. power conversion should be disabled for nvm programming. 2. read-back and verify that ic_device_id and ic_device_rev values match those recorded previously. this ensures that user-parameters being programmed correspond to the same device/revision as previously configured. 3. write page to 00h. 4. write the user_data_00 through user_data_12 commands, with the values recorded previously. 5. write vout_max (page 0) with the value recorded previously. 6. write page to 01h 7. write vout_max (page 1) with the value recorded previously. 8. issue store_default_all. wait appx 100 ms after issuing store_default_all before communicating with the device again. 9. read-back the mfr_serial command, and compare the value to that recorded previously. if the new mfr_serial matches the value recorded previously, nvm programming was successful. advance information
61 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.22 nvm security the mfr_specific_42 command can be optionally used to set a password for nvm programming. to prevent a hacker from simply sending the password command with all possible passwords, the TPSM831D31 goes into a special extra-secure state when an incorrect password is received. in this state, all passwords are rejected, even the valid one. the device must be power cycled to clear this state so that another password attempt may be made. when nvm security is enabled, the TPSM831D31 will not accept writes to any command other than page and phase, which are necessary for reading certain parameters. enabling nvm security 1. set the nvm password. write mfr_specific_42 to a value other than ffffh. 2. issue store_default_all 3. wait 100ms for the nvm store to complete 4. power cycle v3p3. nvm security will be enabled at the next power-up. disabling nvm security to disable nvm security, use the following procedure: 1. write the password to mfr_specific_42 to disable nvm security. once the correct password has been given, nvm security will be disabled, and the device will once again accept write transactions to configuration registers. nvm security will be re-enabled at the next power-on, unless mfr_specific_42 is set to ffffh (nvm security disabled), and an nvm store operation (issue store_default_all and wait 100 ms) is performed. determining whether nvm security is active reads to the mfr_specific_42 command returns one of three values: ? 0000h = nvm security is disabled ? 0001h = nvm security is enabled ? 0002h = mfr_specific_42 is locked due to incorrect password entry 7.5.22.1 (fah) mfr_specific_42 mfr_specific_42 is used for nvm security. the mfr_specific_42 command must be accessed through read word/write word transactions. mfr_specific_42 is a shared register. write transactions to this register will apply to both channels, and read transactions to this register returns the same data regardless of the current page. 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw nvm_security_key 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw nvm_security_key legend: r/w = read/write; r = read only mfr_specific_42 table 59. mfr_specific_42 register field descriptions bit field type reset description 7:0 nvm_security_key rw nvm 16 bit code for nvm security key. advance information
62 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5.23 black box recording the TPSM831D31 provides a "black box" feature to aid in system-level debugging. according to the pmbus specification, status bits are latched whenever the condition causing them occurs, regardless of whether or not other status bits are already set. this, however, makes it difficult for the system designer to understand which fault condition occurred first, in the case that one fault condition causes others to trigger. the mfr_specific_08 command provides a "snapshot" of the first faults to occur chronologically, for each channel, which may be stored to nvm, for future debugging. only the most catastrophic fault conditions are logged, such as the over-voltage fault, over-current fault, and power stage failure. the black box command may also be reset, or cleared by writing 00h to the register, and storing to nvm if the nvm value must also be cleared. resetting the black box record resetting the record allows the user to determine which faults occur first, after the register is cleared. to clear the record, write 00h to mfr_specific_08 , and issue store_default_all. triggering black box recording black box recording is always active, whether or not the TPSM831D31 is converting power. note however many of the critical faults summarized in mfr_specific_08 are only possible to trigger during power conversion. whenever any of the following catastrophic faults occur, the mfr_specific_08 register will be updated according to the register description below, but only if the black box record has been cleared since the last catastrophic faults occurred. faults logged include: ? overvoltage fault (device was converting power) ? overvoltage fault (device was not converting power) ? input overcurrent fault ? output overcurrent fault ? power stage fault ? input over-power fault retrieving the black box record reading the mfr_specific_08 returns the current value of the black box record. if the register reads 00h, no catastrophic faults have occurred since the record was last cleared. if any value other than 00h is stored in the register, then de-code the value according to the register description below. in order to read-back the black box record following a power-down, the store_default_all command must be issued, to store the contents of the black box record to nvm. 7.5.23.1 (d8h) mfr_specific_08 the mfr_specific_08 command is used to identify catastrophic faults which occur first, and store this information to nvm. see the product datasheet for more information. the mfr_specific_08 command must be accessed through write byte/read byte transactions. mfr_specific_08 is a shared register. transactions to this register do not require specific page settings. however, note that channels a and b have independent bit fields within the command. 7 6 5 4 3 2 1 0 r r rw rw rw rw rw rw 0 0 cf_cha cf_chb legend: r/w = read/write; r = read only mfr_specific_08 table 60. mfr_specific_08 register field descriptions bit field type reset description 7:6 not used r 0 not used and set to 0. 5:3 cf_cha rw nvm catastrophic fault record for channel a. 2:0 cf_chb rw nvm catastrophic fault record for channel b. advance information
63 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated whenever a catastrophic fault occurs, the first event detected will trigger the mfr_specific_08 command to update according to the tables below. this recording happens independently for channel a and channel b. if the pmbus host issues a store_default_all, this information will be committed to nvm, and may be retrieved at a later time. in order to clear the record for either channel, the pmbus host must write the corresponding bits (cf_cha for channel a, cf_chb for channel b) to 000b, and issue store_default_all. attempts to write any non-zero value to this command will be treated as invalid data - data will be ignored, the appropriate flags in status_cml, and status_word, will be set, and the pmb_alert pin will be asserted to notify the host of the invalid transaction. table 61. catastrophic fault recording interpretation cf_cha / cf_chb (binary) interpretation 000b no fault occurred 001b ovf occurred, power conversion was disabled 010b ovf occurred, power conversion was enabled 011b iin overcurrent fault occurred 100b iout overcurrent fault occurred 101b overtemperature fault occurred 110b power stage fault occurred 111b input overpower warning occurred 7.5.24 board identification and inventory tracking the TPSM831D31 provides several bytes of arbitrarily programmable nvm-backed memory to allow for inventory management and board identification. by default, these values reflect information about the date/revision of the TPSM831D31 device being used itself. this provides a convenient and easy to use method of tracking boards, revisions and manufacturing dates. the following commands are provided for this purpose: ? mfr_id - 16 bits of nvm for end-users to track the power module supplier name ? mfr_model - 16 bits of nvm for tracking the manufacturer model number ? mfr_revision - 16 bits of nvm for tracking power module revision code ? mfr_date - 16 bits of nvm for tracking power module manufacturing date code 7.5.25 status reporting the TPSM831D31 provides several registers containing status information. the flags in these registers are latched whenever their corresponding condition occurs, and are not cleared until either the clear_faults command is issued, or the host writes a value of 1b to that bit location. register maps for the all of the supported status registers are shown in the following sections. 7.5.25.1 (78h) status_byte the status_byte command returns one byte of information with a summary of the most critical faults, such as over-voltage, overcurrent, over-temperature, etc. the status_byte command must be accessed through read byte transactions. status_byte is a paged register. in order to access status_word command for channel a, page must be set to 00h. in order to access status_word register for channel b, page must be set to 01h. if page is set ffh, the device return value will reflect the status of channel a. 7 6 5 4 3 2 1 0 0 r r r r r r r busy off vout_ov iout_oc vin_uv temp cml other figure 12. status_byte advance information
64 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 62. status_byte register field descriptions bit field type reset description 7 busy r 0 not supported and always set to 0. 6 off r current status this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 0: raw status indicating the ic is providing power to vout. 1: raw status indicating the ic is not providing power to vout. 5 vout_ov r current status output over-voltage fault condition 0: latched flag indicating no vout ov fault has occurred. 1: latched flag indicating a vout ov fault occurred 4 iout_oc r current status output over-current fault condition 0: latched flag indicating no iout oc fault has occurred. 1: latched flag indicating an iout oc fault has occurred. 3 vin_uv r current status input under-voltage fault condition 0: latched flag indicating vin is above the uvlo threshold. 1: latched flag indicating vin is below the uvlo threshold. 2 temp r current status over-temperature fault/warning 0: latched flag indicating no ot fault or warning has occurred. 1: latched flag indicating an ot fault or warning has occurred. 1 cml r current status communications, memory or logic fault 0: latched flag indicating no communication, memory, or logic fault has occurred. 1: latched flag indicating a communication, memory, or logic fault has occurred. 0 other r current status other fault (none of the above) this bit is used to flag faults not covered with the other bit faults. in this case, uvf or ocw faults are examples of other faults not covered by the bits [7:1] in this register. 0: no fault has occurred 1: a fault or warning not listed in bits [7:1] has occurred. per the description in the pmbus 1.3 specification, part ii, TPSM831D31 does support clearing of status bits by writing to status registers. however, the bits in the status_byte are summary bits only and reflect the status of corresponding bits in status_vout, status_iout, etc... to clear these bits individually, the user must clear them by writing to the corresponding status_x register. for example: the output overcurrent fault sets the iout_oc bit in status_byte, and the iout_oc_flt bit in status_iout. writing a 1 to the iout_oc_flt bit in status_iout clears the fault in both status_byte and status_iout. writes to status_byte itself will be treated as invalid transactions. 7.5.25.2 (79h) status_word the status_word command returns two bytes of information with a summary of critical faults, such as over- voltage, overcurrent, over-temperature, etc.. the status_word command must be accessed through read word transactions. status_word is a paged register. in order to access status_word command for channel a, page must be set to 00h. in order to access status_word register for channel b, page must be set to 01h. if page is set ffh, the device return value will reflect the status of channel a. 15 14 13 12 11 10 9 8 r r r r r r r r vout iout input mfr pgood fans other unknown 7 6 5 4 3 2 1 0 r r r r r r r r busy off vout_ov iout_oc vin_uv temp cml other advance information
65 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 13. status_word table 63. status_word register field descriptions bit field type reset description 15 vout r current status output voltage fault/warning. refer to status_vout for more information. 0: latched flag indicating no vout fault or warning has occurred. 1: latched flag indicating a vout fault or warning has occurred. 14 iout r current status output current fault/warning. refer to status_iout for more information. 0: latched flag indicating no iout fault or warning has occurred. 1: latched flag indicating an iout fault or warning has occurred. 13 input r current status input voltage/current fault/warning. refer to status_input for more information. 0: latched flag indicating no vin or iin fault or warning has occurred. 1: latched flag indicating a vin or iin fault or warning has occurred. 12 mfr r current status mfr_specific fault. refer to status_mfr for more information. 0: latched flag indicating no mfr_specific fault has occurred. 1: latched flag indicating a mfr_specific fault has occurred. 11 pgood r current status power good status. note: per the pmbus specification, the pgood bit is not latched, always reflecting the current status of the avr_rdy/bvr_rdy pin. 0: raw status indicating avr_rdy/bvr_rdy pin is at logic high. 1: raw status indicating avr_rdy/bvr_rdy pin is at logic low. 10 fans r 0 not supported and always set to 0. 9 other r 0 not supported and always set to 0. 8 unknown r 0 not supported and always set to 0. 7 busy r 0 not supported and always set to 0. 6 off r current status this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 0: raw status indicating the ic is providing power to vout. 1: raw status indicating the ic is not providing power to vout. 5 vout_ov r current status output over-voltage fault condition 0: latched flag indicating no vout ov fault has occurred. 1: latched flag indicating a vout ov fault occurred 4 iout_oc r current status output over-current fault condition 0: latched flag indicating no iout oc fault has occurred. 1: latched flag indicating an iout oc fault has occurred. 3 vin_uv r current status input under-voltage fault condition 0: latched flag indicating vin is above the uvlo threshold. 1: latched flag indicating vin is below the uvlo threshold. 2 temp r current status over-temperature fault/warning 0: latched flag indicating no ot fault or warning has occurred. 1: latched flag indicating an ot fault or warning has occurred. 1 cml r current status communications, memory or logic fault 0: latched flag indicating no communication, memory, or logic fault has occurred. 1: latched flag indicating a communication, memory, or logic fault has occurred. 0 other r current status other fault (none of the above) this bit is used to flag faults not covered with the other bit faults. in this case, uvf or ocw faults are examples of other faults not covered by the bits [7:1] in this register. 0: no fault has occurred 1: a fault or warning not listed in bits [7:1] has occurred. advance information
66 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated per the description in the pmbus 1.3 specification, part ii, TPSM831D31 does support clearing of status bits by writing to status registers. however, the bits in the status_word are summary bits only and reflect the status of corresponding bits in status_vout, status_iout, etc... to clear these bits individually, the user must clear them by writing to the corresponding status_x register. for example: the output overcurrent fault sets the iout_oc bit in status_word, and the iout_oc_flt bit in status_iout. writing a 1 to the iout_oc_flt bit in status_iout clears the fault in both status_word and status_iout. writes to status_word will be treated as invalid transactions. 7.5.25.3 (7ah) status_vout the status_vout command returns one byte of information relating to the status of the converter's output voltage related faults. the status_vout command must be accessed through read byte/write byte transactions. status_vout is a paged register. in order to access status_vout command for channel a, page must be set to 00h. in order to access status_vout register for channel b, page must be set to 01h. if page is set ffh, the device return value will reflect the status of channel a. 7 6 5 4 3 2 1 0 rw 0 0 rw rw 0 0 0 vout_ovf vout_ovw vout_uvw vout_uvf vout_min_m ax ton_max toff_max vout_track figure 14. status_vout table 64. status_vout register field descriptions bit field type reset description 7 vout_ovf rw current status output over-voltage fault 0: latched flag indicating no vout ov fault has occurred. 1: latched flag indicating a vout ov fault has occurred. 6 vout_ovw r 0 not supported and always set to 0. 5 vout_uvw r 0 not supported and always set to 0. 4 vout_uvf rw current status output under-voltage fault 0: latched flag indicating no vout uv fault has occurred. 1: latched flag indicating a vout uv fault has occurred. 3 vout_min_max rw current status output voltage max/min exceeded warning 0: latched flag indicating no vout_max/vout_min warning has occurred. 1: latched flag indicating that an attempt has been made to set the output voltage to a value higher than allowed by the vout_max/vout_min command. 2 ton_max r 0 not supported and always set to 0. 1 toff_max r 0 not supported and always set to 0. 0 vout_track r 0 not supported and always set to 0. per the description in the pmbus 1.3 specification, part ii, TPSM831D31 does support clearing of status bits by writing to status registers. writing a 1 to any supported bit in this register will attempt to clear it as a fault condition. 7.5.25.4 (7bh) status_iout the status_iout command returns one byte of information relating to the status of the converter's output current related faults. the status_iout command must be accessed through read byte/write byte transactions. status_iout is a paged register. in order to access status_iout command for channel a, page must be set to 00h. in order to access status_iout register for channel b, page must be set to 01h. if page is set ffh, the device return value will reflect the status of channel a. advance information
67 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 0 0 iout_ocf iout_ocuvf iout_ocw iout_ucf cur_sharef pow_limit pout_opf pout_opw figure 15. status_iout table 65. status_iout register field descriptions bit field type reset description 7 iout_ocf rw current status output over-current fault 0: latched flag indicating no iout oc fault has occurred. 1: latched flag indicating a iout oc fault has occurred . 6 iout_ocuvf r 0 not supported and always set to 0. 5 iout_ocw rw current status 0: latched flag indicating no iout oc warning has occurred 1: latched flag indicating a iout oc warning has occurred 4 iout_ucf r 0 not supported and always set to 0. 3 cur_sharef rw current status 0: latched flag indicating no current sharing fault has occurred 1: latched flag indicating a current sharing fault has occurred 2 pow_limit r 0 not supported and always set to 0. 1 pout_opf r 0 not supported and always set to 0. 0 pout_opw r 0 not supported and always set to 0. per the description in the pmbus 1.3 specification, part ii, TPSM831D31 does support clearing of status bits by writing to status registers. writing a 1 to any supported bit in this register will attempt to clear it as a fault condition. 7.5.25.5 (7ch) status_input the status_input command returns one byte of information relating to the status of the converter's input voltage and current related faults. the status_input command must be accessed through read byte/write byte transactions. the status_input command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. 7 6 5 4 3 2 1 0 rw 0 0 rw rw rw rw rw vin_ovf vin_ovw vin_uvw vin_uvf low_vin iin_ocf iin_ocw pin_opw figure 16. status_input register table 66. status_input register field descriptions bit field type reset description 7 vin_ovf r current status input over-voltage fault 0: latched flag indicating no vin ov fault has occurred. 1: latched flag indicating a vin ov fault has occurred. 6 vin_ovw r 0 not supported and always set to 0. 5 vin_uvw r 0 not supported and always set to 0. 4 vin_uvf r current status input under-voltage fault 0: latched flag indicating no vin uv fault has occurred. 1: latched flag indicating a vin uv fault has occurred. 3 low_vin r current status unit off for insufficient input voltage 0: latched flag indicating no low_vin fault has occurred. 1: latched flag indicating a low_vin fault has occurred 2 iin_ocf r current status input over-current fault 0: latched flag indicating no iin oc fault has occurred. 1: latched flag indicating a iin oc fault has occurred. advance information
68 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 66. status_input register field descriptions (continued) bit field type reset description 1 iin_ocw r current status input over-current warning 0: latched flag indicating no iin oc warning has occurred. 1: latched flag indicating a iin oc warning has occurred. 0 pin_opw r current status input over-power warning 0: latched flag indicating no input over-power warning has occurred. 1: latched flag indicating a input over-power warning has occurred. per the description in the pmbus 1.3 specification, part ii, TPSM831D31 does support clearing of status bits by writing to status registers. writing a 1 to any supported bit in this register will attempt to clear it as a fault condition. 7.5.25.6 (7dh) status_temperature the status_temperature command returns one byte of information relating to the status of the converter's temperature related faults. the status_temperature command must be accessed through read byte/write byte transactions. status_temperature is a paged register. in order to access status_temperature command for channel a, page must be set to 00h. in order to access status_temperature register for channel b, page must be set to 01h. if page is set ffh, the device return value will reflect the status of channel a. 7 6 5 4 3 2 1 0 rw rw 0 0 0 0 0 0 otf otw utw utf reserved figure 17. status_temperature register table 67. status_temperature register field descriptions bit field type reset description 7 otf rw current status over-temperature fault 0: (default) a temperature fault has not occurred. 1: a temperature fault has occurred. 6 otw rw current status over-temperature warning 0: (default) a temperature warning has not occurred. 1: a temperature warning has occurred. 5 utw r 0 not supported and always set to 0. 4 utf r 0 not supported and always set to 0. 3-0 reserved r 0000 always set to 0. per the description in the pmbus 1.3 specification, part ii, TPSM831D31 does support clearing of status bits by writing to status registers. writing a 1 to any supported bit in this register will attempt to clear it as a fault condition. 7.5.25.7 (7eh) status_cml the status_cml command returns one byte with contents regarding communication, logic, or memory conditions. the status_cml command must be accessed through read byte/write byte transactions. the status_cml command is shared between channel a and channel b. all transactions to this command will affect both channels regardless of the page command. advance information
69 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 6 5 4 3 2 1 0 rw rw rw rw 0 0 rw 0 iv_cmd iv_data pec_fail mem pro_fault reserved com_fail cml_other figure 18. status_cml register table 68. status_cml register field descriptions bit field type reset description 7 iv_cmd rw current status invalid or unsupported command received 0: latched flag indicating no invalid or unsupported command has been received. 1: latched flag indicating an invalid or unsupported command has been received. 6 iv_data rw current status invalid or unsupported data received 0: latched flag indicating no invalid or unsupported data has been received. 1: latched flag indicating an invalid or unsupported data has been received. 5 pec_fail rw current status packet error check failed 0: latched flag indicating no packet error check has failed 1: latched flag indicating a packet error check has failed 4 reserved r 0 always set to 0. 3 mem rw current status memory/nvm error 0: latched flag indicating no memory error has occurred 1: latched flag indicating a memory error has occurred 2 reserved r 0 always set to 0. 1 com_fail rw current status other communication faults 0: latched flag indicating no communication fault other than the ones listed in this table has occurred. 1: latched flag indicating a communication fault other than the ones listed in this table has occurred. 0 cml_other r 0 not supported and always set to 0. per the description in the pmbus 1.3 specification, part ii, TPSM831D31 does support clearing of status bits by writing to status registers. writing a 1 to any bit in this register will attempt to clear it as a fault condition. 7.5.25.8 (80h) status_mfr_specific the status_mfr_specific command returns one byte containing manufacturer-defined faults or warnings. the status_mfr_specific command must be accessed through read byte/write byte transactions. status_mfr_specific is a paged register. in order to access status_mfr_specific command for channel a, page must be set to 00h. in order to access status_mfr_specific register for channel b, page must be set to 01h. if page is set ffh, the device return value will reflect the status of channel a. figure 19. status_mfr_specific register 7 6 5 4 3 2 1 0 rw rw rw rw rw 0 0 rw flt_ps vsns_open max_ph_war n tsns_low rst_vid (page 0) reserved phflt table 69. status_mfr_specific register field descriptions bit field type reset description 7 mfr_fault_ps rw current status power stage fault 0b: latched flag indicating no fault from ti power stage has occurred. 1b: latched flag indicating a fault from ti power stage has occurred. 6 vsns_open rw current status vsns pin open 0b: latched flag indicating vsns pin was not open at power-up. 1b: latched flag indicating vsns pin was open at power-up. advance information
70 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated table 69. status_mfr_specific register field descriptions (continued) bit field type reset description 5 max_ph_warn rw current status maximum phase warning if the selected operational phase number is larger than the maximum available phase number specified by the hardware, then max_ph_warn is set, and the operational phase number is changed to the maximum available phase number. 0b: latched flag indicating no maximum phase warning has occurred. 1b: latched flag indicating a maximum phase warning has occurred. 4 tsns_low rw current status 0b: latched flag indicating that tsen < 150 mv before soft- start. 1b: latched flag indicating that tsen 150 mv before soft-start. 3 rst_vid (page 0) rw current status rst_vid (page 0 only) 0b: a vid reset operation has not occurred 1b: a vid reset operation has occurred 2:1 reserved r 00b always set to 0. 0 phflt rw current status phase current share fault. the phflt bit is set if any phase has current imbalance warnings occurring repetitively for 7 detection cycles (~500 s continuously). phases with current imbalance warnings may be read back via mfr_specific_03. 0b: no repetitive current share fault has occurred 1b: repetitive current share fault has occurred per the description in the pmbus 1.3 specification, part ii, TPSM831D31 does support clearing of status bits by writing to status registers. writing a 1 to any supported bit in this register will attempt to clear it as a fault condition. advance information
71 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the TPSM831D31 device has a very simple design procedure. all programmable parameters can be configured by pmbus and stored in nvm as the new default values to minimize external component count. this design describes a typical 3-phase, 0.85-v, 120-a application and 1-phase 1.2-v, 40-a application. 8.2 typical application the TPSM831D31 is a highly integrated, dual-output power module that supports pmbus commands. use the following design procedure to select key component values and set the appropriate behavioral options through the pmbus. figure 20. typical dual output schematic (dual outputs: vouta = 0.85 v, 120 a and voutb =1.2 v, 40 a) advance information
72 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.1 design requirements table 70. typical application specifications vouta voutb input voltage range 10.8 v ? 13.2 v output voltage 0.85 v 1.2 v i out 120 a 40 a i dyn(max) 60 a 20 a switching frequeny (f sw ) 400 khz 8.2.2 detailed design procedure for this design, the default settings inside the module are optimal for the application. the amount of input and output capacitors have been selected for operation up to full load for each output and for exceptional transient performance. 8.2.3 application performance plot the transient response waveform, figure 21 , is typical when using the specified input and output capacitors as shown figure 20 . the conditions shown in the waveform are: v in = 12 v, v out = 1 v, 60-a load step at 100a/ s. figure 21. typical transient response advance information
73 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 power supply recommendations the TPSM831D31 device is designed to operate from an input voltage supply between 8 v and 14 v. this supply must be well regulated. these devices are not designed for split-rail operation. proper bypassing of input supplies and internal regulators is also critical for noise performance, as is pcb layout and grounding scheme. 10 layout 10.1 layout guidelines ? use the recommended land pattern including the via pattern for the module footprint. 10.2 layout examples figure 22. top layer (top view) advance information
74 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated layout examples (continued) figure 23. bottom layer (top view) advance information
75 TPSM831D31 www.ti.com slusdc9 ? august 2018 product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks pmbus, d-cap+, e2e are trademarks of texas instruments. broadcom is a registered trademark of broadcom limited . cavium is a registered trademark of cavium, inc.. intel is a registered trademark of intel corporation. marvell is a registered trademark of marvell. nxp is a registered trademark of nxp semiconductors. xilinx is a registered trademark of xilinx inc.. all other trademarks are the property of their respective owners. 11.4 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. advance information
76 TPSM831D31 slusdc9 ? august 2018 www.ti.com product folder links: TPSM831D31 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 1-sep-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples pTPSM831D31moa active qfm moa 32 1 tbd call ti call ti -40 to 105 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
important notice texas instruments incorporated (ti) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. ti ? s published terms of sale for semiconductor products ( http://www.ti.com/sc/docs/stdterms.htm ) apply to the sale of packaged integrated circuit products that ti has qualified and released to market. additional terms may apply to the use or sale of other types of ti products and services. reproduction of significant portions of ti information in ti data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such reproduced documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyers and others who are developing systems that incorporate ti products (collectively, ? designers ? ) understand and agree that designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that designers have full and exclusive responsibility to assure the safety of designers ' applications and compliance of their applications (and of all ti products used in or for designers ? applications) with all applicable regulations, laws and other applicable requirements. designer represents that, with respect to their applications, designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. designer agrees that prior to using or distributing any applications that include ti products, designer will thoroughly test such applications and the functionality of such ti products as used in such applications. ti ? s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, ? 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own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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