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| plls with i nt egrated vco - s m t 1 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z functional d iag ram features ? r f bandwidth: 4 5 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z ? ma ximum phase d et ector r at e 100 m h z ? ul tra low phase n oi se -110 dbc/ h z in b and t yp . ? figure of merit (fom) -227 dbc/ h z ? <1 80 fs r m s j itter ? 24-bit s te p s iz e, r es olution 3 h z ty p ? e xa ct frequency mode ? built in d ig ital s el f t es t ? 40 lead 6x6 mm s m t p ackage: 36 mm 2 t ypical a pplications ? cellular/4 g , w im ax i nf rastructure ? r e peaters and femtocells ? communications t es t e qu ipment ? c at v e qu ipment ? phased a rra y a ppl ications ? dd s r ep lacement ? very h ig h d at a r at e r ad ios ? t un able r ef erence s ou rce for s pu rious- fre e performance for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
plls with i nt egrated vco - s m t 2 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z g eneral d es cription t he h mc834lp6 ge i s a low noise, wide band, fractional- n p hase-locked-loop (pll) that features an integrated voltage controlled oscillator (vco) with a fundamental frequency of 2800 m h z - 42 00 m h z, a nd an integrated vco output d iv ider (divide by 1/2/4/6.../60/62) and doubler, that together allow the h mc 834lp6 ge to g enerate frequencies from 45 m h z to 1050 m h z, from 1400 m h z to 2100 m h z, from 2800 m h z to 4200 m h z, and from 5600 m h z to 8400 m h z. t he i ntegrated phase d et ector (p d ) an d delta-sigma modulator, capable of operating at up to 100 m h z, p ermit wider loop-bandwidths with excellent spectral performance. t he h mc 834lp6 ge f eatures industry leading phase noise and spurious performance, across all frequencies, that enable it to minimize blocker effects, and improve receiver sensitivity and transmitter spectral purity. t he s uperior noise foor (< -170 dbc/ h z) makes the h mc 834lp6 ge an ideal source for a variety of applications - such as; lo for r f mi xers, a clock source for high-frequency data-converters, or a tunable reference source for ultra-low spurious applications. a d ditional features of the h mc 834lp6 ge i nclude r f ou tput power control from 0 to 6 db (~2 db steps), output mute function, and a delta-sigma modulator e xa ct frequency mode which enables users to generate output frequencies with 0 h z fre quency error. parameter condition min. t y p. max. units rf output characteristics output frequency band 1 45 1050 m h z ba nd 2 1400 2100 m h z b and 3 2800 4200 mhz band 4 5600 8400 m h z v co frequency at pll i np ut 2800 4200 m h z r f ou tput frequency at f vco 2800 4200 m h z output power r f output power at f vco = 4000 m h z a cr oss a l l frequencies see figure 9 s in gle-ended power broadband matched i nt ernally [1] -2 0.5 2 dbm output power control ~2 db s te ps 6 7. 5 db r f output power at f vco = 6000 m h z a cr oss a l l frequencies see figure 9 s in gle-ended power broadband matched i nt ernally [1] -11 -9 -7 dbm r f output power at f vco = 8000 m h z a cr oss a l l frequencies see figure 9 s in gle-ended power broadband matched i nt ernally [1] -13.5 -11 -8.5 dbm harmonics for fundamental mode fo mode at 4000 m h z 2n d / 3rd / 4th -25/-29/-38 dbc fo/2 mode at 4000 m h z/ 2 = 2 g h z 2n d / 3rd / 4th -25/-24/-35 dbc fo/30 mode at 2800 m h z/ 28 = 100 m h z 2n d / 3rd / 4th -20/-10/-26 dbc fo/62 mode at 2800 m h z/ 62 = 45 m h z 2n d / 3rd / 4th -14/-8/-21 dbc e lectrical specifcations vpp c p, v dd l s, v cc 1, v cc 2 = 5 v; r v dd , a v dd , d v dd 3 v, v cc p d , v cc h f, v cc ps = 3 .3 v min and max specifed across t em p -40 c t o +85 c [1] measured single-ended. a dd itional 3 db possible with differential outputs. [2] measured with 100 external termination. s ee h it tite pll w/ i nt egraged vcos operating g ui de r ef erence i np ut s ta ge section for more details. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 3 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z parameter condition min. t y p. max. units harmonics in doubler mode 2fo mode at 5600 m h z 1/ 2 / 3rd / 4th/5th -10/-22/-25/-35 dbc vco output divider vco r f d iv ider r an ge 1,2,4,6,8,...,62 1 62 pll rf divider characteristics 19-bit n - d i vider r an ge ( i nt eger) max = 2 19 - 1 16 524,287 19-bit n - d ivi der r an ge (fractional) fractional nominal divide ratio varies (-3 / +4) dynamically max 20 524,283 ref input characteristics max r ef i nput frequency 3 50 m h z r ef i np ut voltage a c co upled [2] 1 2 3.3 vp-p r ef i nput capacitance 5 pf 14-bit r - d i vider r an ge 1 16,383 phase detector (pd) [3] p d f requency fractional mode b [4] d c 10 0 m h z p d f requency fractional mode a ( and r eg ister 6 [17:16] = 11) d c 80 m h z p d f requency i nt eger mode d c 12 5 m h z charge pump output current 0.02 2.54 m a ch arge pump g ai n s te p s iz e 20 a p d /c harge pump s s b ph ase n oi se 50 m h z r ef , i np ut r ef erred 1 k h z -14 3 dbc/ h z 1 0 k h z a dd 1 d b for fractional -150 dbc/ h z 1 00 k h z a dd 3 d b for fractional -153 dbc/ h z logic inputs vsw 40 50 60 % d v dd logic outputs vo h o utput h ig h voltage d v dd v vo l output low voltage 0 v output i mpe dance 100 200 maximum load current 1.5 m a power supply voltages 3.3 v s upplies a v dd , v cc h f , vccp s , vc cp d , r v dd , d v dd 3.0 3 .3 3.5 v 5 v s up plies vppcp, v dd l s , vc c1, vcc2 4.8 5 5.2 v power supply currents +5 v a nalog charge pump v ppcp, v dd l s 8 m a e lectrical specifcations (continued) [3] s lew rate of greater or equal to 0.5 ns/v is recommended, see pll with i nt egrated r f vc os operating g ui de for more details. frequency is guaranteed across process voltage and temperature from -40 c to +85 c. [4] t hi s maximum phase detector frequency can only be achieved if the minimum n v alue is respected. eg. i n th e case of fractional feedback mode, the maximum pf d r ate = fvco/20 or 100 m h z, w hichever is less. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 4 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z e lectrical specifcations (continued) parameter condition min. t y p. max. units +5 v vco core and vco buffer fo/1 mode vcc2 105 m a fo / n m ode vcc2 80 m a +5 v v co d iv ider and r f/ pll buffer s ing le- e nd ed output mode fo/1 mode vcc1 25 m a d iff erential output mode fo/1 mode vcc1 40 m a s ing le- e nd ed output mode fo/ n m ode vcc1 80 100 m a d iff erential output mode fo/ n m ode vcc1 95 115 m a +3 .3 v a v dd , vc c h f, v ccp s , vc cp d , r v dd , d v dd 3v 52 m a po wer d ow n - crystal off r eg 0 1h=0, crystal n ot c locked 10 a po wer d ow n - crystal on, 100 m h z r eg 01h =0, crystal clocked 100 m h z 5 m a power on reset t ypical r eset voltage on d v dd 700 mv m in d v dd v oltage for n o r es et 1.5 v power on r es et d el ay 250 s vco open loop phase noise at fo @ 4 ghz 10 k h z offset -7 8 dbc/ h z 1 00 k h z of fset -108 dbc/ h z 1 m h z of fset -134.5 dbc/ h z 1 0 m h z of fset -156 dbc/ h z 1 00 m h z of fset -171 dbc/ h z vco open loop phase noise at fo @ 4 ghz/2 = 2 ghz 10 k h z offset - 83 dbc/ h z 1 00 k h z of fset -113 dbc/ h z 1 m h z of fset -139.5 dbc/ h z 1 0 m h z of fset -165.5 dbc/ h z 1 00 m h z of fset -167 dbc/ h z vco open loop phase noise at fo @ 2.8 ghz/28 = 100 mhz 10 k h z offset - 111 dbc/ h z 1 00 k h z of fset -141 dbc/ h z 1 m h z of fset -163.5 dbc/ h z 1 0 m h z of fset -170 dbc/ h z 1 00 m h z of fset -173 dbc/ h z vco open loop phase noise at 2fo @ 5.6 ghz 10 k h z offset -7 7 dbc/ h z 1 00 k h z of fset -107 dbc/ h z 1 m h z of fset -132 dbc/ h z 1 0 m h z of fset -154 dbc/ h z 1 00 m h z of fset -162 dbc/ h z for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 5 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z parameter condition min. t y p. max. units vco open loop phase noise at 2fo @ 8 ghz 10 k h z offset -7 0 dbc/ h z 1 00 k h z of fset -100 dbc/ h z 1 m h z of fset -127 dbc/ h z 1 0 m h z of fset -149 dbc/ h z 1 00 m h z of fset -162 dbc/ h z figure of merit floor i nteger mode n or malized to 1 h z -23 0 dbc/ h z f loor fractional mode n or malized to 1 h z -2 27 dbc/ h z f licker (both modes) n or malized to 1 h z -2 68 dbc/ h z vco characteristics vco t uning s en sitivity at 4053 m h z me asured at 2.5 v 15 m h z /v vco t uni ng s en sitivity at 3777 m h z me asured at 2.5 v 13 m h z /v vco t uni ng s en sitivity at 3411 m h z me asured at 2.5 v 12 m h z /v vco t uni ng s en sitivity at 2943 m h z me asured at 2.5 v 11. 5 m h z /v vco s u pply pushing measured at 2.5 v 2 m h z /v for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 6 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z figure 1. t ypi cal c los ed l oo p i nte ger phase n oise [ l oop filter c onfguration t able] figure 5. t ypical v co sensitivity -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 fout 3600 mhz, loop bw 130 khz, rms jitter 136 fs fout 5600 mhz, loop bw 130 khz, rms jitter 116 fs fout 8300 mhz, loop bw 130 khz, rms jitter 212 fs fout 3600 mhz, loop bw 250 khz, rms jitter 86 fs fout 5600 mhz, loop bw 250 khz, rms jitter 76 fs fout 8300 mhz, loop bw 250 khz, rms jitter 98 fs phase noise (dbc/hz) offset (hz) -180 -160 -140 -120 -100 -80 -60 -40 10 3 10 4 10 5 10 6 10 7 10 8 4053 mhz 3777 mhz 3411 mhz 2943 mhz offset (hz) phase noise (dbc/hz) figure 2. t ypi cal c los ed l oo p fractional phase n oise [ l oop filter c onfguration t able] figure 3. free r unning phase n oise at f0 f igure 4. free r unning v co phase n oise vs . t emperat ure 0 1 2 3 4 5 2700 2900 3100 3300 3500 3700 3900 4100 4300 tune voltage after calibration (v) vco frequency(mhz) fmin fmax -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 fout 3605 mhz, loop bw 130 khz, rms jitter 145 fs fout 5605 mhz, loop bw 130 khz, rms jitter 123 fs fout 8305 mhz, loop bw 130 khz, rms jitter 227 fs fout 3605 mhz, loop bw 250 khz, rms jitter 110 fs fout 5605 mhz, loop bw 250 khz, rms jitter 95 fs fout 8305 mhz, loop bw 250 khz, rms jitter 112 fs offset (hz) phase noise (dbc/hz) 0 10 20 30 40 50 60 70 012345 4053 mhz at 2.5v, tuning cap 7 3777 mhz at 2.5v, tuning cap 7 3411 mhz at 2.5v, tuning cap 15 2943 mhz at 2.5v, tuning cap 15 tuning voltage (v) kvco (mhz/v) figure 6. t ypical t uning v oltage a f ter c alibr ation at f0 -180 -160 -140 -120 -100 -80 10 100 1000 10000 27c -40c 85c phase noise (dbc/hz) frequency (mhz) 100 mhz offset 1 mhz offset 100 khz offset for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 7 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z figure 7. i nte grated r ms j itter [1] [1] r m s j itter data is measured in fractional mode with 250 k h z lo op bandwidth using 100 m h z re ference, p d 5 0 m h z. i nt egration bandwidth from 1 k h z to 1 00 m h z. [ 2] measured from a 50 source with a 100 external resistor termination. s ee pll with i ntegrated r f v cos operating g ui de r ef erence i np ut s ta ge section for more details. full fom performance up to maximum 3.3 vpp input voltage. [3] measured from a 50 source with a 100 external resistor termination. s ee pll with i ntegrated r f v cos operating g ui de r eference i np ut s tag e section for more details. full fom performance up to maximum 3.3 vpp input voltage. 40 60 80 100 120 140 160 180 200 10 100 1000 10000 -40c 27c 85c rms jitter (fs) frequency (mhz) -240 -230 -220 -210 -200 10 2 10 3 10 4 10 5 10 6 normalized phase noise (dbc/hz) frequency offset (hz) fom floor fom 1/f noise typ fom vs offset figure 8. figure of merit figure 9. t ypical o utput p ower vs. t emperat ure, maximum g ain f igure 10. r f o utput r etur n l oss -235 -230 -225 -220 -215 -15 -10 -5 0 5 10 14 mhz sq 25 mhz sq 50 mhz sq 100 mhz sq floor fom (dbc/hz) reference power (dbm) 100 mhz 14 mhz 50 mhz 25 mhz figure 12. r efer ence i nput sensiti vity, square w av e, 50 [2] -15 -10 -5 0 5 10 0 1000 2000 3000 4000 5000 6000 7000 8000 27 c -40 c 85 c output power (dbm) offset (mhz) figure 11. r efer ence i nput sensiti vity sinusoid w av e, 50 [3] -235 -230 -225 -220 -215 -210 -205 -200 -20 -15 -10 -5 0 5 reference power (dbm) floor fom (dbc/hz) 14 mhz 25 mhz 50 mhz 100 mhz -30 -25 -20 -15 -10 -5 0 100 1000 10000 frequency (mhz) return loss(db) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 8 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z figure 13. i nte ger boundary spur at 3600.2 m h z [4] -180 -160 -140 -120 -100 -80 -60 -40 -20 0 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) [4] fractional mode mode b, i nt eger boundary s pu r, loop filter bandwidth 130 k h z, r e f in 1 00 m h z, 5 0 m h z p d [5 ] r e f in 1 00 m h z, 5 0 m h z p d , ou tput d iv ider 4 s el ected, loop filter bandwidth 130 k h z, c hannel s pa cing 100 k h z [6] e xa ct frequency mode, r e f in 1 00 m h z, 5 0 m h z p d , ou tput d iv ider 2 s el ected, loop filter bandwidth = 130 k h z, c hannel s pa cing = 100 k h z [7 ] e xa ct frequency mode, channel s pa cing 100 k h z, r f ou t = 3951 m h z, r e f in 1 00 m h z, 5 0 m h z p d , ou tput d iv ider 1 selected, loop filter bandwidth 130 k h z, [ 8] fractional mode b, r f ou t 3591 m h z, r e f in 1 00 m h z, 5 0 m h z p d , ou tput d iv ider 1 selected, loop filter bandwidth 130 k h z. -180 -160 -140 -120 -100 -80 -60 -40 -20 0 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) figure 14. i nte ger boundary spur at 8300.8 m h z [4] -180 -160 -140 -120 -100 -80 -60 -40 -20 0 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) figure 15. i nt eger- n , e x act frequency mode o n , pe rformance at 900 m h z [5] figure 16. fractional- n , e xa ct frequency mode o n , pe rformance at 1813.5 m h z [6] figure 17. fractional- n , e xa ct frequency mode o n , pe rformance at 3591 m h z [7] -180 -160 -140 -120 -100 -80 -60 -40 -20 0 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) figure 18. fractional- n , e xa ct frequency mode o ff , performance at 3591 m h z [8] for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 9 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z loop filter b w (k h z) c1 (pf) c2 (nf) c3 (pf) c4 (pf) r 2 (k ) r 3 (k ) r 4 (k ) loop filter d esign 13 0 100 8.2 120 120 1 1.2 1.2 250 150 3.3 18 18 2.2 1 1 l oop filter c on fguration t ab le figure 19. w or st spur, fixed 50 m h z r ef erence, o ut put freq. = 3900.1 m h z [9] -180 -160 -140 -120 -100 -80 -60 -40 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) figure 20. w or st spur, t una ble r ef erence 47.5 m h z, o ut put frequency = 3900.1 m h z [9] -180 -144 -108 -72 -36 0 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) figure 21. w or st spur, fixed vs. t una ble r efer ence [10] -110 -100 -90 -80 -70 -60 -50 3.9ghz +10 3 hz 3.9ghz +10 4 hz 3.9ghz +10 5 hz 3.9ghz +10 6 hz 3.9ghz +10 7 hz fixed 50 mhz reference tunable reference worst spur (dbc) output frequency [9] capability of h mc 834lp6 ge t o generate low frequencies (as low as 45 m h z) , enables the h mc 834lp6 ge t o be used as a tunable reference source into another h it tite pll. t hi s maximizes spur performance of h it tite plls. please see h mc 834lp6 ge a ppl ication i nf ormation for more information. [10] t he g raph is generated by observing, and plotting, the magnitude of only the worst spur (largest magnitude), at any offset, at each output frequency, while using a fxed 50 m h z re ference and a tunable reference tuned to 47.5 m h z. s ee h mc 834lp6 ge a ppl ication i nf ormation for more details. [11] phase noise performance of the h mc 834lp6 ge w hen used as a tunable reference source. h mc 834lp6 ge i s operating at 4.2 g h z/ 42, 4.2 g h z/ 56, and 2.8 g h z/ 62 for the 100 m h z, 7 5 m h z, a nd 45.16129 m h z cu rves respectively, using a second order loop flter with 230 k h z ba ndwidth. figure 22. l ow f requency performance [11] -170 -160 -150 -140 -130 -120 10 2 10 3 10 4 10 5 10 6 10 7 10 8 carrier frequency 45.16129 mhz carrier frequency = 75 mhz carrier frequency = 100 mhz phase noise (dbc/hz) offset (hz) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 10 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z pin d escriptions pin n umber fu nction d es cription 1 a v dd d c po wer s up ply for analog circuitry. 2, 5, 6, 8, 9, 11 - 14, 18 - 22, 24, 26, 29, 34, 37, 38 n /c t he p ins are not connected internally; however, all data shown herein was measured with these pins connected to r f/ d c gr ound externally. 3 vppcp power s u pply for charge pump analog section 4 cp charge pump output 7 v d d l s po wer s up ply for the charge pump digital section 10 r v dd r ef erence s u pply 15 x re f p r e ference oscillator i np ut 16 d v dd 3v d c po wer s up ply for d ig ital (cmo s ) ci rcuitry 17 c en ch ip e na ble. connect to logic high for normal operation. 23 v t u ne vc o varactor. t un ing port i np ut. 25 vcc2 vco a nalo g s u pply 2 27 vcc1 vco a nalo g s u pply 1 28 r f_ n r f n eg ative output (on in differential and single-ended confguration) 30 sen pl l s er ial port e na ble (cmo s ) lo gic i np ut 31 sdi pl l s er ial port d at a (cmo s ) lo gic i np ut 32 s c k pll s er ial port clock (cmo s ) lo gic i np ut 33 l d _ sd o lo ck d et ect, or s er ial d at a, or g en eral purpose (cmo s ) lo gic output ( g po ) 35 vcc h f d c p ower s u pply for a nalo g circuitry 36 vccp s d c po wer s up ply for a na log prescaler 39 vccp d d c po wer s up ply for phase d et ector 40 b ias e xt ernal bypass decoupling for precision bias circuits. n ot e: 1.920v 20mv reference voltage (b ia s ) is g enerated internally and cannot drive an external load. must be measured with 10 g me ter such as a gi lent 34410 a , no rmal 10m d vm w ill read erroneously. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 11 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z o utline d rawing part n umber pa ckage body material lead finish m s l r ati ng package marking [1] h mc834lp6 ge r o hs -c ompliant low s tr ess i nj ection molded plastic 100% matte s n m s l 1 h 834 xxxx [ 1] 4- d ig it lot number xxxx package i nf ormation n o tes : 1 . p a ck ag e b o d y m at eria l: l o w s tress i n j e c ti o n m ol de d p l as ti c s i l i c a an d s i l i co n i mp re gnated . 2. l ea d a nd g r ou nd p add l e m at eria l: copp er a ll oy. 3. l ea d a nd g r ou nd p ad d l e p l at ing : 10 0% m at te t in . 4. d i m en si o ns a re i n i n c he s [ m i ll i m et ers ]. 5 . l ea d s p a c in g t o l er an c e i s n o n -c umul at i v e . 6. p ad b u rr l en gth s ha ll b e 0 .15mm m a x. p ad b u rr h eight s ha ll b e 0 .25mm m a x. 7 . p a ck ag e w ar p s ha ll n o t e xc ee d 0 .05mm. 8. a ll g r ou nd l ea ds a nd g r ou nd p ad d l e m u st b e s ol de red t o p cb r f gr ou nd . 9 . r e f er t o h ittite a pp l i c at i o n n o t e f o r s u gg ested p cb l an d p at tern . a bsolute maximum r ati ngs a v dd , r v dd , d v dd 3v , vccp d , vcc h f, vccp s -0 .3v to +3.6v vppcp, v dd l s , vc c1, vcc2 -0.3v to +5.5v operating t em perature -40 c to +85c s to rage t em perature -65 c to 150c maximum junction t em perature 125 c t h ermal r es istance ( r th ) (junction to ground paddle) 20 c/ w r efo w s olde ring peak t em perature 260c t im e at peak t em perature 40 sec es d s en sitivity ( h bm ) class 1b s tresses above those listed under a bsolute maximum r atings may cause permanent damage to the device. t his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. e xposure to absolute maximum rating conditions for extended periods may affect device reliability. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 12 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z e valuation p c b s chematic t he circuit board used in the application should use r f ci rcuit design techniques. s ig nal lines should have 50 ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. a s ufficient number of via holes should be used to connect the top and bottom ground planes. t he e valuation circuit board shown is available from h it tite upon request. to view this e valuation pcb s ch ematic please visit www.hittite.com and choose HMC834LP6GE from the search by part number pull down menu to view the product splash page. e valuation p c b i tem c ontents part n um ber e val uation pcb only h mc8 34lp6 ge e va luation pcb e v a l01 - h mc 834lp6 ge e va luation kit h mc8 34lp6 ge e va luation pcb u s b i nt erface board 6 u s b a m ale to u s b b fe male cable c d r om ( contains user manual, e va luation pcb s ch ematic, e va luation s of tware, h i ttite pll d esign s o ftware) e k it 01 - h mc 834lp6 ge e valuation o rde r i nf ormation for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 13 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z h m c 834 l p6 ge a ppli cation i nf ormation large bandwidth, industry leading phase noise and spurious performance, excellent noise foor (<-170 dbc/ h z) , coupled with a high level of integration make the h mc 834lp6 ge i deal for a variety of applications; as an r f or i f st age lo, a clock source for high-frequency data-converters, or a tunable reference source for extremely low spurious applications (~ -100 dbc/ h z sp urs). figure 23. HMC834LP6GE in a typical transmit chain figure 24. HMC834LP6GE in a typical receive chain figure 25. HMC834LP6GE used as a tunable reference for second HMC834LP6GE using the h mc 834lp6 ge w ith a tunable reference as shown in figure 25 , it is possible to drastically improve spurious emissions performance across all frequencies. e xa mple shown in figure 21 graph shows that it is possible to have spurious emissions ~ -100 dbc/ h z ac ross all frequencies. for more information about spurious emissions, how they are related to the reference frequency, and how to tune the reference frequency for optimal spurious performance please see the s pu rious performance section of h it tite pll w/ i nt egraged vcos operating g ui de . n ot e that at very low output frequencies < 100 m h z, h armonics increase due to small internal a c co upling. a pp lications which are sensitive to harmonics may require external low pass fltering. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 14 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z t he output of the h mc 834lp6 ge i s matched to 50 across all output frequencies from 45 m h z to 84 00 m h z wi th gap. a s a re sult of the wideband 50 match, the output power of the h mc 834lp6 ge d ecreases with increas- ing output frequency, as shown in figure 9 . i f re quired, it is possible to adjust the output stage gain setting of the h mc 834lp6 ge ( vco_ r eg 02h biases) at various operating frequencies in order to achieve a more constant output power level across the frequency operating range of the h mc 834lp6 ge . a n ex ample is shown in figure 26 . figure 26. reducing the output power variation of HMC834LP6GE across frequency by adjusting output stage gain control. i f a higher output po wer than that shown in figure 26 is required, it is possible to follow the h mc834lp6 ge output st age with a simple amplifer such as h m c 311 s c7 0 e in order t o achieve a constant and high output power level across the entire operating range of the h mc834lp6 ge . o utp ut gain setting for o ptimal p ower flatness -20 -10 0 10 0 1000 2000 3000 4000 5000 6000 7000 8000 output power (dbm) output frequency (mhz) gain = 0 db gain = 9 db gain = 3 db divider output stage gain = 3 db (vco_reg02h[8] = 1) gain = 0 db for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 15 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.0 t heo ry of o pe ration h mc834lp6 ge i s targeted for ultra low phase noise applications and has been designed with very low noise reference path, phase detector and charge pump. t h e h mc8 34lp6 ge co nsists of the following functional blocks: 1. r ef erence path i np ut buffers and r d iv ider 2. vco path i np ut buffer and multi-modulus n d iv ider 3. ? fractional modulator 4. phase d et ector 5. charge pump 6. s er ial port with r ea d w ri te capability 7. g en eral purpose output ( g po ) port 8. power on r es et circuit 9. vco s ub system 10. built- i n s el f t es t features 1.1 v co su bsystem t he h mc834lp6 ge c ontains a vco subsystem that can be confgured to operate in: ? fundamental frequency (fo) mode (2800 m h z to 42 00 m h z) . ? d iv ide by n ( fo/ n ), w here n = 1 ,2,4,6,8...58,60,62 mode (45 m h z to 14 00 m h z an d 1400 m h z to 21 00 m h z wi th gap). ? d ou bler (2fo) mode (5600 m h z to 84 00 m h z) . a ll m odes are vco register programmable as shown in figure 27 . one loop flter design can be used for the entire frequency of operation of the h mc 834lp6 ge . fi gure 27. pll and vco subsystems for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 16 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.2 v co c alibr ation 1.2.1 v co a ut o- c alibr ation ( a ut o c al) h mc834lp6 ge u ses a step tuned type vco. a s implifed step tuned vco is shown in figure 28 . a s tep tuned vco is a vco with a digitally selectable capacitor bank allowing the nominal center frequency of the vco to be adjusted or stepped by switching in/out vco tank capacitors. a m ore detailed view of a typical vco subsystem confguration is shown in figure 29 . a s tep tuned vco allows the user to center the vco on the required output frequency while keeping the varactor tuning voltage optimized near the mid-voltage tuning point of the h mc 834lp6 ge s c harge pump. t hi s enables the pll charge pump to tune the vco over the full range of operation with both a low tuning voltage and a low tuning sensitivity (kvco). t he vco switches are normally controlled automatically by the h mc 834lp6 ge using the a uto -calibration feature. t he a uto -calibration feature is implemented in the internal state machine. i t ma nages the selection of the vco sub-band (capacitor selection) when a new frequency is programmed. t he v co switches may also be controlled directly via register r eg 0 5h for testing or for other special purpose operation. other control bits specifc to the vco are also sent via r eg 0 5h . figure 28. simplifed step tuned vco figure 29. HMC834LP6GE pll and vco subsystems t o us e a step tuned vco in a closed loop, the vco must be calibrated such that the h mc 834lp6 ge k nows which switch position on the vco is optimum for the desired output frequency. t he h mc 834lp6 ge s upports a uto -calibration ( a uto cal) of the step tuned vco. t he a uto cal fxes the vco tuning voltage at the optimum mid-point of the charge pump output, then measures the free running vco frequency while searching for the setting which results in the free running output frequency that is closest to the for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 17 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z desired phase locked frequency. t hi s procedure results in a phase locked oscillator that locks over a very narrow voltage range on the varactor. a t ypical tuning curve for a step tuned vco is shown in figure 30 . n ot e how the tuning voltage stays in a narrow range over a wide range of output frequencies. 0 1 2 3 4 5 920 960 1000 1040 1080 1120 1160 calibration frequency (mhz) tune voltage after calibration (v) 50mhz pfd, 500khz tuning steps, +25c 256 count calibration ,195khz resolution 31usec total cal time 0 15 31 figure 30. a typical 5-bit 32 switch vco tuning voltage after calibration t he c alibration is normally run automatically once for every change of frequency. t hi s ensures optimum selection of vco switch settings vs. time and temperature. t he u ser does not normally have to be concerned about which switch setting is used for a given frequency as this is handled by the a uto cal routine. t he a ccuracy required in the calibration affects the amount of time required to tune the vco. t he c alibration routine searches for the best step setting that locks the vco at the current programmed frequency, and ensures that the vco will stay locked and perform well over its full temperature range without additional calibration, regardless of the temperature that the vco was calibrated at. a uto -calibration can also be disabled allowing manual vco tuning. r ef er to section 1.2.2 for a description of manual tuning 1.2.1.1 a ut o c al u se of r eg 05h a utocal transfers switch control data to the vco subsystem via r eg 05h . t he address of the vco subsystem in r eg 0 5h is not altered by the a uto cal routine. t he a ddress and i d o f the vco subsystem in r eg 0 5h must be set to the correct value before a uto cal is executed. for more information see section 1.19 . 1.2.1.2 a ut o-re l ock o n l ock d et ect failure i t is possible by setting r eg 0 7h [13] to have the vco subsystem automatically re-run the calibration routine and re-lock itself if lock d et ect indicates an unlocked condition for any reason. w it h this option the system will attempt to re-lock only once. a uto -relock is recommended. 1.2.2 manual v co c alibr ation for fast frequency h op ping i f it is desirable to switch frequencies very quickly it is possible to eliminate the a uto cal time by calibrating the vco in advance and storing the switch number vs frequency information in the host. t hi s can be done by initially locking the pll with i nt egrated vco on each desired frequency using a uto cal, then reading, and storing the vco switch settings selected. t he v co switch settings are available in r eg 10h [7:0] after every a uto cal operation. t he h ost must then program the vco switch settings directly when changing frequencies. manual writes to the vco switches are executed immediately as are writes to the integer and fractional registers when a uto cal is disabled. h en ce frequency changes with manual control and a uto cal disabled, requires a minimum of two serial port transfers to the pll, once to set the vco switches, and once to set the pll frequency. i f a uto cal is disabled r eg 0 a h [ 11]=1 , the vco will update its registers with the value written via r eg 0 5h for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 18 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z immediately. t he v co internal transfer requires 16 v s ck clock cycles after the completion of a write to r eg 0 5h . v s ck a nd the a uto cal controller clock are equal to the input reference divided by 0, 4,16 or 32 as controlled by r eg 0 a h [ 14:13] . 1.2.2.1 r eg isters required for frequency c ha nges in fractional mode a large change of frequency, in fractional mode ( r eg 0 6h [11]=1 ), may require main s er ial port writes to: 1. th e integer register intg, r eg 0 3h (only required if the integer part changes) 2. th e vco s p i r egister, r eg 0 5h ? required for manual control of vco if r eg 0 a h [ 11]=1 (autocal disabled) ? required to change the r f d iv ider value if needed ( vco_ r eg 02h ) ? required to turn on/off the doubler mode if needed ( vco_ r eg 03h [0]) 3. the fractional register, r eg 04h . t he fractional register write triggers a uto cal if r eg 0 a h [ 11]= 0 , and is loaded into the modulator automatically after a uto cal runs. i f a uto cal is disabled, r eg 0 a h [ 11]=1 , the fractional frequency change is loaded into the modulator immediately when the register is written with no adjustment to the vco. s ma ll steps in frequency in fractional mode, with a uto cal enabled ( r eg 0 a h [ 11]= 0 ), usually only require a single write to the fractional register. w or st case, 5 main s er ial port transfers to the h mc 834lp6 ge c ould be required to change frequencies in fractional mode. i f th e frequency step is small and the integer part of the frequency does not change, then the integer register is not changed. i n al l cases, in fractional mode, it is necessary to write to the fractional register r eg 0 4h for frequency changes. 1.2.2.2 r eg isters r eq uired for frequency c ha nges in i nt eger mode a change of frequency, in integer mode ( r eg 0 6h [11]= 0) , requires main s er ial port writes to: 1. vc o s p i r egister, r eg 0 5h ? required for manual control of vco if r eg 0 a h [ 11]=1 (autocal disabled) ? required to change the r f d iv ider value if needed ( vco_ r eg 02h ) ? required to turn on/off the doubler mode if needed ( vco_ r eg 03h [0]) 2. th e integer register r eg 0 3h . ? i n i nteger mode, an integer register write triggers a uto cal if r eg 0 a h [ 11]= 0 , and is loaded into the prescaler automatically after a uto cal runs. i f a uto cal is disabled, r eg 0 a h [ 11]=1 , the integer frequency change is loaded into the prescaler immediately when written with no adjustment to the vco. n or mally changes to the integer register cause large steps in the vco frequency, hence the vco switch settings must be adjusted. a uto cal enabled is the recommended method for integer mode frequency changes. i f a uto cal is disabled ( r eg 0 a h [ 11]=1 ), a priori knowledge of the correct vco switch setting and the corresponding adjustment to the vco is required before executing the integer frequency change. 1.2.3 v co a ut o c al o n frequency c ha nge a ssuming r eg 0 a h [ 11]= 0 , the vco calibration starts automatically whenever a frequency change is requested. i f it i s desired to rerun the a uto cal routine for any reason, at the same frequency, simply rewrite the frequency change with the same value and the a uto cal routine will execute again without changing fnal frequency. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 19 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.2.4 v co a ut o c al t im e & a cc uracy t he vco frequency is counted for t mmt , the period of a single a uto cal measurement cycle. t mmt = t xtal r 2 n ( e q 1) n is s et by r eg 0 a h [ 2:0] and results in measurement periods which are multiples of the p d pe riod, t xtal r . r is th e reference path division ratio currently in use, r eg 0 2h t xtal is the period of the external reference (crystal) oscillator. t he v co a uto cal counter will, on average, expect to register n c ounts, rounded down (foor) to the nearest integer, every p d c ycle. n is t he ratio of the target vco frequency, f vco , to the frequency of the p d , f pd , where n can be a ny rational number supported by the n d ivider. n i s set by the integer ( n int = r eg 03h ) a nd fractional ( n frac = r eg 04h ) register contents n = n int + n frac / 2 24 ( e q 2) t he a uto cal state machine and the data transfers to the internal vco subsystem s p i ( v s p i ) ru n at the rate of the f s m cl ock, t fsm , where the f s m cl ock frequency cannot be greater than 50 m h z. t fsm = t xtal 2 m ( e q 3) m is 0 , 2, 4 or 5 as determined by r eg 0 a h [ 14:13] t he e xpected number of vco counts, v, is given by v = foor (n 2 n ) ( e q 4) t he n ominal vco frequency measured, f vcom , is given by f vcom = v f xtal / (2 n r) ( e q 5) w here the worst case measurement error, f err , is: f err f pd / 2 n + 1 ( e q 6) figure 31. vco calibration a 5 -bit step tuned vco, for example, nominally requires 5 measurements for calibration, worst case 6 measurements, and hence 7 v s p i d ata transfers of 20 clock cycles each. t he m easurement has a programmable number of wait states, k, of 100 f s m cy cles defned by r eg 0 a h [ 7:6] = k. h en ce total calibration time, worst case, is given by: t cal = k100t fsm + 6t pd 2 n + 7 20t fsm ( e q 7) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 20 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z or equivalently t cal = t xtal (6r 2 n + (140+100k) 2 m ) where k = r eg 0 a h [ 7:6] decimal ( e q 8) f or guaranteed hold of lock, across temperature extremes, the resolution should be better than 1/8 th the frequency step caused by a vco sub-band switch change. better resolution settings will show no improvement. 1.2.4.1 v co a ut o c al e xam ple t he vco subsystem must satisfy the maximum f pd limited by the two following conditions: a. n 1 6 (f int ), n 20.0 (f frac ), where n = f vco/ f pd b. f pd 100 m h z s up pose the vco subsystem output frequency is to operate at 2.01 gh z. our example crystal frequency is f xtal = 50 mhz, r=1, and m=0 ( figure 31 ) , hence t fsm = 20 ns (50 m h z) . n ot e, when using a uto cal, the maximum a uto cal finite s ta te machine (f s m) clock cannot exceed 60 m h z ( see r eg 0 a h [ 14:13] ). t he f s m cl ock does not affect the accuracy of the measurement, it only affects the time to produce the result. t hi s same clock is used to clock the 16 bit vco serial port. i f ti me to change frequencies is not a concern, then one may set the calibration time for maximum accuracy, and therefore not be concerned with measurement resolution. using an input crystal of 50 m h z ( r =1 a nd fpd=50 m h z) t he times and accuracies for calibration using ( e q 6) a nd ( e q 8) a re shown in t able 1 . w he re minimal tuning time is 1/8 th of the vco band spacing. a cr oss all vcos, a measurement resolution better than 800 k h z wi ll produce correct results. s et ting m = 0, n = 5, provides 781 k h z of r esolution and adds 8.6 s of a uto cal time to a normal frequency hop. once the a uto cal sets the fnal switch value, 8.64 s after the frequency change command, the fractional register will be loaded, and the loop will lock with a normal transient predicted by the loop dynamics. h en ce we can see in this example that a uto cal typically adds about 8.6 s to the normal time to achieve frequ- ency lock. h en ce, a uto cal should be used for all but the most extreme frequency hopping requirements. t able 1. a ut o c al e xa mple with f xtal = 50 m h z, r = 1 , m = 0 control value reg0ah[2:0] n 2 n t mmt ( s) t cal ( s) f err max 0 0 1 0.02 4.92 25 m h z 1 1 2 0.0 4 5.04 12.5 m h z 2 2 4 0.0 8 5.28 6.25 m h z 3 3 8 0.1 6 5.76 3.125 m h z 4 5 32 0.6 4 8.64 781 k h z 5 6 64 1.2 8 12.48 390 k h z 6 7 128 2. 56 20.16 195 k h z 7 8 256 5 .12 35.52 98 k h z 1.2.5 v co o ut put mute function t he output mute function enables the h mc 834lp6 ge to d isable the vco output while maintaining the pll and vco subsystems fully functional. t he m ute function provides over 40 db of isolation throughout the operating range of the h mc 834lp6 ge . t o mu te the output of the h mc 834lp6 ge , th e following register writes are necessary: 1. vc o_ r eg 0 3h [ 2] = 1, to place the vco subsystem in manual mode 2. vco _ r eg 01h [2] = 1, to disable the vco subsystem output buffer 3. vco _ r eg 01h [ 3] = 0, to disable the vco subsystem limiter. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 21 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z please note that the vco subsystem registers are not directly accessible. t he y are written to via pll r eg 0 5h . more information about vco subsystem s p i i n section 1.19 . 1.3 v co b uilt in t es t with a ut o c al t he frequency limits of the vco can be measured using the b is t f eatures of the a uto cal machine. t hi s is done by setting r eg 0 a h [ 10]=1 which freezes the vco switches in one position. vco switches may then be written manually, with the varactor biased at the nominal mid-rail voltage used for a uto cal. for example to measure the vco maximum frequency use switch 0, written to the vco subsystem via r eg 0 5h =[000000000 0000 vco id ]. w he re vco id = 000b. i f a uto cal is enabled, ( r eg 0 a h [ 11] = 0), and a new frequency is written, a uto cal will run, but with switches frozen. t he v co frequency error relative to the command frequency will be measured and results written to r e g 11h [19:0] where r e g 11h [19] is the sign bit. t he r esult will be written in terms of vco count error ( e q 4) . f or example if the expected vco is 2 g h z, r eference is 50 m h z, a nd n is 6, we expect to measure 2560 counts. i f we m easure a difference of -5 counts in r e g 11h , then it means we actually measured 2555 counts. h en ce the actual frequency of the vco is 5/2560 low, or 1.99609375 g h z, 1 count ~ 781 k h z. 1.4 spurious performance 1 .4.1 i nt eger o pe ration and r e ference spurious t he vco always operates at an integer multiple of the p d fr equency in an integer synthesizer. i n ge neral, spurious signals originating from an integer synthesizer can only occur at multiples of the p d fr equency. t he se unwanted outputs closest to the carrier are often simply referred to as reference sidebands. unwanted reference harmonics can also exist far from the carrier due to circuit isolation. s pu rs unrelated to the reference frequency must originate from outside sources. e xt ernal spurious sources can modulate the vco indirectly through power supplies, ground, or output ports, or bypass the loop flter due to poor isolation of the flter. i t ca n also simply add to the output of the pll. r ef erence spuri ou s levels are typically below -100 dbc with a well designed board layout. a r egulator with low noise and high power supply rejection, such as the h mc 1060lp3 e , i s recommended to minimize external spurious sources. r ef erence spurious levels of below -100 dbc require superb board isolation of power supplies, isolation of the vco from the digital switching of the synthesizer and isolation of the vco load from the synthesizer. t yp ical board layout, regulator design, eval boards and application information are available for very low spurious operation. operation with lower levels of isolation in the application circuit board, from those rec - om mended by h it tite, can result in higher spurious levels. i f th e application environment contains other interfering frequencies unrelated to the p d fr e qu ency, and if the application isolation from the board layout and regulation are insufficient, the unwanted interfering frequencies will mix with the desired synthesizer output and cause additional spurious emissions. t he level of these emissions is dependant upon isolation and supply regulation or rejection (p sr r ). 1.4.2 fractional o pe ration and spurious unlike an integer pll, spurious signals in a fractional pll can occur due to the fact that the vco operates at frequencies unrelated to the p d fr equency. h en ce intermodulation of the vco and the p d h armonics can cause spurious sidebands. s pu rious emissions are largest when the vco operates very close to an integer multiple of the p d . w he n the vco operates exactly at a harmonic of the p d t hen, no in-close mixing products are present. a s s hown in figure 32 , interference is always present at multiples of the p d frequency, f pd , and the vco frequency, f vco . t he difference, , between the vco frequency and the nearest har mo nic of the reference, will create what are referred to as integer boundary spurs. d ep ending upon the mode of operation of for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 22 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z the synthesizer, higher order, lower power spurs may also occur at multiples of integer fractions (sub- harmonics) of the p d fr equency. t ha t is, fractional vco frequencies which are near nf pd + f pd d/m, where n, d and m are all integers and d plls with i nt egrated vco - s m t 23 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z t he specifc level of charge pump offset current r eg 09h [20:14] is determined by this time offset, the comparison frequency and the charge pump current: ( ) ( ) ( ) 9 2.5 10 4 sec ,0.25 required cp offset min vco comparison cp cp t fi i ? ?? ? +? ? ? ? ?? ?? = where: t vco : is the rf period at the fractional prescaler input i cp : is the full scale current setting of the switching charge pump r eg 09h [6:0] r eg 09h [13:7] ( e q 9) o peration with charge pump offset infuences the required confguration of the lock d et ect function. r ef er to the description of lock d et ect function in section 1.11 . n ot e that this calculation can be performed for the center frequency of the vco, and does not need refnement for small differences < 25 % in center frequencies. a no ther factor in the spectral performance in fractional mode is the choice of the d el ta- s ig ma modulator mode. mode a c an offer better in-band spectral performance (inside the loop bandwidth) while mode b offers better out of band performance. s ee r eg 0 6h [3:2] for d s m mo de selection. finally, all fractional synthesizers cre at e fractional spurs at some level. h it tite offers the lowest level fractional spurious in the indus tr y in an integrated solution. 1.4.2.2 spurious r el ated to c ha nnel step size ( c ha nnel spurs) many fractional plls also create spurious emissions at offsets which are multiples of the channel step size. w e re fer to these as channel s pu rs. i t is c ommon in the industry to set the channel step size by use of the so-called modulus. for example, channel step size of 100 k h z re quires a small modulus related to the step size, and often results in 100 k h z ch annel s pu rs. t he h mc 834lp6 ge u ses a large fxed modulus unrelated to the channel step size. a s a re sult, the h mc 834lp6 ge h as extremely low or unmeasurable channel s pu rs. i n ad dition e xa ct frequency mode ( 1.12.2.2 ) allows exact channel step size with no channel s pu rs. t he l ack of channel s pu rs means that the h mc 834lp6 ge h as large regions of operation between i nt eger boundaries with little or no spurs of any kind. large spurious free zones enable the h mc 834lp6 ge to b e used with a tunable reference, to effectively move the spur free zones and hence achieve spur-free operation at all frequencies. t he r esulting pll is virtually spur-free at all frequencies. for more information see 1.4.2.3 . 1.4.2.3 spurious r e duction with t un able r e ference s ection 1. 4.2 discussed fractional mode i nt eger boundary spurious caused by vco operation near reference harmonics. i t is p ossible, with h it tite fractional synthesizers, to virtually eliminate the integer boundary spurious at a given vco frequency by changing the frequency of the reference. t he r eference frequency is normally generated by a crystal oscillator and is not tunable. h ow ever, h it tite wideband plls with i nt egrated vcos, including h mc 834lp6 ge , ca n be used as a high-quality tunable reference source, as shown in figure 33 . figure 33. t unable reference source w it h the setup shown in figure 33 , the h mc 834lp6 ge i s capable of operating across all of its frequency range without sacrifcing phase noise, while virtually eliminating spurious emissions. optimum operation requires appropriate confguration of the two synthesizers to achieve this performance. h it tite apps-support can assist with the required algorithms for ultra-low spurious tunable reference applications. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 24 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z a n h mc830lp6 ge t unable reference pll typically uses a high frequency crystal reference for best performance. phase noise from the mc830lp6 ge t unable reference output at 100 k h z of fset varies typically from -145 dbc at 100 m h z ou tput to -157 dbc at 25 m h z ou tput. t hi s performance of h mc 830lp6 ge a s a tunable reference is equivalent to the phase noise of high performance crystal oscillators. figure 34. phase noise performance of the hmc833lp6ge -170 -160 -150 -140 -130 -120 0.1 1 10 100 1000 10000 100000 carrier frequency = 25 mhz carrier frequency = 55.55 mhz carrier frequency = 100 mhz phase noise (dbc/hz) offset (khz) when used with a tunable reference source. (hmc833lp6ge operating at 3 ghz/30, 3 ghz/54, and 1.55 ghz/62 for the 100 mhz, 55.55 mhz, and 25 mhz curves respectively.) w or st case spurious levels (largest spurs at any offset) of conventional fxed reference vs. a tunable reference can be compared by multiple individual phase noise measurements and summarized on a single plot vs. carrier frequency. for example, figure 35 shows the spectrum of a carrier operating at 2000.1 m h z wi th a 50 m h z fx ed reference. t hi s case is 100 k h z aw ay from an i nt eger boundary (50 m h z x 40 ). w or st case spurious can be observed at 100 k h z of fset and about -52 dbc in magnitude. figure 36 shows the same h mc 834lp6 ge p ll vco operating at the same 2000.1 m h z ca rrier frequency, using a tunable reference at 47.5 m h z ge nerated by h mc 830lp6 ge . w or st case spurious in this case can be observed at 5 m h z of fset and about -100 dbc in magnitude. t he r esults of figure 35 and figure 36 show that the tunable reference source achieves 50 db better spurious performance, while maintaining essentially the same phase noise performance. -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) (a) 2000.1 mhz carrier frequency worst spur at 100 khz offset at ~-52 dbc with 50 mhz crystal -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) (b) 2000.1 mhz carrier frequency worst spur at 5 khz offset at -100 dbc with tunable crystal figure 35. HMC834LP6GE worst spur at any offset, fxed 50 mhz reference, output frequency = 2000.1 mhz figure 36. HMC834LP6GE worst spur at any offset, tunable reference (hmc830lp6ge), output frequency = 2000.1 mhz many spurious measurements, such as the ones in figure 35 and figure 36 can be summarized into a single plot of worst case spurious at any offset vs. carrier frequency as shown in figure 37 . a l og frequency display relative to the 2000 m h z fx ed reference i nt eger boundary was used to emphasize the importance for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 25 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z of the loop bandwidth on spurious performance of the fxed reference case. t hi s technique clearly shows the logarithmic roll-off of the worst case spurious when operating near the i nt eger boundary. i n th is case the loop flter bandwidth of the h mc 834lp6 ge w as 100 k h z. f igure 37. -120 -110 -100 -90 -80 -70 -60 -50 2ghz +1khz 2ghz +10khz 2ghz +100khz 2ghz +1000khz 2ghz +10000khz fixed 50 mhz reference tunable reference worst spur (dbc) output frequency (a) (b) largest observed spurious, at any offset, using a fxed 50 mhz reference source and a tunable reference source. for example worst case spurious operating at 2000.1 m h z (p oint ( a )) i n figure 35 with a fxed 50 m h z re ference) is represented by a single point in figure 37 (point ( a )) o n the blue curve. s im ilarly, worst case spurious from figure 36 with variable reference, operating at 2000.1 m h z is r epresented by a single point in figure 37 (point (b)) on the green curve. t he p lot in figure 37 is generated by tuning the carrier frequency away from i nt eger boundary and recording the worst case spurious, at any offset, at each operating frequency. figure 37 shows that the worst case spurious for the 50 m h z fx ed reference case, is nearly constant between -51 dbc and -55 dbc when operating with a carrier frequency less than 100 k h z fro m the i nt eger boundary (blue curve). i t al so shows that the worst case spurious rolls off at about 25 db/decade relative to 1 loop bandwidth. for example, at an operating frequency of 2001 m h z (e quivalent to 10 loop bandwidths offset) worst case spurious is -80 dbc. s im ilarly, at an operating frequency of 2010 m h z (e quivalent to 100 loop bandwidths) worst case spurious is -100 dbc. i n co ntrast, the green curve of figure 37 shows that the worst case spurious over the same operating frequency range, when using an h mc 830lp6 ge t unable reference, is below -100 dbc at all operating frequencies! i n ge neral all fractional plls have spurious when operating near i nt eger boundaries. h ig h performance tunable reference makes it possible to operate h mc 834lp6 ge , vi rtually spur-free at all frequencies, with little or no degradation in phase noise. 1.5 i ntegrated phase n oi se & jitter t he standard deviation of vco signal jitter may be estimated with a simple approximation if it is assumed t hat the locked vco has a constant phase noise, o | 2 ( f o ), at offsets less than the loop 3 db bandwidth and a 20 db per decade roll-off at greater offsets. t he s imple locked vco phase noise approximation is shown on the left of figure 38 . for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 26 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z figure 38. pll with integrated vco phase noise & jitter w ith this simplifcation the total integrated vco phase noise, o | 2 , in rads 2 in the linear form is given by o | 2 = o | 2 (f o ) b ( e q 10) wh ere o | 2 (f o ) is the single sideband phase noise in rads 2 / h z inside the loop bandwidth, and b is the 3 db co rner frequency of the closed loop pll t he i ntegrated phase noise at the phase frequency detector, o | 2 pd is just scaled by n 2 /n 2 = o | 2 pd o | 2 ( e q 11) t he r ms phase jitter of the vco in rads, o | , is just the square root of the phase noise integral. s in ce the simple integral of ( e q 10 ) is just a product of constants, we can easily do the integral in the log domain. for example if the vco phase noise inside the loop is -100 dbc/ h z at 1 0 k h z of fset and the loop bandwidth is 100 k h z, a nd the division ratio is 100, then the integrated phase noise at the phase frequency detector, in db, is given by: o | 2 = 10log ( o | 2 ( f o )b/ n 2 ) = -100 + 50 + 5 - 40 = -85 dbc pddb or equivalently, o | = 1 0 -85/20 = 53.6e-6 rads = 3.2e-3 degrees. w hi le the phase noise reduces by a factor of 20log n af ter division to the reference, due to the increased period of the p d r eference signal, the jitter is constant. t he r ms jitter from the phase noise is then given by t jpn = t pd o | pd /2 ( e q 12 ) i n th is example if the p d r eference was 50 m h z, t pd = 20ns, and hence t jpn = 179 femto-sec. i t sh ould be noted that this last expression is based upon a closed form integral of the entire spectrum of the oscillator phase noise. t hi s integral starts at d c. i t is c ommon for real system to evaluate jitter over shorter intervals of time, hence the integral often starts at some fnite frequency offset and will produce a jitter that is less than that given by the full expression. finally real oscillators have noise foors that also contribute to jitter. t he p hase noise of a white noise foor is a simple integral of noise foor density times bandwidth of interest to the system. t hi s additional noise power should be added to the expression of ( e q 16 ) to give a more accurate jitter number. d ep ending upon the bandwidth of the system in question this noise foor contribution may be an important factor. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 27 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.6 r ef erence i np ut stage figure 39. reference path input stage t he r eference buffer provides the path from an external reference source (generally crystal based) to the r d ivider, and eventually to the phase detector. t he b uffer has two modes of operation controlled by r eg 0 8h [21]. h ig h g ai n ( r eg 0 8h [21] = 0), recommended below 200 m h z, a nd h ig h frequency ( r eg 0 8h [21] = 1), for 200 to 350 m h z op eration. t he b uffer is internally d c bi ased, with 100 internal termination. for 50 match, an external 100 resistor to ground should be added, followed by an a c c oupling capacitor (impedance < 1 ), then to the x re fp p in of the part. a t l ow frequencies, a relatively square reference is recommended to keep the input slew rate high. a t h igher frequencies, a square or sinusoid can be used. t he f ollowing table shows the recommended operating regions for different reference frequencies. i f op erating outside these regions the part will normally still operate, but with degraded reference path phase noise performance. minimum pulse width at the reference buffer input is 2.5 ns. for best spur performance when r = 1 , the pulse width should be (2.5ns + 8 t ps ), where t ps is the period of the vco at the prescaler input. w he n r > 1 m inimum pulse width is 2.5 ns. t able 2. r e ference sensitivity t ab le s quare i nput s in usoidal i nput r efer ence i nput f requency (m h z) s le w > 0.5v/ns r ecommended s wing (vpp) r ecommended po wer r ange (dbm) r ecommended min max r ecommended min max < 10 y es 0.6 2.5 x x x 10 y es 0.6 2.5 x x x 25 y es 0.6 2.5 ok 8 15 50 y es 0.6 2.5 y es 6 15 100 y es 0.6 2.5 y es 5 15 150 ok 0.9 2.5 y es 4 12 200 ok 1. 2 2.5 y es 3 8 i nput referred phase noise of the pll when operating at 50 m h z is b etween -150 and -156 dbc/ h z at 1 0 k h z of fset depending upon the mode of operation. t he i nput reference signal should be 10 db better than this foor to avoid deg ra dation of the pll noise contribution. i t sh ould be noted that such low levels are only necessary if the pll is the dominant noise contributor and these levels are required for the system goals. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 28 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.7 r ef erence path r d iv ider t he reference path r di vider is based on a 14-bit counter and can divide input signals by values from 1 to 16,383 and is controlled by rdiv ( r eg 0 2h ). minimum pulse width at the reference buffer input is 2.5 ns. for best spur performance when r = 1 , the pulse width should be (2.5 ns + 8 t ps ), where t ps i s the period of the vco at the prescaler input. w he n r > 1 m inimum pulse width is 2.5 ns. 1.8 r f pa th n d iv ider t he main r f p ath divider is capable of average divide ratios between 2 19 -5 (524,283) and 20 in fractional mode, and 2 19 -1 (524,287) to 16 in integer mode. t he v co frequency range divided by the minimum n d ivider value will place practical restrictions on the maximum usable p d fr equency. for example a vco operating at 1.5 gh z i n fractional mode with a minimum n divider value of 20 will have a maximum p d fr equency of 75 m h z. 1.9 c har ge pump & phase d ete ctor t he phase detector (p d ) ha s two inputs, one from the reference path divider and one from the r f pa th divider. w he n in lock these two inputs are at the same average frequency and are fxed at a constant average phase offset with respect to each other. w e re fer to the frequency of operation of the p d a s f pd . most formulae related to step size, delta-sigma modulation, timers etc., are functions of the operating frequency of the p d , f pd . f pd is also referred to as the comparison frequency of the p d . t he p d c ompares the phase of the r f pa th signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. t he o utput current varies linearly over a full 2 radians (360) of input phase difference. 1.10 phase d ete ctor functions phase detector register r eg 0 bh allows manual access to control special phase detector features. pd_up_en ( r eg 0 bh [5]), if 0, masks the p d u p output, which prevents the charge pump from pumping up.` pd_dn_en ( r eg 0 bh [6]), if 0, masks the p d d own output, which prevents the charge pump from pumping down. clearing both pd_up_en and pd_dn_en effectively tri-states the charge pump while leaving all other functions operating internally. p d f orce up r eg 0 bh [9] = 1 and p d f orce d n r eg 0 bh [10] = 1 allows the charge pump to be forced up or down respectively. t hi s will force the vco to the ends to the tuning range which can be useful in test of the vco. 1.11 phase d et ector w in dow based l ock d et ect lock detect enable r eg 0 7h [3]=1 is a global enable for all lock detect functions. t he window based lock d et ect circuit effectively measures the difference between the arrival of the reference and the divided vco signals at the p d . t he a rrival time difference must consistently be less than the lock d et ect window length, to declare lock. e it her signal may arrive frst, only the difference in arrival times is counted. 1.11.1 a na log w in dow l ock d et ect t he lock detect window may be generated by either an analog one shot circuit or a digital one shot based u pon an internal timer. s et ting r eg 0 7h [6]=0 will result in a fxed, analog, nominal 10 ns window, as shown in figure 40 . t he a nalog window cannot be used if the p d r ate is above 50 m h z, o r if the offset is too large. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 29 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z figure 40. normal lock detect window - integer mode, zero offset for example a 25 m h z p d r ate with a 1 m a c harge pump setting ( r eg 09h [6:0]= r eg 09h [13:7]= 32h) and 400 a o ffset down current ( r eg 09h [20:14]= 50h r eg 09h [22]= 1) , would have an offset of about 400/1000 = 40% of the p d p eriod or about 16 ns. i n su ch an extreme case the divided vco would arrive 16 ns after the p d r eference, and would always arrive outside of the 10 ns lock detect window. i n su ch a case the lock detect circuit would always read unlocked, even though the vco might be locked. w he n using the 10 ns analog lock detect window, with a 40 ns p d p eriod, the offset must always be less than 25% of the charge pump setting, 20% to allow for tolerances. h en ce a 1 m a c harge pump setting can not use more than 200 a o ffset with a 25 m h z p d a nd an analog lock detect window. charge pump current, charge pump offset, phase detector rate and lock detect window are related. 1.11.2 d igi tal w indow l oc k d et ect s etting r eg 07h [6]=1 w ill result in a variable length lock detect window based upon an internal digital timer. t he t imer period is set by the number of cycles of the internal l d c lock as programmed by r eg 0 7h [9:7]. t he l d c lock frequency is adjustable by r eg 0 7h [11:10]. t he l d c lock signal can be viewed via the g po t est pins. r ef er 1.16 for details. 1.11.3 d ec laration of l ock wincnt_max in r eg 0 7h [2:0] defnes the number of consecutive counts of the divided vco that must land inside the lock detect window to declare lock. i f fo r example we set wincnt_max = 2048, then the vco arrival would have to occur inside the window 2048 times in a row to be declared locked, which would result in a lock d et ect flag high. a s ingle occurrence outside of the window will result in an out of lock, i.e. lock d et ect flag low. once low, the lock d et ect flag will stay low until the wincnt_max = 2048 condition is met again. t he l ock d et ect flag status is always readable in r eg 12h [1] , if locked = 1. lock d et ect status is also output to the l d _ sd o pi n if r eg 0 fh [4:0]=1 . a ga in, if locked, l d _ sd o wi ll be high. s et ting r eg 0 fh [6]=0 will display the lock d et ect flag on l d _ sd o ex cept when a serial port read is requested, in which case the pin reverts temporarily to the s er ial d at a out pin, and returns to the lock d et ect flag after the read is completed. r ef er to 1.11.5 for t im ing of the lock d et ect information. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 30 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.11.4 phase o ff set & fractional l inear ity w hen operating in fractional mode the linearity of the charge pump and phase detector are much more c ritical than in integer mode. t he p hase detector linearity is degraded when operating with zero phase offset. h en ce in fractional mode it is necessary to offset the phase of the p d r eference and the vco at the phase detector. i n s uch a case, for example with an offset delay, as shown in figure 41 , the vco arrival will always occur after the reference. t he l ock detect circuit window may need to be adjusted to allow for the delay being used. for details see section d ig ital lock d et ect with d ig ital w in dow e xa mple . figure 41. lock detect window - fractional mode with offset 1.11.5 d igi tal l oc k d et ect with d igi tal w indow e xam ple t ypical d igital lock detect window widths are shown in t able 3 . lock d et ect windows typically vary 10% vs voltage and 25% over temperature (-40c to +85c). t able 3. t ypical d igi tal l oc k d et ect w indow ld timer speed reg07[11:10] digital lock detect window nominal value 25% (ns) fastest 00 6.5 8 11 17 29 53 100 195 01 7 8.9 12.8 21 36 68 130 255 10 1.7 9.2 13.3 22 38 72 138 272 s l owest 11 7.6 10.2 15.4 26 47 88 172 338 l d t im er d iv ide s et ting r eg 07[9:7] 0 1 2 3 4 5 6 7 l d t im er d ivi de value 0.5 1 2 4 8 16 32 64 a s a n example, in fractional mode, with a 50 m h z p d , w ith a charge pump gain of 2 m a and a d ow n leakage of -400 a ( r eg 09h [13:7] = 64h, r eg 09h [6:0] = 64h, r eg 09h [20:14] = 50h, r eg 09h [22] = 1), the average offset at the p d will be -0.400/2 = 0.2 of the p d period, or about 4 ns 25%. h en ce, when in lock, the divided vco will arrive at the p d a bout 4 ns after the divided r ef erence. t he l ock d et ect w in dow always starts on the arrival of the frst signal at the p d , in t his case the r ef erence. t he l ock d et ect window must be longer than 4 ns + 25% and shorter than the period of the p d , i n this example, 20 ns. a perfect lock d et ect window would be the geometric mean or 9.8 ns. a c omfortable solution of 12.8 ns with timer speed set at r eg 0 7h [11:10]=1 and t im er divider r eg 07 h [9:7]=2 works well for the example p d fr equency and charge pump offset setting. t ol erance on the window is +25% at +85 c, -25% at -40 c. h er e 12.8 ns nominal window may extend by +25% at +85c to 16 ns, which is fne for a p d p eriod of 20 ns. a ls o the minimum window may shrink by 25% to 9.6 ns at -40c, which again works well for the worst case offset of 4.6 ns. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 31 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z figure 42. lock detect window example with 50 mhz pd and 3.9 ns vco offset t he re is always a good solution for the lock detect window for a given operating point. t he u ser should understand however that one solution does not ft all operating points. i f ch arge pump offset or p d fr equency are changed signifcantly then the lock detect window may need to be adjusted. 1.11.6 c y cle slip prevention ( c sp ) w hen changing vco frequency and the vco is not yet locked to the reference, the instantaneous fr equencies of the two p d i nputs are different, and the phase difference of the two inputs at the p d v aries rapidly over a range much greater than 2 radians. s in ce the gain of the p d v aries linearly with phase up to 2, the gain of a conventional p d w ill cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. t he o utput current from the charge pump will cycle from maximum to minimum even though the vco has not yet reached its fnal frequency. t he c harge on the loop flter small cap may actually discharge slightly during the low gain portion of the cycle. t hi s can make the vco frequency actually reverse temporarily during locking. t hi s phenomena is known as cycle slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically. cycle s li pping increases the time to lock to a value greater than that predicted by normal small signal laplace analysis. t he s ynthesizer p d f eatures an ability to reduce cycle slipping during acquisition. t he c ycle s li p preven - ti on (c s p) f eature increases the p d g ain during large phase errors. t he s pecifc phase error that triggers the momentary increase in p d g ain is set via r eg 0 bh [8:7] 1.11.7 c har ge pump g ain a simplifed diagram of the charge pump is shown in figure 43 . ch arge pump up and d ow n gains are set by cp dn gain and cp up gain respectively ( r eg 09h [6:0] and r eg 0 9h [13:7]) . t he c urrent gain of the pump in a mp s/radian is equal to the gain setting of this register divided by 2. for example if both cp dn gain and cp up gain are set to 50d the output current of each pump will be 1 m a a nd the phase frequency detector gain k p = 1 m a /2 radians, or 159 a /r ad. s ee s ection 1.4 for more information. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 32 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.11.8 c ha rge pump phase o ff set - fractional mode i n integer mode, the phase detector operates with zero offset. t he d ivided reference signal and the divided vco signal arrive at the phase detector inputs at the same time. i n fra ctional mode of operation, charge pump linearity and ultimately, phase noise, is much better if the vco and reference inputs are operated with a phase offset. a p hase offset is implemented by adding a constant d c of fset current at the output of the charge pump. d c of fset may be added to the up or d n s witching pumps using r eg 09h [21] or r eg 09h [22] . t he m agnitude of the offset is controlled by r eg 09h [20:14], and can range from 0 to 635 a i n steps of 5 a . d ow n offset is highly recommended in fractional mode of operation. i nt eger mode of operation works best with zero offset. a s an e xample, a p d c omparison of f pd = 50 m h z (2 0 ns period) with the main pump gain set at 2 m a , an d a down ( dn ) of fset of -385 a wo uld represent a phase offset of about (-385/2000)*360 = -69 degrees. t hi s is equivalent to the divided vco arriving 3.8 ns after the reference at the p d i nput. i t is c ritical that phase offset be used in fractional mode. n or mally, down offsets larger than 3 ns are typical. i f th e charge pump gain is changed, for example to compensate for changes in vco sensitivity, it is recommended to change the charge pump offset proportionally to maintain a constant phase offset. figure 43. charge pump gain & offset control 1.12 frequency t un ing h mc834lp6 ge v co subsystem always operates in fundamental frequency of operation (2800 m h z to 42 00 m h z) . t he h mc 834lp6 ge g enerates frequencies below its fundamental frequency (45 m h z to 28 00 m h z) b y tuning to the appropriate fundamental frequency and selecting the appropriate output d iv ider setting (divide by 2/4/6.../60/62) in vco_ r eg 02h [5:0]. conversely the h mc 834lp6 ge ge nerates frequencies greater than its fundamental frequency (5600 m h z to 84 00 m h z) b y tuning to the appropriate fundamental frequency and enabling the doubler mode ( vco_ r eg 03h [0] = 1 ). t he h mc 834lp6 ge a utomatically controls frequency tuning in the fundamental band of operation, for more information see 1.2.1 vco a uto -calibration ( a uto cal) . t o tu ne to frequencies below the fundamental frequency range (<2800 m h z) i t is required to tune the h mc 834lp6 ge to t he appropriate fundamental frequency, then select the appropriate output divider setting (divide by 2/4/6.../60/62) in vco_ r eg 02h [5:0]. s im ilarly, to tune to frequencies above the fundamental frequency range (>4200 m h z) i t is required to tune the h mc 834lp6 ge to t he appropriate fundamental frequency, and then enable the doubler mode of operation ( vco_ r eg 03h [0] = 1 ). for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 33 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.12.1 i nteger mode t he h mc834lp6 ge i s capable of operating in integer mode. for i nt eger mode set the following registers a. d isabl e the fractional modulator, r eg 0 6h [11]= 0 b. bypass the modulator circuit, r eg 0 6h [7]=1 i n in teger mode the vco step size is fxed to that of the p d fr equency, f pd . i nteger mode typically has 3 d b lower phase noise than fractional mode for a given p d o perating frequency. i nt eger mode, however, often requires a lower p d fr equency to meet step size requirements. t he fr actional mode advantage is that higher p d fr equencies can be used, hence lower phase noise can often be realized in fractional mode. charge pump offset should be disabled in integer mode. 1.12.1.1 i nteger frequency t unin g i n integer mode the digital ? modulator is shut off and the n ( r eg 0 3h ) divider may be programmed to any integer value in the range 16 to 2 19 -1. t o run in integer mode confgure r eg 0 6h as described, then program the integer portion of the frequency as explained by ( e q 13 ) , ignoring the fractional part. a. d isabl e the fractional modulator, r eg 0 6h [11] = 0 b. bypass the delta-sigma modulator r eg 0 6h [7] = 1 c. t o tu ne to frequencies (<2800 m h z) , select the appropriate output divider value vco_ r eg 02h [5:0]. d. t o tu ne to frequencies (>4200 m h z) , enable the doubler mode of operation ( vco_ r eg 0 3h [0] = 1). w ri ting to vco subsystem registers ( vco_ r eg 02h [5:0] and vco_ r eg 0 3h [0] in this case ) is accomplished indirectly through pll register 5 ( r eg 0 5h ). more information on communicating with the vco subsystem through pll r eg 0 5h is available in 1.19 vco s er ial port i nt erface ( s p i ) section. 1.12.2 fractional mode t he h mc834lp6 ge i s placed in fractional mode by setting the following registers: a. e na ble the fractional modulator, r eg 0 6h [11]=1 b. connect the delta sigma modulator in circuit, r eg 0 6h [7]=0 1.12.2.1 fractional frequency t un ing t his is a generic example, with the goal of explaining how to program the output frequency. a ct ual variables are dependant upon the reference in use. t he h mc 834lp6 ge i n fractional mode can achieve frequencies at fractional multiples of the reference. t he fr equency of the h mc 834lp6 ge , f vco , is given by f vco = ( n int + n frac ) = f int + f frac f xtal r ( e q 13) f out = f vco / k ( e q 14 ) w he re: f out is t he output frequency after any potential dividers or doublers. k is 0 .5 for doubler, 1 for fundamental, or k = 1,2,4,6,58,60,62 according to the vco s ub system type n int is th e integer division ratio, r eg 0 3h , an integer number between 20 and 5 24,284 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 34 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z n frac is t he fractional part, from 0.0 to 0.99999..., n frac = r eg 04h /2 24 r is th e reference path division ratio, r eg 0 2h f xtal is t he frequency of the reference oscillator input f pd is t he p d o perating frequency, f xtal /r a s an e xample: f out 1402 .5 m h z k 2 f vco 2, 805 m h z f xtal = 50 m h z r = 1 f pd = 50 m h z n int = 56 n frac = 0 .1 r eg 0 4h = ro und(0.1 x 2 24 ) = round(1677721.6) = 1677722 f vco = ( 56 + - ) = 2805 mhz + 1.92 hz error 1677722 2 24 50e6 1 ( e q 15) f out = = 1402.5 mhz + 0.596 hz error f vco 2 ( e q 16) i n th is example the output frequency of 1402.5 m h z is a chieved by programming the 19-bit binary value of 56d = 38h into intg_reg in r eg 0 3h , and the 24-bit binary value of 1677722d = 19999 a h in to frac_reg in r eg 0 4h . t he 0 .596 h z qu antization error can be eliminated using the exact frequency mode if required. i n th is example the output fundamental is divided by 2. s pe cifc control of the output divider is required. s ee s ection 3.0 and description for more details. 1.12.2.2 e xact frequency t unin g d ue to quantization effects, the absolute frequency precision of a fractional pll is normally limited by t he number of bits in the fractional modulator. for example, a 24 bit fractional modulator has frequency resolution set by the phase detector (p d ) c omparison rate divided by 2 24 . t he value 2 24 in the denominator is sometimes referred to as the modulus. h it tite plls use a fxed modulus which is a binary number. i n so me types of fractional plls the modulus is variable, which allows exact frequency steps to be achieved with decimal step sizes. unfortunately small steps using small modulus values results in large spurious outputs at multiples of the modulus period (channel step size). for this reason h it tite plls use a large fxed modulus. n or mally, the step size is set by the size of the fxed modulus. i n th e case of a 50 m h z p d r ate, a modulus of 2 24 would result in a 2.98 h z st ep resolution, or 0.0596 ppm. i n so me applications it is necessary to have exact frequency steps, and even an error of 3 h z ca nnot be tol er ated. fractional plls are able to generate exact frequencies (with zero frequency error) if n c an be exactly represented in binary (eg. n = 5 0.0,50.5,50.25,50.75 etc.). unfortunately, some common frequencies cannot be exactly represented. for example, n frac = 0.1 = 1/10 must be approximated as round((0.1 x 2 24 )/ 2 24 ) 0.100000024. a t f p d = 50 m h z this translates to 1.2 h z er ror. h it tites exact frequency mode addresses this issue, and can eliminate quantization error by programming the channel step size to f pd /10 in r eg 0ch to 10 (in this example). more generally, this feature can be used whenever the desired for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 35 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z frequency, f vco , can be exactly represented on a step plan where there are an integer number of steps (<2 14 ) across integer- n bo undaries. mathematically, this situation is satisfed if: gcd gcd gcd 1 14 mod 0 where gcd( , ) 2 f pd pd vcok vco f f f f f and f ?? ?? ?? ?? ?? ?? ?? = = ( e q 17 ) w he re: gcd stands for g re atest common d iv isor f n = maximum integer boundary frequency < f vco1 f pd = frequency of the phase d et ector and f vcok are the channel step frequencies where 0 < k < 2 24 -1, a s shown in figure 44 . fi gure 44. exact frequency tuning s om e fractional plls are able to achieve this by adjusting (shortening) the length of the phase a cc umulator (the denominator or the modulus of the d el ta- s ig ma modulator) so that the d el ta- s ig ma modulator phase accumulator repeats at an exact period related to the interval frequency ( f vcok - f vco(k-1) ) in figure 44 . consequently, the shortened accumulator results in more frequent repeating patterns and as a result often leads to spurious emissions at multiples of the repeating pattern period, or at harmonic frequencies of f vcok - f vco(k-1) . for example, in some applications, these intervals might represent the spacing between radio channels, and the spurious would occur at multiples of the channel spacing. t he h it tite method on the other hand is able to generate exact frequencies between adjacent integer- n b oundaries while still using the full 24 bit phase accumulator modulus, thus achieving exact frequency steps with a high phase detector comparison rate, which allows h it tite plls to maintain excellent phase noise and spurious performance in the e xa ct frequency mode. 1.12.2.3.3 us ing h it tite e xa ct frequency mode i f the constraint in ( e q 17 ) is satisfed, h mc 834lp6 ge i s able to generate signals with zero frequency error at the desired vco frequency. e xa ct frequency mode may be re-confgured for each target frequency, or be set-up for a fxed f gcd which applies to all channels. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 36 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.12.2.4.4 c on fguring e xa ct frequency mode for a particular frequency 1. calculate and program the integer register setting r eg 0 3h = n int = foor( f vco /f pd ), where the foor function is the rounding down to the nearest integer. t he n the integer boundary frequency f n = n int ? f pd 2. calculate and program the exact frequency register value r e g 0ch = f pd /f gcd , where f gcd = gcd( f vco , f pd ) 3. cal culate and program the fractional register setting r eg 0 4h ( ) n vco frac pd ff n f ?? ?? ?? ?? ?? ? = = , where ceil is the ceiling function meaning round up to the nearest integer. example: to confgure the HMC834LP6GE for exact frequency mode at f vco = 2800.2 mhz where phase detector (pd) rate f pd = 61.44 mhz proceed as follows: check ( e q 17 ) to confrm that the exact frequency mode for this f vco is possible. ( ) gcd gcd 14 6 66 3 gcd 14 gcd( , ) 2 61.44 10 gcd 2800.2 10 ,61.44 10 120 10 3750 2 pd pd vco f f f f and f f ?? ?? ?? ?? = = => = s ince ( e q 17) i s satisfed, the h mc 834lp6 ge can be confgured for exact frequency mode at f vco = 2800.2 m h z as f ollows: 1. n int = r eg 03h = 6 6 2800.2 10 45 2 61.44 10 vco pd f floor floor d dh f ?? ?? ?? ?? ?? ?? ?? ?? = = = 2. r e g 0ch = ( ) ( ) 66 66 61.44 10 61.44 10 512 200 120000 gcd , gcd 2800.2 10 ,61.44 10 pd pd vco f dh ff = = = = 3. t o p rogram r eg 04h , the closest integer- n boundary frequency f n that is less than the desired vco frequency f vco must be calculated. f n = f pd ? n int . using the current example: ( ) ( ) 6 24 6 6 24 6 45 61.44 10 2764.8 . 2 2800.2 10 2764.8 10 2 then reg04h 9666560 938000 61.44 10 int n pd n vco pd n f f mhz ff ceil ceil d h f ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? = = = ? ? = = = = 1.12.2.5.5 h it tite e xa ct frequency c ha nnel mode i f it is desirable to have multiple, equally spaced, exact frequency channels that fall within t he same interval (ie. f n f vcok < f n+1 ) where f vcok is shown in figure 44 and 1 k 2 14 , it is possible to maintain the same integer- n ( r eg 0 3h ) and exact frequency register ( r e g 0ch ) settings and only update the fractional register ( r eg 0 4h ) setting. t he e xa ct frequency channel mode is possible if ( e q 17 ) is satisfed for at least two equally spaced adjacent frequency channels, i.e. the channel step size. t o co nfgure the h mc 834lp6 ge f or e xa ct frequency channel mode, initially and only at the beginning, integer ( r eg 03h ) and exact frequency ( r e g 0ch ) registers need to be programmed for the smallest f vco frequency ( f vco1 in figure 44 ), as follows: 1. cal culate and program the integer register setting r eg 03h = n int = foor( f vco1 /f pd ), where f vco1 is shown in figure 44 and corresponds to minimum channel vco frequency. t he n the lower integer boundary frequency is given by f n = n int ? f pd . 2. ca lculate and program the exact frequency register value r e g 0ch = f pd /f gcd, where f gcd = gcd(( f vcok+1 - f vcok ), f pd ) = greatest common divisor of the desired equidistant channel spacing and the p d fr equency (( f vcok+1 - f vcok ) and f pd ). for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 37 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z t hen, to switch between various equally spaced intervals (channels) only the fractional register ( r eg 0 4h ) needs to be programmed to the desired vco channel frequency f vcok in the following manner: r eg 0 4h = ( ) n vcok frac pd ff n f ?? ?? ?? ?? ?? ? = where f n = foor( f vco1 /f pd ), and f vco1 , as shown in figure 44 , represents the smallest channel vco frequency that is greater than f n . example: to confgure the HMC834LP6GE for exact frequency mode for equally spaced intervals of 100 khz where frst channel (channel 1) = f vco1 = 2800.200 mhz and phase detector (pd) rate f pd = 61.44 mhz proceed as follows: first check that the exact frequency mode for this f vco1 = 2800.2 m h z (c hannel 1) and f vco2 = 2800.2 m h z + 10 0 k h z = 28 00.3 m h z (c hannel 2) is possible. ( ) ( ) gcd1 gcd1 gcd 2 gcd 2 12 14 14 6 66 3 gcd1 14 6 6 63 gcd 2 14 gcd( , ) gcd( , ) 22 61.44 10 gcd 2800.2 10 ,61.44 10 120 10 3750 2 61.44 10 gcd 2800.3 10 ,61.44 10 20 10 3750 2 pd pd pd pd vco vco ff f f f and f and f f f and f f f ?? ?? ?? ?? ?? ?? ?? ?? = = = => = = => = i f ( e q 17) is satisfed for at least two of the equally spaced interval (channel) frequencies f vco1 ,f vco2 ,f vco3 ,... f vcon , as it is above, h it tite e xa ct frequency channel mode is possible for all desired channel frequencies, and can be confgured as follows: 1. r eg 0 3h = 6 1 6 2800.2 10 45 2 61.44 10 vco pd f floor floor d dh f ?? ?? ?? ?? ?? ?? ?? ?? = = = 2. r e g 0ch = ( ) ( ) ( ) 66 36 1 61.44 10 61.44 10 3072 00 20000 gcd 100 10 ,61.44 10 gcd , pd pd vcok vcok f dc h f ff + = = = = ? where ( f vcok+1 - f vcok ) is the desired channel spacing (100 k h z in t his example). 3. t o pr ogram r eg 0 4h the closest integer- n b oundary frequency f n that is less than the smallest channel vco frequency f vco1 must be calculated. f n = foor( f vco1 /f pd ). using the current example: 6 6 6 2800.2 10 45 61.44 10 2764.8 61.44 10 n pd f f floor mhz ?? ?? ?? ?? = = = t hen r eg 0 4h ( ) ( ) 24 1 1 24 6 6 6 2 for channel 1 where 2800.2 2 2800.2 10 2764.8 10 9666560 938000 61.44 10 n vco vco pd ff ceil f mhz f ceil d h ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ? = = ? = = = 4. t o ch ange from channel 1 ( f vco1 = 2800.2 m h z) to c hannel 2 ( f vco2 = 2800.3 m h z) , only r eg 0 4h needs to be programmed, as long as all of the desired exact frequencies f vcok ( figure 44 ) fall between the same integer- n b oundaries ( f n < f vcok < f n+1 ). i n that case r eg 0 4h = ( ) 24 6 6 6 2 2800.3 10 2764.8 10 9693867 93 61.44 10 ceil d eaabh ?? ?? ?? ?? ?? ?? ? = = , and so on. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 38 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.12.2.6 seed r e gister & a ut oseed mode t he start phase of the fractional modulator digital phase accumulator ( d p a ) ma y be set to one of four possible default values via the seed register r eg 0 6h [1:0] . i f a uto s ee d r eg 0 6h [8] is set, then the h mc 834lp6 ge w ill automatically reload the start phase into the d p a e very time a new fractional frequency is selected. i f a uto s ee d is not set, then the h mc 834lp6 ge w ill start new fractional frequencies with the last value left in the d p a from the last frequency. h en ce the start phase will effectively be random. certain zero or binary seed values may cause spurious energy correlation at specifc frequencies. correlated spurs are advantageous only in very special cases where the spurious are known to be far out of band and are removed in the loop flter. for most cases a random, or non zero, non-binary start seed is recommended. further, since the a uto s ee d always starts the accumulators at the same place, performance is repeatable if a uto s ee d is used. r eg 0 6h [1:0]=2 is recommended. 1.13 soft r es et & power- o n r es et t he h mc834lp6 ge f eatures a hardware power on r es et (po r ). a ll c hip registers will be reset to default states approximately 250 s after power up. t he p ll subsystem s p i r egisters may also be soft reset by an s p i w rite to register rst_swrst ( r eg 0 0h ) . n ot e that the soft reset does not clear the s p i m ode of operation referred to in section 1.17. 2 . i t sh ould be noted that the vco subsystem is not affected by the pll soft reset, the vco subsystem registers can only be reset by removing the power supply. note: if external power supplies or regulators have rise times slower than 250 s, then it is advised to write to the spi reset register ( r eg 0 0h [5]=1) immediately after power up, before any other spi activity. this will ensure starting from a known state. 1.14 power d ow n mode n ote that the vco subsystem is not affected by the c en o r soft reset. h en ce device power down is a two step process. first power down the vco by writing 0 to vco register 1 via r eg 0 5h and then power down the pll by pulling c en p in 17 low (assuming no s p i o verrides ( r eg 01h [0]=1)). t hi s will result in all analog functions and internal clocks disabled. current consumption will typically drop below 10 a i n power d ow n state. t he s erial port will still respond to normal communication in power d ow n mode. i t is p ossible to ignore the c en p in, by clearing rst_chipen_pin_select ( r eg 01h [0]=0) . control of power d ow n mode then comes from the serial port register rst_chipen_from_spi, r eg 01h [1] . i t is a lso possible to leave various blocks on when in power d ow n (see r eg 01h ) , including: a. i nt ernal bias r ef erence s ou rces r eg 01h [2] b. p d b lock r eg 01h [3] c. cp block r eg 01h [4] d. r ef erence path buffer r eg 01h [5] e. vco path buffer r eg 01h [6] f. d ig ital i /o t es t pads r eg 01h [7] t o tu rn off the vco r f bu ffer but leave the vco running and the pll locked write r eg 0 5h = 2 a 98 (manual select) then write r eg 0 5h = 0 d 88 (disable vco r f bu ffer) t o re -enable the r f bu ffer write r eg 0 5h =0f88( e na ble vco r f bu ffer) 1.15 c hip i de ntifcation pll subsystem version information may be read by reading the content of read only register, chip_ id in r eg 0 0h . i t is n ot possible to read the vco subsystem version. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 39 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.16 g en eral purpose o ut put ( g p o ) pi n t he pll shares the l d _ sd o (l ock- d et ect/ s er ial d at a out) pin to perform various functions. w hi le the pin is most commonly used to read back registers from chip via the s p i , it i s also capable of exporting a variety of interesting signals and real time test waveforms (including lock d et ect). i t is d riven by a tri-state cmo s d river with ~200 r ou t. i t ha s logic associated with it to dynamically select whether the driver is enabled, and to decide which data to export from the chip. i n i ts default confguration, after power-on-reset, the output driver is disabled, and only drives during appropriately addressed s p i r eads. t hi s allows it to share the output with other devices on the same bus. d ep ending on the s p i m ode, the read section of s p i c ycle is recognized differently h mc s p i m ode: t he d river is enabled during the last 24 bits of s p i r ead c ycle (not during write cycles). open s p i m ode: t he d river is enabled if the chip is addressed - ie. t he l ast 3 bits of s p i c ycle = 000b before the rising edge of s en ( n ot e a ). t o mo nitor any of the g po s ignals, including lock d et ect, set r eg 0 fh [7] = 1 to keep the s d o dr iver always on. t hi s stops the l d o dr iver from tri-stating and means that the s d o li ne cannot be shared with other devices. t he c hip will naturally switch away from the g po d ata and export the s d o du ring an s p i r ead ( n ot e b). t o pr event this automatic data selection, and always select the g po s ignal, set prevent a uto mux of s d o ( r eg 0 fh [6] = 1). t he phase noise performance at this output is poor and uncharacterized. a ls o, the g po o utput should not be toggling during normal operation. otherwise the spectral performance may degrade. n ot e that there are additional controls available, which may be helpful if sharing the bus with other devices: ? t o al low the driver to be active (subject to the conditions above) even when the chip is disabled - set r eg 01h [7] = 0. ? t o di sable the driver completely, set r eg 0 8h [5] = 0 (it takes precedence over all else). ? t o di sable either the pull-up or pull-down sections of the driver, r eg 0 fh [8] = 1 or r eg 0 fh [9] = 1 respectively. note a: if sen rises before sck has clocked in an invalid (non-zero) chip -address, the HMC834LP6GE will start to drive the bus. note b: in open mode, the active portion of the read is defned between the 1 st sck rising edge after sen, to the next rising edge of sen. e xa mple s ce narios: ? d ri ve s d o du ring reads, tri-state otherwise (to allow bus-sharing) ? n o action required. ? d ri ve s d o du ring reads, lock d et ect otherwise ? s e t g po s e lect r eg 0 fh [4:0] = 00001 (which is default) ? s et prevent g po d river disable ( r eg 0 fh [7] = 1) ? a lw ays drive lock d et ect ? s et p revent a uto mux of s d o r eg 0 fh [6] = 1 ? s e t g po s e lect r eg 0 fh [4:0]= 00001 (which is default) ? s et prevent g po d river disable ( r eg 0 fh [7] = 1)) t he s ignals available on the g po a re selected by changing g po s el ect, r eg 0 fh [4:0]. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 40 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.17 serial port 1 .17.1 se rial port modes of o pe ration t he h mc834lp6 ge s erial port interface can operate in two different modes of operation. a. h mc s p i h mc m ode ( h mc l egacy mode) - s in gle slave per h mc s p i b us b. h mc s p i o pen mode - up to 8 slaves per h mc s p i b us. both modes support 5-bits of register address space. h mc m ode can support up to 6 bits of register address. r eg ister 0 has a dedicated function in each mode. open mode allows wider compatibility with other manufacturers s p i pro tocols. t able 4. r eg ister 0 c om parison - single vs multi-user modes single user hmc mode multi-user open mode re ad ch ip i d 24 -bits chip i d 24 -bits write s o ft r ese t, g e neral s t robes r ea d a dd ress [4:0] s of t reset [5] g en eral s tr obes [23:6] 1.17. 2 h m c sp i p rotocol d ec ision after power- o n r es et on power up both types of modes are active and listening. a d ecision to select the desired s p i p rotocol is made on the frst occurrence of s en or s cl k following a hard reset, after which the protocol is fxed and only changeable by cycling the power off and o n . a. i f a ri sing edge on s en i s detected frst h mc m ode is selected. b. i f a ri sing edge on s cl k is detected frst open mode is selected. 1.17.3 serial port h m c m ode - single p ll h mc mode (legacy mode) serial port operation can only address and talk to a single pll, and is compatible w ith most h it tite plls and plls with i nt egrated vcos. t he h mc m ode protocol, shown in fgures figure 45 and figure 46 , is designed for a 4 wire interface with a fxed protocol featuring a. 1 r ea d/ w ri te bit b. 6 a d dress bits c. 24 data bits d. 3 wire for w ri te only, 4 wire for r ea d/ w ri te capability 1.17.3.1 h m c m ode - serial port w rite o pe ration a v dd = d v dd = 3 v 10%, a gnd = d gnd = 0 v t able 5. sp i h m c m ode - w ri te t im ing c har acteristics parameter conditions min. typ. max units t 1 sen to s clk setup time 8 ns t 2 sdi to s clk setup time 3 ns t 3 s clk to s di h old time 3 ns t 4 sen low duration 20 ns t 5 s ck to s en f all 10 ns max s er ial port clock s pe ed 50 m h z for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 41 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z a typical h mc m ode w rite c ycle is shown in figure 45 . a. t he m aster (host) both asserts s en ( s er ial port e na ble) and clears s di to i ndicate a w rite c ycle, followed by a rising edge of s ck . b. t he s lave (synthesizer) reads s di o n the 1st rising edge of s ck af ter s en . s di l ow indi ca tes a w ri te cycle (/ wr ). c . h os t places the six address bits on the next six falling edges of s ck , m s b fr st. d. s la ve shifts the address bits in the next six rising edges of s ck ( 2-7). e. h os t places the 24 data bits on the next 24 falling edges of s ck , m s b fr st. f. s la ve shifts the data bits on the next 24 rising edges of s ck ( 8-31). g. t he d ata is registered into the chip on the 32nd rising edge of s ck . h. sen i s cleared after a minimum delay of t 5 . t his completes the write cycle. figure 45. hmc mode - serial port timing diagram - write 1.17.3 . 2 h m c m ode - serial port r ead o pe ration a typical h mc m ode r ead c ycle is shown in figure 46 . a. t he m aster (host) asserts both s en ( s er ial port e na ble) and s di to i ndicate a r ead c ycle, followed by a rising edge s cl k. n ot e: t he l ock d et ect (l d ) fu nction is usually multiplexed onto the l d _ sd o pi n. i t is s uggested that l d o nly be considered valid when s en i s low. i n fa ct l d w ill not toggle until the frst active data bit toggles on l d _ sd o, a nd will be restored immediately after the trailing edge of the l s b of s erial data out as shown in figure 46 . b. t he s lave ( h mc 834lp6 ge ) re ads s di o n the 1st rising edge of s cl k after s en . s di h igh initiates the r ead c ycle ( rd ) c. h os t places the six address bits on the next six falling edges of s cl k, m s b fr st. d. s la ve registers the address bits on the next six rising edges of s cl k (2-7). e. s la ve switches from lock d et ect and places the requested 24 data bits on s d _l d o o n the next 24 rising edges of s ck ( 8-31), m s b fr st . f. h os t registers the data bits on the next 24 falling edges of s ck ( 8-31). g. s la ve restores lock d et ect on the 32nd rising edge of s ck . h. d e- assertion of s en c ompletes the cycle for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 42 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z t able 6. sp i h m c m ode - r ea d t im ing c har acteristics parameter conditions min. typ. max units t 1 sen to s clk setup time 8 ns t 2 sdi to s clk setup time 3 ns t 3 s clk to s di h old time 3 ns t 4 sen low duration 20 ns t 5 s clk to s d o de lay 8.2ns+0.2 ns/pf ns t 6 r ecovery t im e 10 ns figure 46. hmc mode - serial port timing diagram - read 1.17.4 serial port o pe n mode t he s erial port open mode, shown in figure 47 a nd figure 48 , features: a. compatibility with general serial port protocols that use shift and strobe approach to communication b. compatible with h it tite pll with i nt egrated vco solutions, useful to address multiple chips of various types from a single serial port bus. t he o pen mode protocol has the following general features: a. 3-bit chip address , can address up to 8 devices connected to the serial bus b. w id e compatibility with multiple protocols from multiple vendors c. s im ultaneous w ri te/ r ea d during the s p i c ycle d. 5-bit address space e. 3 wire for w ri te only capability, 4 wire for r ea d/ w ri te capability h it tite plls with integrated vcos support open mode. s om e legacy pll and microwave plls with integrated vcos only support h mc m ode. consult the relevant data sheets for details. t yp ical serial port operation can be run with s cl k at speeds up to 50 m h z. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 43 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.17.4.1 o pe n mode - serial port w rite o pe ration a v dd = d v dd = 3 v 10%, a gnd = d gnd = 0 v t able 7. sp i o pe n mode - w rite t im ing c har acteristics parameter conditions min. typ. max units t 1 sdi setup time to s cl k r is ing e dg e 3 ns t 2 s clk r ising e dg e to s di h old time 3 ns t 3 sen low duration 1 0 ns t 4 sen high duration 1 0 ns t 5 s clk 32 r is ing e dg e to s en r is ing e dg e 10 ns t 6 r ecovery t im e 20 ns max s er ial port clock s pe ed 50 m h z a typical write cycle is shown in figure 47 . a. t he m aster (host) places 24-bit data, d23:d0, m s b fr st, on s di o n the frst 24 falling edges of s cl k. b. th e slave ( h mc 834lp6 ge ) sh ifts in data on s di o n the frst 24 rising edges of s cl k c. ma ster places 5-bit register address to be written to, r4:r0, m s b f rst, on the next 5 falling edges of s cl k (25-29) d. s la ve shifts the register bits on the next 5 rising edges of s cl k (25-29). e. ma ster places 3-bit chip address, a2:a0, m s b f rst, on the next 3 falling edges of s cl k (30-32). h it tite reserves chip address a2:a0 = 000 for all r f pl l with i nt egrated vcos. f. s la ve shifts the chip address bits on the next 3 rising edges of s cl k (30-32). g. ma ster asserts s en af ter the 32nd rising edge of s cl k. h. s la ve registers the s di d ata on the rising edge of s en . figure 47. open mode - serial port timing diagram - write 1.17.4 . 2 o pe n mode - serial port r ead o pe ration a typical read cycle is shown in figure 48 . i n g eneral, in open mode the l d _ sd o l ine is always active during the wr ite cycle. d ur ing any open mode s p i c ycle l d _ sd o wi ll contain the data from the current address written in r eg 0h[7:3]. i f r eg 0h[7:3] is not changed then the same data will always be present on l d _ sd o w hen an open mode cycle is in progress. i f it i s desired to r ead fr om a specifc address, it is necessary in the frst s p i c ycle to write the desired address to r eg 0h[7:3], then in the next s p i c ycle the desired data will be available on l d _ sd o. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 44 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z a n example of the open mode two cycle procedure to read from any random address is as follows: a . t he m aster (host), on the frst 24 falling edges of s cl k places 24-bit data, d23:d0, m s b fr st, on s di a s shown in figure 48 . d23:d5 should be set to zero. d4:d0 = address of the register to be r ead o n the next cycle. b. th e slave ( h mc 834lp6 ge ) sh ifts in data on s di o n the frst 24 rising edges of s cl k c. ma ster places 5-bit register address , r4:r0, (the r ead a ddress r egister), m s b fr st, on the next 5 falling edges of s cl k (25-29). r4:r0=00000. d. s la ve shifts the register bits on the next 5 rising edges of s cl k (25-29). e. ma ster places 3-bit chip address, a2:a0, m s b fr st, on the next 3 falling edges of s cl k (30-32)..chip address is always 000 for r f pl l with i nt egrated vcos. f. s la ve shifts the chip address bits on the next 3 rising edges of s cl k (30-32). g. ma ster asserts s en af ter the 32nd rising edge of s cl k. h. s la ve registers the s di d ata on the rising edge of s en . i. ma ster clears s en to c omplete the the address transfer of the two part r ead c ycle. j. i f on e does not wish to write data to the chip at the same time as we do the second cycle , then it is recommended to simply rewrite the same contents on s di to r eg ister zero on the r ead b ack part of the cycle. k. ma ster places the same s di d ata as the previous cycle on the next 32 falling edges of s cl k. l. s la ve ( h mc 834lp6 ge ) sh ifts the s di d ata on the next 32 rising edges of s cl k. m. s la ve places the desired read data (ie. data from the address specifed in r eg 0 0h [7:3] of the frst cycle) on l d _ sd o wh ich automatically switches to s d o mo de from l d m ode, disabling the l d o utput. m. ma ster asserts s en af ter the 32nd rising edge of s ck to c omplete the cycle and revert back to lock d et ect on l d _ sd o. t able 8. sp i o pe n mode - r ea d t im ing c har acteristics parameter conditions min. typ. max units t 1 sdi setup time to s cl k r is ing e dg e 3 ns t 2 s clk r ising e dg e to s di h old time 3 ns t 3 sen low duration 1 0 ns t 4 sen high duration 1 0 ns t 5 s clk r ising e dg e to s d o ti me 8.2ns+0.2ns/pf ns t 6 r ecovery t i me 1 0 ns t 7 s ck 32 r ising e dge to sen r ising e dge 10 ns for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 45 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.17.4 .3 h m c sp i o pe n mode r ead o pe ration - 2 c y cles figure 48. serial port timing diagram - read for more information on using the g po p in while in s p i o pen mode please see section 1.16. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 46 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.18 c on fguration at start-up t o confgure the pll after power up, follow the instructions below: 1. co nfgure the reference divider (write to r eg 0 2h ), if required. 2. co nfgure the delta-sigma modulator (write to r eg 0 6h ). ? confguration involves selecting the mode of the delta-sigma modulator (mode a o r mode b), selection of the delta-sigma modulator seed value, and confguration of the delta-sigma modulator clock scheme. i t is r ecommended to use the values found in the h it tite pll evaluation board control software register fles. 3. co nfgure the charge pump current and charge pump offset current (write to r eg 09h ) 4. co nfgure the vco s ub system (write to r eg 0 5h , for more information see section 1.19 , and 3.0 vco s ub system r eg ister map . d et ailed writes to the vco subsystem via pll r eg 05h at start-up are available in the r eg ister s et ting files found in the h i tt ite pll e va luation s of tware received with a product evaluation kit or downloaded from www.hittite.com . 5. pr ogram the frequency of operation ? program the integer part (write to r eg 0 3h ) ? program the fractional part (write to r eg 0 4h ) 6. co nfgure the vco output divider/doubler, if needed in the vco subsystem via pll r eg 0 5h . once the h mc 834lp6 ge i s confgured after startup, in most cases the user only needs to change frequencies by writing to r eg 0 3h integer register, r eg 0 4h fractional register, and r eg 0 5h to change the vco output divider or doubler setting if needed, and possibly adjust the charge pump settings by writing to r eg 09h . for detailed and most up-to-date start-up confguration please refer to the appropriate r eg ister s et ting files found in the h i tt ite pll e va luation s of tware received with a product evaluation kit or downloaded from www.hittite.com . 1.19 v co s erial port i nt erface (sp i ) t he h mc834lp6 ge c ommunicates with the internal vco subsystem via an internal 16 bit vco s er ial port, (e.g. see figure 29 ). t he i nternal serial port is used to control the step tuned vco and other vco subsystem functions, such as r f ou tput divider / doubler control and r f bu ffer enable. n ot e that the internal vco subsystem s p i ( v s p i ) ru ns at the rate of the a uto cal f s m cl ock, t fsm , (section 1. 2.1 ) where the f s m cl ock frequency cannot be greater than 50 m h z. t he v s p i c lock rate is set by r eg 0 a h [ 14:13]. w ri tes to the vcos control registers are handled indirectly, via writes to r eg 0 5h of the pll. a w rite to pll r eg 0 5h causes the pll subsystem to forward the packet, m s b fr st, across its internal serial link to the vco subsystem, where it is interpreted. t he v co serial port has the capability to communicate with multiple subsystems inside the i c. f or this reason each subsystem has a subsystem i d , r eg 0 5h [2:0]. e ac h subsystem has multiple registers to control the functions internal to the subsystem, which may be different from one subsystem to the next. h en ce each subsystem has internal register addresses bits ( r eg 0 5h [6:3]) finally the data required to confgure each register within the vco subsystem is contained in r eg 0 5h [15:7]. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 47 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.19.1 vsp i u se of r eg 05h t he packet data written into, r eg 0 5h is sub-parsed by logic at the vco subsystem into the following 3 felds: 1. [2 :0] - 3 bits - vco_ id , ta rget subsystem address = 000b. 2. [6 :3] - 4 bits - vco_ re gaddr , th e internal register address inside the vco subsystem. 3. [1 5:7] - 9- bits- vco_ da ta , da ta feld to write into the vco register. for example, to write 0_1111_1110 into register 2 of the vco subsystem (vco_ id = 000b), and set the vco output divider to divide by 62, the following needs to be written to r eg 0 5h =0 _1111_1110, 0 010, 0 0 0 b. d ur ing a uto cal, the a uto cal controller only updates the data feld of r eg 0 5h . t he v co subsystem register address ( r eg 0 5h [6:3]) must be set to 0000 for the a uto cal data to be sent to the correct address. vco subsystem i d a nd register address are not modifed by the a uto cal state machine. h en ce, if a manual access is done to a vco s ub system register the user must reset the register address to zero before a change of frequency which will re-run a uto cal. s in ce every write to r eg 0 5h will result in a transfer of data to the vco subsystem, if the vco subsystem needs to be reset manually, it is important to make sure that the vco switch settings are not changed. h en ce the switch settings in r eg 10h [7:0] need to be read frst, and then rewritten to r eg 0 5h [15:8]. i n su mmary, frst read r eg 10h , then write to r eg 0 5h as follows: r eg 10h[7:0] = v v x yyyyy r eg 0 5h = vv x y yyyy 0 0000 iii r eg 0 5h [2:0] = ii i, subsystem i d , 3 bi ts (000) r eg 0 5h [6:3] = 00 00, subsystem register address r eg 0 5h [7] = 0 , ca libration tune voltage off r eg 0 5h [12:8] = yy yyy, vco caps r eg 0 5h [13] = x, d ont care r eg 0 5h [15:14] = vv , vco s el ect for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 48 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.0 p ll r e gister map 2.1 r e g 00h i d r e gister ( r e ad o nl y) bit type name width default description [23:0] r o c hip_ id 24 a 7 975 h mc 834lp6 ge c hip i d 2.2 r eg 0 0h o pe n mode r ea d a dd ress/ r s t s trobe r eg ister ( w ri te o nl y) bit type name width default description [4:0] w o r ea d a dd ress 5 - ( wr ite o n ly ) r ea d a dd ress for next cycle - open mode only [5] w o s oft r es et 1 - s of t r es et - both s p i m odes reset (set to 0 for proper operation) [23:6] w o n ot d e fned 18 - n ot d ef ned (set to 0 for proper operation) 2.3 r e g 01h r s t r e gister ( d efault 000002h) bit type name width default description [0] r / w rst _chipen_pin_select 1 0 1 = take pll enable via c en p in, see power d ow n mode description 0 = take pll enable via s p i ( rst_chipen_from_spi) r eg 01[1] [1] r / w rst _chipen_from_spi 1 1 s p i s p ll enable bit [2] r / w kee p_bias_on 1 0 when pll is disabled, keeps internal bias generators on, ignores chip enable control. [3] r / w ke ep_p d _ on 1 0 when pll is disabled, keeps p d c ircuit on, ignores chip enable control [4] r / w ke e p_ cp_ o n 1 0 when pll is disabled, keeps charge pump on, ignores chip enable control [5] r / w ke ep_ r ef_ buf_on 1 0 when pll is disabled, keeps r ef erence buffer block on, ignores chip enable control [6] r / w ke ep_vco_on 1 0 when pll is disabled, keeps vco divider buffer on, ignores chip enable control [7] r / w ke ep_ g po _driver_on 1 0 when pll is disabled, keeps g po o utput d ri ver on, ignores chip enable control [8] r / w r es erved 1 0 r es erved [9] r / w r es erved 1 0 r es erved 2.4 r e g 02h r e f di v r e gister ( d efault 000001h) bit type name width default description [13:0] r / w rdiv 14 1 r eference d iv ider r value ( e q 1 3)) d iv ider use also requires refbuf e n r eg 08[3]=1and d iv ider min 1d max 16383d for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 49 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.5 r eg 0 3h frequency r eg ister - i nt eger part ( d efault 000019h) bit type name width default description [18:0] r / w in tg 19 25d vco d ivider i nt eger part, used in all modes, see ( e q 13 ) fractional mode min 20d max 2 19 -4 = 7fffch = 524,284d i nt eger mode min 16d max 2 19 -1 = 7ffffh = 524,287d 2.6 r eg 0 4h frequency r eg ister - fractional part ( d efault 000000h) bit type name width default description [23:0] r / w fra c 24 0 vco d ivider fractional part (24-bit unsigned) see f ractional frequency t unin g used in fractional mode only ( n frac = r eg 04h /2 24 min 0d max 2 24 -1 2.7 r eg 0 5h v co s p i r eg ister ( d efault 000000h) bit type name width default description [2:0] r / w vc o s ub system_ id , 3 0 i nt ernal vco s u bsystem i d [6 :3] r / w vc o s u bsystem register address 4 0 for interfacing with the vco please see section 1.19 . [15:7] r / w vc o s ub system data 9 0 n ote: r eg05h is a special register used for indirect addressing of the vco subsystem. w ri tes to r eg 05h are automatically forwarded to the vco subsystem by the vco s p i s tate machine controller. r eg 05h is a r ea d- w ri te register. h ow ever, r eg 05h only holds the contents of the last transfer to the vco subsystem. h en ce it is not possible to read the full contents of the vco subsystem. only the content of the last transfer to the vco subsystem can be read. please take note special considerations for a uto cal related to r eg 05h for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 50 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.8 r eg 0 6h s d c f g r eg ister ( d efault 200b4 a h) bit type name width default description [1:0] r / w see d 2 2 s el ects the s ee d in fractional mode 00: 0 seed 01: lsb seed 02: b29 d 08 h seed 03: 50f1c d h se ed n ot e; w ri tes to this register are stored in the h mc 834lp6 ge a nd are only loaded into the modulator when a frequency change is executed and if a ut o s ee d reg06h[8] =1 [3:2] r / w or der 2 2 s el ect the modulator t yp e 0: 1st order 1: 2nd order 2: t yp e 1 mode b 3: t yp e 2 mode a [6 :4] r / w r es erved 3 4 program to 7d [7] r / w fr ac_bypass 1 0 0: use modulator, r eq uired for fractional mode, 1: bypass modulator, r eq uired for i nt eger mode n ot e: i n by pass fractional modulator output is ignored, but fractional modulator continues to be clocked if frac_ rstb =1, can be used to test the isolation of the digital fractional modulator from the vco output in integer mode [8] r / w a uto s ee d 1 1 1: loads the seed whenever the frac register is written 0: when frac register write changes frequency, modulator starts with previous contents [9] r / w cl krq_refdiv_sel 1 1 selects the modulator clock source- for t es t only 1: vco divider clock ( r ec ommended for normal operation) 0: r ef d ivider clock i gn ored if bits [10] or [21] are set [10] r / w sd m odulator clk s el ect 1 0 0 - s d a uxclk, 1- s d v co clock delay ( r ec ommended) [11] r / w sd e nab le 1 1 0: disable frac core, use for i nt eger mode or i nt eger mode with c s p 1 : e na ble frac core, required for fractional mode, or i nt eger isolation testing t hi s register controls whether a ut ocal starts on an i nt eger or a fractional write [12] r / w r es erved 1 0 [13] r / w r es erved 1 0 [ 15:14] r / w r es erved 2 0 [17:16] r / w r es erved 2 0 program to 3d [18] r / w b ist e na ble 1 0 e na ble built in s el f t es t [20:19] r / w rd iv b is t cy cles 2 0 rd iv b is t cy cles 00: 1032 01: 2047 10: 3071 11: 4095 [21] r / w au to_clock_confg 1 1 s et t o 0 for f pd > 50 m h z [22 ] r / w r es erved 1 0 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 51 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.9 r eg 0 7h l ock d et ect r eg ister ( d e fault 00014 d h) bit type name width default description [2:0] r / w lkd _wincnt_max 3 5d lock detect window sets the number of consecutive counts of divided vco that must land inside the lock d et ect w in dow to declare lock 0: 5 1: 32 2: 96 3: 256 4: 512 5: 2048 6: 8192 7: 65535 [3] r / w e na ble i nt ernal lock d ete ct 1 1 see section 1.16 [5:4] r / w r es erved 2 0 r es erved [6] r / w lo ck d et ect w in dow type 1 1 lock d et ection w in dow t ime r s el ection 1: d ig ital programmable timer 0: a na log one shot, nominal 10 ns window [9:7] r / w l d d ig ital w in dow duration 3 2 0 lock d et ection - d ig ital w in dow d ur ation 0: 1/2 cycle 1: 1 cycle 2: 2 cycles 3: 4 cycles 4: 8 cycles 5: 16 cycles 6: 32 cycles 7: 64 cycles [11:10] r / w l d d ig ital t im er freq control 2 0 lock d et ect d ig ital t im er frequency control 00 fastest 11 slowest [12] r / w l d t im er t es t mode 1 0 1: force t im er clock o n c ontinuously - for t es t only 0: n or mal t ime r operation - one shot [13] r / w a ut o r el ock - one t ry 1 0 1: a tt empts to relock if lock d et ect fails for any reason only tries once. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 52 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.10 r eg 0 8h a na log e n r eg ister ( d efault c1b e f fh) bit t y pe n ame w idth d e fault d es cription [0] r / w bia s_en 1 1 e na bles main chip bias reference [1] r / w cp _en 1 1 charge pump enable [2] r / w p d _e n 1 1 p d en able [3] r / w re fbuf_en 1 r ef erence path buffer enable [4] r / w vc obuf_en 1 1 vco path r f bu ffer enable [5] r / w gpo_ pad_en 1 1 0 - pin l d _ sd o di sabled 1 - and r eg fh[7]=1 , pin l d _ sd o is a lways on required for use of g po p ort 1 - and r eg fh[7]=0 s p i l d o_ s p i i s off if unmatched chip address is seen on the s p i , al lowing a shared s p i w ith other compatible parts [6] r / w re served 1 1 reserved [7] r / w vc o_ d iv _clk_to_dig_en 1 1 vco d iv ider clock to d ig ital e na ble [8] r / w re served 1 0 reserved [9] r / w pr escaler clock enable 1 1 prescaler clock enable [10] r / w vc o buffer and prescaler bias e nab le 1 1 vco buffer and prescaler bias e nab le [11] r / w cha rge pump i nt ernal opamp enable 1 1 s h ould be programmed to 1 [14:12] r / w re served 3 011 reserved [17:15] r / w re served 3 011 reserved [18] r / w sp are 1 0 spare [19] r / w re served 1 0 reserved [20] r / w re served 1 0 reserved program to 0 [21] r / w h ig h frequency r ef erence 1 0 program to 1 for x ta l > 20 0 m h z [22 ] r / w re served 1 1 reserved program to 1 [23] r / w re served 1 1 reserved program to 1 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 53 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2 .11 r e g 09h c ha rge pump r e gister ( d efault 403264h) bit t y pe n ame w idth d e fault d es cription [6:0] r / w cp d n g ai n 7 100d 64h charge pump d n g ai n control 20 a s tep a ff ects fractional phase noise and lock detect settings 0d = 0 a 1d = 2 0 a 2d = 4 0 a ... 12 7d = 2.54m a [1 3:7] r / w cp u p g ai n 7 100d 64h charge pump up g ai n control 20 a p er step a ff ects fractional phase noise and lock detect settings 0d = 0 a 1d = 2 0 a 2d = 4 0 a ... 12 7d = 2.54m a [2 0:14] r / w of fset magnitude 7 0 charge pump offset control 5 a /s tep a ff ects fractional phase noise and lock detect settings 0d = 0 a 1d = 5 a 2d = 1 0 a ... 12 7d = 635 a [2 1] r / w of fset up enable 1 0 recommended setting = 0 [22] r / w of fset dn en able 1 1 recommended setting = 1 in fractional mode, 0 otherwise [23] r / w h ikc p 1 0 h ik cp h ig h current charge pump for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 54 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.12 r e g 0 a h v co a ut o c al c on fguration r e gister ( d e fault 002205h) bit t y pe n ame w idth d e fault d es cription [2:0] r / w vt une r es olution 3 5 r d ivi der cycles 0 - 1 1 - 2 2 - 4 3 - 8 4 - 32 5 - 64 6 - 128 7 - 256 [5:3] r / w vc o curve a dj ustment 3 0 vco curve a dj ustment vs t em p for a ut ocal 0 - d is abled 1 : + 1 curve 2: +2 curves 3: +3 curves 4: -4 curves 5: -3 curves 6: -2 curves 7: -1 curve [7:6] r / w w ai t s ta te s et u p 2 0 w ait s tate s et up 100 t f s m see section 1.2.4 t mmt = 1 measurement cycle of a ut ocal 0: w ai t only at s ta rtup 1: w ai t on startup and after frst t mmt cycle 2: w ai t on startup and after frst two t mmt cycles 3: w ai t on startup and after frst three t mmt cycles [9:8] r / w n um o f s ar b i ts i n vco 2 0 n um ber of s ar b its in vco 0: 8 - recommended 1: 7 2: 6 3: 5 [10] r / w fo rce curve 1 0 force curve sent during t un ing t un e from r eg 5 [11] r / w bypa ss vco t unin g 1 0 bypass vco t unin g [12] r / w n o v s p i t ri gger 1 0 d ont trigger a transfer on writes to r eg 0 5h [14:13] r / w f s m/ v s p i c lock s el ect 2 1 s et t he a ut ocal f s m an d v s p i c lock (50 m h z ma ximum) 0: i nput crystal r ef erence 1: i nput crystal r ef erence/4 2: i nput crystal r ef erence/16 3: i nput crystal r ef erence/32 [15] r / w xt al falling e dg e for f s m 1 0 us e the falling e dg e of the xtal for f s m a ut ocal clock - r eq uired for b is t [16 ] r / w fo rce r d i vider bypass 1 0 force the r d iv ider bypass for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 55 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.13 r e g 0bh p d r e gister ( d e fault 7c061h) bit t y pe n ame w idth d e fault d es cription [2:0] r / w p d _d el_sel 3 1 s et s p d r eset path delay ( r ec ommended setting 001) [3] r / w s ho rt p d i np uts 1 0 s ho rts the inputs ot the phase frequency detector - t es t only [4] r / w pd _phase_sel 1 0 i nve rts the p d p olarity (program to 0) 0- use with a positive tuning slope vco and passive loop filter (default) 1- use with a n eg ative s lo pe vco or with an inverting a ct ive loop filter with a positive s lo pe vco [5] r / w p d _ up_en 1 1 e na bles the p d u p output [6] r / w p d _dn _en 1 1 e na bles the p d d n o utput [8:7] r / w c s p mode 2 0 cycle s li p prevention mode e xt ra current is driven into the loop flter when the phase error is larger than: 0: d is abled 1: 5.4ns 2: 14.4ns 3: 24.1ns t hi s delay varies by +- 10% with temperature, and +- 12% with process. [9] r / w fo rce cp up 1 0 forces cp up output on - use for t es t only [10] r / w fo rce cp d n 1 0 fo rces cp d n o utput on - use for t es t only [11] r / w fo rce cp m i d r ai l 1 0 force cp m i d r ai l - use for t es t only [14:12] r / w r es erved 3 4 program to 100 [16:15] r / w cp i nt ernal op a mp b ias 2 3 program to 11 [18:17] r / w mc ounter clock g at ing 2 3 mcounter clock g at ing 0: mcounter off 1: n <1 28 2: n < 10 23 3: a ll c locks o n ( r ec ommended setting 11) [19] r / w re served 1 0 program to 0 [21:20] r / w re served 2 0 program to 00 [23:22] r / w re served 2 0 program to 00 2.14 r eg 0 c h e xa ct frequency mode r eg ister ( d efault 000000h) bit t y pe n ame w idth d e fault d es cription [13:0] r / w n um ber of channels per fpd 14 0 comparison frequency divided by the correction r at e, must be an integer. frequencies at exactly the correction rate will have zero frequency error. 0: d is abled 1: d is abled 2:16383d (3fffh) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 56 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.15 r e g 0fh g p o _s p i _ rdi v r e gister ( d efault 000001h) bit t y pe n ame w idth d e fault d es cription [4:0] r / w gpo_ select 5 1d s ig nal selected here is output to s d o pi n when enabled 0: d at a from r eg 0f[5] 1: lock d et ect output 2. lock d et ect t ri gger 3: lock d et ect w in dow output 4: r in g osc t es t 5. pullup h ar d from c s p 6. p ull dn h ard from c s p 7. r es erved 8: r ef erence buffer output 9: r ef d i vider output 10: vco divider output 11. modulator clock from vco divider 12. a ux iliary clock 13. a ux s p i c lock 14. a ux s p i e na ble 15. a ux s p i d at a out 16. p d d n 17 . p d u p 18. s d 3 c lock d ela y 19. s d 3 co re clock 20. a ut o s tr obe i nt eger w ri te 21. a ut ostrobe frac w ri te 22. a uto strobe a ux s p i 23 . s p i l atch e na ble 24. vco d iv ider s yn c r es et 25. s ee d load s tr obe 26.-29 n ot u sed 30. s p i o utput buffer e n 31 . s of t r st b [5] r / w g po t es t d at a 1 0 1 - g po t es t d at a [6] r / w pr event a ut omux s d o 1 0 1- outputs g po data only 0 - a ut omuxes between s d o an d g po d ata [7] r / w l d o d ri ver a lw ays on 1 0 1- l d _ sd o pi n d ri ver always on 0 - l d _ sd o pi n driver only on during s p i r ead cycle [8] r / w d is able pf et 1 0 pr ogram to 0 [9] r / w d is able n f et 1 0 pr ogram to 0 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 57 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.16 r eg 1 0h v co t un e r eg ister ( d efault 000020h) bit t y pe n ame w idth d e fault d es cription [7:0] r o v co s wi tch s e tting 8 32 r ea d only r eg ister. i nd icates the vco switch setting selected by the a ut ocal state machine to yield the nearest free running vco frequency to the desired operating frequency. n ot v alid when r eg 10h[8] = 1, a ut ocal busy. n ot e if a manual change is done to the vco switch settings this register will not indicate the current vco switch position. 0 = highest frequency 1 = 2nd highest ... 256 = lowest frequency n ot e: vco subsystems may not use all the m s bs , in which case the unused bits are dont care [8] r o a uto cal busy 1 0 busy when a ut ocal state machine is searching for the nearest switch setting to the requested frequency. 2.17 r e g 11h s ar r e gister ( d efault 007fffh) bit t y pe n ame w idth d e fault d es cription [18:0] r o sa r e rr or mag counts 19 2 19 -1 sar e rro r magnitude counts [19] r o sa r e rr or s ig n 1 0 sa r e rr or s ig n 0=+ve 1=-ve 2.18 r e g 12h g p o 2 r e gister ( d efault 000000h) bit t y pe n ame w idth d e fault d es cription [0] r o g po 1 0 g po s ta te [1] r o l ock d ete ct 1 0 lock d ete ct s ta tus 1 = locked 0 = unlocked 2.19 r eg 1 3h b i s t r eg ister ( d efault 000000h) bit t y pe n ame w idth d e fault d es cription [15:0] r o b ist s ig nature 19 4697d b ist s ig nature [16] r o b ist bu sy 1 0 b ist bu sy for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 58 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 3.0 v co s ubsystem r eg ister map please note that the vco subsystem uses indirect addressing via r eg 05h . for more detailed information on how to write to the vco subsystem please see section 1.19 vco s er ial port i nt erface ( s p i ) . 3.1 v c o _ r eg 00h t un ing bit type name width default description [0] w o ca l 1 0 vco tune voltage is redirected to a temperature compensated calibration voltage [8:1] w o c a p s 8 16 vc o sub-band selection. 0 - max frequency 1111 1111 - min fre quen cy. n ot a ll sub-bands are used on the various products. 3.2 v co _ r eg 01h e n ables bit type name width default description [0] w o m aster e nab le vco s u bsystem 1 1 0 - a ll vco subsystem blocks off m anual mode ( vco_ r eg 03h [2] = 1) 1- a nd ed w ith local enables only a ut o mode ( vco_ r eg 03h [2] = 0) 1- master enable ignores local enables [1] w o m anual mode pll buffer enable 1 1 e na bles pll buffer in manual mode only [2] w o m anual mode r f bu ffer enable 1 1 e na bles r f bu ffer to output in manual mode only [3] w o m anual mode d iv ide by 1 enable 1 1 e na bles r f di vide by 1 in manual mode only [4] w o m anual mode r f d iv ider enable 1 1 e na bles r f di vider in manual mode only [8:5] w o d ont care 4 0 dont care for example, to turn disable the r f bu ffer in the vco subsystem and mute the output of the h mc 834lp6 ge , bi t 2 in vco_ r eg 01h needs to be cleared. i f th e other bits are left unchanged, then 0 0001 1011 needs to be written into vco r eg 01h. t he v co subsystem register is accessed via a write to pll subsystem r eg 0 5h = 0 0001 1011 0001 000 = d 88 h r eg 0 5h [2:0] = 000; vco subsystem i d 0 r eg 0 5h [6:3] = 0001; vco subsystem register address r eg 0 5h [7] = 1; master enable r eg 0 5h [8] = 1; pll buffer enable r eg 0 5h [9] = 0; d is able r f bu ffer r eg 0 5h [10] = 1; d iv ide by 1 enable r eg 0 5h [11] = 1; r f d iv ider enable r eg 0 5h [16:12] = 0; dont care for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 59 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 3.3 v c o _ r eg 02h biases bit type name width default description [5:0] w o r f d ivi de ratio 6 1 0 - mute, vco and pll buffer on, r f ou tput stages off 1 - fo 2 - fo/2 3 - invalid, defaults to 2 4 - fo/4 5 - invalid, defaults to 4 6 - fo/6 ... 60 - fo/60 61 - invalid, defaults to 60 62 - fo/62 > 62 - invalid, defaults to 62 n ot e: t hi s register automatically controls the enables to the, r f ou tput buffer, r f di vider, r f di vide by 1 path, and requires master e na ble ( vco_ r eg 01h [0] = 1) and a ut o r fo m ode ( vco_ r eg 0 3h [2] = 0) n ot e: bit[0] is a dont care in manual r fo m ode. [7:6] w o r f o utput buffer gain control 2 3 11 - max g ai n 10 - max g ai n - 3 db 01 - max g ai n - 6 db 00 - max g ai n - 9 db [8] w o d iv ider output stage gain control 1 0 1 - max g ai n 0 - max g ai n - 3 db used to fatten the output power level across frequency ? for divide-by 1 or divide-by 2 it is recommended to set this bit to 1. 0 will reduce output power and degrade noise foor performance. ? for divide-by 4 or higher, it is recommended to set this bit to 0 to maintain fat output power across divider settings. s et ting this bit to 1, with divide-by 4 or higher provides higher output power compared to the divide- by 1 or two case. for example, to write 0_1111_1110 into vco_ r eg 02h vco subsystem (vco_ id = 000b), and set the vco output divider to divide by 62, the following needs to be written to r eg 0 5h =0 _1111_1110, 0 010, 0 0 0 b. r eg 0 5h [2:0] = 00; subsystem i d 0 r eg 0 5h [6:3] = 0010; vco register address 2d r eg 0 5h [16:7] = 0 _1111_1110 ; d iv ide by 62, max output r f ga in, d iv ider output stage gain = 0 3.4 v c o _ r eg 03h c on fg bit type name width default description [0] w o f undamental/ d oub ler mode s ele ction 1 1 0- e nable the frequency doubler mode of operation 1 - e na ble fundamental mode of operation - for more information please see vco s ub system section. [1] w o r eserved 1 0 reserved [2] w o m anual r fo m ode 1 0 0 - a uto r fo mode (recommended) 1 - m anual r fo m ode a ut o r fo m ode controls output buffers and r f di vider enables according to r f di vider setting in vco_ r eg 02h [5:0] manual r fo mode requires manual enables of individual blocks via vco_ r eg 01h [4:3] w o r f bu ffer bias 2 2 program to 10 when fundamental mode enabled program to 00 when doubler mode enabled [8:5] w o s par e 4 2 dont care for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 60 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 3.5 v co _ r eg 04h c al/ bias s pecifed performance is only guaranteed with the required settings in this table. other settings are not s upported. bit type name width default description [2:0] w o v co bias 3 1 program to 5d [4:3] w o p ll buffer bias 2 1 program to 1d [6:5] w o f ndlmtr bias 2 2 program to 3d [8:7] w o p reset cal 0 2 1 program to 2d 3.6 v c o _ r eg 05h c f_ c al bit type name width default description [1:0] w o c f l 2 2 program to 0d [3:2] w o c f ml 2 2 program to 3d [5:4] w o c f m h 2 2 pr ogram to 3d [7:6] w o c f h 2 2 pr ogram to 3d [8] w o s par e 1 0 program to 0d 3.7 v c o _ r eg 06h msb c al bit type name width default description [1:0] w o m s b l 2 3 pr ogram to 3d [3:2] w o m s b ml 2 3 program to 3d [5:4] w o m s b m h 2 3 pr ogram to 3d [7:6] w o m s b h 2 3 pr ogram to 3d [8] w o s par e 1 0 dont care for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d plls with i nt egrated vco - s m t 61 HMC834LP6GE v01.0112 fractional- n p ll w ith i nt egrated v co 45 - 1 050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z note s: for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d |
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