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sles030 ? february 2002 1 www.ti.com features tas5000 + tas5100a tdaa system-high quality digital audio amplification 93-db dynamic range (tdaa system) thd+n < 0.08% (1 khz, 1 w to 30 w rms into 6 ? ) power efficiency > 90% into 8- ? load low profile, smd 32-pin powerpad ? package requires no heat-sink when using recommended layout 30-w rms continuous power into 4 ? to 8 ? self-protecting design 3.3-v digital interface emi compliant when used with recommended system design applications dvd receiver home theater car audio amplifiers and head units internet music appliance mini/micro component systems description true digital audio amplifier (tdaa) is a new paradigm in digital audio. the tdaa system currently consists of the tas5000 pcm-pwm modulator device + tas5100a pwm power output device. this system accepts a serial pcm digital audio stream and converts it to a 3.3-v pwm audio stream (tas5000). the tas5100a device then provides a large-signal pwm output. this digital pwm signal is then demodulated providing power output for driving loudspeakers. this patented technology provides low-cost, high-quality, high-efficient digital audio applicable to many audio systems developed for the digital age. the tas5100a is a single-channel pwm power audio device. it contains integrated gate drivers, four matched and electrically isolated enhancement- mode n-channel power dmos transistors. also, included are protection and fault-reporting circuitry. this device is optimized for use with the tas5000 digital modulator. typical tdaa stereo audio system digital audio ? tas3001 ? dsp ? spdif ? 1394 tas5000 l-c filter l-c filter left right tas5100 a ? volume ? eq ? drc ? bass ? treble ? serial audio input port ? internal pll ? pcm?pwm modulator ? 2 h-bridge power devices tas5100 a powerpad and equibit are trademarks of texas instruments. copyright ? 2002, texas instruments incorporated please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
sles030 ? february 2002 2 www.ti.com terminal assignments the tas5100a is offered in a thermally enhanced 32-pin htssop surface-mount package (dap). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 pwm_ap pwm_am err1 err0 shutdown dvdd dvss dvss dvss vrfilt bias_a bias_b pwdn reset pwm_bm pwm_bp pvdda2 ldrouta bootstrapa pvdda1 pvdda1 outputa outputa pvss pvss outputb outputb pvddb1 pvddb1 bootstrapb ldroutb pvddb2 dap package (top view) ordering information t a package 0 c to 70 c TAS5100ADAP ?40 c to 85 c tas5100aidap references t as5000 digital audio pwm process data manual ? ti literature number slas270 system design considerations for true digital audio power amplifiers ? ti literature number slaa117 digital audio measurements ? ti literature number slaa114 powerpad thermally enhanced package ? ti literature number slma002
sles030 ? february 2002 3 www.ti.com functional block diagram boot strap gate drive diff rcvr ldr boot strap gate drive diff rcvr ldr control/sense circuit bandgap reference 1/2 h-bridge 1/2 h-bridge outputa outputa pvss bootstrapb pvddb1 pvddb1 outputb outputb dvdd dvss pvss pwm_ap pwm_am pwdn reset shutdown err1 err0 ldroutb vrfilt pvddb2 pwm_bm pwm_bp pvdda2 ldrouta bootstrap a pvdda1 pvdda1 bias_a bias_b
sles030 ? february 2002 4 www.ti.com suggested system block diagrams see application note slaa117 for more details. ? usb ? ieee 1394 ? spdif ? adc ? automotive most network digital audio tas3001 iic audio control tas5000 tas5100a left right ? digital parametric eq ? volume ? drc ? bass ? treble ? serial audio input port ? internal pll ? two h-bridges tas5100a figure 1. system #1: stereo configuration with tas3001 digital audio processor ti dsp ? dolby ac-3 ? dts ? volume ? eq ? drc ? bass ? treble home theater dvd 6-channel encoded digital audio source tas5000 tas5100a ch1 ch2 tas5000 ch3 ch4 tas5000 ch5 ch6 6 tas5100a tas5100a tas5100a tas5100a tas5100a left right surround left surround right center subwoofer tas5100a figure 2. system #3: 6-channel audio playback
sles030 ? february 2002 5 www.ti.com terminal functions terminal i/o description name no. i/o description bias_a 11 i connect external resistor to dvss. see application note slaa117 bias_b 12 i connect external resistor to dvss. see application note slaa117 bootstrapa 30 o bootstrap capacitor pin for h-bridge a bootstrapb 19 o bootstrap capacitor pin for h-bridge b dvdd 6 i 3.3-v digital voltage supply for logic dvss 7, 8, 9 i digital ground for logic is internally connected to pvss. all three pins must be tied together but not connected externally to pvss. see figure 5. err1 3 o error/warning report indicator. this output is open drain with internal pullup resistor. err0 4 o error/warning report indicator. this output is open drain with internal pullup resistor. ldrouta 31 o low voltage drop-out regulator output a (not to be used to supply current to external circuitry) ldroutb 18 o low voltage drop-out regulator output b (not to be used to supply current to external circuitry) outputa 26, 27 o h-bridge output a outputb 22, 23 o h-bridge output b pvdda1 28, 29 i high voltage power supply, h-bridge a pvdda2 32 i high voltage power supply for low-dropout voltage regulator a-side pvddb1 20, 21 i high voltage power supply, h-bridge b pvddb2 17 i high voltage power supply for low-dropout voltage regulator b-side pvss 24, 25 i high voltage power supply ground pwdn 13 i power down = 0, normal mode = 1 pwm_ap 1 i pwm input a(+) pwm_am 2 i pwm input a(?) pwm_bp 16 i pwm input b(+) pwm_bm 15 i pwm input b(?) reset 14 i reset and mute mode = 0, normal mode = 1, when in reset mode, h-bridge mosfets are in low-low output state. asserting the reset signal low causes all fault conditions to be cleared. shutdown 5 o device is in shutdown due to fault condition, normal mode = 1, shutdown = 0, when device is in shutdown mode the h-bridge mosfets are in low-low output state. the latched output can be cleared by asserting the reset signal. this output is open drain with internal pullup resistor. vrfilt 10 o a filter capacitor must be added between vrfilt and dvss pins. note: the four pwm inputs: pwm_ap, pwm_am, pwm_bp, and pwm_bm must always be connected to the tas5000 output pins, and never left floating. floating pwm input pins causes an illegal pwm input state signal to be asserted. dual pins: outputa, outputb, pvdda1 and pvddb1 must have both pins connected externally to the same point on the circuit board, respectively. both pvss pins must also be connected together externally. these multiple pins are for the high current dmos outp ut devices. failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires and can cause the device to fail. all electrical characteristics are specified and measured with all of the multiple pins conne cted to the same node, respectively.
sles030 ? february 2002 6 www.ti.com functional description pwm h-bridge state control the digital interface control signals consists of pwm_ap, pwm_am, pwm_bp, and pwm_bm. these signals are a complementary differential signal format for the a-side h-bridge and the b-side h-bridge. bootstrapped gate drive the tas5100a includes two dedicated bootstrapped power supplies. a bootstrap capacitor is connected between the individual bootstrap pin and the associated output as described in the application note slaa117. for example, a capacitor is connected between the bootstrapa pin and outputa pin, and another capacitor is connected between the bootstrapb pin and the outputb pin. the bootstrap power supply minimizes the number of high voltage power supply levels externally supplied to the system while providing a low noise supply level for driving the high-side n-channel dmos transistors. see application note slaa117 for details. low-dropout voltage regulator two on-chip low-dropout voltage regulators (ldo) are provided to minimize the number of external power supplies needed for the system. these voltage regulators are for internal circuits only and cannot be used for external circuitry. each ldo is dedicated to an h-bridge and its gate driver. an ldo output capacitor is connected between the individual ldo output pin and the associated output return as described in the application note slaa117. for example, a capacitor is connected between the ldrouta pin and pvss pin, and another capacitor is connected between the ldroutb pin and pvss pin. high-current h-bridge output stage the positive outputs of the h-bridge are the two outputa pins. the negative outputs of the h-bridge are the two outputb pins. the logic for the input command to h-bridge outputs is described in the h-bridge output mapping section below. when the tas5100a is in the normal mode, as seen in the h-bridge output mapping tables, the outputs are decoded from the inputs. however, the tas5100a is immediately shut down if any of the following error conditions occur: over-current, over-temperature, low regulator output voltage, or an illegal pwm input state is applied. for these conditions, the outputs are set to the appropriate disabled state as specified in the h-bridge output mapping section, and the shutdown pin is set low. h-bridge output mapping the a-side h-bridge output is designed to the following truth table: inputs outputs description reset pwdn pwm_ap pwm_am shutdown outputa description x x x x 0 0 or hi-z ? shutdown x 0 x x 1 hi-z powerdown 0 1 x x 1 0 reset 1 1 0 0 0 0 shutdown 1 1 0 1 1 0 normal 1 1 1 0 1 1 normal 1 1 1 1 0 0 shutdown ? output is 0 for low voltage, over temperature, and illegal input. hi-z is for over current.
sles030 ? february 2002 7 www.ti.com h-bridge output mapping (continued) the b-side h-bridge output is designed to the following truth table: inputs outputs description reset pwdn pwm_bp pwm_bm shutdown outputb description x x x x 0 0 or hi-z ? shutdown x 0 x x 1 hi-z powerdown 0 1 x x 1 0 reset 1 1 0 0 0 0 shutdown 1 1 0 1 1 0 normal 1 1 1 0 1 1 normal 1 1 1 1 0 0 shutdown ? output is 0 for low voltage, over temperature, or illegal input. hi-z is for over current. control/sense circuitry the control/sense circuitry consists of the following 3.3-v logic level pins: pwdn , reset , err0 , err1 , and shutdown . the active-low pwdn input pin powers down a ll internal circuitry and forces the h-bridge outputs to the hi-z state. when the pwdn pin is low, the open drain err0 , err1 , and shutdown pins are also disabled so that their outputs can be pulled high. the active-low reset input pin forces the h-bridge outputs to the low-low state and resets the over-current shutdown latch. the pwdn pin overrides the reset pin. the err0 , err1 , and shutdown outputs indicate the following conditions in the tas5100a as shown in the table below. these three outputs are open-drain connections with internal pullup resistors so that wire-ored connections can be made by the user with other external control devices. the short circuit protect error condition latches the tas5100a in this shutdown state and force the h-bridge outputs to the hi-z state until the device is reset by means of the reset pin. the illegal pwm input state, over-temperature, and low regulator voltage error conditions do not latch the device in the shutdown condition. instead the h-bridge outputs are forced to the low-low state and the tas5100a returns to normal operation as soon as the error condition ends. loss of clocking pwm signal is also considered an illegal pwm input state. shutdown err1 err0 function outputa outputb 0 0 0 illegal pwm input state low low 0 0 1 short circuit protect (latch) hi-z hi-z 0 1 0 over temperature protect low low 0 1 1 low regulator voltage protect low low 1 0 0 reserved ? ? 1 0 1 reserved ? ? 1 1 0 high temperature ? warning normal normal 1 1 1 normal operation normal normal
sles030 ? february 2002 8 www.ti.com device operation power sequences system power-up/power-down sequencing the recommended power-up/power-down sequence is shown in figure 3. for proper operation the reset signal should be kept low when both dvdd and output power (pvdda1, pvdda2, pvddb1, and pvddb2) are being applied. the reset signal should remain low for at least 1 ms after output power is applied. > 1 ms dvdd ? pwdn pvdda1 pvdda2 pvddb1 pvddb2 reset > 1 ms > 100 s ? for most applications, it is recommended that pin 13 (pwdn ) be connected directly to pin 6 (dvdd). figure 3. power-up/power-down sequence reset function the device is put into a res et condition when the (active low) reset signal is asserted. while in the reset state, the input h-bridge control signals consisting of pwm_ap , pwm_am, pwm_bp, and pwm_bm are ignored, and the h-bridge mosfets are placed in a state where outputa and outputb are both low. asserting the reset signal low also causes the short circuit protection latch to be reset. the reset signal is normally connected to the valid signal from the tas5000. reinitialization sequence proper initial conditions for this device include asserting the reset signal until the reset operation has completed (1 ms). additionally, when using this device with the tas5000 controller, this function can be accomplished by asserting the reset pin on the tas5000 during the reset sequence (see figure 3). audio application considerations power supply decoupling power supply decoupling and layout optimization information should be obtained by following the detailed information in the application note slaa117. optimal power transfer for h-bridge the tas5100a is a power h-bridge that is designed to deliver 30 w/rms into loads of 4 ? to 8 ? . rather than requiring the usual heatsink, the package is designed to deliver this wattage by careful layout as described in the application note slaa117. careful attention must be given to the value of the high-voltage power supply level for a given load resistance. see recommended operating conditions.
sles030 ? february 2002 9 www.ti.com audio application considerations (continued) reconstruction output filter an output reconstruction filter is required between the h-bridge outputs and the loudspeaker load. this second order low-pass filter passes the audio information to the loudspeaker, while filtering out the high frequency out-of-band information contained in the h-bridge output pwm pulses. the values of the l and c components selected are dependent on the loudspeaker load impedance. see application note slaa117. fault indicator usage the tas5100a is a self-protecting device that provides device fault reporting, including over-temperature protect, under-voltage lockout (low-regulator voltage), and short circuit protection. the short circuit protection protects against short circuits that may occur at the loudspeaker load when configured according to the application note slaa117. the t as5100a is not recommended for driving loads less than 4 ?, since the internal current limit protection might be activated. an under-voltage lockout signal occurs when an insufficient voltage level is present on the ldrouta or ldroutb pins. during this condition gate drive levels are not sufficient for driving the power mosfets. normal operation is resumed when the minimum proper ldrouta or ldroutb level is obtained, and the low regulator voltage protect signal is de-asserted. see the control/sense circuitry section for error and warning conditions. a high temperature warning signal is asserted on pin err0 when the device temperature exceeds 130 c typical. if the internal device temperature exceeds 150 c typical, the over temperature protect signal is asserted and the tas5100a is shut down. the device re-enables once the temperature drops to 130 c typical. see the control/sense circuitry section for error and warning conditions. detection of an illegal pwm input state or the loss of a clocking pwm input signal causes an illegal pwm input state signal to be asserted on the err1 and err0 pins and sets the shutdown pin to the low state. absolute maximum ratings over operating free-air temperature (unless otherwise noted) ? dc supply voltage range: dvdd to dvss ?0.3 v to 4.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pwm_ap, pwm_am, pwm_bp, pwm_bm ?0.3 v to dvdd + 0.3 v . . . . . . . . . . . . . . . . . reset , pwdn ?0.3 v to dvdd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pvdda1 to pvss, pvddb1 to pvss ?0.3 v to 28 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pvdda2 to pvss, pvddb2 to pvss ?0.3 v to 27 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output dmos drain-to-source breakdown voltage 28 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous dmos rms drain current, each output 3 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous source-to-drain rms body diode current 3 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating junction temperature range, t j ?40 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds) 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. dissipation derating table package t a 25 c ? power rating derating factor above t a = 25 c t a = 70 c power rating dap 5.3 w 42.5 mw/ c 3.4 w ? see the texas instruments document, powerpad thermally enhanced package application report (literature number slma002), for more information on the powerpad package. the thermal data was measured on a pcb layout based on the information in the section entitled texas instruments recommended board for powerpad ? of the before mentioned document. data in table is for specified layout. under other conditions the thermal performance may vary. see t exas instruments document slaa117 for more detailed application information.
sles030 ? february 2002 10 www.ti.com recommended operating conditions (nominal output power = 30 w (rms), t a = 25 c) thermal data ? parameter min nom max unit shutdown junction temperature, t j(sd) 150 c warning junction temperature, t j(w) 130 c operating ambient temperature, t a 0 25 70 c thermal resistance junction-to-case, jc 2 oz. trace and copper pad with solder 0.32 c/w thermal resistance junction-to-ambient, ja 2 oz. trace and copper pad with solder 23.5 c/w thermal resistance junction-to-case, jc 2 oz. trace and copper pad without solder 0.32 c/w thermal resistance junction-to-ambient, ja 2 oz. trace and copper pad without solder 44.3 c/w ? one of the most influential components on the thermal performance of a package is board design. in order to take full advantage of the heat dissipating abilities of the powerpad packages, a board must be used that acts similar to a heat sink and allows for the use of the exposed (and solderable), deep downset pad. see appendix a of the powerpad thermally enhanced package application note, ti literature number slma002 and the thermal design of the powerpad pcb layout section of the system design considerations for true digital audio power amplifiers application note, ti literature number slaa117. r l = 4 ? to 8 ? parameter min nom max unit digital dvdd to dvss 3 3.3 3.6 v pvdda2 to pvss 16.5 22 24 supply voltage regulator pvddb2 to pvss 16.5 22 24 v supply voltage regulator pvdda2 to pvss 10.5 16.5 v pvddb2 to pvss 10.5 16.5 ? connect ldrouta to pvdda2 and connect ldroutb to pvddb2. under this condition h-bridge forward on-state resistance is increased . this increases internal power dissipation. maximum output power may need to be reduced to meet thermal conditions. r l = 8 ? parameter min nom max unit supply voltage power pvdda1 to dvss 0 26 27 v supply voltage power pvddb1 to pvss 0 26 27 v r l = 6 ? parameter min nom max unit supply voltage power pvdda1 to dvss 0 23 24 v supply voltage power pvddb1 to pvss 0 23 24 v r l = 4 ? parameter min nom max unit supply voltage power pvdda1 to dvss 0 20 21 v supply voltage power pvddb1 to pvss 0 20 21 v
sles030 ? february 2002 11 www.ti.com static digital specifications reset , pwdn , pwm_ap, pwm_am, pwm_bp, pwm_bm, t a = 25 c, dvdd = 3.3 v parameters min max unit high-level input voltage, v ih 2 v low-level input voltage, v il 0.8 v input leakage current ?10 10 a err0 , err1 , shutdown , (open drain with internal pullup resistor) t a = 25 c, dvdd = 3.3 v) parameters min max unit internal pullup resistors from shutdown , err0 , err1 to dvdd 15 k ? low-level output voltage (i o = 4 ma), v ol 0.4 v tas5000/tas5100a system performance measured at the speaker terminals see the ti literature number slaa117 for tas5000/tas5100a system performance. electrical characteristics supply, t a = 25 c (f switching = 384 khz, outputa and outputb not connected, dvdd = 3.3 v, pvdda1 = 25 v, pvddb1 = 25 v, pvdda2 = 22 v, pvddb2 = 22 v, 50% input duty cycle) parameter typ max unit dvdd operating 2 ma dvdd pwdn = 0 500 a supply current pvdda1 operating ? 6.3 ma supply current pvdda1 pvddb1 pwdn = 0 25 a pvdda2 operating 6.5 ma pvdda2 pvddb2 pwdn = 0 250 a ? 13-k ? resistor from bias_a (pin 11) to dvss and 13-k ? resistor from bias_b (pin 12) to dvss. h-bridge transistors, pvdda2 = pvddb2 = 22 v, dvdd = 3.3 v, t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit drain-to-source breakdown voltage i d = 1 ma, pwdn = 0, hi-z state 28 v forward on-state resistance, low side drivers outputa and outputb to pvss i sink = 2.5 a, see notes 2, 3, and 4, pwm_ap = pwm_bp = 0, pwm_am = pwm_bm = 1 0.2 ? forward on-state resistance, high side drivers pvdda1 to outputa, pvddb1 to outputb i source = 2.5 a, see notes 2, 3, and 5, pwm_ap = pwm_bp = 1, pwm_am = pwm_bm = 0 0.2 ? on-state resistance matching low-side drivers 98% on-state resistance matching high-side drivers 98% notes: 1. test time should be < 1 ms to avoid temperature change. 2. these parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 3. connect pvdda2 and pvddb2 to 22-v power supply with respect to pvss. ldrouta, ldroutb, bootstrapa, and bootstrapb pins open. 4. connect pvdda2 to 22-v power supply with respect to pvss. ldrouta, ldroutb, bootstrapa and bootstrapb capacitors are connected respectively. clock pwm inputs to allow bootstrap capacitors to charge. 93?99% modulation must be used on pwm_ap, pwm_am, pwm_bp, and pwm_bm inputs to prevent the activity detector from shutting down the device during this measurement. note that f switching = 384 khz.
sles030 ? february 2002 12 www.ti.com electrical characteristics, voltage regulator, t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit output voltage (ldrouta, ldroutb) i o = 5 ma, pvdda2 = pvddb2 = 18 v to 27 v, see note 6, dvdd = 3.3 v 14.5 15.3 16 v note 5: these voltage regulators are for internal gate drive circuits only and are not to be used under any circumstances to sup ply current to external circuity. thermal information the thermally enhanced dap package is based on the 32-pin htssop, but includes a thermal pad (see figure 4) to provide an effective thermal contact between the ic and the pwb. traditionally, surface mount and power have been mutually exclusive terms. a variety of scaled-down t o-220 type packages have leads formed as gull wings to make them applicable for surface-mount applications. these packages, however, have two shortcomings: they do not address the low profile requirements (<2 mm) of many of today?s advanced systems, and they do not offer a terminal-count high enough to accommodate increasing integration. on the other hand, traditional low-power surface-mount packages require power-dissipation derating that severely limits the usable range of many high-performance analog circuits. the powerpad package (thermally enhanced htssop) combines fine-pitch surface-mount technology with thermal performance comparable to much larger power packages. the powerpad package is designed to optimize the heat transfer to the pwb. because of the very small size and limited mass of a htssop package, thermal enhancement is achieved by improving the thermal conduction paths that remove heat from the component. the thermal pad is formed using a patented lead-frame design and manufacturing technique to provide a direct connection to the heat-generating ic. when this pad is soldered or otherwise thermally coupled to an external heat dissipater, high power dissipation in the ultrathin, fine-pitch, surface-mount package can be reliably achieved. see dissipation derating table. die die thermal pad side view (a) end view (b) bottom view (c) figure 4. views of thermally enhanced dap package
sles030 ? february 2002 13 www.ti.com application information tas5100a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 snubber circuit error reporting snubber circuit _ + dc pwm_ap pwm_am err1 err0 shutdown dvdd dvss dvss dvss vrfilt bias_a bias_b pwdn reset pwm_bm pwm_bp pvdda2 ldrouta bootstrapa pvdda1 pvdda1 outputa outputa pvss pvss outputb outputb pvddb1 pvddb1 bootstrapb ldroutb pvddb2 l1 l2 c1 r1 r2 c2 c3 c4 c5 c6 3.3 v reset pwm_m_l pwm_p_l valid tas5000 c7 22 v 22 v figure 5. typical tas5100a application (one channel shown) see the application note, ti literature number slaa117 for detailed application information.
sles030 ? february 2002 14 www.ti.com mechanical data dap (r-pdso-g**) powerpad ? plastic small-outline package 0,25 0,75 0,50 0,15 nom gage plane nom 6,20 8,40 7,80 thermal pad (see note d) 38 12,60 11,10 32 seating plane 12,40 10,90 4073257/a 07/97 20 0,19 19 a 0,30 38 1 9,80 28 a max pins ** 9,60 a min dim 1,20 max 10,90 11,10 30 38 pins shown 0,10 0,65 m 0,13 0 ? 8 0,15 0,05 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. d. the package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. this pad is electric ally and thermally connected to the backside of the die and possibly selected leads. thermal pad size is 3,86 mm x 3,91 mm for the 32-pin tas5100a device. e. falls within jedec mo-153 powerpad is a trademark of texas instruments.
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) TAS5100ADAP nrnd htssop dap 32 tbd call ti call ti TAS5100ADAPr nrnd htssop dap 32 tbd call ti call ti TAS5100ADAPrg4 nrnd htssop dap 32 tbd call ti call ti tas5100aidap nrnd htssop dap 32 tbd call ti call ti tas5100aidapr nrnd htssop dap 32 tbd call ti call ti tas5100aidaprg4 nrnd htssop dap 32 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 28-dec-2006 addendum-page 1
tape and reel box information device package pins site reel diameter (mm) reel width (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TAS5100ADAPr dap 32 site 60 330 24 8.6 11.5 1.6 12 24 q1 tas5100aidapr dap 32 site 60 330 24 8.6 11.5 1.6 12 24 q1 package materials information www.ti.com 9-oct-2007 pack materials-page 1
device package pins site length (mm) width (mm) height (mm) TAS5100ADAPr dap 32 site 60 367.0 367.0 45.0 tas5100aidapr dap 32 site 60 367.0 367.0 45.0 package materials information www.ti.com 9-oct-2007 pack materials-page 2

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