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? semiconductor components industries, llc, 2018 may, 2018 ? rev. p3 1 publication order number: nv24c64lv/d nv24c64lv product preview eeprom serial 64-kb i 2 c - automotive grade 1 description the nv24c64lv is a eeprom serial 64 ? kb i 2 c ? automotive grade 1 device, organized internally as 256 pages of 32 bytes each. this device supports the standard (100 khz), fast (400 khz) and fast ? plus (1 mhz) i 2 c protocol. data is written by providing a starting address, then loading 1 to 32 contiguous bytes into a page write buffer, and then writing all data to non ? volatile memory in one internal write cycle. data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. external address pins make it possible to address up to eight nv24c64lv devices on the same bus. features ? supports standard, fast and fast ? plus i 2 c protocol ? 1.7 v to 5.5 v supply voltage range ? 32 ? byte page write buffer ? fast write time (4 ms max) ? hardware write protection for entire memory ? schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda) ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? automotive grade 1 temperature range ? us ? 8, udfn ? 8, soic ? 8 and tssop ? 8 packages ? these devices are pb ? free, halogen free/bfr free, and rohs compliant this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. www. onsemi.com see detailed ordering, marking and shipping information in the package dimensions section on p age 9 of this data sheet. ordering information us8 u suffix case 493 pin configuration sda wp v cc v ss a 2 a 1 a 0 1 scl (top view) soic ? 8 dw suffix case 751bd udfn ? 8 muw3 suffix case 517dh tssop ? 8 dt suffix case 948al 1 1 8
nv24c64lv www. onsemi.com 2 figure 1. functional symbols sda scl wp nv24c64lv v cc v ss a 2 , a 1 , a 0 device address a 0 , a 1 , a 2 serial data sda serial clock scl write protect wp power supply v cc ground v ss function pin name pin function table 1. absolute maximum ratings parameters ratings units storage temperature ?65 to +150 c voltage on any pin with respect to ground (note 1) ?0.5 to +6.5 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the dc input voltage on any pin should not be lower than ? 0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than ? 1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. table 2. reliability characteristics symbol parameter max units n end (note 2) endurance 1,000,000 write cycles (note 3) t dr (note 2) data retention 100 years 2. t a = 25 c 3. a write cycle refers to writing a byte or a page.
nv24c64lv www. onsemi.com 3 table 3. d.c. operating characteristics ( v cc = 1.7 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise speci ed.) symbol parameter test conditions min max units i ccr read current read, f scl = 1 mhz 1 ma i ccw write current write, f scl = 1 mhz 1 ma i sb standby current all i/o pins at gnd or v cc 2 a i l i/o pin leakage pin at gnd or v cc 2 a v il input low voltage scl, sda ? 0.5 v cc x 0.3 v v ih input high voltage scl, sda v cc x 0.7 v cc + 0.5 v v ila input low voltage a2, a1, a0 and wp ? 0.5 v cc x 0.3 v v iha input high voltage a2, a1, a0 and wp v cc x 0.8 v cc + 0.5 v v ol1 output low voltage v cc 2.5 v, i ol = 3.0 ma 0.4 v v ol2 output low voltage v cc < 2.5 v, i ol = 1.0 ma 0.2 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. table 4. pin impedance characteristics (v cc = 1.7 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise speci ed.) symbol parameter conditions min max units c in (note 4) sda i/o pin capacitance v in = 0 v 8 pf c in (note 4) input capacitance (other pins) v in = 0 v 6 pf r pd (note 5) wp, a0, a1 or a2 on ? chip pull ? down resistor v in < v iha 50 k i pd (note 5) wp, a0, a1 or a2 on ? chip pull ? down current v in > v iha 2 a 4. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 5. for improved noise immunity (and to allow for float ing input pins), the wp, a0, a1 & a2 inputs are pulled ? down to gnd by relatively strong on ? chip resistors. when attempting to drive these inputs high, the external drivers must be able to supply sufficient current, unt il the input level at the pin exceeds v iha . once the input level at the pin exceeds v iha , the resistive pull ? down (r pd ) converts to a constant current pull ? down (i pd ).
nv24c64lv www. onsemi.com 4 table 5. a.c. characteristics (v cc = 1.7 v to 5.5 v, t a = ? 40 c to +125 c unless otherwise noted.) (note 6) symbol parameter standard fast fast ? plus units min max min max min max f scl clock frequency 100 400 1,000 khz t hd:sta start condition hold time 4 0.6 0.25 s t low low period of scl clock 4.7 1.3 0.45 s t high high period of scl clock 4 0.6 0.40 s t su:sta start condition setup time 4.7 0.6 0.25 s t hd:dat data in hold time 0 0 0 s t su:dat data in setup time 250 100 50 ns t r (note 7) sda and scl rise time 1,000 300 100 ns t f (note 7) sda and scl fall time 300 300 100 ns t su:sto stop condition setup time 4 0.6 0.25 s t buf bus free time between stop and start 4.7 1.3 0.5 s t aa scl low to data out valid 3.5 0.9 0.40 s t dh (note 7) data out hold time 100 100 50 ns t i (note 7) noise pulse filtered at scl and sda inputs 50 50 50 ns t su:wp wp setup time 0 0 0 s t hd:wp wp hold time 2.5 2.5 1 s t wr write cycle time 4 4 4 ms t pu (notes 7, 8) power-up to ready mode 0.35 0.35 0.35 ms *v cc(min) = 1.6 v for read operations, t a = ? 20 c to +85 c 6. test conditions according to ?a.c. test conditions? table. 7. tested initially and after a design or process change that affects this parameter. 8. t pu is the delay between the time v cc is stable and the device is ready to accept commands. table 6. a.c. test conditions input levels 0.2 x v cc to 0.8 x v cc for v cc 2.2 v; 0.15 x v cc to 0.85 x v cc for v cc < 2.2 v input rise and fall times 50 ns input reference levels 0.3 x v cc , 0.7 x v cc output reference levels 0.3 x v cc , 0.7 x v cc output load current source: i ol = 6 ma (v cc 2.5 v); i ol = 2 ma (v cc < 2.5 v); c l = 100 pf
nv24c64lv www. onsemi.com 5 power-on reset (por) each nv24c64lv incorporates power-on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi-directional por behavior protects the device against ?brown-out? failure following a temporary loss of power. pin description scl: the serial clock input pin accepts the clock signal generated by the master. sda: the serial data i/o pin accepts input data and delivers output data. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a 0 , a 1 and a 2 : the address inputs set the device address that must be matched by the corresponding slave address bits. the address inputs are hard-wired high or low allowing for up to eight devices to be used (cascaded) on the same bus. when left floating, these inputs are pulled low internally. wp: when pulled high, the write protect input pin inhibits all write operations. when left floating, this pin is pulled low internally. functional description the nv24c64lv supports the inter-integrated circuit (i 2 c) bus protocol. the protocol relies on the use of a master device, which provides the clock and directs bus traffic, and slave devices which execute requests. the nv24c64lv operates as a slave device. both master and slave can transmit or receive, but only the master can assign those roles. i 2 c bus protocol the 2-wire i 2 c bus consists of two lines, scl and sda, connected to the v cc supply via pull-up resistors. the master provides the clock to the scl line, and either the master or the slaves drive the sda line. a ?0? is transmitted by pulling a line low and a ?1? by letting it stay high. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, sda must remain stable while scl is high. start/stop condition an sda transition while scl is high creates a start or stop condition (figure 2). the start consists of a high to low sda transition, while scl is high. absent the start, a slave will not respond to the master. the stop completes all commands, and consists of a low to high sda transition, while scl is high. device addressing the master addresses a slave by creating a start condition and then broadcasting an 8-bit slave address. for the nv24c64lv, the first four bits of the slave address are set to 1010 (ah); the next three bits, a 2 , a 1 and a 0 , must match the logic state of the similarly named input pins. the r/w bit tells the slave whether the master intends to read (1) or write (0) data (figure 3). acknowledge during the 9 th clock cycle following every byte sent to the bus, the transmitter releases the sda line, allowing the receiver to respond. the receiver then either acknowledges (ack) by pulling sda low, or does not acknowledge (noack) by letting sda stay high (figure 4). bus timing is illustrated in figure 5. start condition stop condition sda scl figure 2. start/stop timing figure 3. slave address bits 1010 device address a 2 a 1 a 0 r/w
nv24c64lv www. onsemi.com 6 figure 4. acknowledge timing 189 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver ack setup ( t su:dat ) ack delay ( t aa ) figure 5. bus timing scl sda in sda out t su:sta t hd:sta t hd:dat t f t low t aa t high t low t r t dh t buf t su:dat t su:sto write operations byte write to write data to memory, the master creates a start condition on the bus and then broadcasts a slave address with the r/w bit set to ?0?. the master then sends two address bytes and a data byte and concludes the session by creating a stop condition on the bus. the slave responds with ack after every byte sent by the master (figure 6). the stop starts the internal write cycle, and while this operation is in progress (t wr ), the sda output is tri-stated and the slave does not acknowledge the master (figure 7). page write the byte w rite operation can be expanded to page w rite, by sending more than one data byte to the slave before issuing the stop condition (figure 8) . up to 32 distinct data bytes can be loaded into the internal page write buffer starting at the address provided by the master. the page address is latched, and as long as the master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). new data can therefore replace data loaded earlier. following the stop, data loaded during the page write session will be written to memory in a single internal write cycle (t wr ). acknowledge polling as soon (and as long) as internal write is in progress, the slave will not acknowledge the master. this feature enables the master to immediately follow-up with a new read or write request, rather than wait for the maximum specified write time (t wr ) to elapse. upon receiving a noack response from the slave, the master simply repeats the request until the slave responds with ack. hardware write protection with the wp pin held high, the entire memory is protected against write operations. if the wp pin is left floating or is grounded, it has no impact on the write operation. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the 1 st data byte (figure 9). if the wp pin is high during the strobe interval, the slave will not acknowledge the data byte and the write request will be rejected. delivery state the nv24c64lv is shipped erased, i.e., all bytes are ffh.
nv24c64lv www. onsemi.com 7 slave address s a * * * c k a c k a c k s t o p p s t a r t a c k bus activity: master slave address byte address byte data byte figure 6. byte write sequence *a 15 ? a 13 are don?t care bits. a 15 ? a 8 a 7 ? a 0 d 7 ? d 0 * figure 7. write cycle timing stop condition start condition address ack 8th bit byte n scl sda t wr slave address s a c k a c k a c k s t a r t a c k s t o p a c k a c k p a c k bus activity: master slave address byte address byte data byte n data byte n+1 data byte n+p figure 8. page write sequence n = 1; p 31 figure 9. wp timing 189 1 8 address byte data byte scl sda wp t su:wp t hd:wp a 7 a 0 d 7 d 0
nv24c64lv www. onsemi.com 8 read operations immediate read to read data from memory, the master creates a start condition on the bus and then broadcasts a slave address with the r/w bit set to ?1?. the slave responds with ack and starts shifting out data residing at the current address. after receiving the data, the master responds with noack and terminates the session by creating a stop condition on the bus (figure 10). the slave then returns to standby mode. selective read to read data residing at a speci c address, the selected address must rst be loaded into the internal address register. this is done by starting a byte write sequence, whereby the master creates a start condition, then broadcasts a slave address with the r/w bit set to ?0? and then sends two address bytes to the slave. rather than completing the byte write sequence by sending data, the master then creates a start condition and broadcasts a slave address with the r/w bit set to ?1?. the slave responds with ack after every byte sent by the master and then sends out data residing at the selected address. after receiving the data, the master responds with noack and then terminates the session by creating a stop condition on the bus (figure 11). sequential read if, after receiving data sent by the slave, the master responds with ack, then the slave will continue transmitting until the master responds with noack followed by st op (figure 12). during sequential read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. figure 10. immediate read sequence and timing scl sda 8th bit stop no ack data out 89 slave address s a c k data byte n o a c k s t o p p s t a r t bus activity: master slave figure 11. selective read sequence slave address s a c k a c k a c k s t a r t slave s a c k s t a r t p s t o p address byte address byte address n o a c k data byte bus activity: master slave figure 12. sequential read sequence s t o p p slave address a c k a c k a c k n o a c k a c k data byte n data byte n+1 data byte n+2 data byte n+x bus activity: master slave
nv24c64lv www. onsemi.com 9 ordering information device order number density (kb) package type specific device marking temperature range shipping ? nv24c64uvlt2g 64 us ? 8 tbd v = automotive grade 1 ( ? 40 c to +125 c) tape & reel, 3,000 units / reel nv24c64muw3vltbg 64 udfn ? 8 wettable flank tbd v = automotive grade 1 ( ? 40 c to +125 c) tape & reel, 3,000 units / reel nv24c64dwvlt3g 64 soic ? 8 tbd v = automotive grade 1 ( ? 40 c to +125 c) tape & reel, 3,000 units / reel NV24C64DTVLT3G 64 tssop ? 8 tbd v = automotive grade 1 ( ? 40 c to +125 c) tape & reel, 3,000 units / reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. on semiconductor is licensed by the philips corporation to carry the i 2 c bus protocol.
mechanical case outline package dimensions us8 case 493 issue d date 15 jul 2015 scale 4 :1 dim a min max min max inches 1.90 2.10 0.075 0.083 millimeters b 2.20 2.40 0.087 0.094 c 0.60 0.90 0.024 0.035 d 0.17 0.25 0.007 0.010 f 0.20 0.35 0.008 0.014 g 0.50 bsc 0.020 bsc h 0.40 ref 0.016 ref j 0.10 0.18 0.004 0.007 k 0.00 0.10 0.000 0.004 l 3.00 3.20 0.118 0.128 m 0 6 0 6 n 0 10 0 10 p 0.23 0.34 0.010 0.013 r 0.23 0.33 0.009 0.013 s 0.37 0.47 0.015 0.019 u 0.60 0.80 0.024 0.031 v 0.12 bsc 0.005 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. 3. dimension a does not include mold flash, protrusion or gate burr. mold flash. protrusion and gate burr shall not exceed 0.14mm (0.0055?) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash and protrusion shall not exceed 0.14mm (0.0055?) per side. 5. lead finish is solder plating with thickness of 0.0076?0.0203mm (0.003?0.008?). 6. all tolerance unless otherwise specified 0.0508mm (0.0002?). l b a p g 4 1 5 8 c k d seating j s r u detail e v f h n r 0.10 typ m detail e t m 0.10 (0.004) xy t 0.10 (0.004) plane xx = specific device code m = date code = pb?free package 1 8 xx m generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. (note: microdot may be in either location) x y t 0.30 8x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* 0.50 recommended 1 pitch 3.40 0.68 8x http://onsemi.com 1 ? semiconductor components industries, llc, 2002 october, 2002 ? rev. 0 case outline number: xxx document number: status: new standard: description: 98aon04475d on semiconductor standard us8 electronic versions are uncontrolled except when accessed directly from the document repository. printed versions are uncontrolled except when stamped ?controlled copy? in red. page 1 of 2
document number: 98aon04475d page 2 of 2 issue revision date o released for production. req by r. forness 19 mar 2001 a changed dim ?p? to 0.23 mm min, 0.34 mm max and 0.010 in min, 0.013 in max. req by j. miller 25 jun 2003 b added soldering footprint. req. by d. truhitte. 13 apr 2006 c modified soldering footprint. req. by b. becker. 23 mar 2015 d modified dimension a min value and dimension c max value for mm. req. by r. avila. 15 jul 2015 ? semiconductor components industries, llc, 2015 july, 2015 ? rev. d case outline number : 49 3 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
udfn8 2x3, 0.5p case 517dh issue o date 06 nov 201 5 scale 2:1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.25mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. 5. for device opn containing w option, detail b alternate construction is not applicable. ?? ?? ?? a d e b c 0.05 pin one indicator top view side view bottom view l d2 e2 c c 0.10 c 0.08 a1 seating plane note 3 b 8x 0.10 c 0.05 c a b dim min max millimeters a 0.45 0.55 a1 0.00 0.05 b 0.20 0.30 d 2.00 bsc d2 1.30 1.50 e 3.00 bsc e2 1.30 1.50 e 0.50 bsc l 0.30 0.50 1 4 8 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 1.55 3.40 1 dimensions: millimeters 1 note 4 0.30 8x detail a a3 0.13 ref a3 a detail b l1 detail a l alternate constructions l l1 ??? 0.15 e recommended 5 1.56 generic marking diagram* xxxxx = specific device code a = assembly location wl = wafer lot y = year w = work week = pb?free package *this information is generic. please refer to device data sheet for actual part marking. pb?free indicator , ?g? or microdot ? ?, may or may not be present. xxxxx awlyw 1 m m 0.68 c 0.05 8x ?? detail b mold cmpd exposed cu alternate constructions ??? mechanical case outline package dimensions http://onsemi.com 1 ? semiconductor components industries, llc, 2002 october, 2002 ? rev. 0 case outline number: xxx document number: status: reference: description: 98aon06579g on semiconductor standard udfn8 2x3, 0.5p electronic versions are uncontrolled except when accessed directly from the document repository. printed versions are uncontrolled except when stamped ?controlled copy? in red. page 1 of 2
document number: 98aon06579g page 2 of 2 issue revision date o released for production. req. by i. hyland. 06 nov 2015 ? semiconductor components industries, llc, 2015 november, 2015 ? rev. o case outline number : 517dh on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
soic 8, 150 mils case 751bd ? 01 issue o date 19 dec 2008 e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35 mechanical case outline package dimensions http://onsemi.com 1 ? semiconductor components industries, llc, 2002 october, 2002 ? rev. 0 case outline number: xxx document number: status: reference: description: 98aon34272e on semiconductor standard soic 8, 150 mils electronic versions are uncontrolled except when accessed directly from the document repository. printed versions are uncontrolled except when stamped ?controlled copy? in red. page 1 of 2
document number: 98aon34272e page 2 of 2 issue revision date o released for production from pod #soic8 ? 002 ? 01 to on semiconductor. req. by b. bergman. 19 dec 2008 ? semiconductor components industries, llc, 2008 december, 2008 ? rev. 01o case outline number: 751bd on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
tssop8, 4.4x3 case 948al ? 01 issue o date 19 dec 2008 e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40 mechanical case outline package dimensions http://onsemi.com 1 ? semiconductor components industries, llc, 2002 october, 2002 ? rev. 0 case outline number: xxx document number: status: reference: description: 98aon34428e on semiconductor standard tssop8, 4.4x3 electronic versions are uncontrolled except when accessed directly from the document repository. printed versions are uncontrolled except when stamped ?controlled copy? in red. page 1 of 2
document number: 98aon34428e page 2 of 2 issue revision date o released for production from pod #tssop8 ? 004 ? 01 to on semiconductor. req. by b. bergman. 19 dec 2008 ? semiconductor components industries, llc, 2008 december, 2008 ? rev. 01o case outline number: 948al on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
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