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? semiconductor components industries, llc, 2015 october, 2015 ? rev. 0 1 publication order number: ncn5121/d ncn5121 transceiver for knx twisted pair networks introduction ncn5121 is a receiver?transmitter ic suitable for use in knx twisted pair networks (knx tp1?256). it supports the connection of actuators, sensors, microcontrollers, switches or other applications in a building network. ncn5121 handles the transmission and reception of data on the bus. it generates from the unregulated bus voltage stabilized voltages for its own power needs as well as to power external devices, for example, a microcontroller. ncn5121 assures safe coupling to and decoupling from the bus. bus monitoring warns the external microcontroller in case of loss of power so that critical data can be stored in time. key features ? 9600 baud knx communication speed ? supervision of knx bus voltage and current ? supports bus current consumption up to 24 ma ? high efficient dc?dc converters ? 3.3 v fixed ? 1.2 v to 21 v selectable ? control and monitoring of power regulators ? linear 20 v regulator ? buffering of sent data frames (extended frames supported) ? selectable uart or spi interface to host controller ? selectable uart and spi baud rate to host controller ? optional crc on uart to the host ? optional received frame?end with marker service ? optional direct analog signaling to host ? operates with industry standard low cost 16 mhz quartz ? generates clock of 8 or 16 mhz for external devices ? auto acknowledge (optional) ? auto polling (optional) ? temperature monitoring ? extended operating temperature range ?40 c to +105 c ? these devices are pb?free and are rohs compliant www. onsemi.com qfn40 mn suffix case 485au see detailed ordering and shipping information in the package dimensions section on page 56 of this data sheet. ordering information a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package marking diagram 40 1 ncn5121 21420?002 awlyywwg
ncn5121 www. onsemi.com 2 block diagram figure 1. block diagram ncn5121 por tw tsd uvd dc/dc converter 1 dc/dc converter 2 ncn5121 cav vbus1 ccp txo fanin vbus2 v20v xtal1 xtal2 xsel xclk saveb resetb anaout vss2 vdd2 vdd2mv vdd2mc vsw2 vss1 vdd1 vdd1m vsw1 vin mode2 mode1 treq csb/uc1 sdo/txd sdi/rxd sck/uc2 vssd vddd vdda vssa vfilt ceq2 ceq1 20v ldo fan?in control bus coupler impedance control transmitter osc receiver uart spi knx dll interface controller mode rc osc diagnostics xclkc trig analog buffer pin out vssa vbus2 txo ccp cav vbus1 ceq1 ceq2 vfilt vdd2mv vdd2mc vdd2 vss2 vsw2 vsw1 vss1 vdd1 vdd1m xclkc trig mode1 mode2 treq csb/uc1 sdi/rxd sdo/txd sck/uc2 vddd vssd xclk xsel xtal2 xtal1 saveb resetb fanin anaout vdda 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 ncn5121 v20v figure 2. pin out ncn5121 (top view) vin
ncn5121 www. onsemi.com 3 pin description table 1. pin list and description name pin description type equivalent schematic vssa 1 analog supply voltage ground supply vbus2 2 ground for knx transmitter supply tx0 3 knx transmitter output analog output type 1 ccp 4 ac coupling external capacitor connection analog i/o type 2 cav 5 capacitor connection to average bus dc voltage analog i/o type 3 vbus1 6 knx power supply input supply type 5 ceq1 7 capacitor connection 1 for defining equalization pulse analog i/o type 4 ceq2 8 capacitor connection 2 for defining equalization pulse analog i/o type 4 vfilt 9 filtered bus voltage supply type 5 v20v 10 20v supply output supply type 5 vdd2mv 11 voltage monitor of voltage regulator 2 analog input type 8 vdd2mc 12 current monitor input 1 of voltage regulator 2 analog input type 9 vdd2 13 current monitor input 2 of voltage regulator 2 analog input type 8 vss2 14 voltage regulator 2 ground supply vsw2 15 switch output of voltage regulator 2 analog output type 6 vin 16 voltage regulator 1 and 2 power supply input supply type 5 vsw1 17 switch output of voltage regulator 1 analog output type 6 vss1 18 voltage regulator 1 ground supply vdd1 19 current input 2 and voltage monitor input of voltage regulator 1 analog input type 8 vdd1m 20 current monitor input 1 of voltage monitor 1 analog input type 9 xclkc 21 clock frequency configure digital input type 12 trig 22 transmission trigger output digital output type 13 mode1 23 mode selection input 1 digital input type 12 mode2 24 mode selection input 2 digital input type 12 treq 25 transmit request input digital input type 12 csb/uc1 26 chip select output (spi) or configuration input (uart) or 20 v ldo disable (analog mode) digital output or digital input type 13 or 14 sdi/rxd 27 serial data input (spi) or receive input (uart) digital input type 14 sdo/txd 28 serial data output (spi) or transmit output (uart) digital output type 13 sck/uc2 29 serial clock output (spi) or configuration input (uart) or voltage regulator 2 disable (analog mode) digital output or digital input type 13 or 14 vddd 30 digital supply voltage input supply type 7 vssd 31 digital supply voltage ground supply xclk 32 oscillator clock output digital output type 13 xsel 33 clock selection (quartz or digital clock) digital input type 12 xtal2 34 clock generator output (quartz) or input (digital clock) analog output or digital input type 10 or 14 xtal1 35 clock generator input (quartz) analog input type 10 saveb 36 save signal (open drain with pull?up) digital output type 15 resetb 37 reset signal (open drain with pull?up) digital output type 15 fanin 38 fan?in input digital input type 11 anaout 39 analog signal output analog output type 16 vdda 40 analog supply voltage input supply type 7 note: type of csb/uc1 and sck/uc2 is depending on status mode1 ? mode2 pin type of xtal1 and xtal2 pin is depending on status xsel pin.
ncn5121 www. onsemi.com 4 equivalent schematics following figure gives the equivalent schematics of the user relevant inputs and outputs. the diagrams are simplified representations of the circuits used. txo 60v ccp 60v 60v cav 7v ceqx 60v type 1: txo?pin type 2: ccp?pin t ype 3: ca v?pin type 4: ceq1 and ceq2?pin vbus1 60v vbus1 vfilt 60v vfilt v20v 60v v20v vin 60v vin vswx vin 60v type 5: vbus1?, vfilt?, v20v and vin?pin type 6: vsw1 and vsw2?pin vdda vdda 7v vddd vddd 7v vdd2mv 7v vdd2 60v vdd1 7v type 7: vddd? and vdda?pin type 8: vdd1?, vdd2? and vdd2mv?pin vdd1m vdd1 7v 7v vdd2mc vdd2 7v 60v xtal2 vddd xtal1 vddd type 9: vdd1m? and vdd2mc?pin type 10: xtal1? and xtal2?pin in vddd r down out vddd in vddd out vddd r up type 12: mode1?, mode2?, treq?, xclkc? and xsel?pin type 13: csb/uc1?, sdo/txd?, sck/uc2?, trig? and xclk?pin type 14: csb/uc1?, sdi/rxd?, sck/uc2 and xtal2?pin type 15: resetb? and saveb?pin type 11: fanin?pin anaout vdda type 16: anaout fanin vaux 7v note: type of csb/uc1 and sck/uc2 is depending on status mode1 ? mode2 pin type of xtal1 and xtal2 pin is depending on status xsel pin. figure 3. in? and output equivalent diagrams
ncn5121 www. onsemi.com 5 electrical specification table 2. absolute maximum ratings (notes 1 and 2) symbol parameter min max unit v txo knx transmitter output voltage ?0.3 +45 v i txo knx transmitter output current (note 3) 250 ma v ccp voltage on ccp?pin ?10.5 +14.5 v v cav voltage on cav?pin ?0.3 +3.6 v v bus1 voltage on vbus1?pin ?0.3 +45 v v anaout voltage on anaout pin ?0.3 +3.6 v i bus1 current consumption vbus1?pin 0 120 ma v ceq voltage on pins ceq1 and ceq2 ?0.3 +45 v v filt voltage on vfilt?pin ?0.3 +45 v v 20v voltage on v20v?pin ?0.3 +25 v v dd2mv voltage on vdd2mv?pin ?0.3 +3.6 v v dd2mc voltage on vdd2mc?pin ?0.3 +45 v v dd2 voltage on vdd2?pin ?0.3 +45 v v sw voltage on vsw1? and vsw2?pin ?0.3 +45 v v in voltage on vin?pin ?0.3 +45 v v dd1 voltage on vdd1?pin ?0.3 +3.6 v v dd1m voltage on vdd1m?pin ?0.3 +3.6 v v dig voltage on pins mode1, mode2, treq, csb/uc1, sdi/txd, sdo/rxd, sck/ uc2, xclk, xsel, saveb, resetb, xclkc, trig, and fanin ?0.3 +3.6 v v dd voltage on vddd? and vdda?pin ?0.3 +3.6 v v xtal voltage on xtal1? and xtal2?pin ?0.3 +3.6 v t st storage temperature ?55 +150 c t j junction temperature (note 4) ?40 +155 c v hbm human body model electronic discharge immunity (note 5) ?2 +2 kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. convention: currents flowing in the circuit are defined as positive. 2. vbus2, vss1, vss2, vssa and vssd form the common ground. they are hard connected to the pcb ground layer. 3. room temperature, 27 shunt resistor for transmitter, 250 ma over temperature range. 4. normal performance within the limitations is guaranteed up to the thermal warning level. between thermal warning and thermal shutdown temporary loss of function or degradation of performance (which ceases after the disturbance ceases) is possible. 5. according to jedec jesd22?a114.
ncn5121 www. onsemi.com 6 recommend operation conditions operating ranges define the limits for functional operation and parametric characteristics of the device. note that the functionality of the chip outside these operating ranges is not guaranteed. operating outside the recommended operating ranges for extended periods of time may affect device reliability. table 3. operating ranges symbol parameter min max unit v bus1 vbus1 voltage (note 6) +20 +33 v v dd digital and analog supply voltage (vddd? and vdda?pin) +3.13 +3.47 v v in input voltage dc?dc converter 1 and 2 (note 7) +33 v v ccp input voltage at ccp?pin ?10.5 +14.5 v v cav input voltage at cav?pin 0 +3.3 v v dd1 input voltage on vdd1?pin +3.13 +3.47 v v dd1m input voltage on vdd1m?pin +3.13 +3.57 v v dd2 input voltage on vdd2?pin +1.2 +21 v v dd2mc input voltage on vdd2mc?pin +1.2 +21.1 v v dd2mv input voltage on vdd2mv?pin +1.2 vdd v v dig input voltage on pins mode1, mode2, treq, csb/uc1, sdi/rxd, sck/uc2, xclkc, and xsel 0 vdd v v fanin input voltage on fanin?pin 0 3.6 v f clk clock frequency external quartz 16 mhz t a ambient temperature ?40 +105 c t j junction temperature (note 8) ?40 +125 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 6. voltage indicates dc value. with equalization pulse bus voltage must be between 11 v and 45 v. 7. minimum operating voltage on vin?pin should be at least 1 v larger than the highest value of vdd1 and vdd2. 8. higher junction temperature can result in reduced lifetime.
ncn5121 www. onsemi.com 7 table 4. dc parameters the dc parameters are given for a device operating within the recommended operating conditions unless otherwise specified. convention: currents flowing in the circuit are defined as positive. symbol pin(s) parameter remark/test conditions min typ max unit power supply v bus1 vbus1 bus dc voltage excluding active and equalization pulse 20 33 v i bus1_int bus current consumption vbus = 30 v, ibus = 10 ma, dc2, v20v disabled, no crystal or clock 2.00 2.70 ma bus current consumption vbus = 20 v, ibus = 20 ma 3.20 4.10 v bush undervoltage release level v bus1 rising, see figure 4 17.1 18.0 18.9 v v busl undervoltage trigger level v bus1 falling, see figure 4 15.9 16.8 17.7 v v bus_hyst undervoltage hysteresis 0.6 v v ddd vddd digital power supply 3.13 3.3 3.47 v v dda vdda analog power supply 3.13 3.3 3.47 v v aux auxiliary supply internal supply, for info only 2.8 3.3 3.6 v knx bus coupler i coupler / t vbus1 bus coupler current slope limitation fanin floating, v filt > v filth 0.40 0.50 a/s fanin = 0, v filt > v filth 0.80 1.00 a/s i coupler_lim, startup vbus1 bus coupler startup current limitation fanin floating, v filt > v filth 20.0 25.0 30.0 ma fanin = 0, v filt > v filth 40.0 50.0 60.0 ma i coupler_lim vbus1 bus coupler current limitation fanin floating, v filt > v filth 10.6 11.4 12.0 ma fanin = 0, v filt > v filth 20.5 22.3 24.0 ma v coupler_drop vbus1, vfilt coupler voltage drop (v coupler_drop = v bus1 ? v filt ) i bus1 = 10 ma 1.72 2.25 v i bus1 = 20 ma 2.34 2.80 v v filth vfilt undervoltage release level v filt rising, see figure 5 10.1 10.6 11.2 v v filtl undervoltage trigger level v filt falling, see figure 5 8.4 8.9 9.4 v fixed dc?dc converter v in vin input voltage 4.47 33 v v dd1 vdd1 output voltage 3.13 3.3 3.47 v v dd1_rip output voltage ripple v in = 25 v, i dd1 = 40 ma, l1 = 220 h 40 mv i dd1_lim overcurrent threshold r 2 = 1 , see figure 13 ?100 ?200 ma vdd1 power efficiency (dc converter only) v in = 25 v, i dd1 = 35 ma, l 1 = 220 h (1.26 esr), see figure 12 90 % r ds(on)_p1 r ds(on) of power switch see figure 18 9 r ds(on)_n1 r ds(on) of flyback switch see figure 18 4 v dd1m vdd1m input voltage vdd1m?pin 3.57 v
ncn5121 www. onsemi.com 8 table 4. dc parameters the dc parameters are given for a device operating within the recommended operating conditions unless otherwise specified. convention: currents flowing in the circuit are defined as positive. symbol unit max typ min remark/test conditions parameter pin(s) adjustable dc?dc converter v in vin input voltage v dd2 + 1 33 v v dd2 vdd2 output voltage v in v dd2 1.2 21 v v dd2h undervoltage release level v dd2 rising, see figure 6 0.9 x v dd2 v v dd2l undervoltage trigger level v dd2 falling, see figure 6 0.8 x v dd2 v v dd2_rip output voltage ripple v in = 25 v, v dd2 = 3.3 v, i dd2 = 40 ma, l2 = 220 h 40 mv i dd2_lim overcurrent threshold r 3 = 1 , see figure 13 ?100 ?200 ma vdd2 power efficiency (dc converter only) v in = 25 v, v dd2 = 3.3 v, i dd2 = 35 ma, l 2 = 220 h (1.26 esr), see figure 13 90 % r ds(on)_p2 r ds(on) of power switch see figure 18 8 r ds(on)_n2 r ds(on) of flyback switch see figure 18 4 v dd2m vdd2mc input voltage vdd2mc?pin 21.1 v r vdd2m vdd2mv input resistance vdd2mv?pin 1 m i leak,vsw2 half?bridge leakage 20 a v20v regulator v 20v v20v v20v output voltage i 20v < i 20v_lim , v filt 21 v 18 20 22 v i 20v, step v20v output current limitation step fanin floating 1.25 ma fanin = 0 2.50 ma i 20v_lim v20v output current limitation (for current limit code 100) fanin floating 6 7.5 9 ma fanin = 0 12 15 18 ma v 20vh v20v undervoltage release level v 20v rising, see figure 7 14.2 15.0 15.8 v v 20vl v20v undervoltage trigger level v 20v falling, see figure 7 13.2 14.0 14.8 v v 20v_hyst v20v undervoltage hysteresis v 20v_hyst = v 20vh ? v 20vl 1.0 v xtal oscillator v xtal xtal1, xtal2 voltage on xtal?pin v ddd v fan?in control i pu,fanin fanin pull?up current fanin?pin fanin shorted to gnd, pull?up connected to v aux 10 20 40 a
ncn5121 www. onsemi.com 9 table 4. dc parameters the dc parameters are given for a device operating within the recommended operating conditions unless otherwise specified. convention: currents flowing in the circuit are defined as positive. symbol unit max typ min remark/test conditions parameter pin(s) digital inputs v il sck/uc2, sdi/rxd, csb/uc1, treq, mode1, mode2, xsel, xclkc , xtal2 logic low threshold 0 0.7 v v ih logic high threshold 2.65 v ddd v r down internal pull?down resistor sck/uc2?, sdi/rxd? and csb/uc1 pin excluded. only valid in normal state. 5 10 28 k digital outputs v ol sck/uc2, sdo/txd, csb/uc1, xclk, trig logic low output level 0 0.4 v v oh logic high output level v ddd ? 0.45 v ddd v i l sck/uc2, xclk, trig load current 8 ma sdo/txd, csb/uc1 4 ma v ol saveb, resetb logic low level open drain i ol = 4 ma 0.4 v r up internal pull?up resistor 20 40 80 k analog output pv bus anaout analog output division ratio for v bus 0.067 0.071 0.075 pv filt analog output division ratio for v filt 0.071 0.075 0.079 pv 20v analog output division ratio for v 20v 0.086 0.091 0.096 pv dda analog output division ratio for v dda 0.438 0.462 0.485 pv dd2 analog output division ratio for v dd2mv 0.950 1.000 1.050 pi bus analog output conversion ratio for i bus 14.0 20.9 28.8 v/a pt j analog output conversion ratio for t junction ?4 mv/k vtj off analog output offset for t junction at 300k 1.309 v v off analog output offset voltage ?12 12 mv t sw,ana time between writing analog control register 1 and stable anaout voltage (<1 nf capacitive load) 33 s temperature monitor t tw thermal warning rising temperature see figure 8 105 115 125 c t tsd thermal shutdown rising temperature see figure 8 130 140 150 c t hyst thermal hysteresis see figure 8 5 11 15 c t delta t tsd and t tw see figure 8 21.7 c package thermal resistance value r , ja thermal resistance junction?to?ambient simulated conform jedec jesd?51, (2s2p) 30 k/w simulated conform jedec jesd?51, (1s0p) 60 k/w r , jp thermal resistance junction?to?exposed pad 0.95 k/w
ncn5121 www. onsemi.com 10 table 5. ac parameters the ac parameters are given for a device operating within the recommended operating conditions unless otherwise specified. symbol pin(s) parameter remark/test conditions min typ max unit power supply t bus_filter vbus1 vbus1 filter time see figure 4 2 ms fixed dc?dc converter t vsw1_rise vsw1 rising slope at vsw1?pin 0.45 v/ns t vsw1_fall falling slope at vsw1?pin 0.6 v/ns adjustable dc?dc converter t vsw2_rise vsw2 rising slope at vsw2?pin 0.45 v/ns t vsw2_fall falling slope at vsw2?pin 0.6 v/ns xtal oscillator f xtal xtal1, xtal2 xtal oscillator frequency 16 mhz watchdog t wdpr prohibited watchdog acknowledge delay see watchdog, p22 2 33 ms t wdto watchdog timeout interval selectable over uart or spi 33 524 ms t wdto_acc watchdog timeout interval accuracy =xtal accuracy t wdrd watchdog reset delay 0 ns t reset reset duration 8 s master serial peripheral interface (master spi) t sck sck spi clock period spi baudrate depending on configuration input bits (see interface mode, p26). toleranc e is equal to xtal oscillator tolerance. see also figure 10 2 s 8 s t sck_high spi clock high time t sck / 2 t sck_low spi clock low time t sck / 2 t sdi_set sdi spi data input setup time 125 ns t sdi_hold spi data input hold time 125 ns t sdo_valid sdo spi data output valid time c l = 20 pf, see figure 10 100 ns t cs_high csb spi chip select high time see figure 10 0.5 x t sck t cs_set spi chip select setup time 0.5 x t sck t cs_hold spi chip select hold time 0.5 x t sck t treq_low treq treq low time see figure 11 125 ns t treq_high treq high time 125 ns t treq_set treq setup time 125 ns t treq_hold treq hold time 125 ns universal asynchronous receiver/transmitter (uart) f uart txd, rxd uart interface baudrate baudrate depending on configuration input pins (see interface mode , p26). tolerance is equal to tolerance of xtal oscillator tolerance. 19200 baud 38400 baud product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncn5121 www. onsemi.com 11 v bus t v bush v busl t bus_filter comments: is an internal signal which can be verified with the internal state service. t bus_filter figure 4. bus voltage undervoltage threshold t v filt v filtl v filth comments: is an internal signal which can be verified with the system state service figure 5. vfilt undervoltage threshold t v dd2 v dd2l v dd2h comments: is an internal signal which can be verified with the system state service figure 6. vdd2 undervoltage thresholds
ncn5121 www. onsemi.com 12 t v 20v v 20vl v 20vh comments: is an internal signal which can be verified with the system state service. v 20v_hyst figure 7. v20v undervoltage threshold levels figure 8. temperature monitoring levels saveb resetb comments: - is an internal signal which can be verified with the system state service. - no spi/uart communication possible when resetb is low! - it's assumed all voltage supplies are within their operating condition. t t t tw t tsd t hyst t hyst t normal stand-by reset start-up normal stand-by analog state
ncn5121 www. onsemi.com 13 wd timer resetb remarks: ? wd timer is an internal timer ?t wdto = ? and are watchdog register bits enable watchdog re?enable watchdog t wdpr t wdto >t wdpr and < t wdto t wdpr and t wdto t wdrd t t t t reset figure 9. watchdog timing diagram do figure 10. spi bus timing diagram do clk di cs treq t treq _set lsb 1 7 2 dummy dummy dummy dummy t treq _low t treq_high t treq_hold figure 11. treq timing diagram
ncn5121 www. onsemi.com 14 typical application schematics figure 12. typical application schematic, 8?bit uart mode (38400bps), single supply, 20 ma bus current limit and 1 ma/ms bus current slopes, 8 mhz microcontroller clock signal ncn5121 vssa 1 vbus2 2 txo 3 ccp 4 cav 5 vbus1 6 ceq1 7 ceq2 8 vfilt 9 vdd2mv 11 vdd2mc 12 vdd2 13 vss2 14 vsw2 15 vin 16 vsw1 17 vss1 18 vdd1 19 vdd1m 20 xclkc 21 trig 22 mode1 23 treq 25 mode2 24 csb/uc1 26 sdi/rxd 27 sdo/txd 28 v20v 10 sck/uc2 29 vddd 30 vssd 31 xclk 32 xsel 33 xtal2 34 xtal1 35 saveb 36 resetb 37 fanin 38 anaout 39 vdda 40 3.3 c 5 d 1 r 1 c 1 c 3 c 4 c 7 c 2 l 1 c 10 3.3 3.3 c 9 c 8 a b gnd vcc 3.3 txd rxd saveb resetb r 2 x 1 uc clk 3.3 c 6 d 2
ncn5121 www. onsemi.com 15 typical application schematics figure 13. typical application schematic, spi (500 kbps), dual supply, 10 ma bus current limit and 0.5 ma/ms bus current slopes, 16 mhz clock for microcontroller ncn5121 vssa 1 vbus2 2 txo 3 ccp 4 cav 5 vbus1 6 ceq1 7 ceq2 8 vfilt vdd2mv 11 vdd2mc 12 vdd2 13 vss2 14 vsw2 15 vin 16 vsw1 17 vss1 18 vdd1 19 vdd1m 20 9 xclkc 21 trig 22 mode1 23 treq 25 mode2 24 csb/uc1 26 sdi/rxd 27 sdo/txd 28 v20v 10 sck/uc2 29 vddd vssd 31 xclk 32 xsel 33 xtal2 34 xtal1 35 saveb 36 resetb 37 fanin 38 anaout 39 vdda 40 30 3.3 3.3 3.3 gnd vcc 3.3 sdo sdi saveb resetb v2 v2 vcc2 sck scb uc clk treq a b d 2 d 1 r 1 c 1 c 2 c 7 c 3 c 4 c 5 x 1 c 8 c 9 c 6 c 10 c 11 r 3 r 5 r 4 r 2 l 2 l 1
ncn5121 www. onsemi.com 16 typical application schematics figure 14. typical application schematic, analog mode, single supply, 20 ma bus current limit and 1.0 ma/ms bus current slopes, 8 mhz clock signal for microcontroller ncn5121 vssa 1 vbus2 2 txo 3 ccp 4 cav 5 vbus1 6 ceq1 7 ceq2 8 vfilt 9 vdd2mv 11 vdd2mc 12 vdd2 13 vss2 14 vsw2 15 vin 16 vsw1 17 vss1 18 vdd1 19 vdd1m 20 xclkc 21 trig 22 mode1 23 treq 25 mode2 24 csb/uc1 26 sdi/rxd 27 sdo/txd 28 v20v 10 sck/uc2 29 vddd 30 vssd 31 xclk 32 xsel 33 xtal2 34 xtal1 35 saveb 36 resetb 37 fanin 38 anaout 39 vdda 40 3.3 c 5 r 1 c 1 c 3 c 4 c 7 c 2 l 1 c 10 3.3 3.3 c 6 gnd vcc 3.3 txd rxd saveb resetb r 2 3.3 d 1 d 2 a b
ncn5121 www. onsemi.com 17 table 6. external components list and description comp. function min typ max unit remarks notes c 1 ac coupling capacitor 42.3 47 51.7 nf 50 v, ceramic 9 c 2 equalization capacitor 198 220 242 nf 50 v, ceramic 9 c 3 capacitor to average bus dc voltage 80 100 120 nf 50 v, ceramic 9 c 4 storage and filter capacitor vfilt 80 100 4000 f 35 v 9, 16 c 5 vdda hf rejection capacitor 80 100 nf 6.3 v, ceramic c 6 vddd hf rejection capacitor 80 100 nf 6.3 v, ceramic c 7 load capacitor v20v 1 f 35 v, ceramic, esr < 2 14, 15, 16 c 8 , c 9 parallel capacitor x?tal 8 10 12 pf 6.3 v, ceramic 10 c 10 load capacitor vdd1 8 10 f 6.3 v, ceramic, esr < 0.1 c 11 load capacitor vdd2 8 10 f ceramic, esr < 0.1 11 r 1 shunt resistor for transmitting 24.3 27 29.7 1 w 9 r 2 dc1 sensing resistor 0.47 1 10 1/16 w r 3 dc2 sensing resistor 0.47 1 10 1/16 w r 4 voltage divider to specify vdd2 0 1/16 w, see p19 for calculating the exact value r 5 0 1 m l 1 , l 2 dc1/dc2 inductor 220 h d 1 reverse polarity protection diode ss16 12 d 2 voltage suppressor 1sma40ca x 1 crystal oscillator fa-238 13 9. component must be between minimum and maximum value to fulfill the knx requirement. 10. actual capacitor value depends on x1. if a crystal oscillator is chosen, the capacitors need to be chosen in such a way that the frequency equals 16 mhz. capacitors are not required if external clock signal is supplied. 11. voltage of capacitor depends on vdd2 value defined by r4 and r5. see p16 for more details on defining vdd2 voltage value. 12. reverse polarity diode is mandatory to fulfill the knx requirement. 13. a clock signal of 16 mhz (50 ppm or less) is mandatory to fulfill the knx requirements. or a crystal oscillator of 16 mhz, 5 0 ppm is used (c8 and c9 need to be of the correct value based on the crystal datasheet), or an external 16 mhz clock is used. 14. it?s allowed to short this pin to vfilt-pin 15. high capacitor value might affect the start up time 16. total charge of c4 and c7 may not be higher than 121 mc to fulfill the knx requirement.
ncn5121 www. onsemi.com 18 analog functional description because ncn5121 follows the knx standard only a brief description of the knx related blocks is given in this datasheet. detailed information on the knx bus can be found on the knx website ( www.knx.org ) and in the knx standards. knx bus interfacing each bit period is 104 s. logic 1 is simply the dc level of the bus voltage which is between 20 v and 33 v. logic 0 is encoded as a drop in the bus voltage with respect to the dc level. logic 0 is known as the active pulse. the active pulse is produced by the transmitter and is ideally rectangular. it has a duration of 35 s and a depth between 6 and 9 v (v act ). each active pulse is followed by an equalization pulse with a duration of 69 s. the latter is an abrupt jump of the bus voltage above the dc level followed by an exponential decay down to the dc level. the equalization pulse is characterized by its height v eq and the voltage v end reached at the end of the equalization pulse. see the knx twisted pair standard (knx tp1?256) for more detailed knx information. dc level v bus t 104 s 35 s69 s active pulse equalization pulse 104 s 0 1 v eq v act v end figure 15. knx bus voltage versus digital value knx bus transmitter the purpose of the transmitter is to produce an active pulse (see figure 15) between 6 v and 10.5 v regardless of the bus impedance (note 1). in order to do this the transmitter will sink as much current as necessary until the bus voltage drops by the desired amount. knx bus receiver the receiver detects the beginning and the end of the active pulse. the detection threshold for the start of the active pulse is ?0.45 v (typ.) below the average bus voltage. the detection threshold for the end of the active pulse is ?0.2 v (typ.) below the average bus voltage giving a hysteresis of 0.25 v (typ.). bus coupler the role of the bus coupler is to extract the dc voltage from the bus and provide a stable voltage supply for the purpose of powering the ncn5121. this stable voltage supplied by the bus coupler will follow the average bus voltage. the bus coupler also makes sure that the current drawn from the bus changes very slowly. for this a large filter capacitor is used on the vfilt?pin. abrupt load current steps are absorbed by the filter capacitor. long?term stability requires that the average bus coupler input current is equal to the average (bus coupler) load current. this is shown by the parameter i coupler / t, which indicates the bus current slope limit. the bus coupler will also limit the current to a maximum of i coupler_lim . at startup, this current limit is increased to i coupler_lim,startup to allow for fast charging of the vfilt bulk capacitance. there are 4 conditions that determine the dimensioning of the vfilt capacitor. first, the capacitor value should be between 12.5 f and 4000 f to garantuee proper operation of the part. the next requirement on the vfilt capacitor is determined by the startup time of the system. according to the knx specification, the total startup time must be below 10 s. this time is comprised of the time to charge the vfilt capacitor to 12 v (where the dcdc convertor becomes operatonal) and the startup time of the rest of the system t startup ,system. this gives the following formula: c 10 s t startup,system i coupler_ilim,startup v filth 1. maximum bus impedance is specified in the knx twisted pair standard
ncn5121 www. onsemi.com 19 the third limit on vfilt capacitor value is the required capacitor value to filter out current steps i step of the system without going into reset. c i step 2 2
(v bus1 v coupler_drop v filtl )
i slope the last condition on the size of vfilt is the desired warning time t warning between saveb and resetb in case the bus voltage drops away. this is determined by the current consumption of the system i system . c i system t warning t busfilter v bus1 v coupler_drop v filtl the bus coupler is implemented as a linear voltage regulator. for ef ficiency purpose, the voltage drop over the bus coupler is kept minimal (see table 4). knx impedance control the impedance control circuit defines the impedance of the bus device during the active and equalization pulses. the impedance can be divided into a static and a dynamic component, the latter being a function of time. the static impedance defines the load for the active pulse current and the equalization pulse current. the dynamic impedance is produced by a block, called an equalization pulse generator, that reduces the device current consumption (i.e. increases the device impedance) as a function of time during the equalization phase so as to return energy to the bus. fixed and adjustable dc?dc converter the device contains two dc?dc buck converters, both supplied from vfilt. dc1 provides a fixed voltage of 3.3 v. this voltage is used as an internal low voltage supply (v dda and v ddd ) but can also be used to power external devices (vdd1?pin). dc1 is automatically enabled during the power?up procedure (see analog state diagram, p23). dc2 provides a programmable voltage by means of an external resistor divider. it is not used as an internal voltage supply making it not mandatory to use this dc?dc converter (if not needed, tie the vdd2mv pin to vdd1, see also figure 12). dc2 can be monitored (, see system status service, p37), and/or disabled by a command from the host controller (, see analog control register 0, p53). dc2 will only be enabled when vfilt?bit is set (, see system status service, p37). the status of dc2 can be monitored (, see system status service, p37). the voltage divider can be calculated as follows: (eq. 1) r 4 r 5 v vdd2 1.2 1.2 both dc?dc converters make use of slope control to improve emc performance (see table 5). to operate dc1 and dc2 correctly, the voltage on the vin?pin should be higher than the highest value of dc1 and dc2. although both dc?dc converters are capable of delivering 100 ma, the maximum current capability will not always be usable. one always needs to make sure that the knx bus power consumption stays within the knx specification. the maximum allowed current for the dc?dc converters and v20v regulator can be estimated as next: v bus i bus i 20v 2 v dd1 i dd1 v dd2 i dd2 1 (eq. 2) i bus will be limited by the knx standard and should be lower or equal to i coupler (see table 4). minimum v bus is 20 v (see knx standard). v dd1 and v dd2 can be found back in table 4. i dd1 , i dd2 and i 20v must be chosen in a correct way to be in line with the knx specification (note 2). although dc2 can operate up to 21 v, it will not be possible to generate this 21 v under all operating conditions. see application note and9135 for defining the optimum inductor and capacitor of the dc?dc converters. when using low series resistance output capacitors on dc2, it is advised to split the the current sense resistor as shown in figure 12 to reduce ripple current for low load conditions. v20v regulator this is the 20 v low drop linear voltage regulator used to supply external devices. as it draws current from vfilt, this current is seen without any power conversion directly at the vbus1 pin. the v20v regulator starts up by default but can be disabled by a command from the host controller (, see analog control register 0, p53). when the v20v regulator is not used, no load capacitor needs to be connected (see c7 of figures 12, 13 and 14). connect v20v?pin with vfilt?pin in this case. v20v regulator will only be enabled when vfil t?bit is set (, see system status service, p37). the host controller can also monitor the status of the regulator (, see system status service, p37). the 20 v regulator has a current limit that depends on the fanin resistor value, and the value of bits 0?3 (v20vclimit) of the analog control register. in t able 4, the typical value of the current limit at startup is given as i 20v_lim (v20vclimit initializes at 100). for each bit difference, the current limit is adjusted up or down by i 20 v, s t e p . xtal oscillator an analog oscillator cell generates the main clock of 16 mhz. this clock is directly provided to the digital block to generate all necessary clock domains. an input pin xsel is foreseen to enable the use of a quartz crystal (see figure 16) or an external clock generator (see figure 17) to generate the main clock. 2. the formula is for a typical knx application. it?s only given as guidance and does not guarantee compliance with the knx stan dard.
ncn5121 www. onsemi.com 20 figure 16. xtal oscillator figure 17. external clock generator xtal1 xtal2 xclk osc xsel 32 35 34 33 21 8 mhz @ xclc = vss 16 mhz @ xclc = vdd vdd xclkc microcontroller xtal1 xtal2 xclk osc xsel 32 35 34 33 21 vdd xclkc 8 mhz @ xclc = vss 16 mhz @ xclc = vdd the xclk?pin can be used to supply a clock signal to the host controller. this clock signal can be switched off by a command from the host controller (, see analog control register 0, p53). after power?up, a 4 mhz (note 3) clock signal will be present on the xclk?pin during stand?by. when normal state is entered, a 8 or 16 mhz clock signal will be present on the xclk?pin. see also figure 20. to output an 8 mhz clock on the xclk pin, the xclkc pin must be pulled to ground. when the xclkc pin is pulled up to vddd, the xclk pin will output a 16 mhz clock signal. when normal state is left and stand?by state is entered due to an issue different than an xtal issue, the 8 or 16 mhz clock signal will still be present on the xclk?pin during the stand?by state. if however stand?by is entered from normal state due to an xtal issue, the 4 mhz clock signal will be present on the xclk?pin. see also table 7. fanin?pin the fanin?pin defines the maximum allowed bus current and bus current slopes. if the fanin?pin is kept floating, pulled up to v dd , or pulled down with a resistance higher than 250 k , ncn5121 will limit the knx bus current slopes to 0.5 ma/ms at all times. ncn5121 will also limit the knx bus current to 30 ma during start?up. during normal operation, ncn5121 is capable of taking up to 12 ma (= i coupler ) from the knx bus for supplying external loads (dc1, dc2 and v20v). if the fanin?pin is pulled to ground with a resistance smaller than 2 k the operation is similar as above with the exception that the knx bus current slopes will be limited to 1 ma/ms at all times, the knx bus current will be limited to 60 ma during start?up and up to 24 ma (i coupler ) can be taken from the knx bus during normal operation. definitions for start?up and normal operation (as given above) can be found in the knx specification. transmit trigger when bit 3 of analog control register 0 is set, the trig?pin will output a signal that goes high 1 bit time before the start of a scheduled transmission, and goes low when the transmission is complete or a collision is detected. this can be used during development as verification of transmission. note that a scheduled transmission is a frame that is sent less than t bus,idle (todo s) after previous communication on the bus. when a frame is transmitted on a bus which has been idle for a longer time, or an ack/nack/busy response is sent, the transmission will start immediately after the trigger goes high, and the time between trigger high and frame transmission start will not be consistent. resetb? and saveb?pin the resetb signal can be used to keep the host controller in a reset state. when resetb is low this indicates that the bus voltage is too low for normal operation and that the fixed dc?dc converter has not started up. it could also indicate a thermal shutdown (tsd). the resetb signal also indicates if communication between host and ncn5121 is possible. the saveb signal indicates correct operation. when saveb goes low, this indicates a possible issue (loss of bus power or too high temperature) which could trigger the host controller to save critical data or go to a save state. saveb goes low immediately when vfilt goes below 14 v (due to sudden large current usage) or after 2 ms when vbus goes below 20 v. resetb goes low when vfilt goes below 12 v. resetb? and saveb?pin are open?drain pins with an internal pull?up resistor to v ddd . voltage supervisors ncn5121 has different voltage supervisors monitoring vbus, vfilt, vdd2 and v20v. the general function of a voltage supervisor is to detect when a voltage is above or below a certain level. the levels for the different voltages monitored can be found back in t able 4 (see also figures 4, 5, 6 and 7). the status of the voltage supervisors can be monitored by the host controller (see system status service, p37). depending on the voltage supervisor outputs, the device can enter different states (see analog state diagram, p23). 3. the 4 mhz clock signal is internally generated and will be less accurate as the crystal generated clock signal of 8 or 16 mhz .
ncn5121 www. onsemi.com 21 figure 18. fixed (vdd1) and adjustable (vdd2) dc?dc converter vsw1 vin vss1 vdd1m vdd1 vsw2 vss2 vdd2mv vdd2mc vdd2 comp switch controller comp switch controller from vfilt 1 10 f vdd1 = 3.3v 0.47 10 f vdd2 = 3.3v ? 20v ncn5121 r 5 r 4 l 2 l 1 p 2 n 2 p 1 n 1 0.47
ncn5121 www. onsemi.com 22 table 7. status of several blocks during the different (analog) states state osc xclk vdd1 vdd2/v20v spi/uart knx reset off off off off inactive inactive start?up off off start?up off inactive inactive stand?by (note 17) off 4 mhz on start?up active inactive (note 22) stand?by (note 18) on (note 20) on (note 20) on on (note 21) active inactive (note 22) normal on on (note 19) on on active active 17. only valid when entering stand?by from start?up state. 18. only valid when entering stand?by from normal state. 19. 8 mhz or 16 mhz depending on xclkc. 20. 4 mhz signal if stand?by state was entered due to oscillator issue. otherwise 8 mhz or 16 mhz clock signal. 21. only operational if stand?by state was not entered due to vdd2 or v20v issue. 22. under certain conditions knx bus is (partly) active. see digital state diagram for more details. temperature monitor the device produces an over?temperature warning (tw) and a thermal shutdown warning (tsd). whenever the junction temperature rises above the thermal w arning level (t tw ), the saveb?pin will go low to signal the issue to the host controller. because the saveb?pin will not only go low on a thermal warning (tw), the host controller needs to verify the issue by requesting the status (, see system status service, p37). when the junction temperature is above tw, the host controller should undertake actions to reduce the junction temperature and/or store critical data. when the junction temperature reaches thermal shutdown (t tsd ), the device will go to the reset state. the thermal shutdown will be stored (, see analog status register, p55) and the analog and digital power supply will be stopped (to protect the device). the device will stay in the reset state as long as the temperature stays above t tsd . if the temperature drops below t tsd , start?up state will be entered (see also figure 19). at the moment vdd1 is back up and the otp memory is read, stand?by state will be entered and resetb will go high. the xtal oscillator will be started. once the temperature has dropped below t tw and all voltages are high enough, normal state will be entered. saveb will go high and knx communication is again possible. the tw?bit will be reset at the moment the junction temperature drops below t tw . the tsd?bit will only be reset when the junction temperature is below t tsd and the bit is read (see analog status register, p55). figure 8 gives a better view on the temperature monitor. watchdog ncn5121 provides a watchdog function to the host controller. the w atchdog function can be enabled by means of the wden?bit (, see w atchdog register, p53). once this bit is set to ?1?, the host controller needs to re?write this bit to clear the internal timer before the watchdog timeout interval expires (watchdog timeout interval = , see watchdog register, p53). in case the watchdog is acknowledged too early (before t wdpr ) or not within the watchdog timeout interval (t wdto ), the resetb?pin will be made low (= reset host controller). table 8 gives the watchdog timings t wdto and t wdpr . details on can be found in the watchdog register, p53. table 8. watchdog timings wdt[3:0] t wdto [ms] t wdpr [ms] 0000 33 2 0001 66 4 0010 98 6 0011 131 8 0100 164 10 0101 197 12 0110 229 14 0111 262 16 1000 295 18 1001 328 20 1010 360 23 1011 393 25 1100 426 27 1101 459 29 1110 492 30 1111 524 31
ncn5121 www. onsemi.com 23 analog state diagram the analog state diagram of ncn5121 is given in figure 19. the status of the oscillator, xclk?pin, dc?dc converters, v20v regulator, serial and knx communication during the different (analog) states is given in table 7. figure 20 gives a detailed view on the start?up behavior of ncn5121. after applying the bus voltage, the filter capacitor starts to charge. during this reset state, the current drawn from the bus is limited to i coupler (for details see the knx standards). once the voltage on the filter capacitor reaches 10 v (typ.), the fixed dc?dc converter (powering vdda) will be enabled and the device enters the start?up state. when v dd1 gets above 2.8 v (typ.), the otp memory is read out to trim some analog parameters (otp memory is not accessible by the user). when done, the stand?by state is entered and the resetb?pin is made high. if at this moment v bus is above v bush , the vbus?bit will be set (, see system status service, p37 ). after aprox. 2 ms the xtal oscillator will start. when v filt is above v filth dc2 and v20v will be started. when the xtal oscillator has started, no thermal w arning (tw) or thermal shutdown (tsd) was detected and the vbus?, vfilt?, vdd2? and v20v?bits are set, the normal state will be entered and saveb?pin will go high. figure 21 gives a detailed view on the shut?down behavior. if the knx bus voltage drops below v busl for more than t bus_filter , the vbus?bit will be reset (, see system status service, p37) and the standy?by state is entered. saveb will go low to signal this. when vfilt drops below v filtl , dc2 and the v20v regulator will be switched off. when vfilt drops below 6.5 v (typ), dc1 will be switched off and v dd1 drops below 2.8 v (typ.) the device goes to reset state (resetb low). analog output a multiplexed analog signal is available on the anaout?pin for monitoring signal levels. the signal read out on this pin can be configured through the analog output control bits (, see analog control register 1, p 52). figure 19. analog state diagram reset resetb = ?0? saveb = ?0? start?up resetb = ?0? saveb = ?0? stand?by resetb = ?1? saveb = ?0? normal resetb = ?1? saveb = ?1? v filt > 12v and temp < tsd v filt < 6.5v v dda ok and otp read done = ?1? or v dda nok remarks: ? , , , , and are internal status bits which can be verified with the system state servi ce. ? is an internal signal indicating a thermal shutdown. this internal signal cannot be read out. ? although reset state could be entered from normal state on a tsd, stand?by state will be entered first due to a tw. enable dc1 disable dc1 enable dc2 and v20v v filt > v filth disable dc2 and v20v v filt < v filtl disable dc1 v filt < 6.5v = ?0? and = ?1? and disable dc1, dc2 and v20v = ?1? or v dda nok = ?1? and = ?1? and = ?1? and = ?1? = ?1? or = ?0? or = ?0? or = ?0? or = ?0? or = ?0? and clock present
ncn5121 www. onsemi.com 24 figure 20. start?up behavior resetb saveb xclk v bus v filt i bus i coupler_lim,startup v dd1 12v v filth 2.8v v xtal xtal oscillator 2ms v bush v dd2 0.9 x v dd2 v 20v v 20vh reset start?up stand?by normal t remarks: vdd1 directly connected to vdda. 2ms
ncn5121 www. onsemi.com 25 figure 21. shut?down behavior resetb saveb xclk v bus v filt i bus v dd1 6.5v v filtl 2.8v v xtal xtal oscillator v bush v dd2 0.9 x v dd2 v 20v reset stand-by normal t remarks: vdd1 directly connected to vdda. v busl t bus_filter t bus_filter normal stand-by
ncn5121 www. onsemi.com 26 interface mode the device can communicate with the host controller by means of a uart interface or an spi interface. the selection of the interface is done by the pins mode1, mode2, treq, sck/uc2 and csb/uc1. table 9. interface selection treq mode2 mode1 sck/uc2 csb/uc1 sdi/rxd sdo/txd description 0 0 0 0 0 rxd txd 9?bit uart?mode, 19200 bps 0 0 0 0 1 9?bit uart?mode, 38400 bps 0 0 0 1 0 8?bit uart?mode, 19200 bps 0 0 0 1 1 8?bit uart?mode, 38400 bps 1 0 0 dc2en v20ven driver receiver analog mode treq 0 1 sck (out) csb (out) sdi sdo spi master, 125 kbps treq 1 0 spi master, 500 kbps note: x = don?t care uart interface the uart interface is selected by pulling pins treq, mode1 and mode2 to ground. pin uc2 is used to select the uart mode (?0? = 9?bit, ?1? = 8?bit) and pin uc1 is used to select the baudrate (?0? = 19200 bps, ?1? = 38400 bps). the uart interface allows full duplex, asynchronous communication. the difference between 8?bit mode and 9?bit mode is that in 9?bit an additional parity bit is transmitted. this parity bit is used as an even parity bit (with exception of the internal register read and write services where the parity bit is meaningless and should be ignored). however, when the ncn5121 detects an acceptance window error or pulse duration error on the knx bus, the parity bit is also encoded to indicate an error in the byte. in 8?bit mode one extra service is available (u_framestate.ind). the sdi/rxd?pin is the ncn5121 uart receive pin and is used to send data from the host controller to the device. pin sdo/txd is the ncn5121 uart transmit pin and is used to transmit data between the device and the host controller. figure 12 gives an uart application example (9?bit, 19200 bps). data is transmitted lsb first. start (= 0) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop (= 1) figure 22. 8?bit uart mode start (= 0) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 parity stop (= 1) figure 23. 9?bit uart mode one special uart mode is foreseen called analog mode. when this mode is selected (treq = ?1?, modex = ?0?) an immediate connection is made with the knx transmitter receiver (see figure 24). bit level coding/decoding has to be done by the host controller. keep in mind that the signals on the sdi/rxd? and sdo/txd?pin are inverted. figure 14 gives an analog mode application example. in analog mode, the uc1 and uc2 pins are used to enable or disable the 20 v regulator and dc2 controller. when pulled low, these blocks are enabled. when one of these pins is pulled to vddd, the respective block is disabled. when using the device in analog mode, no clock needs to be provided to the device.
ncn5121 www. onsemi.com 27 figure 24. analog uart mode por tw/ tsd uvd dc/dc converter 1 dc/dc converter 2 osc ncn5121 cav vbus1 ccp txo fanin vbus2 v20v xtal1 xtal2 xsel xclkc saveb resetb anaout vss2 vdd2 vdd2mv vdd2mc vsw2 vss1 vdd1 vdd1m vsw1 vin mode2 mode1 treq (treq = 1) csb/uc1 sdo/txd sdi/rxd sck/uc2 vssd vddd vdda vssa vfilt ceq2 ceq1 20v ldo fan?in control bus coupler impedance control transmitter receiver rc osc diagnostics osc xclk
ncn5121 www. onsemi.com 28 spi interface the spi interface is selected by mode1? and mode2?pin. the baudrate is determined by which mode?pin is pulled high (mode1 pulled high = 125 kbps, mode2 pulled high = 500 kbps). the spi interface allows full duplex synchronous communication between the device and the host controller. the interface operates in mode 0 (cpol and cpha = ?0?) meaning that the data is clocked out on the falling edge and sampled on the rising edge. the lsb is transmitted first. sck sdi csb lsb 1 2 3 4 5 6 msb sdo 1 0 3 2 5 4 7 6 lsb 1 2 3 4 5 6 msb figure 25. spi transfer during spi transmission, data is transmitted (shifted out serially) on the sdo/txd?pin and received (shifted in serially) on the sdi/rxd?pin simultaneously. sck/uc2 is set as output and is used as the serial clock (sck) to synchronize shifting and sampling of the data on the sdi? and sdo?pin. the speed of this clock signal is selectable (see table 9). the slave select line (csb/uc1?pin) will go low during each transmission allowing to selection the host controller (csb?pin is high when spi is in idle state). shift register control ncn5121 sdo/txd sdi/rxd sck/uc2 csb/uc1 shift register host controller miso mosi sclk ss control figure 26. spi master in an spi network only one spi master is allowed (in this case ncn5121). to allow the host controller to communicate with the device the treq?pin can be used (transmit request). when ncn5121 detects a negative edge on treq, the device will issue dummy transmission of 8 bits which will result in a transmission of data byte from the host controller to the device. see figure 11 for details on the timings. see figure 13 for an spi application example. sck sdi csb sdo treq 01234 567 ddddd ddd 01234 ddddd dummy start dummy transmission figure 27. transmission request
ncn5121 www. onsemi.com 29 digital functional description the implementation of the data link layer as specified in the knx standard is divided in two parts. all functions related to communication with the physical layer and most of the data link layer services are inside ncn5121, the rest of the functions and the upper communication layers are implemented into the host controller (see figure 28). the host controller is responsible for handling: ? checksum ? parity ? addressing ? length the ncn5121 is responsible for handling: ? checksum ? parity ? acknowledge ? repetition ? timing digital state diagram the digital state diagram is given in figure 29. the current mode of operation can be retrieved by the host controller at any time (when resetb?pin is high) by issuing the u_systemstat.req service and parsing back u_systemstat.ind service (see system status service, p37). table 10. ncn5121 digital states state explanation reset entered after power on reset (por) or in response to a u_reset.req service issued by the host controller. in this state ncn5121 gets initialized, all features disabled and services are ignored and not executed. power?up / power?up stop entered after reset state or when vbus, vfilt or xtal are not operating correctly (operation of vbus, vfilt and xtal can be verified by means of the system status service, p37). communication with knx bus is not allowed. u_systemstat.ind can be used to verify this state (code 00). sync ncn5121 remains in this state until it detects silence on the knx bus for at least 40 tbits. although the receiver of ncn5121 is on, no frames are transmitted to the host controller. u_systemstat.ind can be used to verify this state (code 01). stop this state is useful for setting?up ncn5121 safely or temporarily interrupting reception from the knx bus. u_systemstat.ind can be used to verify this state (code 10). normal in this state the device is fully functional. communication with the knx bus is allowed. u_systemstat.ind can be used to verify this state (code 11).
ncn5121 www. onsemi.com 30 application layer presentation layer session layer transport layer network layer data link layer logic link control media access control physical layer 7 6 5 4 3 2 1 ncn5121 host controller figure 28. osi model reference reset initialize device deactivate all features por or u_reset.req power?up code: 00 knx rx = off knx tx = off sync code: 01 knx rx = on knx tx = off stop code: 10 knx rx = off knx tx = off normal code: 11 knx rx = on knx tx = on power?up stop code: 00 knx rx = off knx tx = off = ?1? and = ?1? and = ?1? =?0? or = ?0? or = ?0? = ?1? and = ?1? and = ?1? = ?0? or = ?0? or = ?0? = ?0? or = ?0? or = ?0? send u _reset .ind to host knx bus idle for 40 tbits u_exitstopmode.req send u_stopmode.ind to host u_stopmode.req u_stopmode.req and no activity for 30 tbits u_exitstopmode .req send u_stopmode.ind to host u_stopmode .req figure 29. digital state diagram
ncn5121 www. onsemi.com 31 services execution of services depends on the digital state (figure 29). certain services are rejected if received outside the normal state. the following table gives a view of all services and there acceptance during the different digital states. table 11. acceptance of services service state normal stop sync power?up bus monitor u_reset.req e e e e e u_state.req e e e e i u_setbusy.req e e e e i u_quitbusy.req e e e e i u_busmon.req e e e e i u_setaddress.req e e e e i u_setrepetition.req e e e e i u_l_dataoffset.req e e e e i u_systemstat.req e e e e i u_stopmode.req e i e e e u_exitstopmode.req i e i i e u_ackn.req e r r r i u_configure.req e e e e i u_intregwr.req e e e e e u_intregrd.req e e e e e u_l_datastart.req e r r r i u_l_datacont.req e r r r i u_l_dataend.req e r r r i u_pollingstate.req e e e e i note: bus monitor state is not a separate state. it is applied on top of normal, stop, sync or power?up state. legend: e = service is executed i = service is ignored (not executed and no feedback sent to the host controller) r = service is rejected (not executed, protocol error is sent back to the host controller through u_state.ind) see internal register read service (p39) for limitations of u_intregrd.req
ncn5121 www. onsemi.com 32 table 12. services from host controller control field service name hex remark extra following bytes total bytes 7 6 5 4 3 2 1 0 internal commands ? device specific 0 0 0 0 0 0 0 1 u_reset.req 01 1 0 0 0 0 0 0 1 0 u_state.req 02 1 0 0 0 0 0 0 1 1 u_setbusy.req 03 1 0 0 0 0 0 1 0 0 u_quitbusy.req 04 1 0 0 0 0 0 1 0 1 u_busmon.req 05 1 1 1 1 1 0 0 0 1 u_setaddress.req f1 addrhigh addrlow x (don?t care) 4 1 1 1 1 0 0 1 0 u_setrepetition.req f2 repcntrs x (don?t care) x (don?t care) 4 0 0 0 0 1 i i i u_l_dataoffset.req 08?0c iii = msb byte index (0 4) 1 0 0 0 0 1 1 0 1 u_systemstate.req 0d 1 0 0 0 0 1 1 1 0 u_stopmode.req 0e 1 0 0 0 0 1 1 1 1 u_exitstopmode.req 0f 1 0 0 0 1 0 n b a u_ackn.req 10?17 n = nack b = busy a = addressed 1 0 0 0 1 1 p c m u_configure.req 18?1f p = auto?polling c = crc?ccitt m = frame end with marker 1 0 0 1 0 1 0 a a u_intregwr.req 28?2b aa = address of internal register data to be written 2 0 0 1 1 1 0 a a u_intregrd.req 38?3b 1 1 1 1 0 s s s s u_pollingstate.req e0?ee s = slot number (0 14) polladdrhigh polladdrlow pollstate 4 knx transmit data commands 1 0 0 0 0 0 0 0 u_l_datastart.req 80 control octet (ctrl) 2 1 0 i i i i i i u_l_datacont.req 81?bf i = index (1 63) data octet (ctrle, sa, da, at, npci, lg, tpdu) 2 0 1 l l l l l l u_l_dataend.req 47?7f l = last index + 1 (7 63) check octet (fcs) 2 with respect to command length, there are two types of services from the host controller: ? single?byte commands: the control byte is the only data sent from the host controller to ncn5121. ? multiple?byte commands: the following data byte(s) need to be handled according to the already received control byte. with respect to command purpose there are two types of services from the host controller: ? internal command: does not initiate any communication on the knx bus. ? knx transmit data command: initiates knx communication
ncn5121 www. onsemi.com 33 table 13. services to host controller control field service name remark extra following bytes total bytes 7 6 5 4 3 2 1 0 dll (layer 2) services (device is transparent) 1 0 r 1 p1 p0 0 0 l_data_standard.ind r = not repeated (?1?) or repeated l_data frame (?0?) p1, p0 = priority n 0 0 r 1 p1 p0 0 0 l_data_extended.ind n 1 1 1 1 0 0 0 0 l_poll_data.ind n acknowledge services (device is transparent in bus monitor mode) x x 0 0 x x 0 0 l_ackn.ind x = acknowledge frame 1 z 0 0 0 1 0 1 1 l_data.con z = positive (?1?) or negative (?0?) confirmation 1 control services ? device specific 0 0 0 0 0 0 1 1 u_reset. . ind 1 sc re te pe tw 1 1 1 u_state.ind sc = slave collision re = receive error te = transmit error pe = protocol error tw = temperature warning 1 re ce te 1 res 0 1 1 u_framestate.ind re = parity or bit error ce = checksum or length error te = timing error res = reserved 1 0 b aa ap c m 0 1 u_configure.ind b = reserved aa = auto?acknowledge ap = auto?polling c = crc?ccitt m = frame end with marker 1 1 1 0 0 1 0 1 1 u_frameend.ind 1 0 0 1 0 1 0 1 1 u_stopmode.ind 1 0 1 0 0 1 0 1 1 u_systemstat.ind v20v, vdd2, vbus, vfilt, xtal , tw, mode 2 each data byte received from the knx bus is transparently transmitted to the host controller. an exception is the acknowledge byte which is transmitted to the host controller only in bus monitoring mode. other useful information can be transmitted to the host controller by request using internal control services. a detailed description of the services is given on the next pages. for all figures, the msb bit is always given on the left sid e no matter how the arrow is drawn. host ctrl ncn5121 knx bus msb 6 5 4 3 2 1 lsb msb 6 5 4 3 2 1 lsb msb 6 5 4 3 2 1 lsb msb 6 5 4 3 2 1 lsb figure 30. bit order of services
ncn5121 www. onsemi.com 34 reset service reset the device to the initial state. 0 0 0 0 0 0 0 1 u_reset.req 0 0 0 0 0 0 1 1 u_reset.ind host ctrl ncn5121 knx bus figure 31. reset service remark: u_reset.ind will be send when entering normal state (see digital state diagram, p29). state service get internal communication state of the device. 0 0 0 0 0 0 1 0 u_state.req sc re te pe tw 1 1 1 u_state.ind host ctrl ncn5121 knx bus figure 32. state service sc (slave collision): ?1? if collision is detected during transmission of polling state re (receive error): ?1? if corrupted bytes were sent by the host controller. corruption involves incorrect parity (9?bit uart only) and stop bit of every byte as well as incorrect control octet, length or checksum of frame for transmission. te (transceiver error): ?1? if error detected during frame transmission (sending ?0? but receiving ?1?). pe (protocol error): ?1? if an incorrect sequence of commands sent by the host controller is detected. tw (thermal warning): ?1? if thermal warning condition is detected. set busy service activate busy mode. during this time and when autoacknowledge is active (see set address service p35), ncn5121 rejects the frames whose destination address corresponds to the stored physical address by sending the busy acknowledge. this service has no ef fect if autoacknowledge is not active. 0 0 0 0 0 0 1 1 u_setbusy.req host ctrl ncn5121 knx bus figure 33. set busy service remark: busy mode is deactivated immediately if the host controller confirms a frame by sending u_ackn.req service. quit busy service deactivate the busy mode. restores back to the normal autoacknowledge behavior with ack sent on the bus in response to addressing frame (only if autoacknowledge is active). this service has no effect if autoacknowledge is not active or busy mode was not set. 0 0 0 0 0 1 0 0 u_quitbusy.req host ctrl ncn5121 knx bus figure 34. quit busy service
ncn5121 www. onsemi.com 35 bus monitor service activate bus monitoring state. in this mode all data received from the k nx bus is sent to the host controller without performing any filtering on data link layer. acknowledge frames are also transmitted transparently. this state can only be exited by the reset service (see p34). 0 0 0 0 0 1 0 1 u_busmon.req x x x x x x x x knx message host ctrl ncn5121 knx bus x x x x x x x x knx message x x x x x x x x knx message x x x x x x x x knx message 0 0 0 0 0 0 0 1 u_reset.req 0 0 0 0 0 0 1 1 u_reset.ind x x 0 0 x x 0 0 acknowledge x x 0 0 x x 0 0 acknowledge figure 35. bus monitor service remark: x = don?t care set address service sets the physical address of the device and activates the auto?acknowledge function. ncn5121 starts accepting all frames whose destination address corresponds to the stored physical address or whose destination address is the group address by sending iack on the bus. in case of an error detected during such frame reception, ncn5121 sends nack instead of iack. when issued several times after each other, the first call will set the physical address and activate the auto?acknowledge. following calls will only set the physical address because auto?acknowledge is already activated. ncn5121 confirms activation of auto?acknowledge function by sending the u_configure.ind service to the host controller. 1 1 1 1 0 0 0 1 u_setaddress.req host ctrl ncn5121 knx bus x x x x x x x x address high byte x x x x x x x x address low byte 0 b aa ap c m 0 1 u_configure.ind x x x x x x x x dummy figure 36. set address service
ncn5121 www. onsemi.com 36 b (busy mode): ?1? if busy mode is active. can be enabled with u_setbusy.req (see set busy service, p34) and disabled with u_quitbusy.req service (see quit busy service , p34) or u_ackn.req service (see receive frame service , p47). aa (auto?acknowledge):?1? if auto?acknowledge feature is active. can be enabled with u_setaddress.req service (see set address service , p35). ap (auto?polling): ?1? if auto?polling feature is active. this feature can be enabled with u_configure.req service (see configure service , p38). c (crc?ccitt): ?1? if crc?ccitt feature is active. this feature can be enabled with u_configure.req service (see configure service , p38). m (frame end with marker): ?1? when feature is active. this feature can be enabled with u_configure.req service (see configure service , p38). remarks: ? set address service can be issued any time but the new physical address and the autoacknowledge function will only get active after the knx bus becomes idle. ? autoacknowledge can only be deactivated by a reset service (p34) ? x = don?t care ? dummy byte can be anything. ncn5121 completely disregards this information. set repetition service specifies the maximum repetition count for transmitted frames when not acknowledged with iack. separate counters can be set for nack and busy frames. initial value of both counters is 3. if the acknowledge from remote data link layer is busy during frame transmission, ncn5121 tries to repeat after at least 150 bit times knx bus idle. the busy counter determines the maximum amount of times the frame is repeated. if the busy acknowledge is still received after the last try, an l_data.con with a negative conformation is sent back to the host controlle r. for all other cases (nack acknowledgment received, invalid/corrupted acknowledge received or time?out after 30 bit times) ncn5121 will repeat after 50 bit times of knx bus idle. the nack counter determines the maximum retries. l_data.con with a negative confirmation is send back to the host controller when the maximum retries were reached. in worst case, the same request is transmitted (nack + busy + 1) times before ncn5121 stops retransmission. figure 37. set repetition service 1 1 1 1 0 0 1 0 u_setrepetition.req host ctrl ncn5121 knx bus 0 b 0 n maximum repetitions b b n n x x x x dummy x x x x x x x x dummy x x x x bbb: busy counter (a frame will be retransmitted bbb?times if acknowledge with busy). nnn: nack counter (a frame will be retransmitted nnn?times if acknowledge with nack). remark: bit 3 and 7 of the second byte need to be zero (?0?)!
ncn5121 www. onsemi.com 37 system status service request the internal system state of the device. 0 0 0 0 1 1 0 1 u_systemstat .req host ctrl ncn5121 knx bus 0 1 0 0 1 0 1 1 u_systemstat .ind 2 nd byte xtal vfilt vbus vdd2 v20v tw mode figure 38. system state service v20v: ?1? if v20v linear voltage regulator is within normal operating range vdd2: ?1? if dc2 regulator is within normal operating range vbus: ?1? if knx bus voltage is within normal operating range vfilt: ?1? if voltage on tank capacitor is within normal operating range state service xtal: ?1? if crystal oscillator frequency is within normal operating range tw: ?1? if thermal warning condition is present (can also be verified with u_state.ind service (see state service, p34) mode: operation mode (see also digital state diagram, p29). bit mode 1 0 0 0 power?up 0 1 sync 1 0 stop 1 1 normal note: saveb?pin is low if any of bits 3 to 7 is ?0? (zero) or bit 2 is ?1?. stop mode service go to stop state. a confirmation is sent to indicate that device has switched to the stop state. see also digital state diagram , p29 0 0 0 0 1 1 1 0 u_stopmode.req host ctrl ncn5121 knx bus 0 0 1 0 1 0 1 1 u_stopmode.ind figure 39. stop mode service
ncn5121 www. onsemi.com 38 exit stop mode service request transition from stop to sync state. an acknowledge service is send later to confirm that device has switched from sync to normal state. see also digital state diagram, p29. 0 0 0 0 1 1 1 1 u_exitstopmode .req host ctrl ncn5121 knx bus 0 0 0 0 0 0 1 1 u_reset.ind figure 40. exit stop mode service configure service activate additional features (which are disabled after reset). u_configure.ind service is send back to the host controller at the exact moment when the new features get activated. this is done during bus idle or outside the normal state. it confirms the execution of the request service. host ctrl ncn5121 knx bus 0 0 0 1 1 m u_configure.req c p 0 b aa ap c 1 u_configure.ind 0 m figure 41. configure service p (auto polling): when active, ncn5121 automatically fills in corresponding poll slot of polling telegrams. host controller is responsible to provide appropriate polling information with the u_pollingstate.req service (see slave polling frame service and master polling frame service, p50 and 51). c (crc?ccitt): when active, ncn5121 accompanies every received frame with a 2?byte crc?ccitt value. crc?ccitt is also known as crc?16?ccitt. m (frame end with marker): end of received frames is normally reported with a silence of 2.6 ms on the tx line to the host controller. with this feature active, ncn5121 marks end of frame with u_frameend.ind + u_framestate.ind services (see send frame service and receive frame service, p39 and 47). b: ?1? if busy mode is active. can be enabled with u_setbusy.req (see set busy service, p34) and disabled with u_quitbusy.req service (see quit busy service, p34) or u_ackn.req service (see receive frame service, p47). aa: ?1? if auto?acknowledge feature is active. can be enabled with u_setaddress.req service (see set address service, p35). ap (auto?polling): ?1? if auto? polling feature is active. this feature can be enabled with u_configure.req service. c (crc?ccitt): ?1? if crc?ccitt feature is active. see p52 for info on crc?ccitt. this feature can be enabled with u_configure.req service. m (frame end with marker): ?1? when feature is active. this feature can be enabled with u_configure.req service. remark: activation of the additional features is done by setting the corresponding bit to ?1?. setting the bit to ?0? (zero) has no eff ect (will not deactivate feature). features can only be deactivated by a reset. set all bits (m, c and p) to ?0? (zero) to poll the curre nt configuration status.
ncn5121 www. onsemi.com 39 internal register write service write a byte to an internal device?specific register (see internal device?specific registers , p53). the address of the register is specified in the request. the data to be written is transmitted after the request. 0 0 1 0 1 0 a a u_intregwr .req host ctrl ncn5121 knx bus x x x x x x x x data byte figure 42. internal register write service aa: address of the internal register remarks: ? x = don?t care (in line with internal device?specific registers , p53). ? internal register write is not synchronized with other services. one should only use this service when all previous services are ended. when using communication over spi, it is recommended to go to stop mode when performing a register write. when communicating over uart, this is not required. internal register read service read a byte from an internal device?specific register (see internal device?specific registers , p53). the address of the register is specified in the request. the next byte returns the data of the addressed register. 0 0 1 1 1 0 a a u_intregrd.req host ctrl ncn5121 knx bus x x x x x x x x data byte figure 43. internal register read service aa: address of the internal register remarks: ? x = don?t care (in line with internal device?specific registers , p53). ? it?s advised to only use this service in stop, power?up stop or power?up state. in the other state erroneous behavior could occur. ? internal register read is not synchronized with other services. one should only use this service when all previous services are ended. when using communication over spi or uart, it is recommended to go to stop mode when performing a register write. send frame service send data over the knx bus. the u_l_datastart.req is used to start transmission of a new frame. the byte following this request is the control byte of the knx telegram. the different bytes following the control byte are assembled by using u_l_datacont.req. the byte following u_l_datacont.req is the data byte of the knx telegram. u_l_datacont.req contains the index which specifies the position of the data byte inside the knx telegram. it?s allowed to transmit bytes in random order and even overwrite bytes (= write several times into the same index). it?s up to the host controller to correctly populate all data bytes of the knx telegram. u_l_dataend.req is used to finalize the frame and start the knx transfer. the byte following u_l_dataend.req is the checksum of the knx telegram. if the checksum received by the device corresponds to the calculated checksum, the device starts the transmission on the knx bus. if not, the device returns u_state.ind message to the host controller with receive error flag set (see state service p34 for u_state.ind).
ncn5121 www. onsemi.com 40 u_l_datastart/datacont/dataend only provides space for 6 index bits. because an extended frame can consist out of 263 bytes, an index of 9 bits long is needed. u_dataoffset.req provides the 3 most significant bits of the data byte index. the value is stored internally until a new offset is provided with another call. each transmitted data octet on the knx bus will also be transmitted back to the host controller. each transmission is ended with a l_data.con service where the msb indicates if an acknowledgment was received or not. when operating in spi or uart 8?bit mode, l_data.con is preceded with u_framestate.ind. depending on the activated features, a crc?ccitt service and/or a marker could be included. next figures give different examples of send frames. 1 0 0 0 0 0 0 0 u_l_datastart.req host ctrl ncn5121 knx bus x x x x x x x x control byte 1 0 i i i i i i u_l_datacont.req x x x x x x x x data octet 1 0 0 0 0 1 i i i u_l_dataoffset .req 1 0 i i i i i i u_l_datacont.req x x x x x x x x data octet n 0 1 l l l l l l u_l_dataend .req x x x x x x x x checksum x x x x x x x x control byte x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x 0 r 1 p1 p0 0 0 l_data.ind x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x x x x x x x x immediate ackn re ce te 1 res 0 1 1 u_framestate .ind x 0 0 0 1 0 1 1 l_data.con 2.6ms silence figure 44. send frame, spi or 8?bit uart mode, frame end with silence, no crc?ccitt
ncn5121 www. onsemi.com 41 1 0 0 0 0 0 0 0 u_l_datastart.req host ctrl ncn5121 knx bus x x x x x x x x control byte 1 0 i i i i i i u_l_datacont.req x x x x x x x x data octet 1 0 0 0 0 1 i i i u_l_dataoffset .req 1 0 i i i i i i u_l_datacont.req x x x x x x x x data octet n 0 1 l l l l l l u_l_dataend .req x x x x x x x x checksum x x x x x x x x control byte x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x 0 r 1 p1 p0 0 0 l_data.ind x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x x x x x x x x immediate ackn x 0 0 0 1 0 1 1 l_data.con 2.6ms silence figure 45. send frame, 9?bit uart mode, frame end with silence, no crc?ccitt
ncn5121 www. onsemi.com 42 1 0 0 0 0 0 0 0 u_l_datastart.req host ctrl ncn5121 knx bus x x x x x x x x control byte 1 0 i i i i i i u_l_datacont.req x x x x x x x x data octet 1 0 0 0 0 1 i i i u_l_dataoffset .req 1 0 i i i i i i u_l_datacont.req x x x x x x x x data octet n 0 1 l l l l l l u_l_dataend.req x x x x x x x x checksum x x x x x x x x control byte x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x 0 r 1 p1 p0 0 0 l_data.ind x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x x x x x x x x immediate ackn x x x x x x x x crc?ccitt low byte 2.6 ms silence x x x x x x x x crc? ccitt high byte x 0 0 0 1 0 1 1 l_data.con figure 46. send frame, 9?bit uart mode, frame end with silence, with crc?ccitt
ncn5121 www. onsemi.com 43 1 0 0 0 0 0 0 0 u_l_datastart.req host ctrl ncn5121 knx bus x x x x x x x x control byte 1 0 i i i i i i u_l_datacont.req x x x x x x x x data octet 1 0 0 0 0 1 i i i u_l_dataoffset .req 1 0 i i i i i i u_l_datacont.req x x x x x x x x data octet n 0 1 l l l l l l u_l_dataend .req x x x x x x x x checksum x x x x x x x x control byte x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x 0 r 1 p1 p0 0 0 l_data.ind x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x x x x x x x x immediate ackn x x x x x x x x crc?ccitt low byte 2.6ms silence x x x x x x x x crc? ccitt high byte re ce te 1 res 0 1 1 u_framestate .ind x 0 0 0 1 0 1 1 l_data.con figure 47. send frame, spi or 8?bit uart mode, frame end with silence, with crc?ccitt
ncn5121 www. onsemi.com 44 1 0 0 0 0 0 0 0 u_l_datastart .req host ctrl ncn5121 knx bus x x x x x x x x control byte 1 0 i i i i i i u_l_datacont .req x x x x x x x x data octet 1 0 0 0 0 1 i i i u_l_dataoffset .req 1 0 i i i i i i u_l_datacont .req x x x x x x x x data octet n 0 1 l l l l l l u_l_dataend.req x x x x x x x x checksum x x x x x x x x control byte x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x 0 r 1 p1 p0 0 0 l_data.ind x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x x x x x x x x immediate ackn re ce te 1 res 0 1 1 u_framestate .ind x 0 0 0 1 0 1 1 l_data.con 1 1 0 0 1 0 1 1 u_frameend.ind figure 48. send frame, all modes, frame end with marker, no crc?ccitt
ncn5121 www. onsemi.com 45 1 0 0 0 0 0 0 0 u_l_datastart .req host ctrl ncn5121 knx bus x x x x x x x x control byte 1 0 i i i i i i u_l_datacont .req x x x x x x x x data octet 1 0 0 0 0 1 i i i u_l_dataoffset .req 1 0 i i i i i i u_l_datacont .req x x x x x x x x data octet n 0 1 l l l l l l u_l_dataend.req x x x x x x x x checksum x x x x x x x x control byte x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x 0 r 1 p1 p0 0 0 l_data.ind x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x x x x x x x x immediate ackn x x x x x x x x crc? ccitt low byte x x x x x x x x crc? ccitt high byte re ce te 1 res 0 1 1 u_framestate .ind x 0 0 0 1 0 1 1 l_data.con 1 1 0 0 1 0 1 1 u_frameend.ind figure 49. send frame, all modes, frame end with marker and with crc?ccitt
ncn5121 www. onsemi.com 46 re (receive error): ?1? if newly received frame contained corrupted bytes (wrong parity, wrong stop bit or incorrect bit timings) ce (checksum or length error): ?1? if newly received frame contained wrong checksum or length which does not correspond to the number of received bytes te (timing error): ?1? if newly received frame contained bytes whose timings do not comply with the knx standard res (reserved): reserved for future use (will be ?0?). remarks: ? if the repeat flag is not set (see set repetition service p36), the device will only perform one attempt to send the knx telegram. ? sending of the knx telegram over the knx bus is only started after all data bytes are received and the telegram is assembled. ? when starting transmission of a new frame with u_l_datastart.req, the device automatically resets the internal offset of the data index to zero. ? data offsets of 5, 6 and 7 are forbidden (u_l_dataoffset.req)! remarks on figures 44 to 49: ? x = don?t care (in respect with knx standard) ? see tables 12 and 13 for more details on all the bits ? code of u_frameend.ind (0xcb) can also be part of the knx frame content (data octet). when ncn5121 transmits the data octet (0xcb) on the knx bus, 2 bytes (2 times 0xcb) will be transmitted back to the host controller to make it possible for the host controller to distinguish between a data octet (0xcb) and u_frameend.ind. this remark is only valid if frame end with marker is enabled. ? see p52 for info on crc?ccitt.
ncn5121 www. onsemi.com 47 receive frame service receive data over the knx bus. upon reception from the control byte, the control byte is checked by the device. if correct, the control byte is transmitted back to the host (l_data_standard.ind or l_data_extended.ind depending if standard or extended frame type is received). after the control byte, all data bytes are transparently transmitted back to the host controller. handling of this data is a ta sk for the data link layer which should be implemented in the host controller. the host controller can indicate if the device is addressed by setting the nack, busy or ack flag (u_ackn.req). when working in spi or 8?bit uart mode, each frame is ended with an u_framestate.ind. depending on the activated features, a crc?ccitt or marker could be added to the complete frame. below figures give different examples of receive frames. host ctrl ncn5121 knx bus x x x x x x x x control byte x x x x x x x x data octet 1 x x x x x x x x checksum x 0 r 1 p1 p0 0 0 l_data .ind x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x x x x x x x x immediate ackn re ce te 1 0 0 1 1 u_framestate .ind 0 0 0 1 0 n b a u_ackn .req x x x x x x x x data octet n 2.6 ms silence figure 50. receive frame, spi or 8?bit uart mode, frame end with silence, no crc?ccitt host ctrl ncn5121 knx bus x x x x x x x x control byte x x x x x x x x data octet 1 x x x x x x x x checksum x 0 r 1 p1 p0 0 0 l_data .ind x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x x x x x x x x immediate ackn 0 0 0 1 0 n b a u_ackn .req x x x x x x x x data octet n 2.6 ms silence figure 51. receive frame, 9?bit uart mode, frame end with silence, no crc?ccitt
ncn5121 www. onsemi.com 48 host ctrl ncn5121 knx bus x x x x x x x x control byte x x x x x x x x data octet 1 x x x x x x x x checksum x 0 r 1 p1 p0 0 0 l_data.ind x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x x x x x x x x immediate ackn 0 0 0 1 0 n b a u_ackn.req x x x x x x x x data octet n 2.6ms silence x x x x x x x x crc?ccitt low byte x x x x x x x x crc? ccitt high byte figure 52. receive frame, 9?bit uart mode, frame end with silence, with crc?ccitt host ctrl ncn5121 knx bus x x x x x x x x control byte x x x x x x x x data octet 1 x x x x x x x x checksum x 0 r 1 p1 p0 0 0 l_data.ind x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x x x x x x x x immediate ackn 0 0 0 1 0 n b a u_ackn.req x x x x x x x x data octet n 2.6ms silence x x x x x x x x crc?ccitt low byte x x x x x x x x crc? ccitt high byte re ce te 1 res 0 1 1 u_framestate.ind figure 53. receive frame, spi or 8?bit uart mode, frame end with silence, with crc?ccitt
ncn5121 www. onsemi.com 49 host ctrl ncn5121 knx bus x x x x x x x x control byte x x x x x x x x data octet 1 x x x x x x x x checksum x 0 r 1 p1 p0 0 0 l_data.ind x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x x x x x x x x immediate ackn 0 0 0 1 0 n b a u_ackn.req x x x x x x x x data octet n re ce te 1 res 0 1 1 u_framestate.ind 1 1 0 0 1 0 1 1 u_frameend.ind figure 54. receive frame, all modes, frame end with marker, no crc?ccitt host ctrl ncn5121 knx bus x x x x x x x x control byte x x x x x x x x data octet 1 x x x x x x x x checksum x 0 r 1 p1 p0 0 0 l_data.ind x x x x x x x x data octet 1 x x x x x x x x data octet n x x x x x x x x checksum x x x x x x x x immediate ackn 0 0 0 1 0 n b a u_ackn .req x x x x x x x x data octet n x x x x x x x x crc ? ccitt low byte x x x x x x x x crc ? ccitt high byte re ce te 1 res 0 1 1 u_framestate .ind 1 1 0 0 1 0 1 1 u_frameend .ind figure 55. receive frame, all modes, frame end with marker, with crc?ccitt
ncn5121 www. onsemi.com 50 re (receive error): ?1? if newly received frame contained corrupted bytes (wrong parity, wrong stop bit or incorrect bit timings) ce (checksum or length error): ?1? if newly received frame contained wrong checksum or length which does not correspond to the number of received bytes te (timing error) : ?1? if newly received frame contained bytes whose timings do not comply with the knx standard res (reserved) : reserved for future use (will be ?0?). remarks on figures 50 to 55: ? x = don?t care (in respect with knx standard) ? see tables 12 and 13 for more details on all the bits ? code of u_frameend.ind (0xcb) can also be part of the knx frame content (data octet). to make a distinguish between a data octet and u_frameend.ind, ncn5121 duplicates the data content (if 0xcb). this will result in 2 bytes transmitted to the host controller (two times 0xcb) corresponding to 1 byte received on the knx bus. above is only valid if frame end with marker is enabled. ? see p52 for info on crc?ccitt. slave polling frame service upon reception and consistency check of the polling control byte, the control byte is send back to the host controller (l_poll_data.ind). the host controller will send the slot number to the device (u_pollingstate.req), followed by the polling address and the polling state. at the same time the source address, polling address, slot count and checksum is received over the knx bus. if the polling address received from the knx bus is equal to the polling address received from the host controller , ncn5121 will send the polling data in the slot as define by u_pollingstate.req (only if the slotcount is higher as the define slot). u_pollingstate.req can be sent at any time (not only during a transmission of a polling telegram). the information is stored internally in ncn5121 and can be reused for further polling telegrams if auto?polling function gets activated. host ctrl ncn5121 knx bus 1 1 1 1 0 0 0 0 control byte x x x x x x x x source address x x x x x x x x checksum 1 1 1 1 0 0 0 0 l_poll_data.ind 1 1 1 0 s s s s u_pollingstate .req x x x x x x x x slot 0 x x x x x x x x polladdrhigh x x x x x x x x source address x x x x x x x x polladdrlow x x x x x x x x poll address x x x x x x x x poll address x x x x x x x x slot count x x x x x x x x pollstate x x x x x x x x slot n figure 56. slave polling frame service remarks: x = don?t care (in respect with knx standard) ssss = slot number
ncn5121 www. onsemi.com 51 master polling frame service when ncn5121 receives the polling frame from the host controller, the polling frame will be transmitted over the knx bus. host ctrl ncn5121 knx bus 1 1 1 1 0 0 0 0 control byte x x x x x x x x source address x x x x x x x x checksum 1 1 1 1 0 0 0 0 l_poll_data.ind 1 1 1 0 s s s s u_pollingstate .req x x x x x x x x slot 0 x x x x x x x x poll address x x x x x x x x source address x x x x x x x x polladdrlow x x x x x x x x poll address x x x x x x x x poll address x x x x x x x x slot count x x x x x x x x pollstate x x x x x x x x slot n x x x x x x x x source address x x x x x x x x polladdrhigh x x x x x x x x source address x x x x x x x x poll address x x x x x x x x slot count x x x x x x x x checksum x x x x x x x x slot 0 x x x x x x x x slot n 1 1 1 1 0 0 0 0 control byte x x x x x x x x source address x x x x x x x x checksum x x x x x x x x source address x x x x x x x x poll address x x x x x x x x poll address x x x x x x x x slot count figure 57. master polling frame service remarks: x = don?t care (in respect with knx standard) ssss = slot number
ncn5121 www. onsemi.com 52 crc?ccitt crc order - 16 bit crc polynom (hex) - 1021 initial value (hex) ? ffff final xor value (hex) ? 0 no reverse on output crc test string ?123456789? is 29b1h crc?ccitt value over a buffer of bytes can be calculated with following code fragment in c, where pbuf is pointer to the start of frame buffer ulength is the frame length in bytes unsigned short calc_crc_ccitt(unsigned char* pbuf, unsigned short ulength) { unsigned short u_crc_ccitt; for (u_crc_ccitt = 0xffff; ulength??; p++) { u_crc_ccitt = get_crc_ccitt(u_crc_ccitt, *p); } return u_crc_ccitt; } unsigned short get_crc_ccitt(unsigned short u_crc_val, unsigned char btval) { u_crc_val = ((unsigned char)(u_crc_val >> 8)) | (u_crc_val << 8); u_crc_val ^= btval; u_crc_val ^= ((unsigned char)(u_crc_val & 0xff)) >> 4; u_crc_val ^= u_crc_val << 12; u_crc_val ^= (u_crc_val & 0xff) << 5; return u_crc_val; }
ncn5121 www. onsemi.com 53 internal device?specific registers in total 4 device-specific register are available: ? watchdog register (0x00) ? analog control register 0 (0x01) ? analog control register 1 (0x02) ? analog status register 0 (0x03) ? revision id register (0x05) watchdog register the watchdog register is located at address 0x00 and can be used to enable the watchdog and set the watchdog time. table 14. watchdog register extwatchdogctrl (extwr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 1 1 1 1 data wden - - - wdt table 15. watchdog register parameters parameter value description info wden 0 disable enables/disables the watchdog p22 1 enable wdt 0000 33 ms defines the watchdog time. the watchdog needs to be re-enabled (wden) within this time or a watchdog event will be triggered. 0001 66 ms 0010 98 ms 0011 131 ms 0100 164 ms 0101 197 ms 0110 229 ms 0111 262 ms 1000 295 ms 1001 328 ms 1010 360 ms 1011 393 ms 1100 426 ms 1101 459 ms 1110 492 ms 1111 524 ms remark: bit 4 ? 6 are reserved. analog control register 0 the analog control register 0 is located at address 0x01 and can be used to disable the v20v and the dc2 regulator, to disable the xclk-pin, to enable the transmit trigger signal and to set the 20 v ldo current limit. table 16. analog control register 0 analog control register 0 (anactrl0) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x01 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 1 1 1 0 1 0 0 data ? v20ven dc2en xclken trigen v20vclimit
ncn5121 www. onsemi.com 54 table 17. analog control register 0 parameters parameter value description info v20ven 0 disable enables/disables the v20v regulator p 19 1 enable dc2en 0 disable enables/disables the dc2 converter p 19 1 enable xclken 0 disable enables/disables the xclk output signal p 19 1 enable trigen 0 disable trig/arxd pin outputs the tx activity monitor signal when enabled. when disabled the trig/arxd pin is tri?state. p 19 1 enable v20vclimit 000 ? 111 adjustment of the v20v current limit as configured by r 6 by i 20v, step per bit p 19 remark: bit 7 is reserved. analog control register 1 the analog control register 1 is located at address 0x02 and can be used to configure the voltage monitors. table 18. analog control register 1 analog control register 1 (anactrl1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 1 1 0 0 0 0 0 data ? v20v_ok_m vdd2_ok_m vfilt_ok_m anaoutctrl - table 19. analog control register 1 parameters parameter value description info v20v_ok_m 0 enable enable to include the voltage monitor output in the saveb calculation. p 19 1 disable vdd2_ok_m 0 enable enable to include the voltage monitor output in the saveb calculation. p 19 1 disable vfilt_ok_m 0 enable enable to include the voltage monitor output in the saveb calculation. p 18 1 disable anaoutctr l 000 disable analog output is disabled p 23 001 enable analog output monitors vbus1 010 enable analog output monitors vfilt 011 enable analog output monitors v20v 100 enable analog output monitors vdd2 101 enable analog output monitors vdda 110 enable analog output monitors bus current 111 enable analog output monitors temperature remark: bit 0 and bit 7 are reserved.
ncn5121 www. onsemi.com 55 analog status register the analog status register is located at address 0x03 and can be used to verify the voltage monitors, xtal and thermal status. table 20. analog status register analog status register (anastat) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x03 access r r r r r r r r reset 0 0 0 0 0 0 0 0 data ? v20v vdd2 vbus vfilt xtal tw tsd table 21. analog status register parameters parameter value value description info v20v 0 nok ?1? if voltage on v20v-pin is above the v20v undervoltage level p 19 1 ok vdd2 0 nok ?1? if voltage on vdd2-pin is above the vdd2 undervoltage level p 19 1 ok vbus 0 nok ?1? if bus voltage is above the vbus undervoltage level p 18 1 ok vfilt 0 nok ?1? if voltage on vfilt-pin is above the vfilt undervoltage level p 18 1 ok xtal 0 nok ?1? if xtal is up and running p 19 1 ok tw 0 no tw ?1? if thermal warning detected p 22 1 tw tsd 0 no tsd contains information about the previous thermal shutdown situation 1 tsd remark: bit 7 is reserved. revision id register the revision id register is located at address 0x05 and can be read out to check the revision id of the silicon and by the firmwire of the host controller to determine the part number of the transceiver table 22. revision id register revision id register (revid) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x05 access r r r r r r r r reset x x x 0 1 1 0 1 data revision part number table 23. revision id register parameters parameter value value description info revision silicon revision id part number 01101 ncn5121 transceiver part number
ncn5121 www. onsemi.com 56 package thermal characteristics the ncn5121 is available in a qfn40 package. for cooling optimizations, the qfn40 has an exposed thermal pad which has to be soldered to the pcb ground plane. the ground plane needs thermal vias to conduct the heat to the bottom layer. figure 58 gives an example of good heat transfer. the exposed thermal pad is soldered directly on the top ground layer (left picture of figure 58). it?s advised to make the top ground layer as large as possible (see arrows figure 58). to improve the heat transfer even more, the exposed thermal pad is connected to a bottom ground layer by using thermal vias (see right picture of figure 58). it?s advised to make this bottom ground layer as large as possible and with as less as possible interruptions. for precise thermal cooling calculations the major thermal resistances of the device are given (t able 4). the thermal media to which the power of the devices has to be given are: ? static environmental air (via the case) ? pcb board copper area (via the exposed pad) the major thermal resistances of the device are the rth from the junction to the ambient (rth ja ) and the overall rth from the junction to exposed pad (rth jp ). in table 4 one can find the values for the rth ja and rth jp , simulated according to jesd?51. the rth ja for 2s2p is simulated conform jedec jesd?51 as follows: ? a 4?layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used ? board thickness is 1.46 mm (fr4 pcb material) ? the 2 signal layers: 70 m thick copper with an area of 5500 mm 2 copper and 20% conductivity ? the 2 power internal planes: 36 m thick copper with an area of 5500 mm 2 copper and 90% conductivity the rth ja for 1s0p is simulated conform to jedec jesd?51 as follows: ? a 1?layer printed circuit board with only 1 layer ? board thickness is 1.46 mm (fr4 pcb material) ? the layer has a thickness of 70 m copper with an area of 5500 mm 2 copper and 20% conductivity figure 58. pcb ground plane layout condition (left picture displays the top ground layer, right picture displays the bottom ground layer) ordering information device number temperature range package shipping ? NCN5121MNG ?40 c to 105 c qfn?40 (pb?free) 50 units / tube 100 tubes / box ncn5121mntwg ?40 c to 105 c qfn?40 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncn5121 www. onsemi.com 57 package dimensions qfn40 6x6, 0.5p case 485au issue o seating note 4 k 0.15 c (a3) a a1 d2 b 1 11 20 21 40 e2 40x 10 30 l bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 31 e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 6.00 bsc d2 3.10 3.30 e 6.00 bsc 3.30 e2 3.10 e 0.50 bsc l 0.30 0.50 k plane dimensions: millimeters 0.50 pitch 3.32 0.28 3.32 40x 0.63 40x 6.30 6.30 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1 l1 detail a l optional constructions l 0.20 min l1 ??? 0.15 a 0.10 b c a 0.10 b c package outline on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncn5121/d knx and the knx logos are trademarks of knx association. literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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