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? semiconductor components industries, llc, 2014 february, 2014 ? rev. 2 1 publication order number: ncp6360/d ncp6360 mini buck converter for rf power amplifiers the ncp6360, a pwm synchronous step ? down dc ? to ? dc converter, is optimized for supplying rf power amplifiers (pas) used into 3g/4g wireless systems (mobile/ smart phones, phablets, tablets, ...) powered by single ? cell lithium ? ion batteries. the device is able to deliver up to 800 ma. the output voltage is monitorable from 0.6 v to 3.4 v by an analog control pin vcon. the analog control allows dynamically optimizing the rf power amplifier?s efficiency during a communication while for example in roaming situation with as a benefit an increased talk time. also at light load for optimizing the dc ? to ? dc converter efficiency, the ncp6360 enters automatically in a pfm mode and operates in a slower switching frequency corresponding to a reduced quiescent current in regards to the pwm mode for which the device operates at a switching frequency of 6 mhz. synchronous rectification offers improved system efficiency. the ncp6360 is available in a space saving, low profile 1.5 x 1.0 mm csp ? 6 package. features ? input voltage from 2.7 v to 5.5 v for battery powered applications ? adjustable output voltage (0.6 v to 3.4 v) ? 6 mhz switching frequency ? uses 470 nh inductor and 4.7 f capacitor for optimized footprint and solution thickness ? pfm /pwm automatic mode change for high efficiency ? low 30 a quiescent current ? thermal protections to avoid damage of the ic ? small 1.5 x 1.0 mm / 0.5 mm pitch csp package ? this is a pb ? free device typical applications ? 3g / 4g wireless systems, smart phones, phablets and webtablets figure 1. ncp6360 block diagram ncp6360 enabling thermal protection rev 0.00 vout control dcdc buck 1.0 a 6.0 mhz voltage control from external dac vcon en processor or system supply fb pvin sw pgnd vbat (battery or system supply) 10 f 0.47 h dcdc out 4.7 f wlcsp6, 1.00x1.50 case 568an marking diagram http://onsemi.com (note: microdot may be in either location) see detailed ordering, marking and shipping information on page 16 of this data sheet. ordering information a = assembly location y = year w = work week = pb ? free package 60 ayw
ncp6360 http://onsemi.com 2 figure 2. typical application 3g/4g pas rf in antenna switch modem dac gpi/o coupler rf out rf tx power envelop detection vbat voltage control from external dac battery or system supply 10 uf 0.47 uh 4.7 uf dcdc out ncp6360 fb pvin sw pgnd enabling thermal protection en vcon vout control dcdc buck 1.0 a 6.0 mhz figure 3. pin out (top view) 1.0 mm 1.5 mm a2 b2 a1 b1 c1 c2 en pvin vcon sw fb pgnd
ncp6360 http://onsemi.com 3 pin function description pin name type description a1 en input enable control. active high will enable the part. there is an internal pull down resistor on this pin. a2 pv in power input dc ? dc power supply. this pin must be decoupled to ground by a 10 f and 1 f ceramic capacitors. these capacitors should be placed as close as possible to this pin. b1 vcon input voltage control analog input. this pin controls the output voltage. it must be shielded to protect against noise. v out = 2.5 x vcon b2 sw power output dc ? dc switch power. this pin connects the power transistors to one end of the inductor. typical application (6 mhz) uses 0.470 h inductor; refer to application section for more information. c1 fb power input dc ? dc feedback voltage. must be connected to the output capacitor positive terminal. this is the input of the error amplifier. c2 pgnd ground dc ? dc power ground. this pin is the power ground and carries high switching current. high quality ground must be provided to prevent noise spikes. to avoid high ? density current flow in a limited pcb track, a local ground plane that connects all power grounds together is recommended. maximum ratings rating symbol value unit analog and power pins: pv in , sw, fb v a ? 0.3 to + 7.0 v vcon pin v vcon ? 0.3 to + v a + 0.3 +7.0 v digital pin: en: input voltage (note 3) input current v dg i dg ? 0.3 to v a +0.3 7.0 10 v ma operating ambient temperature range t a ? 40 to +85 c operating junction temperature range (note 1) t j ? 40 to +125 c storage temperature range t stg ? 65 to + 150 c maximum junction temperature t jmax ? 40 to +150 c thermal resistance junction ? to ? ambient (note 2) r ja 85 c/w electrostatic discharge (esd) protection, human body model (note 3) charged device model hbm cdm 2.0 1.5 kv moisture sensitivity (note 4) msl level 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the thermal shutdown set to 165 c (typical) avoids potential irreversible damage on the device due to power dissipation. 2. the junction ? to ? ambient thermal resistance is a function of printed circuit board (pcb) layout and application. this data is measured using 4 ? layer pcbs (2s2p). for a given ambient temperature t a it has to be pay attention to not exceed the max junction temperature t jmax . 3. human body model per jesd22 ? a114, charge device model per jesd22 ? c101. 4. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020a.
ncp6360 http://onsemi.com 4 operating conditions symbol parameter conditions min typ max unit pv in power supply (note 5) 2.7 5.5 v l inductor for dcdc converter (note 6) f = 6 mhz 0.47 h co output capacitor for dcdc converter (note 6) f = 6 mhz, l = 0.47 h 4.7 ? 33 f co output capacitor for dcdc converter (note 6) f = 6 mhz, l = 0.33 h 33 ? 220 f cin input capacitor for dcdc converter (note 6) 4.7 10 f functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 5. operation above 5.5 v input voltage for extended period may affect device reliability. 6. including de ? ratings (refer to application information section of this document for further details) electrical characteristics min and max limits apply for t j up to +125 c unless otherwise specified. pv in = 3.6 v (unless otherwise noted). typical values are referenced to t a = + 25 c and default configuration symbol parameter conditions min typ max unit supply current: pin pv in i q operating quiescent current dcdc on ? no load ? no switching, en = high t a = up to +85 c pvin = 2.7 v to 5.5 v 30 50 a i sleep product sleep mode current pv in = 5.5 v v con < 0.1 v, en = high t a = up to +85 c 25 60 a i off product off current en = low pv in = 4.6 v t a = up to +85 c 0.7 2.0 a dcdc converter pv in input voltage range (note 7) 2.7 5.5 v v out_min minimum output voltage (note 8) v con = 0.24 v 0.55 0.6 0.65 v v out_max maximum output voltage (note 8) v con = 1.36 v 3.30 3.4 3.50 v gain v con to v out gain (note 10) 2.5 v/v v out_acc v out accuracy (note 10) ideal = 2.5 x v con ? 50 ? 3 +50 +3 mv % f sw switching frequency (note 9) 5.4 6.0 6.6 mhz r onhs p ? channel mosfet on resistance from pv in to sw 168 m r onls n ? channel mosfet on resistance from sw1 to pgnd 78 m i pkhs peak inductor current pmos 1.5 a dc max maximum duty cycle (note 10) 100 % efficiency (note 10) pv in = 3.6 v, v out = 0.8 v i out = 10 ma, pfm mode pv in = 3.6 v, v out = 1.8 v i out = 300 ma, pwm mode pv in = 3.9 v, v out = 3.3 v i out = 300 ma, pwm mode 82 90 94 % % % product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 7. operation above 5.5 v input voltage for extended periods may affect device reliability. 8. device tested under closed-loop conditions at pvin = 4.0 v with vout_min and vout_max in line with vout accuracy specification. 9. tested at 6 mhz / 48. 10. guaranteed by design and characterized.
ncp6360 http://onsemi.com 5 electrical characteristics min and max limits apply for t j up to +125 c unless otherwise specified. pv in = 3.6 v (unless otherwise noted). typical values are referenced to t a = + 25 c and default configuration symbol unit max typ min conditions parameter dcdc converter line tr line transient response (note 10) pv in = 3.6 v to 4.2 v i out = 100 ma, v out = 0.8 v t r = t f = 10 s 50 mv pk load tr load transient response (note 10) pv in = 3.1 v / 3.6 v / 4.5 v i out = 50 to 150 ma t r = t f = 0.1 s 50 mv pk en v ih positive going input high voltage threshold 1.1 v v il negative going input low voltage threshold 0.4 v total device i outmax pwm mode (note 10) 800 ma t vcon v out step rise time from 0.6 v to 3.4 v to reach 3.26 v (note 10) pv in = 3.6 v, v out = 0.6 v to 3.4 v, c out = 4.7 f, r l = 10 , t r_vcon < 1 s 25 s v out step fall time from 3.4 v to 0.6 v to reach 0.74 v (note 10) pv in = 3.6 v, v out = 3.4 v to 0.6 v, c out = 4.7 f, r l = 10 , t f_vcon < 1 s 25 s t start soft ? start time (time from en trans- itions from low to high to 90% of output voltage) pv in = 4.2 v, c out = 4.7 f, v out = 3.4 v, no load 100 140 s t sp_en sleep mode enter time (note 10) vcon < 75 mv 4.0 s t sp_ex sleep mode exit time (note 10) vcon > 75 mv 5.0 s v uvlo under voltage lockout pv in falling 2.35 2.5 v v uvloh under voltage lockout hysteresis pv in rising ? pv in falling 100 mv t sd thermal shut down protection (note 10) 155 c t sdh thermal shut down hysteresis (note 10) 35 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 7. operation above 5.5 v input voltage for extended periods may affect device reliability. 8. device tested under closed-loop conditions at pvin = 4.0 v with vout_min and vout_max in line with vout accuracy specification. 9. tested at 6 mhz / 48. 10. guaranteed by design and characterized.
ncp6360 http://onsemi.com 6 typical operating characteristics pv in = en = 3.6 v, l = 0.47 h, c out = 4.7 f, c in = 10 f, f sw = 6 mhz, t a = 25 c (unless otherwise noted) tbd figure 4. shutdown current vs input voltage (en = low, vcon = 0 v) figure 5. shutdown current vs temperature (en = low, vcon = 0 v) figure 6. sleep mode current vs input voltage (en = high, vcon = 0 v, v out = 0 v) figure 7. sleep mode current vs. temperature (en = high, vcon = 0 v, v out = 0 v) figure 8. quiescent current vs input voltage (en = high, vcon = 0.8 v, v out = 2 v, no load) figure 9. quiescent current vs temperature (t a ) (en = high, vcon = 0.8 v, v out = 2 v, no load)
ncp6360 http://onsemi.com 7 typical operating characteristics pv in = en = 3.6 v, l = 0.47 h, c out = 4.7 f, c in = 10 f, f sw = 6 mhz, t a = 25 c (unless otherwise noted) figure 10. v out accuracy vs. output current vs. pv in @ 25 c, v out = 0.8 v figure 11. v out accuracy vs. output current vs. temperature pv in = 3.6 v, v out = 0.8 v figure 12. v out accuracy vs. output current vs. pv in @ 25 c, v out = 1.8 v figure 13. v out accuracy vs. output current vs. temperature pv in = 3.6 v, v out = 1.8 v figure 14. v out accuracy vs. output current vs. pv in @ 25 c, v out = 3.3 v figure 15. v out accuracy vs. output current vs. temperature pv in = 4.2 v, v out = 3.3 v
ncp6360 http://onsemi.com 8 typical operating characteristic pv in = en = 3.6 v, l = 0.47 h, c out = 4.7 f, c in = 10 f, f sw = 6 mhz, t a = 25 c (unless otherwise noted) figure 16. nmos r ds(on) vs. pv in figure 17. pmos r ds(on) vs. pv in figure 18. efficiency vs. v out r l = 6 , temp = 25 c figure 19. efficiency vs. v out r l = 10 , temp = 25 c figure 20. efficiency vs. v out r l = 22 , temp = 25 c
ncp6360 http://onsemi.com 9 typical operating characteristics pv in = en = 3.6 v, l = 0.47 h, c out = 4.7 f, c in = 10 f, f sw = 6 mhz, t a = 25 c (unless otherwise noted) figure 21. efficiency vs. output current v out = 0.8 v, temp = 25 c figure 22. efficiency vs. output current v out = 0.8 v, v in = 3.6 v figure 23. efficiency vs. output current v out = 1.8 v, temp = 25 c figure 24. efficiency vs. output current v out = 1.8 v, v in = 3.6 v figure 25. efficiency vs. output current v out = 3.3 v, temp = 25 c figure 26. efficiency vs. output current v out = 3.3 v, v in = 4.2 v
ncp6360 http://onsemi.com 10 typical operating characteristics pv in = en = 3.6 v, l = 0.47 h, c out = 4.7 f, c in = 10 f, f sw = 6 mhz, t a = 25 c (unless otherwise noted) figure 27. 6 mhz, switching frequency vs. temperature (t a ) figure 28. transient, v out vs. vcon, r l = 10 , v out = 0.4 v to 3.6 v, pv in = 3.9 v w/ t r = 7 s, t f = 10 s figure 29. output voltage waveforms in pfm mode i out = 100 ma, pv in = 3.6 v, v out = 2.5 v, c out = 4.7 f figure 30. output voltage waveforms in pfm mode i out = 100 ma, pv in = 3.6 v, v out = 2.5 v, c out = 2 x 4.7 f figure 31. line transient response < 20 mv peak, pv in = 3.6 v to 4.1 v, r l = 8 , v out = 1.8 v figure 32. load transient response w/ v meas < 50 mv peak, i out = 50 to 150 ma, v out = 2.5 v
ncp6360 http://onsemi.com 11 typical operating characteristics pv in = en = 3.6 v, l = 0.47 h, c out = 4.7 f, c in = 10 f, f sw = 6 mhz, t a = 25 c (unless otherwise noted) figure 33. load transient response w/ v meas < 50 mv peak, i out = 10 to 60 ma, v out = 2.5 v figure 34. power ? up transient response pv in = 4.2 v, v out = 3.4 v, r l = 2.5 k figure 35. power ? up transient response pv in = 4.2 v, v out = 3.4 v, r l = 10 figure 36. power ? down transient response pv in = 4.2 v, v out = 3.4 v, r l = 10
ncp6360 http://onsemi.com 12 operating description general description the ncp6360 is a voltage ? mode standalone synchronous step ? down dc ? to ? dc converter designed to supply rf power amplifiers (pas) used into 3g/4g wireless systems (mobile/ smart phones, phablets, tablets, ...) powered by single ? cell lithium ? ion batteries. the ic can deliver up to 800 ma when operating in pwm mode. the buck converter output voltage ranging from 0.6 v to 3.4 v can be monitored by the system?s pa output rf power through the control pin vcon. the control voltage range is from 0.24 v to 1.36 v and vout is equal to 2.5 times this control voltage. vcon allows the pa to have its efficiency dynamically optimized during communication calls in the case for example of roaming situation involving a constant adjustment of the pa output power. the value ? added benefit is an increase of the absolute talk time. synchronous rectification and automatic pfm/pwm operating mode transitions improve overall solution efficiency. the device operates at 6 mhz switching frequency. buck dc ? to ? dc converter operating the converter is a synchronous rectifier type with both high side and low side integrated switches. neither external transistor nor diodes are required for ncp6360 operation. feedback and compensation network are also fully integrated. the device can operate in four different modes: shutdown mode (en = low, device off), sleep mode when vcon below about 0.1 v, pfm mode for efficiency optimization purpose when operating at light load and pwm mode when operating in medium and high loads. the transitions between pwm and pfm modes occur automatically. shutdown mode the ncp6360 enters shutdown mode when setting the en pin low (below 0.4 v) or when pvin drops below its uvlo threshold value (2.35 v typical). in shutdown mode, the internal reference, oscillator and most of the control circuitries are turned off. the typical current consumption is 0.7 a. applying a voltage above 1.1 v to en pin will enable the device for normal operation. a soft ? start sequence is run when activating en high. en pin should be activated after the input voltage is applied. pwm (pulse width modulation) operating mode in medium and high load conditions, the ncp6360 operates in pwm mode from a fixed clock (6 mhz) and adapts its duty cycle to regulate the desired output voltage. in this mode, the inductor current is in ccm (continuous current mode) and the voltage is regulated by pwm. the internal n ? mosfet switch operates as synchronous rectifier and is driven complementary to the p ? mosfet switch. in ccm, the lower switch (n ? mosfet) in a synchronous converter provides a lower voltage drop than the diode in an asynchronous converter, which provides less loss and higher efficiency. pfm (pulse frequency modulation) operating mode in order to save power and improve ef ficiency at low loads the ncp6360 operates in pfm mode as the inductor drops into dcm (discontinuous current mode). the upper fet on time is kept constant and the switching frequency is variable. output voltage is regulated by varying the switching frequency which becomes proportional to loading current. as it does in pwm mode, the internal n ? mosfet operates as synchronous rectifier after each p ? mosfet on ? pulse. when load increases and current in inductor becomes continuous again, the controller automatically turns back to pwm mode. sleep mode the ncp6360 device enters the sleep mode in about 4 s when the control voltage vcon goes below typically 70 mv. vout is extremely low, close to 0 v and in a state out of regulation. in this vout condition the sleep mode enables a low current state (40 a typical range). the buck converter exits the sleep mode and returns in a regulation state when vcon goes above 110 mv after typically 5 s. inductor peak current limitations during normal operation, peak current limitation will monitor and limit the current through the inductor. this current limitation is particularly useful when size and/or height constrain inductor power. the high side switch (hss) peak current limitation is typically 1.5 a, while the low side switch (lss) has a peak current up to 0.8 a. the hss peak current contributes to limit the current during soft start sequence in high load conditions. under ? voltage lockout (uvlo) ncp6360 core does not operate for voltages below the under voltage lock out (uvlo) level. below uvlo threshold (typical 2.35 v), all internal circuitry (both analog and digital) is held in reset. ncp6360 operation is not guaranteed down to vuvlo when battery voltage is dropping off. to avoid erratic on / off behavior,a typical 100 mv hysteresis is implemented. restart is guaranteed at 2.6 v when vbat voltage is recovering or rising. power ? up / power ? down sequencing the en pin controls ncp6360 start up. en pin low to high transition starts the power up sequencer which is combined with a soft start consisting to limit the inrush current at 800 ma while the output voltage is establishing. if en is made low, the dc to dc converter is turned off and device enters shutdown mode. a built ? in pull ? down resistor disables the device when this pin is left unconnected or not driven.
ncp6360 http://onsemi.com 13 wake up time ~ tbd pv in en v out por rising uvlo < 2.6 v soft start 800ma hss ipeak i out figure 37. power ? up sequence in order to power up the circuit, the input voltage pvin has to rise above the uvlo threshold (rising uvlo). this triggers the internal core circuitry power up which is the ?wake up time? (including ?bias time?). this delay is internal and cannot be bypassed. the power down sequence is triggered by setting low the en pin. the output voltage goes down to 0 v. thermal shutdown feature (tsd) the thermal capability of ic can be exceeded due to step down converter output stage power level. a thermal protection circuitry is therefore implemented to prevent the ic from damage. this protection circuitry is only activated when the core is in active mode (output voltage is turned on). during thermal shut down, output voltage is turned off and the device enters sleep mode. thermal shut down threshold is set at 155 c (typical) when the die temperature increases and, in order to avoid erratic on / off behavior, a 35 c hysteresis is implemented. so, after a typical 155 c thermal shut down, the ncp6360 will return to normal operation when the die temperature cools to 120 c. this normal operation depends on the input conditions and configuration at the time the device recovers.
ncp6360 http://onsemi.com 14 application information figure 38. typical application schematic 3g/4g pas rf in antenna switch modem dac gpi/o coupler rf out rf tx power envelop detection vbat voltage control from external dac battery or system supply 10 uf 0.47 uh 4.7 uf dcdc out ncp6360 fb pvin sw pgnd enabling thermal protection en vcon vout control dcdc buck 1.0 a 6.0 mhz output filter design considerations the output filter introduces a double pole in the system at a frequency of: f lc 1 2 l c (eq. 1) the ncp6360 internal compensation network is optimized for a typical output filter comprising a 470 nh inductor and one 4.7 f capacitor as described in the basic application schematic figure 38. inductor selection the inductance of the inductor is determined by given peak ? to ? peak ripple current i lpp of approximately 20% to 50% of the maximum output current i outmax for a trade ? off between transient response and output ripple. the selected inductor must have high enough saturation current rating to be higher than the maximum peak current that is: i lmax i outmax i lpp 2 (eq. 2) the inductor also needs to have high enough current rating based on temperature rise concern. low dcr is good for efficiency improvement and temperature rise reduction. tables 1 shows recommended inductor references. table 1. recommended inductors when operating at 6 mhz supplier part# value ( h) size (l x l x t) (mm) dc rated current (a) dcr max @ 25 c (m ) tdk tfm201610a ? r47m ? t00 0.47 20x16x1 3.5 46 tdk tfm201210a ? r47m ? t00 0.47 20x12x1 2.5 65 toko dfe201610r ? r47m ? t00 0.47 20x16x1 3.8 48 toko dfe201610a ? r47m ? t00 0.47 20x16x1 3.7 58
ncp6360 http://onsemi.com 15 output capacitor selection the output capacitor selection is determined by output voltage ripple and load transient response requirement. for high transient load performance high output capacitor value must be used. for a given peak ? to ? peak ripple current i lpp in the inductor of the output filter, the output voltage ripple across the output capacitor is the sum of three components as below. v outpp v outpp(c) v outpp(esr) v outpp(esl) (eq. 3) where v outpp(c) is the ripple component coming from an equivalent total capacitance of the output capacitors, v outpp(esr) is a ripple component from an equivalent esr of the output capacitors, and v outpp(esl ) is a ripple component from an equivalent esl of the output capacitors. in pwm operation mode, the three ripple components can be obtained by v outpp(c) i l_pp 8 c f sw (eq. 4) v outpp(esr) i lpp esr (eq. 5) v out_pp(esl) esl esl l v in (eq. 6) and the peak ? to ? peak ripple current is: i lpp pv in v out v out pv in f sw l (eq. 7) in applications with all ceramic output capacitors, the main ripple component of the output ripple is v outpp (c). so that the minimum output capacitance can be calculated regarding to a given output ripple requirement v outpp in pwm operation mode. c min i lpp 8 v outpp f sw (eq. 8) input capacitor selection one of the input capacitor selection guides is the input voltage ripple requirement. to minimize the input voltage ripple and get better decoupling in the input power supply rail, ceramic capacitor is recommended due to low esr and esl. the minimum input capacitance regarding the input ripple voltage v inpp is c inmin i outmax d d 2 v inpp f sw (eq. 9) where d v out v in (eq. 10) in addition the input capacitor needs to be able to absorb the input current, which has a rms value of: i inrms i outmax d d 2 (eq. 11) the input capacitor needs also to be sufficient to protect the device from over voltage spike and a minimum of 4.7 f capacitor is required. the input capacitor should be located as close as possible to the ic. pgnd is connected to the ground terminal of the input cap which then connects to the ground plane. the pv in is connected to the v bat terminal of the input capacitor which then connects to the v bat plane. layout and pcb design recommendations good pcb layout helps high power dissipation from a small package with reduced temperature rise. thermal layout guidelines are: ? a four or more layers pcb board with solid ground planes is preferred for better heat dissipation. ? more free vias are welcome to be around ic to connect the inner ground layers to reduce thermal impedance. ? use large area copper especially in top layer to help thermal conduction and radiation. ? use two layers for the high current paths (pvin, pgnd, sw) in order to split current in two different paths and limit pcb copper self heating. (see demo board example figure 40)
ncp6360 http://onsemi.com 16 figure 39. layout minimum recommended occupied space using 0402 capacitors and 0805 (2.0 x1.2 x1 mm) inductor 0402 1.5 x 0.9 mm 3.60 mm 2.80 mm s < 10.1 mm 0402 tfm201210 2.0 x 1.2 mm pvin sw en vcon fb pgnd 1.5 x 0.9 mm input capacitor placed as close as possible to the ic. ? pv in directly connected to cin input capacitor, and then connected to the vin plane. local mini planes used on the top layer (green) and layer just below top layer with laser vias. ? pgnd directly connected to cin input capacitor, and then connected to the gnd plane: local mini planes used on the top layer (green) and layer just below top layer with laser vias. ? sw connected to the lout inductor with local mini planes used on the top layer (green) and layer just below top layer with laser vias. figure 40. example of pcb implementation (pcb case with 0805 (2.0x1.2 mm) capacitors and 2016 (2.0 x 1.6 x 1 mm) inductors ordering information device package shipping ? NCP6360FCCT2G wlcsp6 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp6360 http://onsemi.com 17 package dimensions wlcsp6, 1.00x1.50 case 567an issue a seating plane 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max 0.54 millimeters a1 d 1.00 bsc e b 0.315 0.335 e 0.50 bsc 0.63 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 6x b 123 c b a 0.05 c a a1 a2 c 0.21 0.26 1.50 bsc 0.50 0.25 6x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.05 c 2x top view side view bottom view note 3 e a2 0.36 ref recommended a1 package outline pitch 0.50 pitch a3 detail a die coat detail a a2 a3 0.02 ref on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp6360/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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