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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9803 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 ccd signal processor for electronic cameras functional block diagram pga 0C30db 0C10db pga clamp 3 ref 10-bit dac intf ad9803 10 pblk pgacont1-2 clpob 3-w intf adcin auxin aclp shp shd adcclk dout auxcont vrt vrb ccdin dac1 dac2 clpdm timing generator mux s/h clamp cds clamp adc 8-bit dac 8-bit dac features 3-wire serial i/f for digital control 18 mhz correlated double sampler low noise pga with 0 dbC30 db range analog pre-blanking function aux input with input clamp and pga 10-bit 18 msps a/d converter direct adc input with input clamp internal voltage reference two auxiliary 8-bit dacs +3 v single supply operation low power: 150 mw at 2.7 v supply 48-lead lqfp package product description the ad9803 is a complete ccd and video signal processor developed for electronic cameras. it is well suited for video camera and still-camera applications. the 18 mhz ccd signal processing chain consists of a cds, low noise pga, and 10-bit adc. required clamping circuitry and a voltage reference are also provided. the aux input features a wideband pga and input clamp, and can be used to sample analog video signals. the ad9803 nominally operates from a single 3 v power sup- ply, typically dissipating 170 mw. the ad9803 is packaged in a space-saving 48-lead lqfp and is specified over an operating temperature range of C20 c to +70 c.
rev. 0 ad9803Cspecifications C2C general specifications parameter min typ max units temperature range operating C20 70 c storage C65 150 c power supply voltage (for functional operation) analog 2.7 3.0 3.6 v digital 2.7 3.0 3.6 v digital driver 2.7 3.0 3.6 v power consumption (power-down modes selected through serial i/f) normal operation (d-reg 00) (specified under each mode of operation) high speed aux-mode (d-reg 01) (specified under aux-mode) reference standby (d-reg 10 or stby pin hi) 10 mw shutdown mode (d-reg 11) 10 mw maximum clock rate (specified under each mode of operation) s/h amplifier gain 0db clock rate 27 mhz a/d converter resolution 10 bits differential nonlinearity 0C255 code 0.5 0.8 lsbs 256C1023 code 0.5 1.0 lsbs no missing codes guaranteed full-scale input range 1.0 v p-p clock rate 0.01 18 mhz reference reference top voltage 1.75 v reference bottom voltage 1.25 v specifications subject to change without notice. digital specifications parameter symbol min typ max units logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 m a low level input current i il 10 m a input capacitance c in 10 pf logic outputs high level output voltage v oh 2.1 v low level output voltage v ol 0.6 v high level output current i oh 50 m a low level output current i ol 50 m a serial interface timing (figure 35) maximum sclk frequency 10 mhz sdata to sclk setup t ds 10 ns sclk to sdata hold t dh 10 ns sload to sclk setup t ls 10 ns sclk to sload hold t lh 10 ns specifications subject to change without notice. (t min to t max , acvdd = advdd = dvdd = +2.8 v, f adcclk = 18 mhz unless otherwise noted) (t min to t max , drvdd = +2.7 v, c l = 20 pf unless otherwise noted)
C3C rev. 0 ad9803 ccd-mode specifications p arameter min typ max units power consumption v dd = 2.7 150 mw v dd = 2.8 170 mw v dd = 3.0 185 mw maximum clock rate 18 mhz cds gain 0db allowable ccd reset transient 1 500 mv max input range before saturation 1 1000 mv p-p pga max input range 1000 mv p-p max output range 1000 mv p-p digital gain control (see figure 26) gain control resolution 10 (fixed) bits minimum gain (code 0) C3.5 C1.5 0 db low gain (code 207) 0 4 8 db medium gain (code 437) 15 db high gain (code 688) 22 26 30 db max gain (code 1023) 32 db analog gain control (see figure 25) pgacont1 = 0.7 v, pgacont2 = 1.5 v 4.5 db pgacont1 = 1.8 v, pgacont2 = 1.5 v 26 db black-level clamp clamp level (selected by the serial i/f) clp(0) (e-reg 00) 34 lsb clp(1) (e-reg 01) 50 lsb clp(2) (e-reg 10) 66 lsb clp(3) (e-reg 11) 18 lsb even-odd offset 2 0.5 lsb signal-to-noise ratio 3 (@ minimum pga gain) 61 db timing specifications 4 pipeline delay even-odd offset correction disabled 5 cycles even-odd offset correction enabled 7 cycles internal clock delay 5 (t id )3ns inhibited clock period (t inhibit )15 ns output delay (t od ) 20 ns output hold time (t hold )2 ns adcclk, shp, shd, clock period 47 55.6 ns adcclk hi-level, or low level 20 28 ns shp, shd minimum pulsewidth 6 10 14 ns shp rising edge to shd rising edge 20 28 ns notes 1 input signal characteristics defined as shown: 6 50mv max optical black pixel 500mv typ reset transient 1v max input signal range 2v max input signal w/pblk enabled 2 even-odd offset is described under the theory of operation section. the even-odd offset is measured with the even-off offset co rrection enabled. 3 snr = 20 log 10 (full-scale voltage/rms output noise). 4 20 pf loading; timing shown in figure 1. 5 internal aperture delay for actual sampling edge. 6 active low clock pulse mode (c-reg 00). specifications subject to change without notice. (t min to t max , acvdd = advdd = dvdd = +2.8 v, f shp = f shd = f adcclk = 18 mhz unless otherwise noted)
rev. 0 ad9803Cspecifications C4C aux-mode specifications parameter min typ max units power consumption normal (d-reg 00) 80 mw high speed (d-reg 01) 110 mw maximum clock rate 18 mhz pga max input range 700 mv p-p max output range 1000 mv p-p digital gain control gain control resolution 8 (fixed) bits gain (selected by the serial i/f) gain(0) C3.5 db gain(255) 10.5 db active clamp (clamp on) clamp level (selectable by the serial i/f) clp(0) (e-reg 00) 34 lsb clp(1) (e-reg 01) 50 lsb clp(2) (e-reg 10) 66 lsb clp(3) (e-reg 11) 18 lsb timing specifications 1 pipeline delay 4 (fixed) cycles internal clock delay (t id ) 5ns output delay (t od ) 20 ns output hold time (t hold )2 ns notes 1 20 pf loading; timing shown in figure 2. specifications subject to change without notice. adc-mode specifications parameter min typ max units power consumption (normal d-reg 00) 65 mw maximum clock rate 18 mhz active clamp (same as aux-mode) timing specifications (same as aux-mode) specifications subject to change without notice. dac specifications (dac1 and dac2) parameter min typ max units resolution 8 (fixed) bits min output 0.1 v max output vdd C 0.1 v max current load 1 ma max capacitive load 500 pf specifications subject to change without notice. (t min to t max , acvdd = advdd = dvdd = +2.8 v, f adcclk = 18 mhz unless otherwise noted) (t min to t max , acvdd = advdd = dvdd = +2.8 v, f adcclk = 18 mhz unless otherwise noted)
ad9803 C5C rev. 0 timing specifications n n+1 n+2 n+3 n+4 t inhibit t id t id t od t h old adcclk rising edge placement nC8 nC7 nC6 nC5 nC4 nC3 ccd shp shd adcclk d0Cd9 notes: 1. shp and shd should be optimally aligned with the ccd signal. samples are taken at the rising edges. 2. adcclk rising edge must occur at least 15ns after the rising edge of shp ( t inhibit ). 3. recommended placement for adcclk rising edge is between the rising edge of shd and falling edge of shp. 4. output latency (7 cycles) shown with even-odd offset correction enabled. 5. active low clock pulse mode is shown. figure 1. ccd-mode timing t id t od t hold n n+1 n+2 n+3 n+4 nC4 nC3 nC2 n+5 video input adcclk d0Cd9 nC1 n note: example of output data latched by adcclk rising edge. figure 2. aux-mode and adc-mode timing ccd signal clpob clpdm pblk effective pixels optical black blanking interval dummy black effective pixels notes: 1. clpob pulsewidth should be a minimum of 10 ob pixels wide, 20 ob pixels are recommended. 2. clpdm pulsewidth should be at least 1 m s wide. 3. pblk is not required, but recommended if the ccd signal amplitude exceeds 1v p-p. 4. clpdm overwrites pblk. 5. active low clamp pulse mode is shown. figure 3. ccd-mode clamp timing
ad9803 C6C rev. 0 ordering guide model temperature range package description package option ad9803jst 0 c to +70 c 48-lead plastic thin quad flatpack st-48 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9803 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device timing specifications (continued) h sync manual clamping automatic clamping video signal aclp figure 4. aux-mode clamp timing note: aclp can be used two different ways. to control the exact time of the clamp, an active low pulse is used to specify the clamp interval. alternatively, aclp may be tied to ground. in this configuration, the clamp circuitry will sense the most negative portion of the signal and use this level to set the clamp voltage. for the video waveform in figure 4, the sync level will be clamped to the black level specified in the e-register. active low clamp pulse mode is shown. absolute maximum ratings* parameter with respect to min max units advdd advss, subst C0.3 6.5 v acvdd acvss, subst C0.3 6.5 v dvdd dvss C0.3 6.5 v drvdd drvss C0.3 6.5 v clock inputs dvss C0.3 dvdd + 0.3 v pgacont1, pgacont2 subst C0.3 acvdd + 0.3 v pin, din subst C0.3 acvdd + 0.3 v dout drvss C0.3 drvdd + 0.3 v vrt, vrb subst C0.3 advdd + 0.3 v ccdbyp1, ccdbyp2 subst C0.3 acvdd + 0.3 v dac1, dac2 subst C0.3 acvdd + 0.3 v drvss, dvss, acvss, advss subst C0.3 +0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly; functional operation of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. exposure t o absolute maximum ratings for extended periods may affect device reliability.
ad9803 C7C rev. 0 pin function descriptions p in # pin name type description (see figures 37 and 38 for circuit configurations) 1, 24 nc no connect (should be left floating or tied to ground) 2C11 d0Cd9 do digital data outputs 12 drvdd p digital driver supply (3 v) 13 drvss p digital driver ground 14 dvss p digital ground 15 aclp p aux-mode/adc-mode clamp 16 adcclk di adc sample clock input 17 dvdd p digital supply (3 v) 18 stby di power-down mode (active hi/internal pull-down). enables reference stand-by mode. 19 pblk di pixel blanking 20 clpob di black level restore clamp 21 shp di ccd reference sample clock input 22 shd di ccd data sample clock input 23 clpdm di input clamp 25 ccdbyp2 ao cds ground bypass (0.1 m f to ground) 26 din ai cds negative input (tie to pin 27 and ac-couple to ccd input signal) 27 pin ai cds positive input (see above) 28 ccdbyp1 ao cds ground bypass (0.1 m f to ground) 29 pgacont1 ai pga coarse gain analog control 30 pgacont2 ai pga fine gain analog control 31 acvss p analog ground 32 clpbyp ao bias bypass (0.1 m f to ground) 33 acvdd p analog supply (3 v) 34 auxin ai aux-mode input 35 auxcont ai aux-mode pga gain analog control 36 adcin ai adc-mode input 37 cmlevel ao common-mode level (0.1 m f to ground) 38 vtrbyp ao bias bypass (0.1 m f to ground) 39 dac1 ao dac1 output 40 dac2 ao dac2 output 41 sl di serial i/f load signal 42 sck di serial i/f clock 43 advdd p analog supply (3 v) 44 sdata di serial i/f input data 45 advss p analog ground 46 subst p analog ground 47 vrb ao bottom reference (0.1 m f to ground and 1 m f to vrt) 48 vrt ao top reference (0.1 m f to ground) note type: ai = analog input, ao = analog output, di = digital input, do = digital output, p = power. pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) dvdd dvss aclp adcclk stby nc (lsb) d0 d1 d2 d3 d4 d5 d6 d7 d8 (msb) d9 drvdd pblk clpob shp shd ad9803 nc adcin auxcont auxin acvdd clpbyp acvss pgacont2 pgacont1 ccdbyp1 pin din ccdbyp2 vrt vrb subst advss sdata advdd sck sl dac2 dac1 vtrbyp cmlevel clpdm drvss nc = no connect
ad9803 C8C rev. 0 equivalent input circuits dvdd drvdd dvss drvss figure 5. pins 2C11 (d0Cd9) dvdd dvss 200 v dvss figure 6. pin 16, 21, 22 (adcclk, shp, shd) acvdd subst acvss 50 v figure 7. pins 25, 28 (ccdbyp) acvdd subst acvss 50 v 10pf figure 8. pin 26 (din) and pin 27 (pin) acvdd subst pgacont1 1k v cmlevel 8k v 8k v 10k v pgacont2 open C analog control closed C digital control figure 9. pin 29 (pgacont1) and pin 30 (pgacont2) acvdd subst acvss 10k v 30k v 200 v figure 10. pin 32 (clpbyp)
ad9803 C9C rev. 0 acvdd subst acvss 50 v 50 v figure 11. pin 34 (auxin) and pin 36 (adcin) acvdd subst cmlevel 5.5k v open C analog control closed C digital control figure 12. pin 35 (auxcont) advdd advss 9.3k v figure 13. pin 37 (cmlevel) advdd internal dac out advss 39k v 39k v 1.4pf 70 v dac1, dac2 output figure 14. pin 39 (dac1) and 40 (dac2) dvdd drvdd dvss drvss data in sdata data out rnw figure 15. pin 44 (sdata) advdd subst advss 3k v 200 v 1.1k v figure 16. pin 47 (vrb) and pin 48 (vrt)
ad9803 C10C rev. 0 Ctypical performance characteristics sample rate C mhz 240 4 power dissipation C mv 220 200 180 160 140 120 6 8 10 12 14 16 18 v dd = 3.3v v dd = 3.0v v dd = 2.8v figure 17. ccd-mode power vs. clock rate title title 0.6 0 0.4 0.2 0.0 C0.2 C0.4 C0.6 150 300 450 600 750 900 1023 figure 18. ccd-mode dnl at 18 mhz 0 4 2 0 C2 C4 C6 150 300 450 600 750 900 1023 C8 figure 19. ccd-mode inl at 18 mhz digital output code C decimal 800000 29 number of hits 700000 600000 500000 400000 300000 200000 100000 0 30 31 32 33 34 35 36 37 38 39 s = 0.8 lsb figure 20. ccd-mode grounded-input noise (pga gain = min) frequency C mhz 60 dc db 123456789 50 40 30 20 10 0 C10 C20 C30 C40 C50 C60 5th 4th 2nd 3rd fund thd = C38.7db figure 21. aux-mode thd at 18 mhz (f in = 3.54 mhz at C3 db) frequency C mhz 60 dc db 123456789 50 40 30 20 10 0 C10 C20 C30 C40 C50 C60 2nd 3rd fund thd = C54.1db 4th 5th figure 22. adc-mode at 18 mhz (f in = 3.54 mhz at C3 db)
ad9803 C11C rev. 0 theory of operation introduction the ad9803 is a 10-bit analog-to-digital interface for ccd cameras. the block level diagram of the system is shown in figure 23. the device includes a correlated double sampler (cds), 0 dbC30 db programmable gain amplifier (pga), black level correction loop, input clamp and voltage reference. the only external analog circuitry required at the system level is an emitter follower buffer between the ccd output and ad9803 inputs. clpdm input clamp pin din cds sha adc integ black level clamp pga differential signal path clpob figure 23. ccd mode signal path correlated double sampling (cds) cds is important in high performance ccd systems as a method for removing several types of noise. basically, two samples of the ccd output are taken: one with the signal present (data) and one without (reference). subtracting these two samples removes any noise which is commonor correlatedto both. figure 24 shows the block diagram of the ad9803s cds. the s/h blocks are directly driven by the input and the sampling function is performed passively, without the use of amplifiers. this implementation relies on the off-chip emitter follower buffer to drive the two 10 pf sampling capacitors. only one capacitor at a time is seen at the input pin. 10pf q1 s/h q2 s/h s out from ccd figure 24. cds block diagram the ad9803 actually uses two cds circuits in a ping pong fashion to allow the system more acquisition time. in this way, the output from one of the two cds blocks will be valid for an entire clock cycle. thus, the bandwidth requirement of the subsequent gain stage is reduced as compared to that for a single- channel cds system. this lower bandwidth translates to lower power and noise. programmable gain amplifier (pga) the on-chip pga provides a gain range of 0 dbC30 db, which is linear in db. typical gain characteristics are shown in figures 25 and 26. 40 gain C db pgacont1 C volts 0 35 30 25 20 15 10 5 0 C5 0.5 1.0 1.5 2.0 2.5 3.0 figure 25. pga gain curveanalog control 40 gain C db pga gain register 0 35 30 25 20 15 10 5 0 C5 1023 171 341 511 682 852 figure 26. pga gain curvedigital control as shown in figure 27, analog pga control is provided through the pgacont1 and pgacont2 inputs. pgacont1 pro- vides coarse and pgacont2 fine (1/16) gain control. the pga gain can also be controlled using the internal 10-bit dac through the serial digital interface. the gain characteristic shown in figure 26, with the internal dac providing the same control range as pgacont1. see the serial interface specifi- cations for more details. a pgacont1 pgacont2 pgacont1 = coarse control pgacont2 = fine (1/16) control figure 27. analog pga control
ad9803 C12C rev. 0 black level clamping for correct signal processing, the ccd signal must be refer- enced to a well established black level. the ad9803 uses the ccds optical black (ob) pixels as a calibration signal, which is used to establish the black level. two sources of offset are addressed during the calibrationthe ccds own black level offset, and the ad9803s internal offsets in the cds and pga circuitry. the feedback loop shown in figure 28 is closed around the pga during the calibration interval (clpob = low) to set the black level. as the black pixels are being processed, an inte- grator block measures the difference between the input level and the desired reference level. this difference, or error, signal is amplified and passed to the cds block where it is added to the incoming pixel data. as a result of this process, the black pixels are digitized at one end of the adc range, taking maxi- mum advantage of the available linear range of the system. using the ad9803s serial digital interface, the black level reference may programmed to 16 lsb, 32 lsb, 48 lsb, or 64 lsb. pga adc in clpob neg ref integrator cds figure 28. black level correction loop (simplified) the actual implementation of this loop is slightly more compli- cated as shown in figure 29. because there are two separate cds blocks, two black level feedback loops are required and two offset voltages are developed. figure 29 also shows an additional pga block in the feedback loop labeled rpga. the rpga uses the same control inputs as the pga, but has the inverse gain. the rpga functions to attenuate by the same factor as the pga amplifies, keeping the gain and bandwidth of the loop constant. there exists an unavoidable mismatch in the two offset voltages used to correct both cds blocks. this mismatch causes a slight difference in the offset level for odd and even pixels, often called pixel-to-pixel offset or even-odd offset. to compen- sate for this mismatch, the ad9803 uses a digital correction circuit after the adc which removes the even-odd offset be- tween the channels. pga adc in clpob neg ref control cds1 rpga2 int2 cds2 rpga1 int1 figure 29. black level correction loop (detailed) input bias level clamping the buffered ccd output is connected to the ad9803 through an external coupling capacitor. the dc bias point for this cou- pling capacitor is established during the clamping (clpdm = low) period using the dummy clamp loop shown in figure 30. when closed around the cds, this loop establishes the desired dc bias point on the coupling capacitor. black level clp ccd input clamp clpdm to adc pga cds figure 30. input clamp input blanking in some applications, the ad9803s input may be exposed to large signals from the ccd, either during blanking intervals or high speed modes. if the signals are larger than the ad9803s 1 v p-p input signal range, then the on-chip input circuitry may saturate. recovery time from a saturated state could be substantial. to avoid problems associated with processing these large tran- sients, the ad9803 includes an input blanking function. when active (pblk = low) this function stops the cds operation and allows the user to disconnect the cds inputs from the ccd buffer. additionally, the ad9803s digital outputs will all go to zero while pblk is low. if the input voltage exceeds the supply rail by more than 0.3 volts, then protection diodes will be turned on, increasing current flow into the ad9803 (see equivalent input circuits). such voltage levels should be externally clamped to prevent possible device damage. 10-bit analog-to-digital converter (adc) the adc employs a multibit pipelined architecture which is well-suited for high throughput rates while being both area and power efficient. the multistep pipeline presents a low input capacitance resulting in lower on-chip drive requirements. a fully differential implementation was used to overcome head- room constraints of the single +3 v power supply. differential reference the ad9803 includes a 0.5 v reference based on a differential, continuous-time bandgap cell. use of an external bypass capaci- tor reduces the reference drive requirements, thus lowering the power dissipation. the differential architecture was chosen for its ability to reject supply and substrate noise. required decou- pling is shown in figure 31. vrt ref vrb 1 m f 0.1 m f 0.1 m f figure 31. reference decoupling internal timing the ad9803s on-chip timing circuitry generates all clocks necessary for operation of the cds and adc blocks. the user needs only to synchronize the shp and shd clocks with the ccd waveform, as all other timing is handled internally. the adcclk signal is used to strobe the output data, and can be adjusted to accommodate desired timing. figure 1 shows the recommended placement of adcclk relative to shp and shd.
ad9803 C13C rev. 0 even-odd pixel offset correction the ad9803 includes digital correction circuitry following the 10-bit adc. the purpose of the digital correction is remove the residual offset between the even and odd pixel channels, which results from the ping-pong cds architecture of the ad9803. the digital offset correction tracks the black level of the even and odd channels, applying the necessary digital cor- rection value to keep them balanced. there is an additional two cycle delay when using the offset correction, resulting in pipe- line delay of 7 adcclk cycles (see figure 1). a/d converter + even odd 2:1 mux adcclk 10 digital offset correction dout clpob figure 32. digital offset correction auxiliary dacs the ad9803 includes two 8-bit dacs for controlling any off- chip system functions. these are voltage output dacs with near rail-to-rail output capability. output voltage levels are programmed through the serial interface. dac specifications are shown on page 4, and the dac equivalent output circuit is shown in figure 14. aux-mode operation in addition to the ccd signal-processing path, the ad9803 includes an analog video-processing path. the auxin (pin 34) input consists of an input clamp, pga, and adc. figure 33 shows the input configuration of this mode. the recommended value of the external ac-coupling capacitor is 0.1 m f. the volt- age droop with this capacitor value is 20 m v/ m s. the recommended method of controlling the input clamp is to simply ground the aclp input (pin 15) to activate the autom atic clamping capability of the ad9803. the clamp may also be controlled with a separate clock signal. see the clamp timing in figure 4 for more details. the thd performance for f s = 18 mhz is shown in figure 21. when operating at f s = 18 mhz, the linearity performance is comparable to the ccd-mode linearity, shown in figure 18. the aux-mode can be operated at a sampling rate of up to 28.6 mhz. if the sample rate exceeds 18 mhz, then the high speed aux-mode should be programmed through the serial interface (d-register 01). auxin clp aclp pga sha clamp level (e-reg) + C 0.1 m f video signal gnd ad9803 0~10 db adcclk 2 m a adc lpf 34 15 16 aux cont 35 0.1 m f figure 33. aux-mode circuit configuration adc-mode operation the adc-mode of operation is the same as the aux-mode, except there is no pga in the signal path, only the input clamp and adc. input specifications and timing for adc-mode are the same as those for aux-mode. the thd performance is shown in figure 22.
ad9803 C14C rev. 0 serial interface specifications modes2 1 sdata select dac2 dac1 pga modes a0 1 0 1 0 1 a1 1 0 1 1 0 a2 1 1 0 0 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 e0 e1 d0 d1 c0 c1 b0 b1 a0 a1 clamp level power down modes clock modes output modes operation modes f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 pga gain level selection g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7 m0 0 k0 j0 dac1 input dac2 input operation and power down modes shift register f-reg f0Cf9 e-reg e0Ce1 d-reg (d) power down modes d0Cd1 c-reg c0Cc1 b-reg b0Cb1 a-reg (a) operation modes a0Ca1 (b) output modes (c) clock modes (e) clamp level (f) pga gain m-reg m0 k-reg (k) external pga gain control k0 j-reg j0 h-reg h0Ch7 g-reg (g) dac1 input g0Cg7 (h) dac2 input (j) even-odd offset correction (m) dac1 and dac2 power down select note 1 modes2 register bit d1 must be set to zero. figure 34. internal register map rising edge triggered t dh t ls t lh register loaded on rising edge rnw a0 a1 a2 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 sdata sck sl t ds figure 35. serial write operation sdata rnw a0 a1 a2 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 xx xx dummy bits ignored sck sl figure 36. 16-bit serial write operation
ad9803 C15C rev. 0 register description (a) a-register: modes of operation (power-on default value = 11) a1 a0 modes 0 0 adc-mode 0 1 aux-mode 1 0 ccd-mode 1 1 ccd-mode (b) b-register: output modes (default = 00) b1 b0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 normal 0 1 0101010101 1 0 1010101010 1 1 high impedance (c) c-register: clock modes (default = 00) c1 c0 shp-shd clock pulses clamp active pulses 0 0 active low active low 0 1 active low active high 1 0 active high active low 1 1 active high active high (d) d-register: power-down modes (default = 00) modes d1 d0 description normal 0 0 normal operation high speed 0 1 high speed aux-mode power-down 1 1 0 reference stand-by (same mode as stby pin 18) power-down 2 1 1 total shut-down (e) e-register: clamp level selection (default = 00) e1 e0 clamp level clp (0) 0 0 32 lsbs clp (1) 0 1 48 lsbs clp (2) 1 0 64 lsbs clp (3) 1 1 16 lsbs (f) f-register: pga gain selection (default = 00 ...0) f 9 f 8 f 7 f6 f 5 f 4 f 3 f 2 f 1 f 0 ccd-gain gain (0) 0 0 0 0 0 0 0 0 0 0 minimum gain (1023) 1 1 1 1 1 1 1 1 1 1 maximum (f) f-register: pga gain selection (default = 00 ...0) f 9 f8 f 7 f 6 f5 f 4 f 3 f 2 aux-gain gain (0) 0 0 0 0 0 0 0 0 minimum gain (255) 1 1 1 1 1 1 1 1 maximum (g) g-register: dac1 input (default = 00 ...0) g7 g6 g5 g4 g3 g2 g1 g0 dac1 output code (0) 0 0 0 0 0 0 0 0 minimum code (255) 1 1 1 1 1 1 1 1 maximum (h) h-register: dac2 input (default = 00 ...0) h7 h6 h5 h4 h3 h2 h1 h0 dac2 output code (0) 0 0 0 0 0 0 0 0 minimum code (255) 1 1 1 1 1 1 1 1 maximum (j) j-register: even-odd offset correction (default = 0) j0 even-odd offset correction 0 offset correction in use 1 offset correction not used (k) k-register: external pga gain control (default = 0) k0 pga gain control 0 external voltage control through auxcont or pgacont1 and pgacont2 1 internal 10-bit dac control of pga gain (m) m-register: dac1 & dac2 pdn (default = 0) m0 power-down of 8-bit dacs 0 8-bit dacs powered-down 1 8-bit dacs operational
ad9803 C16C rev. 0 note : with the exception of a write to the pga register dur- ing aux-mode, all data writes must be 10 bits. during an aux-mode write to the pga register, only 8 bits of data are required. if more than 14 sck rising edges are applied during a write operation, additional sck pulses will be ignored (see figure 35). all reads must be 10 bits to receive valid register contents. all registers default to 0s on power-up, except for the a-register which defaults to 11. thus, on power-up, the ad9803 defaults to ccd mode. during the power-up phase, it is recom- mended that sl be high and sck be low to prevent acci- dental register write operations. sdata may be unknown. the rnw bit (read/not write) must be low for all write opera- tions to the serial interface, and high when reading back from the serial interface registers. applications information power and grounding recommendations the ad9803 should be treated as an analog component when used in a system. the same power supply and ground plane should be used for all of the pins. in a two-ground system, this requires that the digital supply pins be decoupled to the analog ground plane and the digital ground pins be connected to ana- log ground for best noise performance. separate digital supplies can be used, particularly if slightly different driver supplies are needed, but the digital power pins should still be decoupled to the same point as the digital ground pins (the analog ground plane). if the ad9803 digital outputs need to drive a bus or substantial load, then a buffer should be used at the ad9803s outputs, with the buffer referenced to system digital ground. in some cases, when system digital noise is not substantial, it is acceptable to split the ground pins on the ad9803 to separate analog and digital ground planes. if this is done, be sure to connect the two ground planes together at the ad9803. to further improve performance, isolating the driver supply drvdd from dvdd with a ferrite bead can help reduce kick- back effects during major code transitions. alternatively, the use of damping resistors on the digital outputs will reduce the output rise times, also reducing the kickback effect. application circuit utilizing the ad9803s digital gain control figure 37 shows the recommended circuit configuration for ccd-mode operation when using the 3-wire serial interface. the analog pga control pins, pgacont1 and pgacont2, should be shorted together and decoupled to ground. if the two auxiliary dacs are not used, then pins 39 and 40 (dac1 and dac2) may be grounded. using the ad9803 in ad9801 sockets the ad9803 may be easily used in existing ad9801 designs without any circuit modifications. most of the pin assignments are the same for both ics. table i outlines the differences. the circuit of figure 38 shows the necessary connections for the ad9803 when used in an existing ad9801 socket. the power- on reset in the ad9803 assures that the device will power-up in ccd-mode, with analog pga gain control. table i. ad9801/ad9803 pin differences pin no. ad9801 ad9803 ad9801 connection 1 advss nc ground 14 dsubst dvss ground 15 dvss aclp ground 24 dvss nc ground 32 clamp_bias clpbyp decoupled with 0.1 m f to ground 34 acvdd auxin +3 volt supply 35 acvdd auxcont +3 volt supply 36 int_bias1 adcin decoupled with 0.1 m f to ground 38 int_bias2 vtrbyp decoupled with 0.1 m f to ground 39 mode2 dac1 ground 40 mode1 dac2 ground 41 advss sl ground 42 advdd sck +3 volt supply 44 advss sdata ground
ad9803 C17C rev. 0 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f ccd signal input v dd 0.1 m f digital output data 48 47 46 45 44 39 38 37 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 nc d0 (lsb) d1 d2 d3 d4 d5 d6 d7 d8 d9 (msb) drvdd ad9803 13 14 15 16 17 18 19 20 21 22 23 24 dvdd dvss aclp adcclk stby pblk clpob shp shd nc vrt vrb subst advss sdata advdd sck sl dac2 dac1 vtrbyp cmlevel clpdm drvss 36 35 34 33 32 31 30 29 28 27 26 25 adcin auxcont auxin acvdd clpbyp acvss pgacont2 pgacont1 ccdbyp1 pin din ccdbyp2 nc = no connect 0.1 m f v dd v dd 0.1 m f clpdm shd shp clpob pblk adcclk 0.1 m f 0.1 m f vout1 vout2 sdata sck sl 0.1 m f 0.1 m f 1.0 m f 0.1 m f v dd figure 37. ccd-mode circuit configurationdigital pga control
ad9803 C18C rev. 0 digital output data 48 47 46 45 44 39 38 37 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 nc d0 (lsb) d1 d2 d3 d4 d5 d6 d7 d8 d9 (msb) drvdd ad9803 13 14 15 16 17 18 19 20 21 22 23 24 dvdd dvss aclp adcclk stby pblk clpob shp shd nc vrt vrb subst advss sdata advdd sck sl dac2 dac1 vtrbyp cmlevel clpdm drvss 36 35 34 33 32 31 30 29 28 27 26 25 adcin auxcont auxin acvdd clpbyp acvss pgacont2 pgacont1 ccdbyp1 pin din ccdbyp2 nc = no connect 0.1 m f v dd v dd 0.1 m f clpdm shd shp clpob pblk adcclk 0.1 m f 0.1 m f 0.1 m f ccd signal input 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 1.0 m f 0.1 m f v dd stby pgacont1 pgacont2 v dd 0.1 m f 0.1 m f 0.1 m f 0.1 m f figure 38. recommended circuit for ad9801 sockets
ad9803 C19C rev. 0 outline dimensions dimensions shown in inches and (mm). 48-lead plastic thin quad flatpack (lqfp) (st-48) 0.354 (9.00) bsc 0.276 (7.0) bsc 1 12 13 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.009 (0.225) 0.006 (0.17) 0.019 (0.5) bsc seating plane 0.063 (1.60) max 0 min 0 C 7 0.076 max no min 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09)

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