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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k32-xh2x october 2004 rev. 4 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary* 128k x 32 sram/flash module features access times of 25ns (sram) and 70, 90 and 120ns (flash) packaging: ? 66-pin, pga type, 1.385 inch square hip, hermetic ceramic hip (package 402) 128kx32 sram 128kx32 5v flash organized as 128kx32 of sram and 128kx32 of flash memory with common data bus low power cmos commercial, industrial and military temperature ranges ttl compatible inputs and outputs built-in decoupling caps and multiple ground pins for low noise operation weight - 13 grams typical flash memory features 10,000 erase/program cycles sector architecture ? 8 equal size sectors of 16k bytes each ? any combination of sectors can be concurrently erased. also supports full chip erase 5 volt programming; 5v 10% supply embedded erase and program algorithms hardware write protection page program operation and internal program control time. * this product is under development, not fully characterized, and is subject to change without notice. note: programming information available upon request. figure 1 C pin configuration for wsf128k32-xh2x block diagram i/o 8 i/o 9 i/o 10 a 14 a 16 a 11 a 0 nc i/o 0 i/o 1 i/o 2 fwe 2 # swe 2 # gnd i/o 11 a 10 a 9 a 15 v cc fcs# scs# i/o 3 i/o 15 i/o 14 i/o 13 i/o 12 oe# nc fwe 1 # i/o 7 i/o 6 i/o 5 i/o 4 i/o 24 i/o 25 i/o 26 a 7 a 12 swe 1 # a 13 a 8 i/o 16 i/o 17 i/o 18 v cc swe 4 # fwe 4 # i/o 27 a 4 a 5 a 6 fwe 3 # swe 3 # gnd i/o 19 i/o 31 i/o 30 i/o 29 i/o 28 a 1 a 2 a 3 i/o 23 i/o 22 i/o 21 i/o 20 11 22 33 44 55 66 1 12 23 34 45 56 top view oe# fcs# scs# a 0-16 fwe 1 # swe 1 #fwe 2 #swe 2 #fwe 3 #swe 3 #fwe 4 #swe 4 # 128k x 8 flash 128k x 8 sram i/o 0-7 128k x 8 flash 128k x 8 sram i/o 8-15 128k x 8 flash 128k x 8 sram i/o 16-23 128k x 8 flash 128k x 8 sram i/o 24-31 pin description d0-31 data inputs/outputs a0-16 address inputs swe1-4# sram write enable scs# sram chip selects oe# output enable v cc power supply gnd ground nc not connected fwe1-4# flash write enable fcs# flash chip select
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k32-xh2x october 2004 rev. 4 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary dc characteristics v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol conditions min max unit input leakage current i li v cc = 5.5, v in = gnd to v cc 10 a output leakage current i lo scs# = v ih , oe# = v ih , v out = gnd to v cc 10 a sram operating supply current x 32 mode i ccx32 scs# = v il , oe# = fcs# = v ih , f = 5mhz, v cc = 5.5 670 ma standby current i sb fcs# = scs# = v ih , oe# = v ih , f = 5mhz, v cc = 5.5 80 ma sram output low voltage v ol i ol = 8ma, v cc = 4.5 0.4 v sram output high voltage v oh i oh = -4.0ma, v cc = 4.5 2.4 v flash v cc active current for read (1) i cc1 fcs# = v il , oe# = scs# = v ih 220 ma flash v cc active current for program or erase (2) i cc2 fcs# = v il , oe# = scs# = v ih 280 ma flash output low voltage v ol i ol = 8.0ma, v cc = 4.5 0.45 v flash output high voltage v oh1 i oh = -2.5 ma, v cc = 4.5 0.85 x v cc v flash output high voltage v oh2 i oh = -100 a, v cc = 4.5 v cc -0.4 v flash low v cc lock out voltage v lko 3.2 v notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (@ 5 mhz). the frequency component typically is less than 2 ma/mhz, with oe# at v ih . 2. i cc active while embedded algorithm (program or erase) is in progress. 3. dc test conditions: v il = 0.3v, v ih = v cc - 0.3v sram truth table scs# oe# swe# mode data i/o power h x x standby high z standby l l h read data out active l h h read high z active l x l write data in active note: 1. fcs# must remain high when scs# is low. capacitance ta = +25c parameter symbol conditions max unit oe# capacitance c oe v in = 0 v, f = 1.0 mhz 80 pf f/s we 1-4 # capacitance c we v in = 0 v, f = 1.0 mhz 30 pf f/s cs# capacitance c cs v in = 0 v, f = 1.0 mhz 50 pf d 0-31 capacitance c i/o v in = 0 v, f = 1.0 mhz 30 pf a 0-16 capacitance c ad v in = 0 v, f = 1.0 mhz 80 pf this parameter is guaranteed by design but not tested. absolute maximum ratings parameter symbol min max unit operating temperature t a -55 +125 c storage temperature t stg -65 +150 c signal voltage relative to gnd v g -0.5 7.0 v junction temperature t j 150 c supply voltage v cc -0.5 7.0 v parameter flash data retention 10 years flash endurance (write/erase cycles) 10,000 note: 1. stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. recommended operating conditions parameter symbol min max unit supply voltage v cc 4.5 5.5 v input high voltage v ih 2.2 v cc + 0.3 v input low voltage v il -0.5 +0.8 v
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k32-xh2x october 2004 rev. 4 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary i current source d.u.t. c = 50 pf eff i ol v 1.5v (bipolar supply) z current source oh sram ac characteristics v cc = 5.0v, -55c t a +125c parameter read cycle symbol -25 units min max read cycle time t rc 25 ns address access time t aa 25 ns output hold from address change t oh 0ns chip select access time t acs 25 ns output enable to output valid t oe 15 ns chip select to output in low z t clz 1 3ns output enable to output in low z t olz 1 0ns chip disable to output in high z t chz 1 12 ns output disable to output in high z t ohz 1 12 ns 1. this parameter is guaranteed by design but not tested. sram ac characteristics v cc = 5.0v, -55c t a +125c parameter write cycle symbol -25 units min max write cycle time t wc 25 ns chip select to end of write t cw 20 ns address valid to end of write t aw 20 ns data valid to end of write t dw 15 ns write pulse width t wp 20 ns address setup time t as 3ns address hold time t ah 0ns output active from end of write t ow 1 3ns write enable to output in high z t whz 1 15 ns data hold from write time t dh 0ns 1. this parameter is guaranteed by design but not tested. figure 2 C ac test circuit ac test conditions parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z0 = 75 ?. v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance.
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k32-xh2x october 2004 rev. 4 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary address data i/o t aw t as t cw t ah t wp t dh t dw t wc scs# swe# data valid figure 3 C sram timing waveform - read cycle figure 4 C sram write cycle - swe# controlled figure 5 C sram write cycle - scs# controlled address data i/o t aa t oh t rc data valid previous data valid read cycle 1, (scs# = oe# = v il , swe# = fcs# = v ih ) read cycle 2, (swe# = fcs# = v ih ) write cycle 2, scs# controlled (fcs# = v ih ) write cycle 1, swe# controlled (fcs# = v ih ) address data i/o t aa t acs t oe t clz t olz t ohz t rc data valid high impedance scs# soe# t chz address data i/o t aw t cw t ah t wp t dw t whz t as t ow t dh t wc data valid scs# swe#
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k32-xh2x october 2004 rev. 4 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary flash ac characteristics C write/erase/program operations, fwe# controlled v cc = 5.0v, -55c t a +125c parameter symbol -70 -90 -120 unit min max min max min max write cycle time t avav t wc 70 90 120 ns chip select setup time t elwl t cs 000ns write enable pulse width t wlwh t wp 45 45 50 ns address setup time t avwl t as 000ns data setup time t dvwh t ds 45 45 50 ns data hold time t whdx t dh 000ns address hold time t wlax t ah 45 45 50 ns chip select hold time t wheh t ch 000ns write enable pulse width high t whwl t wph 20 20 20 ns duration of byte programming operation (min) t whwh1 14 14 14 s chip and sector erase time t whwh2 2.2 60 2.2 60 2.2 60 sec read recovery time before write t ghwl 000s v cc set-up time t vcs 50 50 50 s chip programming time 12.5 12.5 12.5 sec output enable setup time t oes 000ns output enable hold time (1) t oeh 10 10 10 ns 1. for toggle and data# polling. flash ac characteristics C read only operations v cc = 5.0v, -55c t a +125c parameter symbol -70 -90 -120 unit min max min max min max read cycle time t avav t rc 70 90 120 ns address access time t avqv t acc 70 90 120 ns chip select access time t elqv t ce 70 90 120 ns oe# to output valid t glqv t oe 35 40 50 ns chip select to output high z (1) t ehqz t df 20 25 30 ns oe# high to output high z (1) t ghqz t df 20 25 30 ns output hold from address, fcs# or oe# change, whichever is ? rst t axqx t oh 000ns 1. guaranteed by design, not tested.
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k32-xh2x october 2004 rev. 4 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary flash ac characteristics C write/erase/program operations, fcs# controlled v cc = 5.0v, -55c t a +125c parameter symbol -70 -90 -120 unit min max min max min max write cycle time t avav t wc 70 90 120 ns fwe# setup time t wlel t ws 000ns fcs# pulse width t eleh t cp 35 45 50 ns address setup time t avel t as 000ns data setup time t dveh t ds 30 45 50 ns data hold time t ehdx t dh 000ns address hold time t elax t ah 45 45 50 ns fwe# hold from fwe# high t ehwh t wh 000ns fcs# pulse width high t ehel t cph 20 20 20 ns duration of programming operation t whwh1 14 14 14 s duration of erase operation t whwh2 2.2 60 2.2 60 2.2 60 sec read recovery before write t ghel 000ns chip programming time 12.5 12.5 12.5 sec
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k32-xh2x october 2004 rev. 4 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary figure 6 C ac waveforms for flash memory read operations a ddresses fcs# oe# fwe# outputs high z addresses stable t oe t rc output valid t ce t acc t oh high z t df note: scs# = v ih
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k32-xh2x october 2004 rev. 4 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary figure 7 C write/erase/program operation, flash memory fwe# controlled notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d 7 # is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. 6. scs# = v ih addresses fcs# oe# fwe# data 5.0 v 5555h pa pa t wc t cs pd d 7 # d out t ah t wph t dh t ds data# polling t as t rc t wp a0h t oe t df t oh t ce t ghwl t whwh1
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k32-xh2x october 2004 rev. 4 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary figure 8 C ac waveforms chip/sector erase operations for flash memory notes: 1. sa is the sector address for sector erase. 2. scs# = v ih addresses fcs# oe# fwe# data v cc 5555h 2aaah 2aaah sa 5555h 5555h t wp t cs t vcs 10h/30h 55h 80h 55h aah aah t ah t as t ghwl t wph t dh t ds
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k32-xh2x october 2004 rev. 4 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary figure 9 C ac waveforms for data# polling during embedded algorithm operations for flash memory fcs# oe# fwe# t oe t oe d7 d7 valid data t ce t ch t oh high z d7# d7 = valid data high z d0-d6 = invalid d0-d7 valid data t df d7 d7 d0-d6 t oeh t whwh 1 or 2 t whwh 1 or 2 note: scs# = v ih
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k32-xh2x october 2004 rev. 4 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary figure 10 C write/erase/program operation for flash memory, cs# controlled notes: 1. pa represents the address of the memory location to be programmed. 2. pd represents the data to be programmed at byte address. 3. d 7 # is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates the last two bus cycles of a four bus cycle sequence. 6. scs# = v ih addresses fwe# oe# fcs# data 5.0 v 5555h pa pa t wc t ws pd d 7 # d out t ah t cph t cp t dh t ds data# polling t as t ghel a0h t whwh1
12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k32-xh2x october 2004 rev. 4 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary ordering information lead finish: blank = gold plated leads a = solder dip leads device grade: m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c package type: h2 = ceramic hex in-line package, hip (package 402) access time (ns) 22 = 25ns sram and 120ns flash 29 = 25ns sram and 90ns flash 27 = 25ns sram and 70ns flash organization, 128k x 32 flash prom sram white electronic designs corp. w s f 128k32 - xx h2 x x package 402: 66 pin, pga type, ceramic hex-in-line package, hip (h2) 35.2 (1.385) 0.38 (0.015) sq 25.4 (1.0) typ 15.24 (0.600) typ 0.76 (0.030) 0.1 (0.005) 5.7 (0.223) max 3.81 (0.150) 0.1 (0.005) 2.54 (0.100) typ 25.4 (1.0) typ 1.27 (0.050) 0.1 (0.005) 1.27 (0.050) typ dia 0.46 (0.018) 0.05 (0.002) dia pin 1 identifier square pad on bottom all linear dimensions are millimeters and parenthetically in inches

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