rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a integrated circuit voltage-to-frequency converter ad537* product description the ad537 is a monolithic v-f converter consisting of an input amplifier, a precision oscillator system, an accurate internal ref- erence generator and a high current output stage. only a single external rc network is required to set up any full-scale (f.s.) frequency up to 100 khz and any f.s. input voltage up to 30 v. linearity error is as low as 0.05% for 10 khz f.s., and operation is guaranteed over an 80 db dynamic range. the over- all temperature coefficient (excluding the effects of external components) is typically 30 ppm/ c. the ad537 operates from a single supply of 5 v to 36 v and consumes only 1.2 ma quiescent current. a temperature-proportional output, scaled to 1.00 mv/k, enables the circuit to be used as a reliable temperature-to- frequency converter; in combination with the fixed reference output of 1.00 v, offset scales such as 0 c or 0 f can be generated. the low drift (1 v/ c typ) input amplifier allows operation directly from small signals (e.g., thermocouples or strain gages) while offering a high (250 m ? ) input resistance. unlike most v? converters, the ad537 provides a square-wave output, and can drive up to 12 ttl loads, leds, very long cables, etc. the excellent temperature characteristics and long-term stability of the ad537 are guaranteed by the primary bandgap reference generator and the low t.c. silicon chromium thin film resistors used throughout. the device is available in either a 14-lead ceramic dip or a 10- lead metal can; both are hermetically sealed packages. * protected by patent nos. 3,887,963 and re 30,586. features low cost a? conversion versatile input amplifier positive or negative voltage modes negative current mode high input impedance, low drift single supply, 5 v to 36 v linearity: 0.05% fs low power: 1.2 ma quiescent current full-scale frequency up to 100 khz 1.00 v reference thermometer output (1 mv/k) f-v applications mil-std-883 compliant versions available pin configurations d-14 package h-10a package logic gnd sync +v in v temp v ref i in ? in output +v s v os v os ? s cap cap 1 2 14 13 5 6 7 10 9 8 3 4 12 11 ad537 driver curr- to-freq conv buf precision voltage reference v t v r driver curr- to-freq conv precision voltage reference v t v r ad537 ? in +v in v ref logic gnd output +v s cap cap ? s (connected to case) buf 10 9 8 7 6 5 4 3 2 1 v temp the ad537 is available in three performance/temperature grades; the j and k grades are specified for operation over the 0 c to +70 c range while the ad537s is specified for operation over the extended temperature range, ?5 c to +125 c. product highlights 1. the ad537 is a complete v-f converter requiring only an external rc timing network to set the desired full-scale fre- quency and a selectable pull-up resistor for the open collec- tor output stage. any full-scale input voltage range from 100 mv to 10 volts (or greater, depending on +v s ) can be accommodated by proper selection of timing resistor. the full-scale frequency is then set by the timing capacitor from the simple relationship, f = v/10rc. 2. the power supply requirements are minimal, only 1.2 ma quiescent current is drawn from a single positive supply from 4.5 volts to 36 volts. in this mode, positive inputs can vary from 0 volts (ground) to (+v s ?4) volts. negative inputs can easily be connected for below ground operation. 3. f-v converters with excellent characteristic are also easy to build by connecting the ad537 in a phase-locked loop. ap- plication particulars are shown in figure 6. 4. the versatile open-collector npn output stage can sink up to 20 ma with a saturation voltage less than 0.4 volts. the logic common terminal can be connected to any level be- tween ground (or ? s ) and 4 volts below +v s . this allows easy direct interface to any logic family with either positive or negative logic levels. 5. the ad537 is available in versions compliant with mil- std-883. refer to the analog devices military product databook or current ad537/883b data sheet for detailed specifications. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ?analog devices, inc., 2000
ad537?pecifications (typical @ +25 c with v s (total) = 5 v to 36 v, unless otherwise noted) ad537kd ad537sd 1 model ad537jh ad537jd ad537kh ad537sh 1 current-to-frequency converter frequency range 0 khz to 150 khz * * * nonlinearity 1 f max = 10 khz 0.15% max (0.1% typ) * 0.07% max ** f max = 100 khz 0.25% max (0.15% typ) * 0.1% max ** full-scale calibration error c = 0.01 f, i in = 1.000 ma 10% max 7% max 5% max * * vs. supply (f max < 100 khz) 0.1%/v max (0.01% typ) * * * vs. temp (t min to t max ) 150 ppm/ c max (50 ppm typ) * 50 ppm/ c max (30 ppm typ) 2 250 ppm/ c max analog input amplifier (voltage-to-current converter) voltage input range single supply 0 to (+v s ?4) volts (min) * * * dual supply ? s to (+v s ?4) volts (min) * * * input bias current (either input) 100 na * * * input resistance (noninverting) 250 m ? ** * input offset voltage (trimmable in ??package only) 5 mv max * 2 mv max ** vs. supply 200 v/v max 100 v/v max 100 v/v max ** vs. temp (t min to t max )5 v/ c*1 v/ c10 v/ c max safe input voltage 3 v s ** * reference outputs voltage reference absolute value 1.00 volt 5% max * * * vs. temp (t min to t max ) 50 ppm/ c * 100 ppm/ c max ** vs. supply 0.03%/v max * * * output resistance 4 380 ? ** * absolute temperature reference 5 nominal output level 1.00 mv/k * * * initial calibration @ +25 c 298 mv ( 5 mv typ) * 298 mv ( 5 mv max) ** slope error from 1.00 mv/k 0.02 mv/k * * * slope nonlinearity 0.1 k * * * output resistance 5 900 ? ** * output interface (open collector output) (symmetrical square wave) output sink current in logic ? v out = 0.4 v max (t min to t max ) 20 ma min 20 ma min 20 ma min 10 ma min output leakage current in logic ? (t min to t max ) 200 na max * * 2 a max logic common level range ? s to (+v s ?4) volts * * * rise/fall times (c t = 0.01 f) i in = l ma 0.2 s** * i in = 1 a1 s** * power supply voltage, rated performance single supply 4.5 v to 36 v * * * dual supply 5 v to 18 v * * * quiescent current 1.2 ma (2.5 ma max) * * * temperature range rated performance 0 c to +70 c** 55 c to +125 c storage ?5 c to +150 c** * package options 6, 7 d-14 ceramic dip ad537jd ad537kd ad537sd h-10a header ad537jh ad537kh ad537sh notes * specifications same as ad537jh. **specifications same as ad537k. 1 nonlinearity is specified for a current input level (i in ) to the converter from 0.1 a to 1000 a. converter has 100% overrange capability up to i in = 2000 a with slightly reduced linearity. nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a percentage of full scale. 2 guaranteed not tested. 3 maximum voltage input level is equal to the supply on either input terminal. however, large negative voltage levels can be appl ied to the negative terminal if the input is scaled to a nominal 1 ma full scale through an appropriate value resistor (see figure 2). 4 loading the 1.0 volt or 1 mv/k outputs can cause a significant change in overall circuit performance, as indicated in the applic ations section. to maintain normal operation, these outputs should be operated into the external buffer or an external amplifier. 5 temperature reference output performance is specified from 0 c to +70 c for ??and ??devices, ?5 c to +125 c for ??model. 6 d = ceramic dip; h = hermetic metal can. for outline information see package information section. 7 for ad537/883b specifications, refer to analog devices military products databook . specifications subject to change without notice. rev. c ?
applying the ad537 circuit operation block diagrams of the ad537 are shown above. a versatile operational amplifier (buf) serves as the input stage; its pur- pose is to convert and scale the input voltage signal to a drive current in the npn follower. optimum performance is achieved when, at the full-scale input voltage, a 1 ma drive current is delivered to the current-to-frequency converter. the drive cur- rent to the current-to-frequency converter (an astable multivibrator) provides both the bias levels and the charging current to the externally connected timing capacitor. this ?daptive?bias scheme allows the oscillator to provide low non- linearity over the entire current input range of 0.1 a to 2000 a. the square wave oscillator output goes to the output driver which provides a floating base drive to the npn power transistor. this floating drive allows the logic interface to be ref- erenced to a different level than ? s . the ?ync?input (? package only) allows the oscillator to be slaved to an external master oscillator; this input can also be used to shut off the oscillator. the reference generator uses a bandgap circuit (this allows single-supply operation to 4.5 volts which is not possible with low t.c. zeners) to provide the reference and bias levels for the amplifier and oscillator stages. the reference generator also pro- vides the precision, low t.c. 1.00 volt output and the v temp output which tracks absolute temperature at 1 mv/k. v-f connection for positive input voltages the positive voltage input range is from ? s (ground in single supply operation) to 4 volts below the positive supply. the con- nection shown in figure 1 provides a very high (250 m ? ) input impedance. the input voltage is converted to the proper drive current at pin 3 by selecting a scaling resistor. the full-scale current is 1 ma, so, for example a 10 volt range would require a nominal 10 k ? resistor. the trim range required will depend on capacitor tolerance. full-scale currents other than 1 ma can be chosen, but linearity will be reduced; 2 ma is the maximum allowable drive. as indicated by the scaling relationship in figure 1, a 0.01 f timing capacitor will give a 10 khz full-scale frequency, and 0.001 f will give 100 khz with a 1 ma drive current. the maximum frequency is 150 khz. polystyrene or npo ceramic capacitors are preferred for t.c. and dielectric absorption; polycarbonate or mica are acceptable; other types will degrade linearity. the capacitor should be wired very close to the ad537. 1 2 14 13 5 6 7 10 9 8 3 4 12 11 ad537 driver curr- to-freq conv precision voltage reference v t v r guard ring r2 r1 v in 10k ? 10f optional input filter c r t 20k r out f out +v s f o = v in 10 (r 1 + r 2 ) c buf figure 1. standard v-f connection for positive input voltages v-f connections for negative input voltage or current a wide range of negative input voltages can be accommodated with proper selection of the scaling resistor, as indicated in fig- ure 2. this connection, unlike the buffered positive connection, is not high impedance since the 1 ma f.s. drive current must be supplied by the signal source. however, very large negative volt- ages beyond the supply can be handled easily; just modify the scaling resistors appropriately. diode cr1 (hp50822811) is necessary for overload and latchup protection for current or voltage inputs. if the input signal is a true current source, r1 and r2 are not used. full-scale calibration can be accomplished by connecting a 200 k ? pot in series with a fixed 27 k ? from pin 7 to ? s (see calibration section, below). 1 2 14 13 5 6 7 10 9 8 3 4 12 11 ad537 buf driver curr- to-freq conv precision voltage reference v t v r v in 0 to 10v c 20k ? 5k ? (typ) f out +v s f o = v in 10 (r 1 + r 2 ) c cr1 0 to 1ma i in r 1 r 2 f out = i in 10c figure 2. v-f connections for negative input voltage or current calibration there are two independent adjustments: scale and offset. the first is trimmed by adjustment of the scaling resistor r and the second by the (optional) potentiometer connected to +v s and the v os pins (??package only). precise calibration requires the use of an accurate voltage standard set to the desired fs value and a frequency meter; a scope is useful for monitoring output waveshape. verification of linearity requires the availability of a switchable voltage source (or a dac) having a linearity error below 0.005%, and the use of long measurement intervals to minimize count uncertainties. every ad537 is automatically tested for linearity, and it will not usually be necessary to perform this verification, which is both tedious and time-consuming. although drifts are small it is good practice to allow the operat- ing environment to attain stable temperature and to ensure that the supply, source and load conditions are proper. begin by set- ting the input voltage to 1/10,000 of full scale. adjust the offset pot until the output frequency is 1/10,000 of full scale (for ex- ample 1 hz for fs of 10 khz). this is most easily accomplished using a frequency meter connected to the output. then apply the fs input voltage and adjust the gain pot until the desired fs frequency is indicated. in applications where the fs input is small, this adjustment will very slightly affect the offset voltage, due to the input bias current of the buffer amplifier. a change of lk ? in r will affect the input by approximately 100 v, which is as much as 0.1% of a 100 mv fs range. therefore, it may be necessary to repeat the offset and scale adjustments for the high- est accuracy. the design of the input amplifier is such that the input voltage drift after offset nulling is typically below l v/ c. rev. c 3
ad537 rev. c 4 the ? in , +v in and i in pins should not be driven more than 300 mv below ? s . this would cause internal junctions to con- duct, possibly damaging the ic. the ad537 can be protected from ?elow ? s ?inputs by a schottky diode, cr1 (hp5082- 2811) as shown in figure 3. it is also desirable not to drive +v in , ? in and i in above +v s . in operation, the converter will become very nonlinear for inputs above (+v s ?3.5 v). control currents above 2 ma will also cause nonlinearity. the 80 db dynamic range of the ad537 guarantees operation from a control current of 1 ma (nominal fs) down to 100 na (equivalent to 1 mv to 10 v fs). below 100 na improper op- eration of the oscillator may result, causing a false indication of input amplitude. in many cases this might be due to short-lived noise spikes which become added to the input. for example, when scaled to accept a fs input of 1 v, the ?0 db level is only 100 v, so when the mean input is only 60 db below fs (1 mv), noise spikes of 0.9 mv are sufficient to cause momen- tary malfunction. this effect can be minimized by using a simple low-pass filter ahead of the converter and a guard ring around the i in or ? in pins. for a fs of 10 khz a single-pole filter with a time-constant of 100 ms (figure 2) will be suitable, but the optimum configu- ration will depend on the application and type of signal process- ing. noise spikes are only likely to be a cause of error when the input current remains near its minimum value for long periods of time; above 100 na (1 mv) full integration of additive input noise occurs. the ad537 is somewhat susceptible to interference from other signals. the most sensitive nodes (besides the inputs) are the capacitor terminals and the sync pin. the timing capacitor should be located as close as possible to the ad537 to minimize signal pickup in the leads. in some cases, guard rings or shield- ing may be required. the sync pin should be decoupled through a 0.005 f (or larger) capacitor to pin 13 (+v s ). this minimizes the possibility that the ad537 will attempt to syn- chronize to a spurious signal. this precaution is unnecessary on the metal can package since the sync function is not brought out to a package pin and is thus not susceptible to pickup. decoupling it is good engineering practice to use bypass capacitors on the supply-voltage pins and to insert small-valued resistors (10 ? to 100 ? ) in the supply lines to provide a measure of decoupling between the various circuits in a system. ceramic capacitors of 0.1 f to 1.0 f should be applied between the supply-voltage pins and analog signal ground for proper bypassing on the ad537. a decoupling capacitor may also be useful from +v s to sync in those applications where very low cycle-to-cycle period varia- tion (jitter) is demanded. by placing a capacitor across +v s and sync this noise is reduced. on the 10 khz fs range, a 6.8 f capacitor reduces the jitter to one in 20,000 which adequate for most applications. a tantalum capacitor should be used to avoid errors due to dc leakage. in some cases the signal may be in the form of a negative cur- rent source. this can be handled in a similar way to a negative input voltage. however, the scaling resistor is no longer re- quired, eliminating the capability of trimming full scale in this fashion. since it will usually be impractical to vary the capaci- tance, an alternative calibration scheme is needed. this is shown in figure 3. a resistor-potentiometer connected from the v r output to ? s will alter the internal operating conditions in a predictable way, providing the necessary adjustment range. with the values shown, a range of 4% is available; a larger range can be attained by reducing r1. this technique does not degrade the temperature-coefficient of the converter, and the linearity will be as for negative input voltages. the minimum supply voltage may be used. unless it is required to set the input node at exactly ground potential, no offset adjustment is needed. the capacitor c is se- lected to be 5% below the nominal value; with r2 in its midposition the output frequency is given by: f = i 10.5 c where f is in khz, i is in ma and c is in f. for example, for a fs frequency of 10 khz at a fs input of 1 ma, c = 9500 pf. calibration is effected by applying the full-scale input and ad- justing r2 for the correct reading. this alternative adjustment scheme may also be used when it is desired to present an exact input resistance in the negative volt- age mode. the scaling relationship is then f = v r exact 1 10.5 c the calibration procedure is then similar to that used for posi- tive input voltages, except that the scale adjustment is by means of r2. 1 2 14 13 5 6 7 10 9 8 3 4 12 11 ad537 r1 27k r2 200k c +v s i in 10c f = output v logic cap v s v os v os logic gnd i v adj. scale dec/syn v temp v ref buf driver curr- to-freq conv precision voltage reference v t v r i in figure 3. scale adjustment for current inputs input protection the ad537 was designed to be used with a minimum of addi- tional hardware. however, the successful application of a preci- sion ic involves a good understanding of possible pitfalls and the use of suitable precautions.
ad537 rev. c 5 nonlinearity specification the preferred method for specifying linearity error is in terms of the maximum deviation from the ideal relationship after cali- brating the converter at full scale and zero . this error will vary with the full-scale frequency and the mode of operation. the ad537 operates best at a 10 khz full-scale frequency with a negative voltage input; the linearity is typically within 0.05%. operating at higher frequencies or with positive inputs will degrade the linearity as indicates in the specification table. the shape of a typical linearity plot is given in figure 4. 0.18 0.04 0.10 0.06 10 0.08 1 0.16 0.12 0.14 10k 1k 100 output frequency hz nonlinearity % of full scale 0.08 0.02 0.06 0.04 0 0.02 ad537j ad537k, s test conditions: +v s = +15v v s = 0v c t = 0.01f r t = 10k ? v fs = 10v pos input fig. 3 neg input fig. 4 figure 4a. typical nonlinearity error envelopes with 10 khz f.s. output 0.18 0.04 0.10 0.06 100 0.08 10 0.16 0.12 0.14 100k 10k 1k output frequency hz nonlinearity % of full scale 0.08 0.02 0.06 0.04 0 0.02 ad537j ad537k, s test conditions: +v s = +15v v s = 0v c t = 0.001f r t = 10k ? v fs = 10v pos input fig. 3 neg input fig. 4 figure 4b. typical nonlinearity error with 100 khz f.s. output output interfacing considerations the design of the output stage allows easy interfacing to all digi- tal logic families. the collector and emitter of the output npn transistor are both uncommitted; the emitter can be tied to any voltage between v s and 4 volts below +v s . the open collector can be pulled up to a voltage 36 volts above the emitter regard- less of +v s . the high power output stage can supply up to 20 ma (10 ma for h package) at a maximum saturation volt- age of 0.4 volts. the stage limits the output current at 25 ma; it can handle this limit indefinitely without damaging the device. figure 5 shows the ad537 with a standard 0 to +10 volt input connection and the output stage connections. the values for the logic common voltage, pull-up resistor, positive logic level, and v s supply are given in the accompanying chart for several logic forms. 1 2 14 13 5 6 7 10 9 8 3 4 12 11 ad537 c f out +v s (+15v) 10k v in r l logic v cc logic com v ee v os 20k v s ttl/dtl 5v cmos 15v cmos/ hnil ecl 10k ecl2.5k pmos v cc +5 +5 +15 0 +1.3 0 v ee gnd gnd gnd 8 2 15 r l 5k 20k 10k 5k 5k 10k v s gnd gnd gnd 8 to 15 5 15 buf driver curr- to-freq conv precision voltage reference v t v r figure 5. interfacing standard logic families applications the diagrams and descriptions of the following applications are provided to stimulate the discerning engineer with alternative circuit design ideas. applications of the ad537 ic voltage- to-frequency converter , available from analog devices on request, covers a wider range of topics and concepts in data conversion and data transmission using voltage-to-frequency converters. true two-wire data transmission figure 6 shows the ad537 in a true two-wire data transmission scheme. the twisted-pair transmission lines serves the dual pur- pose of supplying power to the device and also carrying fre- quency data in the form of current modulation. the pnp circuit at the receiving end represents a fairly simple way for converting the current modulation back into a voltage square wave which will drive digital logic directly. the 0.6 volt square wave which will appear on the supply line at the device terminals does not affect the performance of the ad537 because of its excellent supply rejection. also, note that the circuit operates at nearly constant average power regardless of frequency. driver curr- to-freq conv precision voltage reference v t v r buf ad537 +v in v temp v ref logic gnd +v s v s (connected to case) 10 9 8 7 6 5 4 3 2 1 r scale r cal c two-wire link v s +5 +15 r s 0 1k r l 1k 3.3k 120 r s 220 ? +v s output r l v in figure 6. true two-wire operation
ad537 rev. c 6 f-v converters the ad537 can be used as a high linearity vco in a phase- locked loop to accomplish frequency-to-voltage conversion. by operating the loop without a low-pass filter in the feedback path (first-order system), it can lock to any frequency from zero to an upper limit determined by the design, responding in three or four cycles to a step change of input frequency. in practice, the overall response time is determined by the characteristics of the averaging filter which follows the pll. figure 7 shows a connection using a low power ttl quad open-collector nand gate which serves as the phase comparator. the input signal should be a pulse train or square wave with characteristics similar to ttl or 5-volt cmos outputs. any duty cycle is acceptable, but the minimum pulse width is 40 s. the output voltage is one volt for a 10 khz input frequency. the output as shown here is at a fairly high impedance level; for many situations an additional buffer may be required. trimming is similar to v-f application trimming. first set the v os trimmer to mid-scale. apply a 10 khz input frequency and trim the 2 k ? potentiometer for 1.00 volts out. then apply a 10 hz waveform and trim the v os for 1 mv out. finally, retrim the full-scale output at 10 khz. other frequency scales can be obtained by appropriate scaling of timing components. 1 2 14 13 5 6 7 10 9 8 3 4 12 11 ad537 driver precision voltage reference curr -to- freq conv buf 20k v os f in (0-10khz) 2k 10k 0.001f 1n4148 0.005f 3.9k 120k output 1v f.s. 0.33f 10k 10k 74lo3 + 5v 10k 9.09k figure 7. 10 khz f-v converter temperature-to-frequency conversion the linear temperature-proportional output of the ad537 can be used as shown in these applications to perform various direct temperature-to-frequency conversion functions; it can also be used with other external connections in a temperature sensing or compensation scheme. if the sensor output is used externally, it should be buffered through an op amp since loading that point will cause significant error in the sensor output as well as in the main v-f converter circuitry. an absolute temperature (kelvin)-to-frequency converter is very easily accomplished, as shown in figure 8. the 1 mv per k out- put serves as the input to the buffer amplifier, which then scales the oscillator drive current to a nominal 298 a at +25 c (298k). use of a 1000 pf capacitor results in a corresponding frequency of 2.98 khz. setting the single 2 k ? trimmer for the correct frequency at a well-defined temperature near +25 c will normally result in an accuracy of 2 c from 55 c to +125 c (using an ad537s). an npo ceramic capacitor is recom- mended to minimize nonlinearity due to capacitance drift. driver curr- to-freq conv precision voltage reference v t v r ad537 +v v temp v ref logic gnd +v s v s (connected to case) 10 9 8 7 6 5 4 3 2 1 9.1k ? 10k ? f = 10hz/k 1000pf 2k ? buf figure 8. absolute temperature to frequency converter offset temperature scales many other temperature scales can be set up by offsetting the temperature output with the voltage reference output. such a scheme is shown by the celsius-to-frequency converter in figure 9. corresponding component values for a fahrenheit-to- frequency converter which give 10 hz/ f are given in parentheses. 1 2 14 13 5 6 7 10 9 8 3 4 12 11 ad537 10k f out 10hz/ c (10hz/ f) +5v 2.74k (4.02k) 500 ? 3900 pf (1500pf) 2k 6.04k (10k) 49 ? (205 ? ) buf driver curr- to-freq conv precision voltage reference v t v r figure 9. offset temperature scale converters centigrade and (fahrenheit) to frequency a simple calibration procedure which will provide 2 c accu- racy requires substitution of a 7.27k resistor for the series com- bination of the 6.04k with the 2k trimmer; then simply set the 500 ? trimmer to give 250 hz at +25 c. high accuracy calibration procedure: 1. measure room temperature in k. 2. measure temperature output at pin 6 at that temperature. 3. calculate offset adjustment as follows: offset voltage ( mv ) = v temp ( pin 6 ) ( mv ) room temp ( k ) 273.2 4. temporarily disconnect 49 ? resistor (or 500 ? pot) and trim 2 k ? pot to give the offset voltage at the indicated node. reconnect 49 ? resistor. 5. adjust slope trimmer to give proper frequency at room tem- perature (+25 c = 250 hz). adjustment for f or any other scale is analogous.
ad537 rev. c 7 synchronous operation the sync terminal at pin 2 of the dip package can be used to synchronize a free running ad537 to a master oscillator, either at a multiple or a sub-multiple of the primary frequency. the preferred connection is shown in figure 10. the diodes are used to produce the proper drive magnitude from high level signals. the sync terminal can also be used to shut off the oscillator. shorting the terminal to +v s will stop the oscillator, and the output will go high (output npn off). 1 2 14 13 5 6 7 10 9 8 3 4 12 11 ad537 r +v s c t f out v in c s v sync 1000pf 2 c s v sync 1n4148 10k note: if v sync >2v p-p use this limiter buf driver curr- to-freq conv precision voltage reference v t v r figure 10. connection for synchronous operation figure 11 shows the maximum pull-in range available at a given signal level; the optimum signal is a 0.8 to 1.0 volt square wave; signals below 0.1 volt will have no effect; signals above 2 volts p-p will disable the oscillator. the ad537 can normally be syn- chronized to a signal which forces it to a higher frequency up to 30% above the nominal free-running frequency, it can only be brought down about 1 2%. 0.2 0.4 0.6 0.8 1.0 v sync square-wave input volts p-p 30% 20% 10% frequency lock-in range figure 11. maximum frequency lock-ln range vs. sync signal linear phase locked loop the phase-locked-loop f/v circuit described earlier operates from an essentially noise-free binary input. pll s are also used to extract frequency information from a noisy analog signal. to do this, the digital phase-comparator must be replaced by a lin- ear multiplier. in the implementation shown in figure 12, the triangular waveform appearing across the timing capacitor is used as one of the multiplier inputs; the signal provides the other input. it can be shown that the mean value of the multi- plier output is zero when the two signals are in quadrature. in this condition, the ripple in the error signal is also quite small. thus, the voltage at pin 5 is essentially zero, and the frequency is determined primarily by the current in the timing resistor, controlled either manually or by a control voltage. 1 2 14 13 5 6 7 10 9 8 3 4 12 11 ad537 cap 0.01f output +v s v os v s signal input 12v pk 1 2 6 7 8 10 12 11 14 +15v com- posite error signal 1v pk 15v 10k dec/ syn freq control input 0 to 10v v temp v ref recovered frequency signal 3.9v driver precision voltage reference curr -to- freq conv buf logic gnd v r v t figure 12. linear phase-locked loop noise on the input signal affects the loop operation only slightly; it appears as noise in the timing current, but this is averaged out by the timing capacitor. on the other hand, if the input fre- quency changes there is a net error voltage at pin 5 which acts to bring the oscillator back into quadrature. thus, the output at pin 14 is a noise-free square-wave having exactly the same fre- quency as the input signal. the effectiveness of this circuit can be judged from figure 13 which shows the response to an input of 1 v rms 1 khz sinusoid plus 1 v rms gaussian noise. the positive supply to the ad537 is reduced by about 4 v in order to keep the voltages at pins 11 and 12 within the common-mode range of the ad534. since this is also a first-order loop the circuit possesses a very wide capture range. however, even better noise-integrating properties can be achieved by adding a filter between the multi- plier output and the vco input. details of suitable filter charac- teristics can be found in the standard texts on the subject. 1v rms signal +1v rms noise output figure 13. performance of ad537 linear phase locked loop by connecting the multiplier output to the lower end of the tim- ing resistor and moving the control input to pin 5, a high resis- tance frequency-control input is made available. however, due to the reduced supply voltage, this input cannot exceed +6 v. transducer interface the ad537 was specifically designed to accept a broad range of input signals, particularly small voltage signals, which may be converted directly (unlike many v-f converters which require signal preconditioning). the 1.00 v stable reference output is also useful in interfacing situations, and the high input resis- tance allows nonloading interfacing from a source of varying resistance, such as the slider of a potentiometer.
ad537 rev. c 8 printed in u.s.a. c397f 0 4/00 (rev. c) thermocouple input the output of a chromel-constantan (type e) thermocouple, using a reference junction at 0 c, varies from 0 mv to 53.14 mv over the temperature range 0 c to +700 c with a slope of 80.678 v/degree over most of its range and some nonlinearity over the range 0 c to +200 c. for this example, we assume that it is desired to indicate temperature in degrees celsius using a counter/display with a 100 ms gate width. thus, the v-f converter must deliver an output of 7 khz for an input of 53.14 mv. if very precise operation down to 0 c is imperative, some sort of linearizing is necessary (see, for example, analog devices?nonlinear circuits handbook , pp. 92 97) but in many cases operation is only needed over part of the range. the circuit shown in figure 14 provides good accuracy from +300 c to +700 c. the extrapolation of the temperature volt- age curve back to 0 c shows that an offset of 3.34 mv is required to fit the curve most exactly. this small amount of voltage can be introduced without an additional calibration step using the +1.00 v output of the ad537. to adjust the scale, the thermocouple should be raised to a known reference tempera- ture near 500 c and the frequency adjusted to value using r1. the error should be within 0.2% over the range 400 c to 700 c. 1 2 14 13 5 6 7 10 9 8 3 4 12 11 ad537 +5v v logic 10hz/ c 0.005f 47k i offset 21a 120 r1 scale 50 t meas t ref (0 c) 0 to 53mv buf driver curr- to-freq conv precision voltage reference v t v r 360a f s figure 14. thermocouple interface with first-order linearization outline dimensions dimensions shown in inches and (mm). 14-lead side-brazed ceramic dip (to?16) (d?4) pin 1 0.310 (7.87) 0.220 (5.59) 0.098 (2.49) max 0.005 (0.13) min 8 7 14 1 0.200 (5.08) max 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min seating plane 0.785 (19.94) max 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 10-lead metal can (to-100) (h-10a) 36 bsc 0.034 (0.86) 0.028 (0.71) 0.045 (1.14) 0.029 (0.74) 0.115 (2.92) bsc 0.230 (5.84) bsc 6 8 57 1 4 2 39 10 reference plane base & seating plane 0.355 (9.02) 0.305 (7.75) 0.370 (9.40) 0.335 (8.51) 0.562 (14.30) 0.500 (12.70) 0.040 (1.01) 0.010 (0.25) 0.050 (1.27) max 0.019 (0.48) 0.016 (0.41) 0.021 (0.53) 0.016 (0.41) 0.185 (4.70) 0.165 (4.19) 0.044 (1.12) 0.032 (0.81)
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