View 87016I_8366508.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet low skew, 1-to-16 lvcmos/lvttl clock generator 87016I 87016I rev c 3/23/15 1 ?2015 integrated device technology, inc. description the 87016I is a low skew, 1:16 lvcmos/lvttl clock generator. the device has four banks of four outputs and each bank can be independently selected for ? 1 or ? 2 frequency operation. each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3v, 2.5v, and 1.8v. the low impedance lvcmos/lvttl outputs are designed to drive 50 ? series or parallel terminated transmission lines. the divide select inputs, div_ sela:div_seld, control the output frequency of each bank. the out put banks can be independently selected for ? 1 or ? 2 operation. the bank enable inputs, clk_ena:clk_end, support enabling and disabling each bank of outputs individually. the clk_ena:clk_end circuitry has a synchronizer to prevent runt pulses when enabling or disabling the clock outputs. the master reset input, mr/oe , resets the ? 1/ ? 2 flip flops and also controls the active and high impedance states of all outputs. this pin has an internal pul l-up resistor and is normally used only for test purposes or in systems which use low power modes. the 87016I is characterized to operat e with the core at 3.3v or 2.5v and the banks at 3.3v, 2.5v, or 1.8v. guaranteed bank, output, and part-to-part skew characteristics make the 87016I ideal for those clock applications demanding well-defined performance and repeatability. features ? sixteen lvcmos/lvttl outputs (4 banks of 4 outputs) ? selectable differential clk1/clk1 or lvcmos/lvttl clock input ? clk1, clk1 pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? clk0 supports the following input types: lvcmos, lvttl ? maximum output frequency: 250mhz ? independent bank control for 1 or 2 operation ? independent output bank voltage setti ngs for 3.3v, 2.5v, or 1.8v operation ? asynchronous clock enable/disable ? output skew: 170ps (maximum) ? bank skew: 50ps (maximum ? part-to-part skew: 800ps (maximum) ? supply modes: core/output 3.3v/3.3v 3.3v/2.5v 3.3v/1.8v 2.5v/2.5v 2.5v/1.8v ? -40c to 85c ambient operating temperature ? lead-free packaging block diagram pin assignment 87016I 48-lead lqfp 7mm x 7mm x 1.4mm package body y package top view mr/oe clk0 clk1 clk1 clk_sel div_sela div_selb div_selc div_seld clk_ena clk_enb clk_enc clk_end qa0:qa3 qb0:qb3 qc0:qc3 qd0:qd3 0 1 1 0 1 0 1 0 1 0 1 2 4 4 4 4 le le le le d d d d 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 v dd clk0 div_sela div_selb div_selc div_seld clk_ena clk_enb clk_enc clk_end mr/oe gnd gnd qb0 v ddob qb1 gnd qb2 v ddob qb3 gnd qc0 v ddoc qc1 qd3 v ddod qd2 gnd qd1 v ddod qd0 gnd qc3 v ddoc qc2 gnd clk1 clk1 clk_sel gnd qa0 v ddoa qa1 gnd qa2 v ddoa qa3 v dd 48 47 46 45 44 43 42 41 40 39 38 37
rev c 3/23/15 2 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1, 48 v dd power positive supply pins. 2 clk0 input pulldown single-ended clock inpu t. lvcmos/lvttl interface levels. 3 div_sela input pullup controls frequency division for bank a outputs. see table 3. lvcmos / lvttl interface levels. 4 div_selb input pullup controls frequency division for bank b outputs. see table 3. lvcmos / lvttl interface levels. 5 div_selc input pullup controls frequency division for bank c outputs. see table 3. lvcmos / lvttl interface levels. 6 div_seld input pullup controls frequency division for bank d outputs. see table 3. lvcmos / lvttl interface levels. 7 clk_ena input pullup output enable for bank a outputs. acti ve high. if pin is low, outputs drive low. lvcmos/lvttl interface levels. see table 3. 8 clk_enb input pullup output enable for bank a outputs. acti ve high. if pin is low, outputs drive low. lvcmos/lvttl interface levels. see table 3. 9 clk_enc input pullup output enable for bank a outputs. acti ve high. if pin is low, outputs drive low. lvcmos/lvttl interface levels. see table 3. 10 clk_end input pullup output enable for bank a outputs. acti ve high. if pin is low, outputs drive low. lvcmos/lvttl interface levels. see table 3. 11 mr/oe input pullup master reset. when low, resets the 1/ 2 flip flops and sets the outputs to high impedance. lvcmos / lvttl interface levels. 12, 16, 20, 24, 28, 32, 36, 40, 44 gnd power power supply ground 13, 15, 17, 19 qd3, qd2, qd1, qd0 output bank d single-ended clock outputs. lvcmos/lvttl interface levels. 14, 18 v ddod power bank d output supply pins. 21, 23, 25, 27 qc3, qc2, qc1, qc0 output bank c single-ended clock outputs. lvcmos/lvttl interface levels. 22, 26 v ddoc power bank c output supply pins. 29, 31, 33, 35 qb3, qb2, qb1, qb0 output bank c single-ended clock outputs. lvcmos/lvttl interface levels. 30, 34 v ddob power bank b output supply pins. 37, 39, 41, 43 qa3, qa2, qa1, qa0 output bank a single-ended clock outputs. lvcmos/lvttl interface levels. 38, 42 v ddoa power bank b output supply pins. 45 clk_sel input pulldown clock select input. when high, selects clk1, clk1 inputs. when low, selects clk0 input. lvcmos / lvttl interface levels. 46 clk1 input pullup inverting differential clock input. 47 clk1 input pulldown non-inverting differential clock input.
rev c 3/23/15 3 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet table 2. pin characteristics note 1: v ddox denotes v ddoa, v ddob, v ddoc, v ddod. function tables table 3. function table symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? c pd power dissipation capacitance (per output); note 1 v dd, v ddox = 3.465v 18 pf v dd, v ddox = 2.625v 12 pf v dd = 3.465v, v ddox = 2.625v 20 pf v dd = 3.465v, v ddox = 1.89v 30 pf v dd = 2.625v, v ddox = 1.89v 14 pf r out output impedance 5 7 12 ? inputs outputs mr/oe clk_enx div_selx bank [a:d] qx frequency 0xxhi-zn/a 1 1 0 active fin/2 111activefin 10xlown/a
rev c 3/23/15 4 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or an y conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating condit ions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, v ddox = 3.3v 5%, 2.5v 5%, 1.8v 5%, t a = -40c to 85c table 4b. power supply dc characteristics, v dd = 2.5v 5%, v ddox = 2.5v 5%, 1.8v 5%, t a = -40c to 85c item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd ox + 0.5v package thermal impedance, ? ja 47.9 ? c/w (0 lfpm) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v v ddoa, v ddob, v ddoc, v ddod output supply voltage 3.135 3.3 3.465 v 2.375 2.5 2.625 v 1.71 1.8 1.89 v i dd power supply current 100 ma i ddoa, i ddob, i ddoc, i ddod output supply current 15 ma symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v v ddoa, v ddob, v ddoc, v ddod output supply voltage 2.375 2.5 2.625 v 1.71 1.8 1.89 v i dd power supply current 95 ma i ddoa, i ddob, i ddoc, i ddod output supply current 8ma
rev c 3/23/15 5 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet table 4c. lvcmos/lvttl dc characteristics, t a = -40c to 85c note 1: outputs terminated with 50 ? to v ddox /2. see parameter measurement information, output load test circuit diagrams. table 4d. differential dc characteristics, t a = -40c to 85c note 1: common mode input voltage is defined as v ih . note 2: for single-ended applications, the maximum input voltage for clk1, clk1 is v dd + 0.3v. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 3.465v 2 v dd + 0.3 v v dd = 2.625v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.465v -0.3 0.8 v v dd = 2.625v -0.3 0.7 v i ih input high current clk0, clk_sel v dd = v in = 3.465v or 2.625v 150 a clk_en[a:d], div_sel[a:d], mr/oe v dd = v in = 3.465v or 2.625v 5 a i il input low current clk0, clk_sel v dd = 3.465v or 2.625v, v in = 0v -5 a clk_en[a:d], div_sel[a:d], mr/oe v dd = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage; note 1 v ddox = 3.3v 5% 2.6 v v ddox = 2.5v 5% 1.8 v v ddox = 1.8v 5%; i oh = -2ma v ddox ? 0.45 v v ol output low voltage; note 1 v ddox = 3.3v 5% 0.5 v v ddox = 2.5v 5% 0.5 v v ddox = 1.8v 5%; i oh = 2ma 0.45 v i ozl output hi-z current low -5 a i ozh output hi-z current high 5a symbol parameter test conditio ns minimum typical maximum units i ih input high current clk1 v dd = v in = 3.465v or 2.625v 5 a clk1 v dd = v in = 3.465v or 2.625v 150 a i il input low current clk1 v dd = 3.465v or 2.625v, v in = 0v -150 a clk1 v dd = 3.465v or 2.625v, v in = 0v -5 a v pp peak-to-peak voltage 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v
rev c 3/23/15 6 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet ac electrical characteristics table 5a. ac characteristics, v dd = v ddox = 3.3v 5%, t a = -40c to 85c all parameters measured at 250 mhz unless noted otherwise. note 1a: measured from the v dd /2 of the input to v ddox /2 of the output. note 1b: measured from the differential input crossing point to v ddox /2 of the output. note 2: defined as skew within a bank with equal load conditions. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddox /2. note 4: defined as skew between outputs on different devices operating a the same supply voltages and with equal load condition s. using the same type of input on each device, the output is measured at v ddox /2. note 5: these parameters are guaranteed by characterization. not tested in production. note 6: this parameter is defined in accordance with jedec standard 65. table 5b. ac characteristics, v dd = v ddox = 2.5v 5%, t a = -40c to 85c for notes, please see above, table 5a. parameter symbol test conditio ns minimum typical maximum units f max output frequency 250 mhz tp lh propagation delay, low to high clk0; note 1a 2.8 3.4 3.9 ns clk1/clk1 ; note 1b 2.75 3.4 4.1 ns t sk(b) bank skew; note 2, 6 m easured on the rising edge 50 ps t sk(o) output skew; note 3, 6 measured on the rising edge 170 ps t sk(pp) part-to-part skew; note 4, 6 800 ps t r / t f output rise/fall time; note 5 20% to 80% 200 700 ps odc output duty cycle ? < 175mhz 45 55 % ? ? 175mhz 40 60 % t en output enable time; note 5 10 ns t dis output disable time; note 5 10 ns parameter symbol test conditio ns minimum typical maximum units f max output frequency 250 mhz tp lh propagation delay, low to high clk0; note 1a 2.9 3.8 4.7 ns clk1/clk1 ; note 1b 3.0 3.6 4.3 ns t sk(b) bank skew; note 2, 6 m easured on the rising edge 70 ps t sk(o) output skew; note 3, 6 measured on the rising edge 210 ps t sk(pp) part-to-part skew; note 4, 6 800 ps t r / t f output rise/fall time; note 5 20% to 80% 150 700 ps odc output duty cycle ? ? 125mhz 40 60 % t pw output pulse width ? > 125mhz t period /2 ? 800 t period /2 + 800 ps t en output enable time; note 5 10 ns t dis output disable time; note 5 10 ns
rev c 3/23/15 7 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet table 5c. ac characteristics, v dd = 3.3v 5%, v ddox = 2.5v 5%, t a = -40c to 85c all parameters measured at 250 mhz unless noted otherwise. note 1a: measured from the v dd /2 of the input to v ddox /2 of the output. note 1b: measured from the differential input crossing point to v ddox /2 of the output. note 2: defined as skew within a bank with equal load conditions. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddox /2. note 4: defined as skew between outputs on different devices operating a the same supply voltages and with equal load condition s. using the same type of input on each device, the output is measured at v ddox /2. note 5: these parameters are guaranteed by characterization. not tested in production. note 6: this parameter is defined in accordance with jedec standard 65. table 5d. ac characteristics, v dd = 3.3v 5%, v ddox = 1.8v 5%, t a = -40c to 85c for notes, please see above, table 5c. parameter symbol test conditio ns minimum typical maximum units f max output frequency 250 mhz tp lh propagation delay, low to high clk0; note 1a 2.9 3.5 4.0 ns clk1/clk1 ; note 1b 3.0 3.5 4.0 ns t sk(b) bank skew; note 2, 6 measured on the rising edge 50 ps t sk(o) output skew; note 3, 6 measured on the rising edge 170 ps t sk(pp) part-to-part skew; note 4, 6 800 ps t r / t f output rise/fall time; note 5 20% to 80% 200 700 ps odc output duty cycle ? < 175mhz 45 55 % ? ? 175mhz 40 60 % t en output enable time; note 5 10 ns t dis output disable time; note 5 10 ns parameter symbol test conditio ns minimum typical maximum units f max output frequency 250 mhz tp lh propagation delay, low to high clk0; note 1a 3.0 3.9 4.7 ns clk1/clk1 ; note 1b 3.0 3.9 4.7 ns t sk(b) bank skew; note 2, 6 measured on the rising edge 50 ps t sk(o) output skew; note 3, 6 measured on the rising edge 170 ps t sk(pp) part-to-part skew; note 4, 6 800 ps t r / t f output rise/fall time; note 5 20% to 80% 200 700 ps odc output duty cycle ? < 175mhz 45 55 % ? ? 175mhz 40 60 % t en output enable time; note 5 10 ns t dis output disable time; note 5 10 ns
rev c 3/23/15 8 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet table 5e. ac characteristics, v dd = 2.5v 5%, v ddox = 1.8v 5%, t a = -40c to 85c all parameters measured at 250 mhz unless noted otherwise. note 1a: measured from the v dd /2 of the input to v ddox /2 of the output. note 1b: measured from the differential input crossing point to v ddox /2 of the output. note 2: defined as skew within a bank with equal load conditions. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddox /2. note 4: defined as skew between outputs on different devices operating a the same supply voltages and with equal load condition s. using the same type of input on each device, the output is measured at v ddox /2. note 5: these parameters are guaranteed by characterization. not tested in production. note 6: this parameter is defined in accordance with jedec standard 65. parameter symbol test conditio ns minimum typical maximum units f max output frequency 250 mhz tp lh propagation delay, low to high clk0; note 1a 3.1 4.1 5.2 ns clk1/clk1 ; note 1b 3.0 3.9 4.7 ns t sk(b) bank skew; note 2, 6 measured on the rising edge 70 ps t sk(o) output skew; note 3, 6 measured on the rising edge 210 ps t sk(pp) part-to-part skew; note 4, 6 800 ps t r / t f output rise/fall time; note 5 20% to 80% 150 700 ps odc output duty cycle ? < 175mhz 45 55 % ? ? 175mhz 40 60 % t en output enable time; note 5 10 ns t dis output disable time; note 5 10 ns
rev c 3/23/15 9 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet parameter measureme nt information 3.3v core/3.3v lvcmos output load test circuit 3.3v core/2.5v lvcmos output load test circuit 2.5v core/1.8v lvcmos output load test circuit 2.5v core/2.5v lvcmos output load test circuit 3.3v core/1.8v lvcmos output load test circuit differential input level scope qx gnd v dd, 1.65v5% -1.65v5% v ddo scope qx gnd v ddo v dd 1.25v5% -1.25v5% 2.05v5% scope qx gnd v ddo v dd 0.9v5% 1.6v0.9v -0.9v5% scope qx gnd v dd, 1.25v5% -1.25v5% v ddo scope qx gnd v dd v ddo 0.9v5% 2.4v0.9v -0.9v5% v dd gnd v cmr cross points v pp clk1 clk1
rev c 3/23/15 10 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet parameter measurement in formation, continued output skew propagation delay output rise/fall time part-to-part skew output duty cycle/pulse width/period t sk(o) v ddx 2 v ddx 2 qx qy tp lh v ddo 2 v dd 2 clk1 clk1 qa0:qa3, qb0:qb3, qc0:qc3, qd0:qd3 clk0 clock outputs 20% 80% 80% 20% t r t f t sk(pp) v ddox 2 v ddox 2 part 1 part 2 qx qy part 1 part 2 t period t pw t period odc = v ccox 2 x 100% t pw qa0:qa3, qb0:qb3, qc0:qc3, qd0:qd3
rev c 3/23/15 11 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet application information wiring the differential input to accept single ended levels figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. fo r example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 1. single-ended signal driving differential input recommendations for unused input and output pins inputs: clk/clk inputs: for applications not requiring the us e of the differential input, both clk and clk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. clk input: for applications not requiring the us e of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk input to ground. lvcmos control pins: all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs: all unused lvcmos output can be left floating. there should be no trace attached. v_ref single ended clock input v dd clk nclk r1 1k c1 0.1u r2 1k
rev c 3/23/15 12 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet differential clock input interface the clk /clk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the clk/clk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. clk/clk input driven by an idt lv h s t l d r i v e r figure 2c. clk/clk input driven by a 3.3v lvpecl driver figure 2e. clk/clk input driven by a 3.3v lvpecl driver with ac couple figure 2b. clk/clk input driven by a 3.3v lvpecl driver figure 2d. clk/clk input driven by a 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input
rev c 3/23/15 13 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet reliability information table 6. ? ja vs. air flow table for a 48 lead lqfp note: most modern pcb design use multi-layered boards. the data in the second row pertains to most designs. transistor count the transistor count for 87016I is: 2034 ? ja vs. air flow linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard te st boards 47.9c/w 42.1c/w 39.4c/w
rev c 3/23/15 14 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet package outline and package dimension package outline - y suffix for 48 lead lqfp table 7. package dimensions for 48 lead lqfp reference document: jedec publication 95, ms-026 jedec variation: abc - hd all dimensions in millimeters symbol minimum nominal maximum n 48 a 1.20 a1 0.05 0.10 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.50 ref. d3 & e3 2.0 7.0 e 0.5 basic l 0.45 0.60 0.75 ? 0 7 ccc 0.08 -h d v ersion expo sed pad do w n - t ab, expo sed part of c o nn ection bar or ti e ba r 0.20 t ab
rev c 3/23/15 15 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet ordering information table 8. ordering information part/order number marking package shipping packaging temperature ics87016ayilf ics87016ayil ?lead-free? 48 lead lqfp tray -40 ? c to 85 ? c ics87016ayilft ics87016ayil ?lead-free? 48 lead lqfp tape & reel -40 ? c to 85 ? c
rev c 3/23/15 16 low skew, 1-to-16 lvcmos/lvttl clock generator 87016I data sheet revision history sheet rev table page description of change date b t2 t4b t4c t4d t5b t5e 1 3 4 5 5 6 8 9 11 15 features section - added 2.5v/2.5v and 2.5v/1.8v to supply mode bullet. added lead-free bullet pin characteristics table - added 2.5v/2.5v and 2.5v/1.8v to c pd . added 2.5v power supply dc characteristics table. lvcmos dc characteristics table - added 2.5v to v ih /v il . differential dc characteristic s table - added 2.5v to i ih /i il . added 2.5v power supply dc characteristics table. added 2.5v/1.8v power supply dc characteristics table. parameter measurement information - added 2.5v core/2.5v output load test circuit and 2.5v core/1.8v output load test circuit diagrams. added recommendations for unused input and output pins. ordering information table - added lead-free order/part number. 3/30/07 ct5b6 2.5v ac characteristics table - changed output duty cycle test condition and limits. added output pulse width. 5/25/07 c t8 15 remove leaded parts from ordering information table 11/15/12 c 4c 5 corrected typo, voh: v dd ? 0.45 to v ddox ? 0.45 3/28/13 c t8 15 ordering information - updated part marking. updated data sheet format. 3/23/15
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this produ ct is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

▲Up To Search▲

Price & Availability of 87016I

	To Download 87016I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .