View HVLED815PFTR_8342454.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. february 2014 docid023409 rev 5 1/34 hvled815pf offline led driver with primary-sensing and high power factor up to 15 w datasheet - production data features ? high power factor capability (> 0.9) ? 800 v, avalanche rugged internal 6 ? power mosfet ? internal high voltage startup ? primary sensing regulation (psr) ? 3% accuracy on constant led output current ? quasi-resonant (qr) operation ? optocoupler not needed ? open or short led string management ? automatic self supply applications ? ac-dc led driver bulb replacement lamps up to 15 w, with high power factor ? ac-dc led drivers up to 15 w description the hvled815pf device is a high voltage primary switcher intended for operating directly from the rectified main s with minimum external parts and enabling high power factor (> 0.90) to provide an efficient, compact and cost effective solution for led driving. it combines a high- performance low voltage pwm controller chip and an 800 v, avalanche rugged power mosfet, in the same package. there is no need for the optocoupler thanks to the patented primary sensing regulation (psr) technique. the device assures protection against led string fault (open or short). so16n table 1. device summary order code package packaging hvled815pf so16n tube HVLED815PFTR tape and reel www.st.com
contents hvled815pf 2/34 docid023409 rev 5 contents 1 principle application circuit and block diag ram . . . . . . . . . . . . . . . . . . . 4 1.1 principle application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 high voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 secondary side demagnetization detection and triggering block . . . . . . . 17 4.5 constant current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 constant voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.7 voltage feedforward block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.8 burst mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 24 4.9 soft-start and starter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.10 hiccup mode ocp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.11 high power factor implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.12 layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
docid023409 rev 5 3/34 hvled815pf list of figures 34 list of figures figure 1. application circuit for high power factor led driv er - single range input. . . . . . . . . . . . . . . . 4 figure 2. application circuit for standard led driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. off-state drain and source current test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. c oss output capacitance variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. startup current test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. quiescent curren t test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. operating supply current test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. quiescent current during fault te st circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. multi-mode operation of hvled815pf (constant voltage operation) . . . . . . . . . . . . . . . . . 15 figure 12. high voltage start-up generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. timing diagram: normal power-up and power-dow n sequences . . . . . . . . . . . . . . . . . . . . 17 figure 14. dmg block, triggering block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15. drain ringing cycle skipping as the load is pr ogressively reduced . . . . . . . . . . . . . . . . . . . 18 figure 16. current control principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 17. constant current operation: switching cycle wavefo rms . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 18. voltage control principle: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 figure 19. feedforward compensation: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 20. load-dependent operating modes: timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 21. hiccup mode ocp: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 figure 22. high power factor implementation connection - single range input . . . . . . . . . . . . . . . . . . 27 figure 23. suggested routing for the led driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 24. so16n package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 25. so16n recommended footprint (dimensions are in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
principle application circuit and block diagram hvled815pf 4/34 docid023409 rev 5 1 principle application circuit and block diagram 1.1 principle application circuit figure 1. application circui t for high power factor led driver - single range input cin c12 cout bulk cs rpf csnubber t1 transformer 4 5 6 3 1 10 2 7 9 8 rsnubber s nubber diode na rdmg r12 minimum load d5 vin c_iled (10uf) lf lf cf rf rb rf j1 con1 vcc j3 con1 emi filter rf b cf cs dmg cs j2 con1 j4 con1 f1 1a_dip d4 u1 hvled8xxpf source 1 iled 5 cs 2 gnd 4 dmg 6 vcc 3 comp 7 n.a. 8 drain 13 drain 14 drain 15 drain 16 dmg cf (330nf-680nf) rf (8k-15k) c_vcc (10uf min) cp (1n-10nf) o utpout diode c10 y1 - safety vout vcc 220pf-1nf ra r1 (500 - 1.5k) c13 cout smd ros cos filter (1uf) cin - + bridge diode 2 1 3 4 d2 1n4148 r-vcc (10-100ohm) c_vcc (470nf) vin rsense rsense lin am13207v1
hvled815pf principle application circuit and block diagram docid023409 rev 5 5/34 figure 2. application circuit for standard led driver c16 cout bulk csnubber t2 tr an sf or mer 4 5 6 3 1 10 2 7 9 8 rsnubber s nubber diode na rdmg r18 minimum load c_iled (10uf) lf lf cf rf rf j5 con1 vcc j6 con1 emi filter rf b cf dmg j7 con1 j8 con1 f2 1a_dip u2 hvled8xxpf source 1 iled 5 cs 2 gnd 4 dmg 6 vcc 3 comp 7 n.a. 8 drain 13 drain 14 drain 15 drain 16 dmg cf (330nf/680nf) rf (8.2k-15k) c_vcc (10uf) cp (1nf/10nf) o utpout diode1 c23 y1 - safety vout vcc c27 cout smd cin - + bridge diode 2 1 3 4 d8 1n4148 r-vcc (10ohm) c_vcc (470nf) vin rsense rsense am13208v1
principle application circuit and block diagram hvled815pf 6/34 docid023409 rev 5 1.2 block diagram figure 3. block diagram 3.3 v dmg source + vin vref drain driving logic comp demag logic gnd iled protection & feedforward logic viled 1 v hv start-up & supply logic r fb r dmg r sense r comp c comp c led vcc cs constant voltage regulation ocp constant current regulation vref led r pf r os r a r 1 vcs am13209v1
docid023409 rev 5 7/34 hvled815pf pin description and connection diagrams 34 2 pin description and connection diagrams figure 4. pin connection (top view) 2.1 pin description n.a. n.a. n.a. source drain cs gnd iled dmg comp vcc drain drain drain n.a. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 n.c. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 d r a i n d r a i n d r a i n d r a i n am13210v1 table 2. pin description no. name function 1 source source connection of the internal power section. 2cs current sense input. connect this pin to the source pin (through an r 1 resistor) to sense the current flowing in the mosfet through an r sense resistor connected to gnd. the cs pin is also connected through dedicated r os , r pf resistors to the input and auxiliary voltage, in order to modulate the input current flowing in the mosfet accordin g to the input voltage and therefore achieving a high power factor. see section 4.11: high power factor implementation on page 26 for more details. the resulting voltage is compared with the voltage on the iled pin to determine mosfet turn- off. the pin is equipped with 250 ns blanking ti me after the gate drive output goes high for improved noise immunity. if a second comparison level located at 1 v is exceeded, the ic is stopped and restarted after v cc has dropped below 5 v. 3vcc supply voltage of the device. a capacitor, connected between this pin and ground, is initially charged by the internal high voltage startup generator; when the device is ru nning, the same generator keeps it charged in case the voltage supplied by the auxiliary winding is not sufficient. this feature is disabled in case a protection is tripped. a small bypass capacitor (100 nf typ.) to gnd may be useful to get a clean bias voltage for the signal part of the ic.
pin description and connection diagrams hvled815pf 8/34 docid023409 rev 5 2.2 thermal data 4gnd ground. current return for both the signal part of th e ic and the gate drive. all of the ground connections of the bias components should be tied to a trace going to this pin and kept separate from any pulsed current return. 5iled constant current (cc) regulat ion loop reference voltage. an external capacitor c led is connected between this pin and gnd. an internal circuit develops a voltage on this capacitor that is used as the reference for the mosfet?s peak drain current during cc regulation. the voltage is aut omatically adjusted to keep the average output current constant. 6dmg transformer demagnetization sensing for quasi-re sonant operation and output voltage monitor. a negative-going edge triggers the mosfet turn -on, to achieve quasi-resonant operation (zero voltage switching). the pin voltage is also sampled-and-held right at the end of transformer demagnetization to get an accurate image of the output voltage to be fed to the inverting input of the internal, transconductance-type, error amplifier, whose non- inverting input is referenced to 2.5 v. the maximum i dmg sunk/sourced current must not exceed 2 ma (amr) in all the v in range conditions. no capacitor is allowed between the pin and the auxiliary transformer. 7comp output of the internal transconductance error amplifier. the compensation network is placed between this pin and gnd to achieve stability and good dynamic performance of the voltage control loop. 8 n. a. not available. these pi ns must be connected to gnd. 9 - 11 n. a. not available. these pins must be left not connected. 12 n. c. not internally connected. provision for cl earance on the pcb to meet safety requirements. 13 - 16 drain drain connection of the internal power section. the internal high voltage startup generator sinks current from this pin as well. pins connected to the internal metal frame to facilitate heat dissipation. table 2. pin description (continued) no. name function table 3. thermal data symbol parameter max. value unit r thjp thermal resistance, junction to pin 10 c/w r thja thermal resistance, junction to ambient 110 c/w p tot maximum power dissipation at t a = 50 c 0.9 w t stg storage temperature range -55 to 150 c t j junction temperature range -40 to 150 c
docid023409 rev 5 9/34 hvled815pf electrical specifications 34 3 electrical specifications 3.1 absolute maximum ratings 3.2 electrical characteristics table 4. absolute maximum ratings symbol pin parameter value unit v ds 1, 13 - 16 drain-to-source (ground) voltage -1 to 800 v i d 1, 13 - 16 drain current (1) 1a eav 1, 13 - 16 single pulse avalanche energy (t j = 25 c, i d = 0.7 a) 50 mj v cc 3 supply voltage (i cc < 25 ma) self limiting v i dmg 6 zero current detector current 2 ma v cs 2 current sense analog input -0.3 to 3.6 v v comp 7 analog input -0.3 to 3.6 v 1. limited by maximum temperature allowed. table 5. electrical characteristics (1) (2) symbol parameter test condition min. typ. max. unit power section v (br)dss drain-source breakdown i d < 100 a; t j = 25 c 800 v i dss off-state drain current v ds = 750 v; t j = 125 c (3) see figure 5 80 a r ds(on) drain-source on-state resistance i d = 250 ma; t j = 25 c 6 7.4 ? i d = 250 ma; t j = 125 c (3) 14.8 c oss effective (energy related) output capacitance (3) see figure 6 high voltage startup generator v start min. drain start voltage i charge < 100 a 40 50 60 v i charge v cc startup charge current v drain > v start ; v cc < v ccon t j = 25 c 45.57 ma v drain > v start ; v cc electrical specifications hvled815pf 10/34 docid023409 rev 5 v cc_off turn-off threshold (4) 91011v v z internal zener voltage i cc = 20 ma 23 25 27 v supply current i cc_start-up startup current see figure 7 200 300 a iq quiescent current see figure 8 11.4ma i cc operating supply current at 50 khz see figure 9 1.4 1.7 ma iq (fault) fault quiescent current see figure 10 250 350 a startup timer t start start timer period 105 140 175 s t restart restart timer period during burst mode 420 500 700 s demagnetization detector i dmgb input bias current v dmg = 0.1 to 3 v 0.1 1 a v dmgh upper clamp voltage i dmg = 1 ma 3.0 3.3 3.6 v v dmgl lower clamp voltage i dmg = - 1 ma -90 -60 -30 mv v dmga arming voltage positive-going edge 100 110 120 mv v dmgt triggering voltage negative-going edge 50 60 70 mv t blank trigger blanking time after mosfet turn-off v comp ? 1.3 v 6 s v comp = 0.9 v 30 line feedforward r ff equivalent feedforward resistor i dmg = 1 ma 45 ? transconductance error amplifier v ref voltage reference t j = 25 c 2.45 2.51 2.57 v (3) t j = -25 to 125 c and v cc = 12 v to 23 v 2.4 2.6 gm transconductance ? i comp = 10 a v comp = 1.65 v 1.3 2.2 3.2 ms gv voltage gain (5) open loop 73 db gb gain-bandwidth product (5) 500 khz i comp source current v dmg = 2.3 v, v comp = 1.65 v 70 100 a sink current v dmg = 2.7 v, v comp = 1.65 v 400 750 a v comph upper comp voltage v dmg = 2.3 v 2.7 v v compl lower comp voltage v dmg = 2.7 v 0.7 v v compbm burst mode threshold 1 v hys burst mode hysteresis 65 mv table 5. electrical characteristics (1) (2) (continued) symbol parameter test condition min. typ. max. unit
docid023409 rev 5 11/34 hvled815pf electrical specifications 34 figure 5. off-state drain and source current test circuit note: the measured i dss is the sum between the current across the startup resistor and the effective mosfet?s off-state drain current. current reference v iledx maximum value v comp = v compl 1.5 1.6 1.7 v v cled current reference voltage (6) v iled = 0.41 v, v dmg = 0 v; t j = 25 c 207.76 212 216.24 mv current sense t leb leading-edge blanking (5) 330 ns t d delay-to-output (h-l) 90 200 ns v csx max. clamp value (4) dvcs/dt = 200 mv/s 0.7 0.75 0.8 v v csdis hiccup mode ocp level (4) 0.92 1 1.08 v 1. v cc = 14 v (unless otherwise specified). 2. limits are production tested at t j = t a = 25 c, and are guaranteed by stat istical characterization in the range t j -25 to +125 c. 3. not production tested, guaranteed statistical characterization only. 4. parameters tracking each other (in the same section). 5. guaranteed by design. 6. production tested only. table 5. electrical characteristics (1) (2) (continued) symbol parameter test condition min. typ. max. unit 2.5v comp source dr ain vdd + - cu rr ent control iled gnd dm g cs vin 750v a idss 14v am13211v1
electrical specifications hvled815pf 12/34 docid023409 rev 5 figure 6. c oss output capacitance variation figure 7. startup current test circuit figure 8. quiescent current test circuit & rvv >s)@ 9gv>9@ $0y 11.8 v a iccstart-up 2.5v com p sour ce drain vdd + - cu rr ent con tr ol iled gnd dm g cs am13213v1 14v a iq_meas 0.2v 3v 33k 0.8v 10k 2.5v comp source drain vdd + - cu rr ent control iled gnd dm g cs am13214v1
docid023409 rev 5 13/34 hvled815pf electrical specifications 34 figure 9. operating supply current test circuit note: the circuit across the dmg pin is used for switch on synchronization. figure 10. quiescent current during fault test circuit 15v 150v a icc -5v 10k 2.8v 5.6 2.5v comp source drain vdd + - cu rr ent control iled gnd dm g cs 1.5k 2w 220k 27k 10k 50 khz 10 am13215v1 a iq(fault) 14v 2.5v com p sour ce drain vdd + - cu rr ent con tr ol iled gnd dm g cs am13216v1
device description hvled815pf 14/34 docid023409 rev 5 4 device description the hvled815pf device is a high voltage primary switcher intended for operating directly from the rectified mains with minimum external parts to provide high power factor (> 0.90) and an efficient, compact and cost effective solution for led drivin g. it combines a high- performance low voltage pwm controller chip and an 800 v, avalanche rugged power mosfet, in the same package. the pwm is a current mode controller ic sp ecifically designed for zvs (?zero voltage switching?) flyback led drivers, with constant output current (cc) regulation using primary sensing feedback (psr). this eliminates the need for the optocoupler, the secondary voltage reference, as well as the current sense on the secondary side, while still maintaining a good led current accuracy. moreover, it guarantees a safe operation when short-circuit of one or more leds occurs. the device can also provide a constant output voltage regulation (cv): it allows the application to be able to work safely when the led string opens due to a failure. in addition, the device offers the shorted sec ondary rectifier (i.e. led string shorted due to a failure) or transformer saturation detection. quasi-resonant operation is achieved by mean s of a transformer demagnetization sensing input that triggers mosfet turn -on. this input serves also as both output voltage monitor, to perform cv regulation, and input voltage monitor, to achieve mains-independent cc regulation (line voltage feedforward). the maximum switching frequency is top limite d below 166 khz, so that at medium-light load a special function automati cally lowers the operating fr equency while still maintaining the operation as close to zvs as possible. at very light load, the device enters a controlled burst mode operation that, along with the built-in high voltage startup circuit and the low operating current of the device, helps mi nimize the residual input consumption. although an auxiliary winding is required in the transformer to corr ectly perform cv/cc regulation, the chip is able to power itself directly from the re ctified mains. this is useful especially during cc regulation, where the flyback voltage generated by the winding drops. 4.1 application information the device is an off-line led driver with all-primary sensing, based on quasi-resonant flyback topology, with high powe r factor capability. in particul ar, using different application schematic the device is able to provide a co mpact, efficient and cost-effective led driver solution with high power factor (pf > 0.9 - see application schematic in figure 1 on page 4 ) or with standard power factor (pf > 0. 5/0.6 - see application schematic in figure 2 on page 5 ), based on the specific application requirements. referring to the application schematic in figure 1 , the ic modulates the input current according to the input voltage providing the hi gh power factor capabilit y (pf > 0.9) keeping a good line regulation. this application schem atic is intended for a single range input voltage. for wide range application a different reference schematic can be used; refer to an4346 application note for further details.
docid023409 rev 5 15/34 hvled815pf device description 34 moreover, the device is able to work in different modes depending on the led's driver load condition (see figure 11 ): 1. qr mode at heavy load. quasi-resonant operation lies in synchronizing mosfet's turn-on to the transformer's demagnetizatio n by detecting the resulting negative-going edge of the voltage across any winding of the transformer. then the system works close to the boundary between discontin uous (dcm) and continuous conduction (ccm) of the transformer. as a result, the sw itching frequency is different for different line/load conditions (see the hyperb olic-like portion of the curves in figure 11 ). minimum turn-on losses, low emi emission a nd safe behavior in short-circuit are the main benefits of this kind of operation. 2. valley-skipping mode at medium/ light load. depending on voltage on comp pin, the device defines the maximum operating frequency of the converter. as the load is reduced, mosfet's turn-on does not occur any more on the first valley but on the second one, the third one and so on. in this way the switching frequency is no longer increased (piecewise linear portion in figure 11 ). 3. burst mode with no or very light load. when the load is extremely light or disconnected, the converter enters a controlled on/off operation with constant peak current. decreasing the load result in frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequen cy-related losses and making it easier to comply with energy saving regulations or recommendations. being the peak current very low, no issue of audible noise arises. figure 11. multi-mode operation of hvled815pf (constant voltage operation) 4.2 power section and gate driver the power section guarantees safe avalanche op eration within the specified energy rating as well as high dv/dt capability. the power mosfet has a v dss of 800 v min. and a typical r ds(on) of 6 ? . the internal gate driver of the power mosf et is designed to supply a controlled gate current during both turn-on and turn-off in order to minimize common mode emi. under uvlo conditions an internal pull-down circuit hol ds the gate low in order to ensure that the power mosfet cannot be turned on accidentally. am13561v1 0 f sw pinmax input voltage p in f osc burst-mode valley-skipping mode quasi-resonant mode
device description hvled815pf 16/34 docid023409 rev 5 4.3 high voltage startup generator figure 12 shows the internal schematic of the high voltage start-up generator (hv generator). it includes an 800 v-rated n-channel mosfet, whose gate is biased through the series of a 12 m ? resistor and a 14 v zener diode, with a controlled, temperature compensated current generator connected to its source. the hv generator input is in common with the dr ain pins, while its output is the supply pin of the device (vcc pin). a mains ?uvlo? circ uit (separated from the uvlo of the device that sense vcc) keeps the hv generator off if the drain voltage is below v start (50 v typical value). figure 12. high voltage start-up generator: internal schematic with reference to the timing diagram of figure 13 , when power is applied to the circuit and the voltage on the input bulk capacitor is hi gh enough, the hv generator is sufficiently biased to start operating, thus it will draw about 5.5 ma (typical) to the v cc capacitor. most of this current will charge the bypass capacitor connected be tween the vcc pin and ground and make its voltage rise linearly. as soon as the vcc pin voltage reaches the v cc_on turn on threshold (13 v typ.) the chip starts operating, the internal power mosfet is enabled to switch and the hv generator is cut off by the vcc_ok signal asserted high. the ic is powered by the energy stored in the v cc capacitor. the chip is able to power itself directly from the rectified mains: when the voltage on the vcc pin falls below v cc_restart (10.5 v typ.), during each mosfet's off-time the hv current generator is turned on and charges the supply capacitor until it reaches the v cc_on threshold. in this way, the self-supply circuit develops a vo ltage high enough to sustain the operation of the device. this feature is useful especially during constant current (cc) regulation, when the flyback voltage generated by the auxiliary winding alone may not be able to keep vcc pin above v cc_restart . am13562v1 vcc icharge control mains u vlo ihv drain 12m hv_en vcc_ok 14v gnd
docid023409 rev 5 17/34 hvled815pf device description 34 figure 13. timing diagram: normal power-up and power-down sequences 4.4 secondary side demagnetizati on detection and triggering block the demagnetization detection (dmg) and trig gering blocks switch on the power mosfet if a negative-going edge falling below 50 mv is applied to the dmg pin. to do so, the triggering block must be previously armed by a positive-going edge exceeding 100 mv. this feature is used to detect transformer demagnetization for qr operation, where the signal for the dmg input is obta ined from the transf ormer's auxiliary windi ng used also to supply the ic. figure 14. dmg block, triggering block the triggering block is blanked after mosfet's turn-off to prevent any negative-going edge that follows leakage inductance demagnet ization from triggering the dmg circuit am13563v1 vcc drain vcc on vcc restart t t vin v start 5.5 ma t t power-on power-off normal operation cv mode cc mode normal operation i charge am13564v1 dmg 60mv 110mv blanking ti me turn-on logic starter s r q leb + - rf b aux rdmg dmg clamp to d riv er from cc/cv block from ocp
device description hvled815pf 18/34 docid023409 rev 5 erroneously. this t blank blanking time is dependent on the voltage on comp pin: it is t blank = 30 s for v comp = 0.9 v, and decreases almost linearly down to t blank = 6 s for v comp = 1.3 v. the voltage on the pin is both top and bo ttom limited by a double clam p, as illustrated in the internal diagram of the dmg block of figure 14 . the upper clamp is typically located at 3.3 v, while the lower clamp is located at -60 mv. the interface between the pin and the auxiliary winding will be a resistor divider. its resistance ratio as well as the individual resistance values will be properly chosen (see section 4.6 , section 4.7 on page 22 and section 4.11 on page 26 ). please note that the maximum i dmg sunk/sourced current has to not exceed 2 ma (amr) in all the v in range conditions. no capacitor is a llowed between dmg pi n and the auxiliary transformer. the switching frequency is top limited belo w 166 khz, as the converter's operating frequency tends to increase excessively at light load and high input voltage. a starter block is also used to start up the sys tem, that is, to turn on the mosfet during converter power-up, when no or a too small signal is available on the dmg pin. the starter frequency is 2 khz if comp pin is below burst mode threshold, i.e. 1 v, while it becomes 8 khz if this voltage exceeds this value. after the first few cycles initiat ed by the starter, as the voltage developed across the auxiliary winding becomes large enough to arm the dmg circuit, mosf et's turn-on will start to be locked to transformer demagnetization, hence setting up qr operation. the starter is activated also when the ic is in ?constant curr ent? regulation and the output voltage is not high enough to allow the dmg triggering. if the demagnetization completes - hence a negative-going edge appears on the dmg pin - after a time exceeding time t blank from the previous turn-on, the mosfet will be turned on again, with some delay to ensure minimum voltage at turn-on. if, instead, the negative- going edge appears before t blank has elapsed, it will be ignored and only the first negative-going edge after t blank will turn-on the mosfet. in th is way one or more drain ringing cycles will be skipped (??valley-skipping mode?, figure 15 ) and the switching frequency will be prevente d from exceeding 1/t blank . figure 15. drain ringing cy cle skipping as the load is progressively reduced note: that when the system operates in valley skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the off-time of the mosfet is allowed to change with discre te steps of one ringing cycle, while the off-time needed for cycle-by-cycle energy balance may fall in betw een. thus one or more longer switching cycles will be compensated by one or more shorter cycles and vice versa. however, this mechanism is absolutely normal and there is no appreciable effect on the performance of the converter or on its output voltage. am13565v1 p in = p in'' < p in' p in = p in''' < p in'' v ds t fw t on v ds v ds t osc t osc t osc p in = p in' (limit condition) t w t t t
docid023409 rev 5 19/34 hvled815pf device description 34 4.5 constant current operation figure 16 presents the principle used for contro lling the average outp ut curren t of the flyback converter. the voltage of the aux iliary winding is used by the dema gnetization block to generate the control signal for the internal mosfet switch q. a resistor r in series with it absorbs a current equal to v iled/r , where v iled is the voltage developed across the capacitor c led capacitor. the flip-flop's output is high as long as the transformer delivers current on secondary side. this is shown in figure 17 . figure 16. current control principle figure 17. constant current operation: switching cycle waveforms am13566v1 viled icled + - cc s r q dmg iled q r . iref cled demag logic aux rf b rdmg from cs pin to pwm logic am13567v1 i prim t iref i sec q i cled t t t viled/r t t onsec
device description hvled815pf 20/34 docid023409 rev 5 the capacitor c led has to be chosen so that its voltage v iled can be considered as a constant. since it is charged and discharged by currents in the range of some ten a (i ref = 20 a typ.) at the switching frequency rate, a capacitance value in the range 4.7 - 10 nf is suited for switching frequenc ies in the ten khz. when high power factor schematic is implemented, a higher capacitor value should be used (i.e. 1 f - 10 f). the average output current i out can be expressed as: equation 1 where i sec is the secondary peak current, t onsec is the conduction time of the secondary side and t is the switching period. taking into account the transformer rati o n between primary and secondary side, i sec can also be expressed as a function of the primary peak current i prim : equation 2 as in steady state the average current i cled : equation 3 which can be solved for v iled : equation 4 where v cled = r * i ref and it is internally de fined (0.2 v typical - see table 5: electrical characteristics on page 9 ). the v iled pin voltage is internally compared with the cs pin voltage (constant current comparator): equation 5 combining (1), (2), (4), and (5) the average output current results: equation 6
docid023409 rev 5 21/34 hvled815pf device description 34 equation 6 shows that the average output current i out does not depend anymore on the input voltage v in or the output voltage v out , neither on transformer inductance values. the external parameters defining the output current are the transformer ratio n and the sense resistor r sense . equation 6 is valid for both standard and high power factor implementation. 4.6 constant voltage operation the ic is specifically desig ned to work in primary regulation and the output voltage is sensed through a voltage partitio n of the auxiliary winding, just before the aux iliary rectifier diode. figure 18 shows the internal schematic of the constant voltage mode and the external connections. due to the parasitic wires resist ance, the auxiliary voltage is re presentative of the output just when the secondary current becomes zero. for this purpose, the signal on dmg pin is sampled-and-held at the end of transformer's demagnetization to get an accurate image of the output voltage and it is compared with the error amplifier internal reference voltage v ref (2.51 v typ. - see table 5: electrical characteristics on page 9 ). during the mosfet's off-time the leakage inductance resonates with the drain capacitance and a damped oscilla tion is superimposed on th e reflected voltage. the s/h logic is able to discriminate such oscillation s from the real transf ormer's demagnetization. when the dmg logic detects the transformer's demagnetization, the sampling process stops, the information is frozen and compar ed with the error amplifier internal reference. the internal error amplifier is a transconductance type and delivers an output current proportional to the voltage unbalance of the two outputs: the output generates the control voltage that is compared with the voltage across the sense resistor, thus modulating the cycle-by-cycle peak drain current. the comp pin is used for the frequency compensation: usually, an rc network, which stabilizes the overall voltage control loop, is connected be tween this pin and ground. as a result, the output voltage v out at zero-load (i.e. no led on the led driver output) can be selected trough the r fb resistor in according to equation 7 : equation 7 where n aux and n sec are the auxiliary and secondar y turn's number respectively. the r dmg resistor value can be defined depending on the application parameters (see section 4.7: voltage feedforward block ).
device description hvled815pf 22/34 docid023409 rev 5 figure 18. voltage control principle: internal schematic 4.7 voltage feedforward block the current control structure uses the v cled voltage to define the output current, according to equation 6 in section 4.5 . actually, the constant current comparator will be affected by an internal propagation delay t d , which will switch off the mosf et with a peak current than higher the foreseen value. this current overshoot will be equal to: equation 8 the previous terms introduce a small error on the calculated average output current set- point, depending on the input voltage. the hvled815pf device implements a line feedfor ward function, which solves the issue by introducing an input voltage dependent offset on the current sense signal, in order to adjust the cycle-by-cycle current limitation. the internal schematic is shown in figure 19 . am13568v1 rdmg aux rf b from cs pin + - cv to pwm logic r c comp dmg s/h demag logic + - ea 2.5v
docid023409 rev 5 23/34 hvled815pf device description 34 figure 19. feedforward compensation: internal schematic during mosfet's on-time the current sour ced from dmg pin is mirrored inside the ?feedforward logic? block in order to provide a feedforward current, i ff . such ?feedforward current? is proportional to the input voltage according to equation 9 : equation 9 where m is the primary-to-a uxiliary turns ratio. according to the schematic in figure 19 , the voltage on the non-in verting comparator will be: equation 10 the offset introduc ed by feedforward compensation will be: equation 11 as r ff >> r sense , the previous one can be simplified as: equation 12 this offset is proportional to v in and it is used to compen sate the current overshoot, according to equation 13 : am13569v1 cs . if f feedf orward logic + - cc rf f rsense pwm logic dmg cc block aux rf b rdm g source drain
device description hvled815pf 24/34 docid023409 rev 5 equation 13 finally, the r dmg resistor can be calculated as follows: equation 14 in this case the peak drain current does not depend on input voltage anymore, and as a consequence the average output current i out does not depend from the v in input voltage. when high power factor is implemented (see section 4.11 ), the feedforward current has to be minimized because the line regulation is assured by the external offset circuitry (see figure 1: application circuit for high power fact or led driver - single range input on page 4 ). the maximum value is limited by the minimum i dmg internal current needed to guarantee the correct functionality of the internal circuitry: equation 15 4.8 burst mode operation at no load or very light load when the voltage at the comp pin falls 65 mv is below the internally fixed threshold v compbm , the ic is disabled with the mosfet kept in off state and its consumption reduced at a lower value to minimize v cc capacitor discharge. in this condition the converter operates in burst mode (one pulse train every t start = 500 s), with minimum energy transfer. as a result of the energy de livery stop, the output voltage decreases: after 500 s the controller switches on the mosfet again a nd the sampled voltage on the dmg pin is compared with the internal reference v ref . if the voltage on the ea output, as a result of the comparison, exceeds the v compl threshold, the device restarts switching, otherwise it stays off for another 500 s period. in this way the converter will work in burst mode with a nearly constant peak current defined by the internal disable level. a load decrease will then caus e a frequency r eduction, which can go down even to few hundred hertz, thus minimizing all frequency-related losses and making it easier to comply with energy saving regulations. this kind of operation, shown in the timing diagrams of figure 20 along with the others previously described, is noise-free since the peak current is low.
docid023409 rev 5 25/34 hvled815pf device description 34 figure 20. load-dependent operating modes: timing diagrams 4.9 soft-start and starter block the soft-start feature is automatically implem ented by the constant current block, as the primary peak current will be limi ted from the voltage on the c led capacitor. during the startup, as the outp ut voltage is zero, the ic will st art in constant current (cc) mode with no high peak current operations. in this way the voltage on the output capacitor will increase slowly and the soft -start feature will be ensured. actually the c led value is not important to define the soft-start time, as its duration depends on others circuit parameters, like transformer ratio, sense resistor, output capacitors and load. the user will define the best app ropriate value by experiments. 4.10 hiccup mode ocp the device is also protected ag ainst short-circuit of the seconda ry rectifier, short-circuit on the secondary winding or a hard-saturated flyback transformer. an internal comparator monitors continuously the voltage on cs pin and activates a protection circuitry if this voltage exceeds an internally fixed threshold v csdis (1 v typ. - see table 5: electrical characteristics on page 9 ). to distinguish an actual malfunction from a disturbance (e.g. induced during esd tests), the first time the comparator is trip ped, the protection circuit enters a ?warning state?. if in the subsequent switching cycle the comparator is not tripped, a tempor ary disturbance is assumed and the protection logic will be reset in its idle state; if the co mparator will be tripped again a real malf unction is assumed and th e device will be stopped. this condition is latched as lo ng as the device is supplied. wh ile it is disabled, however, no energy is coming from the self-supply circuit; hence the voltage on the v cc capacitor will decay and cross the uvlo threshold after some time, which clears the latch. the internal start-up generator is still off, then the vcc voltage still needs to go below its restart voltage before the v cc capacitor is charged again and the device restarted. am13570v1 i ds v compl comp t t 50 mv hysteresis (hys) burst-mode normal-mode normal-mode
device description hvled815pf 26/34 docid023409 rev 5 ultimately, this will result in a low-frequency interm ittent operation (hic cup mode operation), with very low stress on the power circuit. this special condition is illu strated in the timing diagram of figure 21 . figure 21. hiccup mode ocp: timing diagram 4.11 high power factor implementation referring to the principle application schematic in figure 1 on page 4 , two contributions are added on the cs pin in orde r to implement the high powe r factor capability (trough r pf resistor) and keeping a good line regulation (trough r os resistor). the application schematic on figure 1 is intended for a single range input voltage. for wide range application a different reference schematic can be used; refer to an4346 application note for further details. through the r pf resistor a contribution proportional to the input voltage is added on the cs pin: as a consequence the input current is prop ortional to the input voltage during the line period, implementing a high power factor corr ection. the contribution proportional to the input voltage is generat ed using the auxiliary winding, as a consequence a diode in series to the r pf resistor is needed. through the r os resistor a positive contribution proportional to the average value of the input voltage is added on the cs pin in order to keep a good line regulation. the voltage contribution proportional to the av erage value of the input voltage is generated trough the low pass filter r a /r b resistor and c os capacitor. a diode in series to the r a /r b resistor is suggested to avoid the discharge of c os capacitor in any condition. the r 1 resistor between cs and source pin is needed to add on the cs pin also the contribution proportional the output current trough the r sense resistor. am13571v1 v ds vcc on vcc off vcc rest secondary diode is shorted here t t t v cs 1 v two switching cycles v cc vcs dis
docid023409 rev 5 27/34 hvled815pf device description 34 figure 22. high power factor implementa tion connection - single range input the components selection flow starts from the r dmg resistor: this resistor has to be selected in order to minimize the internal feedforward effect. the maximum selectable value is limited by the minimum internal current circuitry i dmg needed to guarantee the correct functionality of the internal circuitry: equation 16 where n aux and n prim are the auxiliary an d primary turn's number respectively and v in_min is the minimum rms input voltage of the application (i.e. 88 v for 110 vac or 175 v for 230 vac range). the r fb resistor defines the v out output voltage value in the open circuit condition (no-load condition, i.e. no led on the output of led dr iver) and it can be selected using the following relationship: equation 17 where n aux and n sec are the auxiliary and secondary tu rn's number respectively and v ref is the internal reference voltage (v ref = 2.51 v typ - see table 5: electrical characteristics on page 9 ). the r 1 resistor is typically selected in the range of 500 ?? - 1.5 k ? in order to minimize the internal feedforward effect and to minimize the power dissipation on the r a /r b resistor offset circuitry. am13572v1 cos . drain source iff feedf orward logic1 + - cc rf f rsense pwm logic2 dmg cc block1 ros r1 rpf rb ra vin (after bridge diode) cs aux rf b rdmg
device description hvled815pf 28/34 docid023409 rev 5 the r a , r b , r os resistors are selected to add a positive offset on cs pin in order to keep a good line regulation over the input voltage range and cab be selected using equation 18 : equation 18 where v os_typ is the desired voltage across c os capacitor applying the v in_typ typical input voltage (i.e. v in_typ = 220 v for 176/264 vac input range); f sw is the switching frequency and can be estimated using equation 19 , where f t and f r are the transition and resonant frequency respectively: equation 19 equation 20 equation 21 where c d is the total equivalent capacitor afferent at the drain node. based on the desired voltage across the c os capacitor and calculated r os resistor, then the sum of r a and r b can then calculated as a results of partitioning divider: equation 22 using the previous r os resistor value the r pf resistor can be estimated using equation 23 : equation 23 ?
docid023409 rev 5 29/34 hvled815pf device description 34 finally the current sense resistor r sense can be estimated in order to select the desiderated average output current value: equation 24 where v cled is internally defined (0.2 v typical - see table 5: electrical characteristics on page 9 ). system design tips starting from the previous estimated components value, further fine-tuning on the real led driver board could be necessary and it can be easily done considering that: ? decreasing/increasing the r pf resistor value, the power factor effect increases/decreases. ? decreasing/increasing the r os resistor value, the line regulation effect increases/decreases. ? decreasing/increasing the r os resistor value, the r a + r b resistors value should be increased/decreased to keep the desiderated voltage across the c os capacitor ( equation 22 ). ? decreasing/increasing the r sense resistor value the average output current increases/decreases ( equation 24 ). 4.12 layout recommendations a proper printed circuit board layout is essent ial for correct operation of any switch-mode converter and this is true for the hvled815pf device as well. careful component placing, correct traces routing, appropriate traces wid ths and compliance with isolation distances are the major issues. in particular: ? current sense resistor (r sense ) should be connected as close as possible to the source pin, maintaining the trace fo r the gnd as short as possible. ? resistor connected on cs pin (r os , r pf , r 1 ) should be connected as close as possible to the pin. ? compensation network (r comp , c comp ) should be connected as close as possible to the comp pin, maintaining the trace for the gnd as short as possible. ? signal ground should be routed separately fr om power ground, as well from the sense resistor trace. ? dmg partition resistors (r dmg , r fb ) should be connected as close as possible to the dmg pin, minimizing the equivalent parasitic capacitor on dmg pin.
device description hvled815pf 30/34 docid023409 rev 5 figure 23. suggested routing for the led driver am13573v1 dmg source ac comp iled r fb r dmg r pf r comp c comp c led vcc cs drain gnd r sense r os ac r 1
docid023409 rev 5 31/34 hvled815pf package information 34 5 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. figure 24. so16n package outline 0016020_f
package information hvled815pf 32/34 docid023409 rev 5 table 6. so16n package mechanical data figure 25. so16n recommended footprint (dimensions are in mm) symbol dimensions (mm) min. typ. max. a 1.75 a1 0.10 0.25 a2 1.25 b0.31 0.51 c0.17 0.25 d 9.80 9.90 10.00 e 5.80 6.00 6.20 e1 3.80 3.90 4.00 e1.27 h0.25 0.50 l0.40 1.27 k0 8 ccc 0.10
docid023409 rev 5 33/34 hvled815pf revision history 34 6 revision history 22-oct table 7. document revision history date revision changes 26-jul-2012 1 initial release. 29-aug-2012 2 added table 2: pin description on page 7 . 23-oct-2012 3 modified t j value on table 3: thermal data . updated t j value in note 2 (below table 5: electrical characteristics ). minor text changes. 31-jan-2013 4 added sections from 4.1 to 4.12 . modified figure 1: application circuit for high power factor led driver - single range input and figure 2: application circuit for standard led driver . 18-feb-2014 5 updated section : features on page 1 (replaced 5% by 3% in accuracy on constant led output current). updated table 5: electrical characteristics (updated test condition, values and units of v cled symbol, added note 6. below table 5 ). updated section 5: package information (reversed order of figure 24: so16n package outline and table 6: so16n package mechanical data , updated titles of figure 24 and table 6 ). minor modifications throughout document.
hvled815pf 34/34 docid023409 rev 5 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of HVLED815PFTR

	To Download HVLED815PFTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .