? semiconductor components industries, llc, 2011 october, 2011 ? rev. 1 1 publication order number: NTD6414AN/d NTD6414AN, nvd6414an n-channel power mosfet 100 v, 32 a, 37 m features ? low r ds(on) ? high current capability ? 100% avalanche tested ? aec q101 qualified ? nvd6414an ? these devices are pb ? free and are rohs compliant maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 100 v gate ? to ? source voltage ? continuous v gs 20 v continuous drain current r jc steady state t c = 25 c i d 32 a t c = 100 c 22 power dissipation r jc steady state t c = 25 c p d 100 w pulsed drain current t p = 10 s i dm 117 a operating and storage temperature range t j , t stg ? 55 to +175 c source current (body diode) i s 32 a single pulse drain ? to ? source avalanche energy (v dd = 50 vdc, v gs = 10 vdc, i l(pk) = 32 a, l = 0.3 mh, r g = 25 ) e as 154 mj lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c thermal resistance ratings parameter symbol max unit junction ? to ? case (drain) steady state r jc 1.5 c/w junction ? to ? ambient (note 1) r ja 37 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. surface mounted on fr4 board using 1 sq in pad size, (cu area 1.127 sq in [1 oz] including traces). http://onsemi.com marking diagram & pin assignments 6414an = device code y = year ww = work week g = pb ? free package dpak case 369aa style 2 yww 64 14ang 4 drain 3 source 1 gate 2 drain ipak case 369d style 2 4 drain 1 gate 2 drain 3 source yww 64 14ang 4 1 2 3 v (br)dss r ds(on) max i d max (note 1) 100 v 37 m @ 10 v 32 a 1 2 3 4 see detailed ordering and shipping information in the package dimensions section on p age 5 of this data sheet. ordering information g s d n ? channel
NTD6414AN, nvd6414an http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 100 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j 107 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 100 v t j = 25 c 1.0 a t j = 125 c 100 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 3) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 2.0 4.0 v negative threshold temperature coefficient v gs(th) /t j 8.3 mv/ c drain ? to ? source on ? resistance r ds(on) v gs = 10 v, i d = 32 a 30 37 m forward transconductance gfs v gs = 5.0 v, i d = 10 a 18 s charges, capacitances and gate resistance input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 25 v 1450 pf output capacitance c oss 230 reverse transfer capacitance c rss 95 total gate charge q g(tot) v gs = 10 v, v ds = 80 v, i d = 32 a 40 nc threshold gate charge q g(th) 1.7 gate ? to ? source charge q gs 8.0 gate ? to ? drain charge q gd 20 plateau voltage v gp 5.9 v gate resistance r g 1.9 switching characteristics (note 4) turn ? on delay time t d(on) v gs = 10 v, v dd = 80 v, i d = 32 a, r g = 6.1 11 ns rise time t r 52 turn ? off delay time t d(off) 38 fall time t f 48 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 32 a t j = 25 c 0.87 1.2 v t j = 125 c 0.76 reverse recovery time t rr v gs = 0 v, di s /dt = 100 a/ s, i s = 32 a 68 ns charge time t a 51 discharge time t b 16 reverse recovery charge q rr 195 nc 2. surface mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [1 oz] including traces). 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
NTD6414AN, nvd6414an http://onsemi.com 3 typical characteristics 0 10 20 30 40 012345 v ds , drain ? to ? source voltage (v) i d , drain current (a) figure 1. on ? region characteristics t j = 25 c 10 v 7.5 v 6.5 v 6.0 v 5.5 v 5.0 v 0 10 20 30 40 50 2345678 v gs , gate ? to ? source voltage (v) i d , drain current (a) figure 2. transfer characteristics v ds 10 v t j = 125 c t j = ? 55 c t j = 25 c 0.02 0.03 0.04 0.05 5678910 v gs , gate ? to ? source voltage (v) r ds(on) , drain ? to ? source resistance ( ) figure 3. on ? region versus gate voltage i d = 32 a t j = 25 c 0.00 0.02 0.04 0.10 0.06 10 35 15 t j = 125 c t j = 175 c v gs = 10 v t j = 25 c t j = ? 55 c i d , drain current (a) figure 4. on ? resistance versus drain current and gate voltage r ds(on) , drain ? to ? source resistance ( ) 0.5 1 1.5 2 2.5 3 ? 50 ? 25 0 25 50 75 100 125 150 175 t j , junction temperature ( c) figure 5. on ? resistance variation with temperature r ds(on) , drain ? to ? source resistance (normalized) i d = 32 a v gs = 10 v 10 1000 10000 10 20 30 40 50 60 70 80 90 100 v ds , drain ? to ? source voltage (v) i dss , leakage (na) figure 6. drain ? to ? source leakage current versus voltage t j = 125 c t j = 150 c v gs = 0 v 0.06 0.07 4.5 v 60 70 0.08 20 25 30 100 50 60 70
NTD6414AN, nvd6414an http://onsemi.com 4 typical characteristics 0 400 800 1200 1600 0 20406080100 v ds , drain ? to ? source voltage (v) c, capacitance (pf) figure 7. capacitance variation t j = 25 c v gs = 0 v c iss c oss c rss 0 2 4 6 8 10 0 5 10 15 20 q t q gd q gs q g , total gate charge (nc) figure 8. gate ? to ? source voltage and drain ? to ? source voltage versus total charge i d = 32 a t j = 25 c v gs , gate ? to ? source voltage (v) 1 10 100 1000 1 10 100 r g , gate resistance ( ) t, time (ns) figure 9. resistive switching time variation versus gate resistance t d(off) t f t r t d(on) v ds = 80 v i d = 32 a v gs = 10 v 0 5 10 15 20 0.5 0.6 0.7 0.8 0.9 0.4 v sd , source ? to ? drain voltage (v) figure 10. diode forward voltage versus current i s , source current (a) t j = 25 c v gs = 0 v 0.1 1 10 100 1 10 100 1000 v ds , drain ? to ? source voltage (v) i d , drain current (a) figure 11. maximum rated forward biased safe operating area r ds(on) limit thermal limit package limit v gs = 10 v single pulse t c = 25 c 10 s 100 s 10 ms dc 1 ms 0 20 40 60 25 50 75 100 125 150 175 avalanche energy (mj) t j , starting junction temperature figure 12. maximum avalanche energy versus starting junction temperature i d = 32 a v ds , drain ? to ? source voltage (v) 100 80 60 40 20 0 v ds v gs 100 2000 2800 80 2400 25 30 35 40 25 30 35 120 160 140
NTD6414AN, nvd6414an http://onsemi.com 5 typical characteristics 0.001 0.01 0.1 1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 figure 13. thermal response t, pulse time (s) 0.2 0.02 d = 0.5 0.05 0.01 single pulse 0.1 r(t) ( c/w) 10 ordering information device package shipping ? NTD6414ANt4g dpak (pb ? free) 2500 / tape & reel NTD6414AN ? 1g ipak (pb ? free) 75 units / rail nvd6414ant4g dpak (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
NTD6414AN, nvd6414an http://onsemi.com 6 package dimensions dpak (single guage) case 369aa ? 01 issue b b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw style 2: pin 1. gate 2. drain 3. source 4. drain
NTD6414AN, nvd6414an http://onsemi.com 7 package dimensions 123 4 v s a k ? t ? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? ipak case 369d ? 01 issue c style 2: pin 1. gate 2. drain 3. source 4. drain on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NTD6414AN/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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