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| MV6601C datasheet mvd-6601-04-ds-en version: 0.7 may 2008
MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 2 of 48 http://www.mavrixtech.com declarations circuit diagrams and other information relating to products of mavrix technology, inc. ( mavrix ) are included as a means of illustrating typical applications. consequently, complete information sufficient for construction is not necessarily given. although the information has been examined and is believed to be accurate, mavrix makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and disclaims any responsibility for inaccuracies. information in this document is provided solely to enable use of mavrix products. the information presented in this document does not form part of any quotation or contract of sale. mavrix assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of mavrix s products, except as expressed in mavrix s terms and conditions of sale for. all sales of any mavrix products are conditional on your agreement of the terms and conditions of recently dated version of mavrix s terms and conditions of sale agreement dated before the date of your order. this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights, copyright, trademark rights, rights in trade secrets and/or know how, or any other intellectual property rights of mavrix or others, however denominated, whether by express or implied representation, by estoppels, or otherwise. information documented here relates solely to mavrix products described herein supersedes, as of the release date of this publication, all previously published data and specifications relating to such products provided by mavrix or by any other person purporting to distribute such information. mavrix reserves the right to make changes to specifications and product descriptions at any time without notice. contact your mavrix sales representative to obtain the latest specifications before placing your product order. mavrix product may contain design defects or errors known as anomalies or errata which may cause the products functions to deviate from published specifications. anomaly or errata sheets relating to currently characterized anomalies or errata are available upon request. designers must not rely on the absence or characteristics of any features or instructions of mavrix s products marked reserved or undefined. mavrix reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. mavrix s products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of mavrix and further testing and/or modification will be fully at the risk of the customer. copies of this document and/or other mavrix product literature, as well as the terms and conditions of sale agreement, may be obtained by visiting mavrix s website at http://www.mavrixtech.com/ or from an authorized mavrix representative. the word mavrix , the mavrix s logo, whether used separately and/or in combination, and the phrase m , are trademarks of mavrix technology, inc.. names and brands of other companies and their products that may from time to time descriptively appear in this product data sheet are the trademarks of their respective holders; no affiliation, authorization, or endorsement by such persons is claimed or implied except as may be expressly stated therein. mavrix disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any course of dealing or usage of trade. in no event shall mavrix be reliable for any direct, incidental, indirect, special, punitive, or consequential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of mavrix or others; strict liability; breach of warranty; or otherwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whether mavrix has been advised of the possibility of such damages or not. additional support: additional product and company information can be obtained by visiting the mavrix website at: http://www.mavrixtech.com/ . MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 3 of 48 http://www.mavrixtech.com contents revision history........................................................................................................5 1. general description...........................................................................................6 2. feature..............................................................................................................7 2.1 processor......................................................................................................................7 2.3 multimedia decoder....................................................................................................7 2.4 video interface.............................................................................................................7 2.5 audio interface.............................................................................................................7 2.6 host interface..............................................................................................................7 2.8 peripheral interface.....................................................................................................7 2.9 memory controller.......................................................................................................7 2.10 stack sdram...............................................................................................................7 2.11 power and package.....................................................................................................8 3. block diagram...................................................................................................9 4. functional description.....................................................................................10 4.1 32-bit risc core........................................................................................................10 4.2 multi-core "class-dsp"...............................................................................................10 4.3 dma controller...........................................................................................................10 4.4 host interface............................................................................................................11 4.4.1. i2c interface...........................................................................................................12 4.4.2. spi interface...........................................................................................................13 4.4.3. uart interface.......................................................................................................15 4.4.4. lcm-like 8-bit i80 interface..................................................................................16 4.5. peripheral interface .................................................................................................17 4.5.1 i 2 c...........................................................................................................................18 4.5.2 spi...........................................................................................................................18 4.5.3 pwm.......................................................................................................................18 4.6. display interface ......................................................................................................18 4.7.1 display scalar.........................................................................................................18 4.7.2 image control.........................................................................................................19 4.7.3 display overlay.......................................................................................................19 4.7.4 camera emulation output.....................................................................................19 4.7.5 lcd display controller...........................................................................................21 4.7. audio interface .........................................................................................................24 4.8.1 i 2 s audio interface.................................................................................................24 4.8.2 internal audio dac.................................................................................................24 MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 4 of 48 http://www.mavrixtech.com 4.8. memory interface ....................................................................................................26 4.9.1 nor flash controller.............................................................................................26 4.9. gpio ..........................................................................................................................27 4.10.1 general purpose input/output interface.............................................................27 5. signal description...........................................................................................28 5.1 pins description........................................................................................................28 5.2 io-trap setting...........................................................................................................35 5.3 boot-up sequence....................................................................................................36 5.3.1 host-boot sequence..............................................................................................36 5.3.2 flash-boot sequence.............................................................................................37 6. electrical characteristic...................................................................................38 6.1 absolute maximum rating.......................................................................................38 6.2 operating condition..................................................................................................38 6.3 dc characteristic......................................................................................................39 6.4 crystal input timing..................................................................................................40 6.4.1 crystal oscillation..................................................................................................40 6.4.2 external clock........................................................................................................40 6.5 ac characteristic........................................................................................................41 6.5.1 hif timing..............................................................................................................41 6.5.2 lcd controller timing............................................................................................41 6.5.3 camera emulation timing.....................................................................................41 6.5.4 i2s interface timing..............................................................................................41 6.5.5 nor flash controller timing.................................................................................41 6.6 i/o pad characteristic..............................................................................................42 7. physical information........................................................................................43 7.1 package dimension..................................................................................................43 7.2 pin map.....................................................................................................................44 7.3 ordering information ...............................................................................................44 7.4 storage condition and period for package .........................................................44 7.5 recommended smt temperature profile ...........................................................44 appendix.................................................................................................................46 acronym and abbreviation.....................................................................................47 contact information...............................................................................................48 MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 5 of 48 http://www.mavrixtech.com revision history date version description 2007/07/05 0.1 initial draft 2007/07/06 0.2 added boot up sequence, overview, group connection diagram. modified tables, pin assignment, pin description 2007/07/09 0.3 remove section 1.3 advance feature list, modify pin description, makes viewable graphics 2007/07/11 0.4 edit acronym and abbreviations 2008/05/10 0.6 update 2008/05/12 0.7 update MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 6 of 48 http://www.mavrixtech.com 1. general description the MV6601C ? multi-core processor is a versatile high-performance, low-power, high integration system-on-chip (soc) targeted at multimedia enabled cell phones, personal media players (pmp), multimedia clients, and devices where low power multimedia features are valued. the MV6601C soc features a multimedia processing engine that removes the need for additional external dsp chip. with built-in tft lcd controller, MV6601C is designed to support directly driver lcd module with a 18bit rgb666 lcd controller and diver, and support both 8bit parallel camera input and output interface conforming to ycbcr 4:2:2 format. with built-in audio dac & amplifier, MV6601C is designed to support both digital and analog audio output, support digital audio protocol - i2s, and can output analog audio directly or with headphone amplifier. the MV6601C also including various host processor interface (i2c/spi/uart/lcm-like), nor flash interface, i 2 c & spi serial interfaces, pwm output port, the MV6601C is an ideal choice for system integrators seeking to maximize performance and minimize system cost. the MV6601C stacked with 8m bytes sdram in single package. the MV6601C chip also supports risc instruction set which enables user customization. designed for minimal integration effort for multimedia resolutions, maximum performance at low power, the device only needs to run at speed no more than 150 mhz so the overall power dissipation is less than 250mw. in addition, MV6601C is integrated with on-chip memory controllers and flexible input/output options and can run a variety of operating systems. MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 7 of 48 http://www.mavrixtech.com 2. feature 2.1 processor 2 integrated risc core supports 32-bit architecture and instruction set 2 multi-core class-dsp for multimedia processors 2.3 multimedia decoder 2 support various video format: mpeg1/2/4, h.264, avs, rm/rmvb, avi 2 support various video solution qvga/cif/qqvga/qcif @ 30fps 2 support various audio format: mp3/aac/aac+ 2.4 video interface 2 support lcd display base on rgb565 /rgb666 format 2 support directly driver the tft color lcd module 2 yuv 4:2:2 outputs for emulate as camera sensor connect to host 2 yuv 4:2:2 input for connect to camera sensor module 2 support multi-resolution with video scalar 2 support overlay and osd with alpha blending 2 support hue and gamma correct 2.5 audio interface 2 support digital audio interface i2s input & output for external audio codec. 2 support stereo analog audio output with built-in audio dac 2 support directly stereo headphone output with built-in 24mw amplifier 2.6 host interface 2 support various serial interfaces (slave to host) i2c, spi, uart 2 support various parallel interface (slave to host) lcm-like 8-bit memory bus interface 2.8 peripheral interface 2 most of pins in MV6601C can act as gpio 2 serial peripheral (master) interface: i2c, spi 2 4 channel pwm outputs 2.9 memory controller 2 4 channel independent multi-priority based dma 2 support self-boot nor flash size up to 8m bytes 2.10 stack sdram 2 stack with 8m bytes sdram in single package 2 stack sdram speed up to pc133 MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 8 of 48 http://www.mavrixtech.com 2.11 power and package 2 operating voltages core: 1.2v pll: 1.2v (sensitive) host interface: 1.8v ~ 3.3v general i/o: 1.8v ~ 3.3v sdram: 2.3v ~ 2.7v analog: 2.7v ~ 3.6v 2 multiple power domains and gated clocks 2 power modes: active and shutdown 2 0.13 m cmos 2 package: 0.5mm pitch, 10mmx10mmx1.2mm, 208 ball tfbga MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 9 of 48 http://www.mavrixtech.com 3. block diagram the following figure shows the functional block diagram. figure 1 functional block diagram MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 10 of 48 http://www.mavrixtech.com 4. functional description 4.1 32-bit risc core MV6601C integrated a general purpose risc processor, which provides a versatile high integrate, high-performance, low-power soc. it also supports 32-bit architecture and instruction set. the cache is a four ways associative type with separate 16k bytes instruction and 16k bytes data. our general purpose risc processor supports essential instructions and features which are found in industry-standard risc processors such as arm and ppc. 4.2 multi-core "class-dsp" 4.2.1 rice processor description the mavrix s 32-bit risc processor named rice (risc instruction core engine) is designed to be used as the backbone for all mavrix s class oriented pipeline processors. therefore, the rice was architected from inception with power, area, and performance in mind. the focus is to make the rice nimble but complete. architectural simplicity not only leads to small area and low power, it also facilitates firmware coding and future enhancements. the rice has the essential instructions and features that are found in industry-standard risc processors such as arm and mips, with the coprocessor support needed for the mavrix s class specific instructions. 4.2.2 matrix processor description the mavrix m2 matrix processor is an innovative multimedia processing core designed to accelerate the processing of popular media compression/decompression schemes. the m2 s unique matrix data path and instruction set allows for efficient processing of h.264/avc, jpeg/mpeg, rm/rmvb in a fully programmable core. 4.3 dma controller the global dma is a general purpose direct memory access controller. it is in charge of moving data between different internal modules and external devices. the global dma servers the following dma clients: peripheral devices, dram, video processor. there are 4 independent channels, one per source and destination pair. each source and destination address is programmable, and data endian is programmable conversion during transfer. interrupt generation on transfer complete. MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 11 of 48 http://www.mavrixtech.com 4.4 host interface the MV6601C provides various host interfaces which allows an external master to connect to MV6601C. by the software level, a pair of software api will be implemented inside the MV6601C soc and the host processor (we call the software run at the host processor as hif supplied by mavrix). commands from host will be sent to MV6601C, explained and executed by MV6601C, and also information inside MV6601C will be obtained by the host. briefly, it is the main interface which exchanges data by MV6601C to help our customer to integrate whole MV6601C function. media streaming is also send to MV6601C for viewing by the host interface. the MV6601C supports multiple types of serial host interface and one parallel interface. the cpu interprets the host commands, performs corresponding operations and then sends the status back to the host processor. optionally, MV6601C also output one level-trigger signal to interrupt the host. (intr) the MV6601C supports the following types of host interfaces: l i2c (slave) l spi (slave, mode 0/1/2/3) l uart l lcm-like 8-bit i80 interface note : the data field may contain multiple bytes when necessary. note : multiple bytes data is transfer by little-endian that is low byte transferred first. note : since MV6601C risc is based on 32bit access, all data bytes after the addresses are treated as 4-chained bytes. that is, the api in the host processor will group 4 consecutive bytes access together as a single 32bit access. MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 12 of 48 http://www.mavrixtech.com 4.4.1. i2c interface the MV6601C acted as an i 2 c slave. through the io-trap configuration, alternative i 2 c slave addresses can be selected (default address is 0x65). the speed of i 2 c interface in MV6601C is up to 1.5mbps. the following diagram shows the access timing: write timing : to write data to MV6601C, only one i 2 c cycle is needed, both the command and the contents are send to the bus. figure 2 i 2 c write timing C multiple bytes access read timing : to read from MV6601C, two i 2 c cycles are needed. first cycle writes the register address to be accessed from, and second cycle read the contents. figure 3 i 2 c read timing note: when write data to slave, the ack handshake is always needed and driven by the i 2 c slave device - MV6601C. when read data from MV6601C, the ack handshake should be driven by the host. MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 13 of 48 http://www.mavrixtech.com 4.4.2. spi interface the serial peripheral interface (spi) is a synchronous four wires serial link used to connect to MV6601C. the two serial data lines with master out, slave in (mosi) or master in, slave out (miso) signals. MV6601C supports all four clocking modes for data exchange, and the serial clock frequency is up to 24mhz. each clock cycle shifts data out and data in; the clock doesn t cycle except when there is data to shift. an io-trap option defines the access clocking mode. the access mode can be read or write, depending on the bit-7 of address transfer. multiple data bytes can be transferred, following the address. the following diagrams illustrate the timing of MV6601C access via the spi serial interface. spi mode-0 (clock stops at logic 0 when idle, rising edge latch data) write cycle timing figure 4 spi mode-0 write timing read cycle timing start sck sdi sdo cs_n a6 a5 a2a1 a4a3 rd _n a0 rd 6 rd 3 rd 2 rd 5 rd 4 rd 0 rd 1 rd 7 figure 5 spi mode-0 read timing MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 14 of 48 http://www.mavrixtech.com spi mode-1 (clock stops at logic 0 when idle, falling edge latch data) write cycle timing figure 6 spi mode-1 write timing read cycle timing figure 7 spi mode-1 read timing spi mode-2 (clock stops at logic 1 when idle, falling edge latch data) write cycle timing figure 8 spi mode-2 write timing read cycle timing figure 9 spi mode-2 read timing MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 15 of 48 http://www.mavrixtech.com spi mode-3 (clock stops at logic 1 when idle, rising edge latch data) write cycle timing figure 10 spi mode-3 write timing read cycle timing figure 11 spi mode-3 write timing 4.4.3. uart interface MV6601C provide an uart serial interface connect to host. MV6601C need 9-bit data transfer protocol. the last bit bit-8 defines whether the transfer is a command or a data. all data transfer must be followed by one command transfer. the command transfer defines the access address and mode. the access mode can be read or write, depending on eighth bit bit-7 of the command. the write transfer can send multiple data followed by one command. the read transfer send the read command at first, after MV6601C received the read command, it would transfer following data back to host. the default baud rate is 9600bps after hardware reset, and the baud rates can be programmed from 1200bps to 1.5mbps. the time interval between each read byte is also programmable from 0 to 255 bits. the following diagrams show the timing. write cycle timing MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 16 of 48 http://www.mavrixtech.com figure 12 uart write timing read cycle timing figure 13 uart read timing note : the (dlt-t) represents the internal time between each read data transfer. 4.4.4. lcm-like 8-bit i80 interface the MV6601C also provides an 8bit width parallel interface, which is a memory bus and standard ram interface, and which could significantly improve the data throughput. the interface is compatible to the lcd module (lcm) interface meeting the i80 interface protocol, so we call it lcm-like. the command is send when a0 is low, and the data is send/receive when a0 is high. due to MV6601C access in 32bit width, so four clock cycles complete one transfer, and it uses lsb data format transfer. the cs desert indicates one transfer beginning, so must always keep cs low in one transfer duration time. b_lcm_cs_n b_lcm_wr_n cs wr b_lcm_rd_n b_lcm_a0 rd a21 b_lcm_d[0:7] data[0:7] 8 caution : the MV6601C lcm-like interface is 8bit width, but the host may be 16bit or 32 bit width system. in both case, it should put the address at the msb of command, may fill zero at begin bytes. MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 17 of 48 http://www.mavrixtech.com write cycle timing figure 14 lcm i80 interface write timing read cycle timing figure 15 lcm i80-series interface read timing 4.5. peripheral interface in addition, MV6601C also supports multiple types of peripheral interfaces to control and communication to other peripheral devices. MV6601C supports the following types of peripheral interfaces: l 1 i2c master interface MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 18 of 48 http://www.mavrixtech.com l 1 spi master interface l 4 pwm output l gpio 4.5.1 i 2 c to communicate with peripheral devices, MV6601C will act as an i2c master. the interface timing and read/write protocol are the same as the interface used by the host interface. please refer to the host interface section for detail. 4.5.2 spi similar to the i2c master interface, MV6601C also supports a spi serial interface in master mode. the MV6601C supports all four spi clocking modes. please refer to the host interface section for detail. 4.5.3 pwm pwm (pulse width modulation) block is a powerful interface for controlling analogy circuits with a processor s digital outputs. pwm is a way of digitally encoding analogy signal levels. there are four pwm output pins in the MV6601C. pwm timing diagram figure 16 wm timing diagram 4.6. display interface the display interface controller block is designed to output images to an lcd panel display or to the camera sensor input of host processor. and it also has a camera sensor input port that can receive image data from the sensor and put into memory via dma, or directly bypass all sensor signals to output port. this interface have rich feature which including video scalar, display overlay, 16/18bit rgb output, 8bit yuv output, gamma control, alpha blending. 4.7.1 display scalar MV6601C implements a video scalar in its display path, depending on the register setting, the scalar can handle quarter macro block (smb) inputs (media streaming MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 19 of 48 http://www.mavrixtech.com playback). the input to the display and scaling block is assumed to be dram. in the lcd parallel display modes, the pixel format is selectable as ycbcr 4:2:2 or ycbcr 4:2:0, and the pixel placement within dram is assumed to be planar. that is, y, cb, and cr are all separately placed in the source memory instead of interleaved together. the scalar allows for integer decimation by 2. in both horizontal or vertical direction and an independently controlled fractional horizontal and vertical scale down to 2x. both the camera emulation output and the lcd parallel output can be scaled. please note that since the scalar hardware sometimes needs to handle smb inputs, a built-in buffer is required. to reduce the overall buffer size, the width of input frame to scalar block should be restricted to be no larger than 800 pixels (y being the worst case). 4.7.2 image control the MV6601C can easily adjust image parameters, including hue saturation and gamma. the gamma adjustment uses the 16-element color palette. the overlay images can be mixed with graphic image through alpha blending mode, thus to form applications such as transparent menu. 4.7.3 display overlay to allow for users to draw menus icons over the video in the display output, MV6601C implements a graphics overlay sub-block. the display overlay merges inputs from a separate dram location (a graphics buffer) to the output of the color-space-conversion sub block. it is up to the firmware to define the size of the graphic buffer as well as the overlay area . the overlay region is defined as a single region with starting line number as well as ending line number. (only the y-direction can be specified, the x-direction is assumed to be entire row) figure 17 display overlay block diagram 4.7.4 camera emulation output the MV6601C supports a camera emulation output interface. this interface can be used by the host processor to obtain media graphic data from MV6601C for display by the host processor. the camera emulation output port supports the camera yuv 4:2:2 display data outputs, qvga 320x240 at 30fps. the lcm_mclk is used as master clock supplied by the host (or outside oscillator) to MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 20 of 48 http://www.mavrixtech.com MV6601C. the MV6601C will generate an internal pixel clock (lcd_pclk) based on the mclk. since the frequency of the master clock is normally multiples of the pixel-clock, the MV6601C utilizes an internal divider for the internal pixel clock generation and synchronization to the input clock. in addition, lcd_vs and lcd_hs provide the necessary vertical sync (frame valid) and horizontal sync (line valid) signals to the host. display data is streamed to the host via the 8bit yuv bus which supports ycbcr 4:2:2 formats. the data output can either be in the sequence of y0-cb-y1-cr or cb-y0-cr-y1 format. the following figures illustrate the interconnection examples between the MV6601C and a host processor supporting camera-interfaces. o_lcd_d[0:7] i_lcd_mclk o_lcd_pclk video_data[7:0] mclk (to sensor) pixel clock (from sensor) vsync senor interface o_lcd_vs o_lcd_hs h_valid figure 18 sensor mode interface (vsync + h_valid) o_lcd_d[0:7] i_lcd_mclk o_lcd_pclk video_data[7:0] mclk (to sensor) pixel clock (from sensor) v_valid senor interface o_lcd_vs o_lcd_hs h_valid figure 19 sensor mode interface (v_valid + h_valid) data transfer timing this sub-section describes the timings in sensor mode: (vsync + h_valid) & (v_valid + h_valid) for the video data transfer between mv6600 and the host processor. MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 21 of 48 http://www.mavrixtech.com figure 20 sensor mode interface yuv data transfer timing (vsync + h_valid) symbol name unit value range a vs period line 250 0~4096 b start blank lines line 10 0~1024 c valid lines line 240 0~1024 d active phase line 2 0~4096 e hs period dot 800 0~4096 f start blank dots dot 140 0~1024 g valid dots dot 640 0~1024 h active phase dot 40 0~4096 note : during this particular sensor mode, polarity for vsync and h_valid, are programmable as either active high or active low. pulse width for the vertical synchronization is programmable, and both horizontal blanking and vertical blanking are programmable. in addition, the number of dummy pixels at the beginning of each line and the number of dummy lines (will show up as a delay before h_valid goes active after vsync) at the beginning of each frame are programmable as well. 4.7.5 lcd display controller the MV6601C provides a parallel interface to driver the lcd panels. the lcd display interface is based on 18/16 bit rgb format. the rgb protocol uses vertical and horizontal synchronization signals (vs and hs) to construct timing of a display frame. either 18bit or 16bit rgb data is sent to the lcd per clock. max frame rate is 60 fps. the configuration for the lcd interface is summarized below: l 18-bit rgb interface C rgb666 format MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 22 of 48 http://www.mavrixtech.com l 16-bit rgb interface C rgb565 format note : if the lcd panel is 16-bit rgb 565 format, lcd_r0 and lcd_b0 are open drain. figure 21 lcd display interface (18-bit rgb666) figure 22 lcd display interface (16-bit rgb565) data transfer timing MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 23 of 48 http://www.mavrixtech.com v_active_w v_start v_sync_period v_width_i blk h_active_w h_start h_sync_period h_width_i(n) blk data[ 17:0] pixel clock vsync r g b6 --- - --- - xx 1 r g b5 xx 2 r g b0 r g b1 r g b2 r g b n- 2 r g b n- 1 xx xx --- - r g b4 r g b3 xx 0 --- - hsync hsync de r g b n- 3 --- - xx figure 23 lcd (18bit/16bit) transfer mode C (vsync + hsync) note : when in lcd data transfer mode, polarity for vertical synchronization (vsync) and horizontal synchronization (hsync) are programmable as either active high or active low. pulse width for the vsync and the pulse width for the hsync are both programmable. both horizontal blanking time and vertical blanking time are also programmable. and finally, the number of dummy pixels at the beginning of each line and the number of dummy lines at the beginning of each frame are programmable. MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 24 of 48 http://www.mavrixtech.com 4.7. audio interface the audio interface controller block is designed to output audio data to an internal or external audio dac, base on i2s protocol. and it also has a digital audio data input port that can receive audio data from external device and put into memory via dma, or directly bypass all i2s signals to output port. the built-in stereo audio dac can output audio in analog (line out), and headphone output through built-in headphone amplifier, so it can directly driver stereo headphone. 4.8.1 i 2 s audio interface the following diagram shows the connection between the MV6601C and an external audio dac in the playback mode application (video clip playback, audio playback). the MV6601C provides the master i2s clock and the i2s dac that are controlled via the i2c or spi interface in master mode. figure 24 connection between MV6601C and an external dac i2s controller timing diagram figure 25 i2s controller read/write timing 4.8.2 internal audio dac MV6601C integrates a low-cost stereo audio dac with single-ended analog voltage input and output. the dac employ anti-pop and de-emphasis filter. it provides power down mode, which works on the dac simultaneously; customer can control the headphone power and dac power separately. it also supports digital loop back. MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 25 of 48 http://www.mavrixtech.com the following list is the features of the internal audio dac: l supports 16/18/20/24-bit input format l analog supply range: 2.7 v ~ 3.6 v l 90 db snr sigma-delta dac @ 48 khz a-weighted l supports 8 khz C 192 khz sampling rate l 90 db dr sigma-delta dac @ 48 khz a-weighted l digital interpolation filter l stereo line outputs l de-emphasis filter supports 44.1 khz, 32 khz and 48 khz MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 26 of 48 http://www.mavrixtech.com 4.8. memory interface the MV6601C soc contains two external memory controllers, one for sdram and one for static device (nor flash). 4.9.1 nor flash controller the MV6601C supports flash and boot memory controller type. the flash interface has 23 address pins, so it can support 8m single chip flash. the data width bus is 8bit. for reading data from the flash, when ce and oe are low and we is high, data stored at the memory location determined by the address pin is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility to extend the flash capacity. when using flash address pin number less than 23, example a flash only has 19 pins. then we must connect flash to MV6601C address pin a0-a18. read timing diagram figure 26 flash read timing program timing diagram MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 27 of 48 http://www.mavrixtech.com figure 27 flash program timing 4.9. gpio 4.10.1 general purpose input/output interface most pins on the MV6601C board can act as gpio. there are 105 gpio pins. each gpio_enb bit is reset to 1'b1, except for those gpio pins that are shared with the host interfaces, jtag, ejag, and flash, which are powered on to functional mode. all other gpio-able pins power on to gpio functional mode. MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 28 of 48 http://www.mavrixtech.com 5. signal description 5.1 pins description no. pin name dir. description default memo system (6 pins) 1 i_rst_n i(*1) external reset (*2) (*3) 2 i_test i 0: normal chip operation. - 3 b_osc_io osc crystal output or external clock input - 4 i_osc_i osc crystal input - 5 i_osc_z i 0: use internal oscillator with crystal 1: use external clock input in 6 i_osc_f i 0: crystal frequency is 12~24mhz 1: crystal frequency is 24~48mhz in host interface (20 pins) 1 b_i2c_s_scl b i2c clock pin func 2 b_i2c_s_sda b i2c data pin func 3 b_spi_s_ce_n b spi chip enable pin func 4 b_spi_s_sclk b spi clock pin func 5 b_spi_s_miso b spi master in slave out func 6 b_spi_s_mosi b spi master out slave in func 7 b_txd b uart transfer data out func 8 b_rxd b uart receive data in func 9 b_lcm_cs_n b lcm chip select func 10 b_lcm_wr_n b lcm write clock func 11 b_lcm_rd_n b lcm read clock func 12 b_lcm_a0 b lcm address select func 13 b_lcm_d0 b lcm data 0 func 14 b_lcm_d1 b lcm data 1 func 15 b_lcm_d2 b lcm data 2 func 16 b_lcm_d3 b lcm data 3 func 17 b_lcm_d4 b lcm data 4 func 18 b_lcm_d5 b lcm data 5 func 19 b_lcm_d6 b lcm data 6 func 20 b_lcm_d7 b lcm data 7 func lcd controller interface (23 pins) rgb mode yuv mode MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 29 of 48 http://www.mavrixtech.com 1 b_lcd_de b lcd data enable pin yuv data enable pin in 2 i_lcd_mclk i lcd main clock input yuv main clock input in 3 o_lcd_pclk o lcd pixel clock yuv pixel clock in 4 o_lcd_hs o lcd hsync clock yuv hsync clock in 5 o_lcd_vs o lcd vsync clock yuv vsync clock in 6 o_lcd_d0 o red data 0 yuv0 in 7 o_lcd_d1 o red data 1 yuv1 in 8 o_lcd_d2 o red data 2 yuv2 in 9 o_lcd_d3 o red data 3 yuv3 in 10 o_lcd_d4 o red data 4 yuv4 in 11 o_lcd_d5 o red data 5 yuv5 in 12 o_lcd_d6 o green data 0 yuv6 in 13 o_lcd_d7 o green data 1 yuv7 in 14 b_lcd_d8 b green data 2 in 15 b_lcd_d9 b green data 3 in 16 b_lcd_d10 b green data 4 in 17 b_lcd_d11 b green data 5 in 18 b_lcd_d12 b blue data 0 in 19 b_lcd_d13 b blue data 1 in 20 b_lcd_d14 b blue data 2 in 21 b_lcd_d15 b blue data 3 in 22 b_lcd_d16 b blue data 4 in 23 b_lcd_d17 b blue data 5 in camera interface (12 pins) 1 o_c_mclk o sensor main clock output in 2 i_c_pclk i sensor pixel clock input in 3 b_c_hs b sensor hsync pin in 4 b_c_vs b sensor vsync pin in 5 b_c_yuv0 b sensor yuv 0 in 6 b_c_yuv1 b sensor yuv 1 in 7 b_c_yuv2 b sensor yuv 2 in 8 b_c_yuv3 b sensor yuv 3 in 9 b_c_yuv4 b sensor yuv 4 in 10 b_c_yuv5 b sensor yuv 5 in 11 b_c_yuv6 b sensor yuv 6 in 12 b_c_yuv7 b sensor yuv 7 in audio interface (14 pins) MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 30 of 48 http://www.mavrixtech.com 1 b_i2s_i_clk b i2s input main clock in 2 b_i2s_i_lrck b i2s input leftright clock in 3 b_i2s_i_data b i2s input data signal in 4 b_i2s_o_mclk b i2s output clock in 5 b_i2s_o_clk b i2s output main clock in 6 b_i2s_o_lrck b i2s output leftright clock in 7 b_i2s_o_data b i2s output data signal in 8 o_dac_vcm o dac common mode voltage - 9 i_dac_vrefp i dac positive reference voltage - 10 i_dac_vrefn i dac negative reference voltage - 11 o_dac_lhp ao left headphone sound output - 12 o_dac_rhp ao right headphone sound output - 13 o_dac_r ao stereo sound right output - 14 o_dac_l ao stereo sound left output - adc interface (11 pins) 1 b_clk_rst b clock module reset control pin in 2 b_clk_pwdn b clock module power down control pin in 3 o_clk_out b clock module output out 4 o_adc_vcm ao adc common mode voltage - 5 o_adc_vref ao adc reference voltage - 6 o_adc_vrp ao adc positive reference voltage - 7 o_adc_vrn ao adc negative reference voltage - 8 i_adc_qp ai q channel + input - 9 i_adc_dn ai q channel C input - 10 i_adc_ip ai i channel + input - 11 i_adc_in ai i channel C input - peripheral interface (12 pins) 1 b_pwm0 b pulse width modulator output 0 in 2 b_pwm1 b pulse width modulator output 1 in 3 b_pwm2 b pulse width modulator output 2 in 4 b_pwm3 b pulse width modulator output 3 in 5 b_i2c_m_scl b (master) i2c clock pin in 6 b_i2c_m_sda b (master) i2c data pin in 7 b_spi_m_ce_n b (master) spi chip enable in 8 b_spi_m_sclk b (master) spi clock in 9 b_spi_m_miso b (master) spi master in slave out in 10 b_spi_m_mosi b (master) spi master out slave in in 11 b_gpio_0 b gpio 0 in 12 b_gpio_1 b gpio 1 in MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 31 of 48 http://www.mavrixtech.com nor flash controller (35 pins) 1 b_nor_rst_n b nor flash reset pin func 2 b_nor_ce_n b nor flash chip enable pin func 3 b_nor_we_n b nor flash write enable pin func 4 b_nor_oe_n b nor flash out put enable pin func 5 b_nor_d0 b nor flash data 0 func 6 b_nor_d1 b nor flash data 1 func 7 b_nor_d2 b nor flash data 2 func 8 b_nor_d3 b nor flash data 3 func 9 b_nor_d4 b nor flash data 4 func 10 b_nor_d5 b nor flash data 5 func 11 b_nor_d6 b nor flash data 6 func 12 b_nor_d7 b nor flash data 7 func 13 b_nor_a0 b nor flash address 0 func 14 b_nor_a1 b nor flash address 1 func 15 b_nor_a2 b nor flash address 2 func 16 b_nor_a3 b nor flash address 3 func 17 b_nor_a4 b nor flash address 4 func 18 b_nor_a5 b nor flash address 5 func 19 b_nor_a6 b nor flash address 6 func 20 b_nor_a7 b nor flash address 7 func 21 b_nor_a8 b nor flash address 8 func 22 b_nor_a9 b nor flash address 9 func 23 b_nor_a10 b nor flash address 10 func 24 b_nor_a11 b nor flash address 11 func 25 b_nor_a12 b nor flash address 12 func 26 b_nor_a13 b nor flash address 13 func 27 b_nor_a14 b nor flash address 14 func 28 b_nor_a15 b nor flash address 15 func 29 b_nor_a16 b nor flash address 16 func 30 b_nor_a17 b nor flash address 17 func 31 b_nor_a18 b nor flash address 18 func 32 b_nor_a19 b nor flash address 19 func 33 b_nor_a20 b nor flash address 20 func 34 b_nor_a21 b nor flash address 21 func 35 b_nor_a22 b nor flash address 22 func test interface (21 pins) jtag gpio 1 b_tck b jtag test clock func MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 32 of 48 http://www.mavrixtech.com 2 b_tdi b jtag test data in func 3 b_tdo b jtag test data out func 4 b_tms b jtag test mode select func 5 b_ej_tck b ejtag test clock func 6 b_ej_tdi b ejtag test data in func 7 b_ej_tdo b ejtag test data out func 8 b_ej_tms b ejtag test mode select func 9 b_ej_trst_n b ejtag test reset func power / ground (43 pins) 1 vcck pg voltage supply of core - 2 vcck pg voltage supply of core - 3 vcck pg voltage supply of core - 4 vcck pg voltage supply of core - 5 vcck pg voltage supply of core - 6 vcck pg voltage supply of core - 7 vcck pg voltage supply of core - 8 vcck pg voltage supply of core - 9 vcck pg voltage supply of core - 10 vcck pg voltage supply of core - 11 vcck pg voltage supply of core - 12 gndk pg ground of core - 13 gndk pg ground of core - 14 gndk pg ground of core - 15 gndk pg ground of core - 16 gndk pg ground of core - 17 gndk pg ground of core - 18 gndk pg ground of core - 19 gndk pg ground of core - 20 gndk pg ground of core - 21 gndk pg ground of core - 22 gndk pg ground of core - 23 vccio_bb pg voltage supply of host interface - 24 vccio_bb pg voltage supply of host interface - 25 vccio_bb pg voltage supply of host interface - 26 vccio_spi pg voltage supply of spi interface - 27 vccio_c pg voltage supply of camera interface - 28 vccio_clk pg voltage supply of clock controller - 29 vccio_pwm pg voltage supply of pwm - 30 vccio_nor pg voltage supply of nor flash controller - MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 33 of 48 http://www.mavrixtech.com 31 vccio_nor pg voltage supply of nor flash controller - 32 gndio pg ground of io - 33 gndio pg ground of io - 34 gndio pg ground of io - 35 gndio pg ground of io - 36 gndio pg ground of io - 37 gndio pg ground of io - 38 gndio pg ground of io - 39 gndio pg ground of io - 40 gndio pg ground of io - 41 vcc3io pg voltage supply of i/o - 42 gnd3io pg ground of io - 43 vccio_lcd pg voltage supply of lcd controller - 44 vccio_lcd pg voltage supply of lcd controller - 45 gndio_lcd pg ground of lcd controller - 46 gndio_lcd pg ground of lcd controller - 47 vccio_sd pg voltage supply of sdram controller - 48 vccio_sd pg voltage supply of sdram controller - 49 vccio_sd pg voltage supply of sdram controller - 50 vccio_sd pg voltage supply of sdram controller - 51 vccio_sd pg voltage supply of sdram controller - 52 gndio_sd pg ground of sdram controller - 53 gndio_sd pg ground of sdram controller - 54 gndio_sd pg ground of sdram controller - 55 gndio_sd pg ground of sdram controller - 56 gndio_sd pg ground of sdram controller - 57 vcc12a_pll pg voltage supply of pll - 58 gnda_pll pg ground of pll - 59 vcc12a_sdpll pg voltage supply of sdram pll - 60 gnda_sdpll pg ground of sdram pll - 61 vcc12a_adc pg voltage supply of internal adc - 62 gnda_adc pg ground of internal adc - 63 vcc3a_dac pg voltage supply of internal dac - 64 gnda_dac pg ground of internal dac - 65 vcc3a_dachp pg voltage supply of headphone dac - 66 gnda_dachp pg ground of headphone dac - note : (*1) i only input pin; o only output pin; b bidirectional pin; a analog pin; pg power or ground pin. MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 34 of 48 http://www.mavrixtech.com (*2) func means power on to functional mode; in means power on to input gpio mode; (*3) tbd MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 35 of 48 http://www.mavrixtech.com 5.2 io-trap setting MV6601C can be set to different configurations when powered on. the configuration setting is configure by connect pull-up or pull-down resistors to some pins. pin name description note b_nor_d[0:1] xtal[0:1] crystal frequency selection xtal[2], xtal[1], xtal[0] 3 b000: 24.576 mhz 3 b001: 19.2 mhz 3 b010: 16.384 mhz 3 b011: 13 mhz 3 b100: 48 mhz 3 b101: 36 mhz 3 b110: 30 mhz 3 b111: 26 mhz io_trap[0:1] b_nor_d[2:3] spimode[0:1] spi mode setting, spimode[1], spimode[0] 2 b00: mode 0 2 b01: mode 1 2 b10: mode 2 2 b11: mode 3 io_trap[2:3] b_nor_d4 bootsource 1 b0: boot from extern nor flash 1 b1: boot from sdram io_trap[4] b_nor_d5 i2caddress hif i2c device address setting 1 b0: 0x56 1 b1: 0x65 io_trap[5] b_nor_d6 xtal[2] the another crystal selection pin io_trap[6] b_nor_d7 pllbypass 1 b0: bypass pll use oscillator clock as pll output clock 1 b1: no bypass io_trap[7] i_osc_z osctype 1 b0: use internal oscillator with crystal 1 b1: use external oscillator clock input osc_trap[0] i_osc_f oscfreq frequency selection if use internal oscillator with crystal, 1 b0: 12 ~ 24mhz 1 b1: 24 ~ 42mhz osc_trap[1] MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 36 of 48 http://www.mavrixtech.com 5.3 boot-up sequence the MV6601C supports two types of boot source. l host-boot : the host processor initiated and downloading code from host, then booting from sdram. l flash-boot : it will auto boot from flash. both boot-up sequences need some pre-strap setup, such as select crystal or oscillator as clock input, pll configuration, host interface configuration, and configure MV6601C risc processor as auto run mode or no-auto run mode. refer to io-trap setting for detail. 5.3.1 host-boot sequence the io-trap option should be configured as no-auto run mode. after MV6601C power on and reset have been done. the host should program the necessary clock register, and initiate the setting of sdram. then sdram is ready for access, host can download the firmware into sdram via the burst access mode through the host interface (i2c, spi, lcm, etc.). it is the software s responsibility to ensure the program data integrity after the download (looking for hw checksum logic or at least word count logic). once the download is verified, the host processor should soft reset MV6601C risc to run the firmware, then check response from MV6601C to ensure firmware running correctly. now MV6601C is ready for work. 1. setting clock 2. initiate sdram 3. download the firmware 4. soft reset & startup 5. wait response from chip 6. start application figure 28 host-boot sequence MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 37 of 48 http://www.mavrixtech.com 5.3.2 flash-boot sequence the io-trap option should be configured as auto run mode. after power-on-reset been done, the MV6601C will auto run from flash in default. then the host processor must check response from MV6601C to ensure firmware running correctly,. now MV6601C is ready for work. figure 29 flash-boot sequence MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 38 of 48 http://www.mavrixtech.com 6. electrical characteristic 6.1 absolute maximum rating parameter symbol value unit voltage on any pin relative to vss vt -0.5 to 4.6 v supply voltage relative to vss vdd -0.5 to 4.6 v operating temperature topt -10 to +70 storage temperature tstg -55 to +125 6.2 operating condition min. typ. max. unit internal 1.1 1.2 1.3 v pll 1.1 1.2 1.3 v sdram 2.3 2.5 2.7 v host interface 1.8 3.0 3.3 v gpio 1.8 3.0 3.3 v analog (interval dac) 2.7 3.0 3.6 v internal core - 96 160 mhz integrated risc core - 96 250 mhz MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 39 of 48 http://www.mavrixtech.com 6.3 dc characteristic ta=25 symbol parameter min. typ. max. unit vcck core operating voltage 1.1 1.2 1.3 v vcc3io vccio_bb vccio_spi vccio_clk vccio_c vccio_pwm vccio_nor vccio_lcd i/o operation voltage 1.8 3.0 3.3 v vccio_sd sdram controller operation voltage 2.3 2.5 2.7 v vcc12a_pll vcc12a_sdpll pll operation voltage 1.1 1.2 1.3 v vcc12a_adc internal adc operation voltage 1.1 1.2 1.3 v vcc3a_dac vcc3a_dachp internal dac operation voltage 2.7 3.0 3.6 v ii/o (standby) - tbd tbd ma idd icore (standby) - tbd tbd ma ii/o (bypass) - tbd tbd ma idd icore (bypass) - tbd tbd ma ii/o (idle) - tbd tbd ma idd icore (idle) - tbd tbd ma ii/o (play avi) - tbd tbd ma idd icore (play avi) - tbd tbd ma ii/o (play rmvb) - tbd tbd ma idd icore (play rmvb) - tbd tbd ma note : 1. the current is average value, and connect to 16.384mhz crystal as clock input. 2. the operation power: ii/o: the io current; icore: the core logic current 3. the maximum condition is measure by 1.2v core power, 3.0v io power, 3.3v dac power, and 25 temperature. 5. standby mode: the clock inputs of all modules are stopped and all voltage supply of most modules is power on. 6. bypass mode: base on standby mode, enable all bypass functions. 7. idle mode: cpu works in low frequency and other modules do nothing. 8. play mode: display output qvga (320*240) size. MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 40 of 48 http://www.mavrixtech.com 6.4 crystal input timing 6.4.1 crystal oscillation parameter min. typ. max. unit resistor (r) - nc - m capacitor (c1) - 12 - pf capacitor (c2) - 12 - pf note : typical value is suitable for 16.384mhz crystal input. 6.4.2 external clock parameter min. typ. max. unit resistor (r) - nc - m capacitor (c1) - 1000 - pf frequency (clock in) 12 16.384 48 mhz clock in amplitude (peak to peak) - 1.8 3.3 v MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 41 of 48 http://www.mavrixtech.com 6.5 ac characteristic 6.5.1 hif timing i i2c slave interface timing MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 42 of 48 http://www.mavrixtech.com 6.6 i/o pad characteristic most pins on the MV6601C board can act as gpio. there are 105 gpio pins. all gpio-able pins power on to gpio functional mode, except those gpio pins that are shared with the host interfaces, jtag, ejag, and flash, which are powered on to functional mode, symbol parameter min. typ. max. unit vil input low voltage -0.3 - 0.3 vccio v vih input high voltage 0.7 vccio - vccio+10% v iol output low current - 8 20 ma ioh output high current - 8 20 ma iil input leakage current - - 1 a rd pull down resistor 10k - 150k ohm rd pull up resistor 10k - 150k ohm MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 43 of 48 http://www.mavrixtech.com 7. physical information 7.1 package dimension figure 30 MV6601C package top view figure 31 MV6601C package bottom and side view MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 44 of 48 http://www.mavrixtech.com 7.2 pin map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 a gpio96 gpio14 gpio12 gpio16 gpio18 gpio20 gpio22 gpio79 gpio48 gpio50 gpio52 gpio54 a b_clk_rst i_osc_f b_lcm_wr_nb_lcm_a0 b_lcm_d1 b_lcm_d3 b_lcm_d5 b_lcm_d7 i_osc_i b_osc_io b_nor_ce_n b_nor_rst_n b_nor_a1 b_nor_a3 b_nor_a5 b_nor_a7 b gpio97 gpio11 gpio13 gpio15 gpio17 gpio19 gpio21 gpio80 gpio78 gpio47 gpio49 gpio51 gpio53 gpio56 gpio55 b i_adc_qp b_clk_pwdni_osc_z b_lcm_cs_n b_lcm_rd_n b_lcm_d0 b_lcm_d2 b_lcm_d4 b_lcm_d6 gnd3io b_nor_oe_nb_nor_we_nb_nor_a0 b_nor_a2 b_nor_a4 b_nor_a6 b_nor_a9 b_nor_a8 c gpio81 gpio58 gpio57 c i_adc_qn b_i2c_m_scl vccio_clk gndio vccio_bb gndio vccio_bb gndio_sd vccio_sd vcc3io vcck vcc12a_pll gndk gnda_pll gndio vccio_nor b_nor_a11 b_nor_a10 d gpio82 gpio60 gpio59 d i_adc_in b_i2c_m_sda gndio gndio b_nor_a13 b_nor_a12 e gpio9 gpio62 gpio61 e i_adc_ip o_adc_vrefb_txd vccio_nor b_nor_a15 b_nor_a14 f gpio10 gpio70 gpio64 gpio63 f o_adc_vrn o_adc_vcm b_rxd b_nor_d0 b_nor_a17 b_nor_a16 g gpio90 gpio71 gpio66 gpio65 g o_adc_vrp b_spi_s_ce_n o_clk_out vcc12a_adcgnda_adc vcck vcck vccio_sd vccio_sd b_nor_d1 b_nor_a19 b_nor_a18 h gpio94 gpio91 gpio72 gpio68 gpio67 h b_i2c_s_scl b_spi_s_sclk vccio_bb vcck gndk gndk gndk gndio_sd gndio_sd b_nor_d2 b_nor_a21 b_nor_a20 j gpio95 gpio92 gpio73 gpio46 gpio69 j b_i2c_s_sdab_spi_s_miso gndio vcck gndk gndk vcck b_nor_d3 b_lcd_de b_nor_a22 k gpio0 gpio93 gpio74 k gpio0 b_spi_s_mosii_rst_n vcck gndk gndk vcck b_nor_d4 i_lcd_mclk o_lcd_pclk l gpio1 gpio102 gpio75 l gpio1 b_gpio_0 i_test gndio_sd gndio_sd gndk gndk gndk vcck b_nor_d5 o_lcd_vs o_lcd_hs m gpio2 gpio103 gpio98 gpio76 m gpio2 b_gpio_1 b_pwm0 vccio_sd vccio_sd vcck vcck vcc12a_sdpll gnda_sdpll b_nor_d6 o_lcd_d1 o_lcd_d0 n gpio3 gpio104 gpio77 n gpio3 b_i2s_mclk vccio_pwm b_nor_d7 o_lcd_d3 o_lcd_d2 p gpio83 p b_spi_m_ce_n vccio_spi gndio gndio_lcd o_lcd_d5 o_lcd_d4 r gpio84 gpio99 r b_spi_m_sclk gndio b_pwm1 vccio_lcd o_lcd_d7 o_lcd_d6 t gpio85 gpio100 gpio101 gpio4 gpio5 gpio6 gpio7 gpio8 gpio27 gpio26 t b_spi_m_misob_pwm2 b_pwm3 vccio_c gndio gpio4 gpio5 gpio6 gpio7 gpio8 vcc3a_dachp gnda_dachpvcc3a_dac gnda_dac gndio_lcd vccio_lcd b_lcd_d9 b_lcd_d8 u gpio86 gpio36 gpio38 gpio40 gpio42 gpio44 gpio87 gpio89 gpio24 gpio35 gpio33 gpio31 gpio29 gpio28 u b_spi_m_mosio_c_mclk b_c_hs b_c_yuv0 b_c_yuv2 b_c_yuv4 b_c_yuv6 b_i2s_i_clk b_i2s_i_data b_i2s_o_lrck i_dac_vrefno_dac_vcm i_dac_vrefpb_lcd_d17 b_lcd_d15 b_lcd_d13 b_lcd_d11 b_lcd_d10 v gpio37 gpio39 gpio41 gpio43 gpio45 gpio88 gpio23 gpio25 gpio34 gpio32 gpio30 v i_c_pclk b_c_vs b_c_yuv1 b_c_yuv3 b_c_yuv5 b_c_yuv7 b_i2s_i_lrckb_i2s_o_clk b_i2s_o_data o_dac_lhp o_dac_rhp o_dac_r o_dac_l b_lcd_d16 b_lcd_d14 b_lcd_d12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 7.3 ordering information product number package type memo MV6601C tfbga 208 balls 10*10*1.2 0.13um cmos 7.4 storage condition and period for package package moisture sensitivity level max. reflow temperature floor life storage condition dry pack bga level 3 220 +5/-0 168hrs@ 30/60% r.h. yes note : please refer to ip/jedec standard j-std-020c or refer to the caution note on dry pack bag. 7.5 recommended smt temperature profile this recommended temperature profile is a rough guideline for smt process reference. the mavrix mv600 follows the jedec standard for reflow profile j-std-020c july 2004. MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 45 of 48 http://www.mavrixtech.com process volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 snpb eutectic 240 +0/-5 225 +0/-5 225 +0/-5 pb-free process 260 +0 260 +0 260 +0 MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 46 of 48 http://www.mavrixtech.com appendix group connection diagram figure 32 MV6601C group connection diagram MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 47 of 48 http://www.mavrixtech.com acronym and abbreviation acronym and abbreviation full name io input/output b bi-directional s slave m master sclk signal clock mclk master clock pclk pixel clock txd transfer data rxd receive data lrc left-right clock hs, vs horizontal synchronization, vertical synchronization miso master in slave out mosi master out slave in ce, cs chip enable, chip select dac digital-to-analog converters MV6601C data sheet(v0.7) mvd-6601-04-ds-en mavrix confidential page 48 of 48 http://www.mavrixtech.com contact information mavrix technology, inc. 4340 von karman ave #320 newport beach, ca 92660 (office) +1(949) 756-8898 (fax) +1(949) 756-8999 e-mail info@mavrixtech.com website www.mavrixtech.com ?????? ?????? 200 3501-3503 ? 201204 +86 (21) 5109-5958 +86 (21) 5027-7658 e-mail info@mavrixtech.com.cn website www.mavrixtech.com |
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