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september 2013 rev 2 1/17 17 vnd7n04, vnd7n04-1 vnk7n04fm "omnifet": fully autoprotected power mosfet features n linear current limitation n thermal shut down n short circuit protection n integrated clamp n low current drawn from input pin n diagnostic feedback through input pin n esd protection n direct access to the gate of the power mosfet (analog driving) n compatible with standard power mosfet description the vnd7n04, vnd7n04-1 and vnk7n04fm are monolithic devices made using stmicroeletronics vipower m0 technology, intended for replacement of standard power mosfets in dc to 50 khz applications. built-in thermal shut-down, linear current limitation and overvoltage clamp protect the chip in harsh enviroments. fault feedback can be detected by monitoring the voltage at the input pin. type v clamp r ds(on) i lim vnd7n04 vnd7n04-1 vnk7n04fm 42 v 42 v 42 v 0.14 w 0.14 w 0.14 w 7 a 7 a 7 a table 1. device summary part number order code vnd7n04 vnd7n04, vnd7n04-1-e, VND7N04-E, vnd7n0413tr, vnd7n04tr-e vnd7n04-1 vnd7n04-1 vnk7n04fm vnk7n04fm www.st.com
contents vnd7n04, vnd7n04-1, vnk7n04fm 2/17 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
vnd7n04, vnd7n04-1, vnk7n04fm block diagram 3/17 1 block diagram figure 1. block diagram
electrical specification vnd7n04, vnd7n04-1, vnk7n04fm 4/17 2 electrical specification 2.1 absolute maximum rating 2.2 thermal data 2.3 electrical characteristics table 2. absolute maximum rating symbol parameter value unit dpak ipak sot-82fm v ds drain-source voltage (v in = 0) internally clamped v v in input voltage 18 v i d drain current internally limited a i r reverse dc output current -7 a v esd electrostatic discharge (c = 100 pf, r=1.5 k w ) 2000 v p tot total dissipation at t c = 25 c 60 9 w t j operating junction temperature internally limited c t c case operating temperature internally limited c t stg storage temperature -55 to 150 c table 3. thermal data dpak/ipak sot82-fm r thj-case thermal resistance junction-case max 3.75 14 c/w r thj-amb thermal resistance junction-ambient max 100 100 c/w table 4. electrical characteristics: off (-40 < tj < 125 c unless otherwise specified) symbol parameter test conditions min. typ. max. unit v clamp drain-source clamp voltage i d = 200 ma v in = 0 32 42 52 v v clth drain-source clamp threshold voltage i d = 2 ma v in = 0 31 v v incl input-source reverse clamp voltage i in = -1 ma -1.1 -0.25 v i dss zero input voltage drain current (v in = 0) v ds = 13 v v in = 0 v ds = 25 v v in = 0 75 200 a a i iss supply current from input pin v ds = 0 v v in = 10 v 250 550 a
vnd7n04, vnd7n04-1, vnk7n04fm electrical specification 5/17 table 5. electrical characteristics: on symbol parameter test conditions min. typ. max. unit v in(th) input threshold voltage v ds = v in i d + i in = 1 ma 0.8 3 v r ds(on) static drain-source on resistance v in = 10 v i d = 3.5 a v in = 5 v i d = 3.5 a -40 < t j < 25 c v in = 10 v i d = 3.5 a v in = 5 v i d = 3.5 a t j = 125 c 0.14 0.28 0.28 0.56 ww w w table 6. electrical characteristics: dynamic symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds = 13 v i d = 3.5 a 2 5 s c oss output capacitance v ds = 13 v f = 1 mhz v in = 0 250 500 pf 1. pulsed: pulse duration = 300 s, duty cycle 1.5 % table 7. electrical characteristics: switching symbol parameter test conditions min. typ. max. unit t d (on) t r t d (off) t f turn-on delay time rise time turn-off delay time fall time v dd = 15 v i d = 3.5 a v gen = 10 v r gen = 10 w (see figure 26 ) 50 60 130 50 150 180 300 200 ns ns ns ns t d (on) t r t d (off) t f turn-on delay time rise time turn-off delay time fall time v dd = 15 v i d = 3.5 a v gen = 10 v r gen = 1000 w (see figure 26 ) 140 0.4 2.5 1 500 1.1 74 ns s s s (di/dt)on turn-on current slope v dd = 15 v i d = 3.5 a v in = 10 v r gen = 10 w 50 a/s q i total input charge v dd = 12 v i d = 3.5 a v in = 10 v 18 nc table 8. electrical characteristics: source drain di ode symbol parameter test conditions min. typ. max. unit v sd (1) forward on voltage i sd = 3.5 a v in = 0 1.7 v t rr (2) q rr (2) i rrm (2) reverse recovery time reverse recovery charge reverse recovery current i sd = 3.5 a di/dt = 100 a/s v dd = 30 v t j = 25 c (see test circuit, figure 28 ) 40 0.2 3.6 ns c a 1. pulsed: pulse duration = 300 s, duty cycle 1.5 % 2. parameters guaranteed by design/characterization
electrical specification vnd7n04, vnd7n04-1, vnk7n04fm 6/17 table 9. electrical characteristics: protection symbol parameter test conditions min. typ. max. unit i lim drain current limit v in = 10 v v ds = 13 v v in = 5 v v ds = 13 v 4 4 7 7 11 11 a a t dlim (1) step response current limit v in = 10 v v in = 5 v 13 15 20 25 s s t jsh (1) overtemperature shutdown 150 c t jrs (1) overtemperature reset 135 c i gf (1) fault sink current v in = 10 v v ds = 13 v v in = 5 v v ds = 13 v 50 20 ma ma e as (1) single pulse avalanche energy starting t j = 25c v dd = 20 v v in = 10 v r gen = 1 k w l = 30 mh 0.4 j 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %
vnd7n04, vnd7n04-1, vnk7n04fm protection features 7/17 3 protection features during normal operation, the input pin is electrica lly connected to the gate of the internal power mosfet. the device then behaves like a standa rd power mosfet and can be used as a switch from dc to 50 khz. the only difference f rom the user?s standpoint is that a small dc current (i iss ) flows into the input pin in order to supply the i nternal circuitry. the device integrates: l overvoltage clamp protection: internally set at 42 v , along with the rugged avalanche characteristics of the power mosfet stage give this device unrivalled ruggedness and energy handling capability. this feature is mainly important when driving inductive loads. l linear current limiter circuit: limits the drain cu rrent id to ilim whatever the input pin voltage. when the current limiter is active, the de vice operates in the linear region, so power dissipation may exceed the capability of the heatsink. both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold t jsh . l overtemperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input volt age. the location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. overtemperature cutout occurs at minimum 150 c. the device is automatically restarted when the chip temperatur e falls below 135 c. l status feedback: in the case of an overtemperature fault condition, a status feedback is provided through the input pin. the internal pro tection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100 w . the failure can be detected by monitoring the volta ge at the input pin, which will be close to ground potential. additional features of this device are esd protecti on according to the human body model and the ability to be driven from a ttl logic circu it (with a small increase in r ds(on) ).
protection features vnd7n04, vnd7n04-1, vnk7n04fm 8/17 figure 2. thermal impedance for dpak / ipak figure 3. derating curve figure 4. output characteristics figure 5. transconduc tance figure 6. static drain-source on resistance vs input voltage figure 7. static drain-source on resistance (part 1/2)
vnd7n04, vnd7n04-1, vnk7n04fm protection features 9/17 figure 8. static drain-source on resistance (part 2/2) figure 9. input charge vs input voltage figure 10. capacitance variations figure 11. normalize d input threshold voltage vs temperature figure 12. normalized on resistance vs temperature (part 1/2) figure 13. normalized on resistance vs temperature (part 2/2)
protection features vnd7n04, vnd7n04-1, vnk7n04fm 10/17 figure 14. turn-on current slope(part 1/2) figure 15. turn-on current slope(part 2/2) figure 16. turn-off drain-source voltage slope (part 1/2) figure 17. turn-off drain-source voltage slope (part 2/2) figure 18. switching time resistive load (part 1/3) figure 19. switching time resistive load (part 2/3)
vnd7n04, vnd7n04-1, vnk7n04fm protection features 11/17 figure 20. switching time resistive load (part 3/3) figure 21. current limit vs junction temperature figure 22. step response current limit figure 23. sour ce drain diode forward characteristics
protection features vnd7n04, vnd7n04-1, vnk7n04fm 12/17 figure 24. unclamped inductive load test circuits figure 25. unclamped inductive waveforms figure 26. switching times test circuits for r esistive load figure 27. input charge test circuit figure 28. test circuit for inductive load s witching and diode recovery times figure 29. waveforms
vnd7n04, vnd7n04-1, vnk7n04fm package information 1 3/17 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 30. to-252 (dpak) mechanical data
package information vnd7n04, vnd7n04-1, vnk7n04fm 14/17 figure 31. to-251 (ipak) mechanical data
vnd7n04, vnd7n04-1, vnk7n04fm package information 15/17 figure 32. sot-82fm mechanical data
revision history vnd7n04, vnd7n04-1, vnk7n04fm 16/17 5 revision history table 10. document revision history date revision changes 21-jun-2004 0.1 initial release. 18-mar-2009 1 document reformatted. added table 1: device summary on page 1 . u pdated section 4: package information on page 13
docid4336 rev 2 16/17 vnd7n04, vnd7n04-1, vnk7n04fm revision history 17 5 revision history table 10. document revision history date revision changes 21-jun-2004 1 initial release. 25-sep-2013 2 updated disclaimer
docid4336 rev 2 17/17 vnd7n04, vnd7n04-1, vnk7n04fm 17 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. a ll st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industr y domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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