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s1d16702 series rev.1.0 epson 5C1 1. description the s1d16702 is a 68 output low-power resistance common (row) driver which is suitable for driving a very high capacity dotmatrix lcd panels up to a duty ratio of 1/300. it is intended to be used in conjunction with the s1d16006 as a pair. since the s1d16006 is so designed to drive lcds over a wide range of voltages, and also the maximum potential v 0 of its lcd drive bias voltages is isolated from v dd to allow the lcd driving bias voltages to be externally generated optionally with a high accuracy, it can cope with a wide range of lcd panels. the s1d16702 is featured in its simple pad layout which is easy in mounting pc boards in addition to its selectable bidirectional driver output sequence. it also has 68 lcd output segments of high pressure resistance and low output impedance. it can display the 65 132 panel when used as the expansion driver of s1d15301 being built in ram (s1d16702 * 01 ** ). 2. features ? number of lcd drive output segments: 68 ? common output on resistance: 700 w (typ.) ? display duty ratio: 1/64 to 1/300 (reference) ? display capacity: possible to display 640 480 dots when used in combination with s1d16006. ? selectable pin output shift direction ? instantaneous display blanking enabled by inhibit function (s1d16702 * 00 ** ) ? non-bias display off function (s1d16702 * 01 ** ) ? adjustable offset bias of lcd power to v dd level ? wide range of lcd drive voltages: C7 v to C28 v (absolute maximum rated voltage: C30 v) ? logic system power supply: C2.7 v to C5.5 v ? shipping pattern S1D16702D00A * (al pad chip) s1d16702d01a * (al pad chip) s1d16702f00a * (80-pin qfp5) ? no radial rays countermeasure taken in designing ? non-bias display off function
s1d16702 series 5C2 epson rev.1.0 com0 com67 v1 v4 lcd driver 68 bit shift register 68 bit shift register 68 bit v0 v5 fr dio1 dio2 yscl shl inh com1 com2 v dd v ss * doff * inh in s1d16702 * 00 ** doff in s1d16702 * 01 ** 3. block diagram
s1d16702 series rev.1.0 epson 5C3 number of pins pin name com0 to com67 dio1, dio2 yscl shl doff inh fr v dd , v ss v 0 , v 1 , v 4 , v 5 i/o o i/o i i i i i power supply power supply shl com output shift direction dio1 dio2 low 0 ? 67 input output high 67 ? 0 ourput input function lcd drive common (row) output the output changes at the yscl falling edge. 100-bit shift register serial data input/output to be set to input or output according to the shl input the output changes at the yscl falling edge. serial data shift clock input the scanning data is shifted at the falling edge. display data latch pulse input (falling edge trigger) shift direction selection and dio pin i/o control input lcd display blanking control input when low is input, the content of shift register is cleared and all common outputs become the non-select level instantaneously. (s1d16702 * 01 ** ) lcd display blanking control input when low is input, the content of shift register is cleared and all common outputs become the non-select level instantaneously. common output = v 4 (when fr = low) common output = v 1 (when fr = high) (s1d16702 * 00 ** ) lcd drive output ac converted signal input logic power supply v dd : 0 v (gnd) v ss : C5.0 v lcd drive power supply v 5 : C7 v to C28 v v dd 3 v 0 3 v 1 >v 4 3 v 5 68 2 1 1 1 (1) 1 2 4 inh in s1d16702 * 00 ** doff in s1d16702 * 01 ** 4. pin description
s1d16702 series 5C4 epson rev.1.0 124 64 41 80 65 25 40 s1d16702f00a index 1 com 3 2 com 4 3 com 5 4 com 6 5 com 7 6 com 8 7 com 9 8 com 10 9 com 11 10 com 12 11 com 13 12 com 14 13 com 15 14 com 16 15 com 17 16 com 18 17 com 19 18 com 20 19 com 21 20 com 22 pin no. pin name 21 com 23 22 com 24 23 com 25 24 com 26 25 com 27 26 com 28 27 com 29 28 com 30 29 com 31 30 com 32 31 com 33 32 com 34 33 com 35 34 com 36 35 com 37 36 com 38 37 com 39 38 com 40 39 com 41 40 com 42 41 com 43 42 com 44 43 com 45 44 com 46 45 com 47 46 com 48 47 com 49 48 com 50 49 com 51 50 com 52 51 com 53 52 com 54 53 com 55 54 com 56 55 com 57 56 com 58 57 com 59 58 com 60 59 com 61 60 com 62 61 com 63 62 com 64 63 com 65 64 com 66 65 com 67 66 dio2 67 inh 68 fr 69 yscl 70 shl 71 v dd 72 v ss 73 v 0 74 v 1 75 v 4 76 v 5 77 dio1 78 com 0 79 com 1 80 com 2 pin no. pin name pin no. pin name pin no. pin name 5. pin layout package type: qfpC5 80pin
s1d16702 series rev.1.0 epson 5C5 pad pin xy no. name pad pin xy no. name pad pin xy no. name 61 com 56 C195 1357 62 com 57 C324 63 com 58 C453 64 com 59 C583 65 com 60 C712 66 com 61 C841 67 com 62 C970 68 com 63 C1099 69 com 64 C1229 70 com 65 C1358 71 com 66 C1487 72 dm C1616 1357 73 dm C1865 1201 74 com 67 1071 75 dio2 941 76 inh 715 77 fr 585 78 yscl 455 79 shl 325 80 v dd 195 81 v ss 55 82 v 0 C112 83 v 1 C252 84 v 4 C391 85 v 5 C531 86 dio1 C671 87 com 0 C810 88 com 1 C941 89 com 2 C1071 90 dm C1865 C1201 1 dm C1579 C1357 2 com 3 C1449 3 com 4 C1320 4 com 5 C1191 5 com 6 C1062 6 com 7 C933 7 com 8 C803 8 com 9 C674 9 com 10 C545 10 com 11 C416 11 com 12 C287 12 com 13 C154 13 com 14 C28 14 com 15 101 15 com 16 230 16 com 17 359 17 com 18 489 18 com 19 618 19 com 20 747 20 com 21 876 21 com 22 1005 22 com 23 1135 23 com 24 1264 24 com 25 1393 25 com 26 1522 26 dm 1651 27 dm 1781 C1357 28 dm 1976 C1098 29 com 27 1976 C969 30 com 28 1976 C840 31 com 29 1976 C711 32 com 30 C581 33 com 31 C452 34 com 32 C323 35 com 33 C194 36 com 34 C65 37 com 35 65 38 com 36 194 39 com 37 323 40 com 38 452 41 com 39 581 42 com 40 711 43 com 41 840 44 com 42 969 45 dm 1976 1098 46 dm 1743 1357 47 dm 1614 48 com 43 1485 49 com 44 1355 50 com 45 1226 51 com 46 1097 52 com 47 968 53 com 48 839 54 com 49 709 55 com 50 580 56 com 51 451 57 com 52 322 58 com 53 193 59 com 54 63 60 com 55 C66 1357 chip size: 4.27 3.03 mm chip thickness: 400 m m (for al pad product) and 525 m m (for bump product). al pad product: pad opening is 100 100 m m. bump product: vertical au bump. bump size is 90 90 m m. bump height is 17 to 25 m m. 1 27 72 y x (0,0) 46 28 45 90 dieno. 73 pad no. 76: inh for s1d16702 * 00 ** doff for s1d16702 * 01 ** *1 *1 pad center coordinates 6. pad pad layout
s1d16702 series 5C6 epson rev.1.0 (s1d16702 * 00 ** ) doff contents of fr com output voltage shift register high high v 5 (select level) high low v 0 low high v 1 (non-select low v 4 level) low fixed to low v 0 (non-select level) inh contents of fr com output voltage shift register high high v 5 (select level) high low v 0 low high v 1 (non-select low v 4 level) low fixed to low high v 1 (non-select low v 4 level) (s1d16702 * 01 ** ) 7. functional description shift register this is a bidirectional shift register to transfer common data. level shifter this is a level interface circuit used to convert the signal voltage level from the logic system level to lcd drive level. lcd driver circuit this driver outputs the lcd drive voltage. the relationship among the display blanking signal inh , contents of shift register, ac converted signal fr and common output voltage is as shown in the table below: the relationship among the display blanking signal inh , contents of shift register, ac converted signal fr and common output voltage is as shown in the table below.
s1d16702 series rev.1.0 epson 5C7 dio1 yscl shl=low 1/200 duty fr 1 frame shift register (200 lines) dio2 o0 o1 o2 q0 v 0 v 1 v 4 v 5 v 0 v 1 v 4 v 5 v 0 v 1 v 4 v 5 q1 q2 inh 68 lines 8. timing chart
s1d16702 series 5C8 epson rev.1.0 v dd =0v parameter symbol rating unit supply voltage (1) v ss C7.0 to +0.3 v supply voltage (2) v 5 C30.0 to +0.3 v supply voltage (3) v 0 , v 1 , v 4 v 5 C0.3 to +0.3 v input voltage v i v ss C0.3 to +0.3 v output voltage v o v ss C0.3 to +0.3 v output current (1) i o 20 ma output current (2) i ocom 20 ma operating temperature topr C40 to + 85 c storing temperature tstg C65 to +150 c soldering temperature and time tsol 260 c 10sec C 9. absolute maximum ratings notes: 1. the voltage of v 0 , v1 and v 4 must always satisfy the condition of v dd 3 v 0 3 v 1 3 v 4 3 v 5 . 2. floating of the logic system power during while the lcd drive system power is applied, or exceeding v ss = C2.6 v or more can cause permanent damage to the lsi. functional operation under these conditions is not implied. care should be taken to the power supply sequence especially in the system power on or off. 3. all the above voltage is based on v dd = 0 v.
s1d16702 series rev.1.0 epson 5C9 condition C C functional operation recommended value recommended value recommended value v ss =C2.7v to C5.5v v ss =C2.7v to C5.5v i oh =C0.3ma i oh =C0.2ma (v ss =C2.7 to C4.5v) i ol =+0.3ma i ol =+0.2ma (v ss =C2.7 to C4.5v) v ss v in 0v v ss v in 0v v 5 =C7.0 to C28.0v v ih =v dd , v il =v ss d von v 5 = =0.5v C20.0v v ss =C5.0v, v ih =vdd, v il =v ss , f yscl =12khz, frame frequency=60hz input data; high at no load every 1/200 duy other conditions are the same as v ss = C3.0 v v ss =C5.0v, v 1 =C2.0v, v 4 =C18.0v, v 5 =C20.0v other conditions are the same as in the item of i ss1 . ta=25 c min. C5.5 C28.0 C C2.5 2/9v 5 v 5 0.2v ss v ss 0.2v ss v ss C 0.4 v ss C C C C C C C C C typ. C5.0 C C C C C C C C C C C C C C 0.70 7 5 7 C C max. C2.7 C7.0 C7.0 0 v dd 7/9v 5 0 0.8v ss 0 0.85v ss 0 v ss +0.4 2.0 5.0 25 1.40 15 10 15 8 15 unit v v v v v v v v v v v v m a m a m a k w m a m a pf pf parameter supply voltage (1) recommended operating voltage operation enable voltage supply voltage (2) supply voltage (3) supply voltage (4) high input voltage (1) low input voltage (1) high input voltage (2) low input voltage (2) high output voltage low output voltage input leakage current input/output leakage current static current output resistance average operating current consumption (1) average operating current consumption (2) input pin capacitance input/output pin capacitance unless otherwise specified, v dd = v 0 = 0v, v ss = C5.0v 10%, ta = C40 to 85 c. symbol v ss v 5 v 5 v 0 v 1 v 4 v ih v il v iht v ilt v oh v ol i li i li/o i dds r com i ss1 i ss2 c i c i/o applicable pin v ss v 5 v 5 v 0 v 1 v 4 dio1, dio2, yscl, shl, fr inh dio1, dio2 yscl, shl, inh, fr dio1, dio2 v dd com0 to com99 v ss v 5 yscl, shl, inh, fr dio1, dio2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - when the v 1 , v 4 , v 0 or v 5 level is output 10. electrical characteristics dc characteristics
s1d16702 series 5C10 epson rev.1.0 ?.0 ?.4 ?.0 ?.0 ?.0 ?.5 ?. v ss ( v ) ?0 ?8 ?0 ?0 ? 0 0 v 5 (v) operating voltage range operating voltage range vss C v5 v 5 voltage must be set within the following operating voltage range of v ss C v 5 .
s1d16702 series rev.1.0 epson 5C11 fr yscl t r t f t wclh t dfr v ih =0.2 v ss v il =0.8 v ss t ds t dh t ccl t wcll dio1 dio2 unless otherwise specified v ss =C5.0v 10%, ta=C40 to 85 c parameter symbol condition min. max. unit input signal rise time t r CC50ns input signal fall time t f CC50ns yscl period t ccl C 500 C ns yscl high pulsewidth t wclh C70Cns yscl low pulsewidth t wcll C 330 C ns data setup time t ds C 100 C ns data hold time t dh C10Cns allowable fr delay time t dfr C C500 500 ns unless otherwise specified v ss =C2.7v to C4.5v, ta=C40 to 85 c parameter symbol condition min. max. unit input signal rise time t r CC50ns input signal fall time t f CC50ns yscl period t ccl C 1000 C ns yscl high pulsewidth t wclh C 160 C ns yscl low pulsewidth t wcll C 330 C ns data setup time t ds C 200 C ns data hold time t dh C10Cns allowable fr delay time t dfr C C500 500 ns the standard applicable to t ccl , t wclh , t wcll , t ds and t dh when v ss = C2.4 v must be 1.3 times of that applies when v ss = C2.7 v to C4.5 v. ac characteristics input timing characteristics
s1d16702 series 5C12 epson rev.1.0 unless otherwise specified v ss =C5.0v 10%, ta=C40 to 85 c parament symbol condition min. max. unit (yscl - fall to dio) delay time tpd docl cl=15pf 30 300 ns (yscl - fall to com output) delay time tpd ccl v 5 =C7.0 to C 3.0 m s (inh to com output) delay time tpd cinh C28.0v (fr to com output) delay time tpd cfr cl=100pf C 3.0 m s unless otherwise specified v ss =C2.7v to C4.5v, ta=C40 to 85 c parament symbol condition min. max. unit (yscl - fall to dio) delay time tpd docl cl=15pf 60 600 ns (yscl - fall to com output) delay time tpd ccl v 5 =C7.0 to C 3.0 m s (inh to com output) delay time tpd cinh C28.0v (fr to com output) delay time tpd cfr cl=100pf C 3.0 m s fr vn?.5v vn+0.5v t pddocl t pdccl t pdcfr t pdcinh yscl v ih =0.2 v ss v il =0.8 v ss inh com dio1 dio2 the standard applicable when v ss = C2.4 v must be 1.3 times of that applies when v ss = C2.7 v to C4.5 v. output timing characteristics
s1d16702 series rev.1.0 epson 5C13 11. lcd drive power each voltage level forming method to obtain each voltage level for lcd driving, it is the most simple to divide the resistance of potential as shown in the connection example. on the other hand, to obtain a high quality display, it is necessary to raise the accuracy and constancy of each voltage level and to set the divided resistance value as low as possible in the range of system power capacity. especially when a low-power lcd driving is required, set the divided resistance to a higher value and drive the lcd with a voltage follower by means of operational amplifier instead. in taking into consideration of a case where the operational amplifier is employed, the maximum potential level v 0 for lcd driving has been isolated from the v dd pin. when the potential of v 0 lowers than that of v dd and the potential difference between the two becomes larger, however, the capacity of lcd drive output driver lowers. to avoid it, use the system with the potential difference of 0 v to 2.5 v between v 0 and v dd . when no operational amplifier is used, connect v 0 and v dd pins. note in power on/off since this lsi is high in the voltage of lcd driving system, when a high voltage is applied to the lcd driving system with the logic system power supply kept floating, an overcurrent flows and lsi breaks down in some cases. be sure to follow the power on/off sequence as shown below: at power on ... logic system on ? lcd driving system on or simultaneous on of the both at power off ... lcd driving system off ? logic system off or simultaneous off of the both precautions: users of this development specification are reminded of the following precautions. 1. this development specification is subject to change without previous notice. 2. this specificatino does not warrant the user to exercise the industrial property right or other rights, nor does this specification vest such rights to the user. application examples provided in this specification are solely intended to ensure better understanding of the product. the manufacturer shall not be liable for any circuit related problem arising from using such examples. numeric representation of measure or size provided in the characteristics table is one obtained from the numeric line. 3. no part of this specification may be reproduced or duplicated in any form or by any means without the written permission of the manufacturer. 4. as for use of semiconductor elements, users are required to pay attention to the following points. [precautions on the product handling in light] characteristics of semiconductor elements are changed if they are exposed to light. thus, exposing this ic to light can result in its in malfunction. in order to prevent ic malfunctioning due to light, make sure that the following measures are taken for the boards or products equipped with our ic. (1) design and mounting procedure employed do not allow light to ic. (2) the inspection process is implemented in the environment that does not allow light to ic. (3) light shielding measures are established not only for surface of ic but also for rear face and side faces, too.
s1d16702 series 5C14 epson rev.1.0 s1d16702 * 00 ** s1d16300 ***** function bidirectional shift register bidirectional shift register inh inh 68 output segments 68 output segments output tr configuration fig. 1 fig. 2 pad layout identical to the equivalent product C pad coordinates different from the equivalent product C com v 0 v 1 v 4 v 5 com v 0 v 5 v 1 v 4 fig. 2 fig. 1 12. different points from replacement product

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