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  (c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 1/34 no reproduction and redistribution allowed. document version: 6 date: 2004/10/03 product functional specification 15.4 inch wxga color tft lcd module model name : b154ew01 v1 ( u ) preliminary specification ( ) final specification note: this specification is subject to change without notice. www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 2/34 no reproduction and redistribution allowed. i. contents 1.0 handling precautions 2.0 general description 2.1 characteristics 2.2 functional block diagram 3.0 absolute maximum ratings 4.0 optical characteristics 5.0 signal interface 5.1 connectors 5.2 signal pin 5.3 signal description 5.4 signal electrical characteristics 5.5 signal for lamp connector 6.0 pixel format image 7.0 parameter guide line for cfl inverter 8.0 interface timings 8.1 timing characteristics 8.2 timing definition 9.0 power consumption 10.0 power on/off sequence 11.0 reliability test condition 12.0 mechanical characteristics 13.0 shipping label format 14.0 carton package 15.0 shipping package of palletizing sequence 16.0 appendix: edid descriptipn ii record of revision version and date page old description new description remark 0.1. 2003/12/19 all first edition for customer all 0.2. 2004/01/08 5 weight: 580g weight: 585g www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 3/34 no reproduction and redistribution allowed. 5 add surface treatment 18 ccfl frequency: 55khz-65khz ccfl frequency: 50khz-70khz 23 mechanical drawing updated 0.3 2004/03/15 25 add description of screw hole length and torque 27 add carton package description 0.4 2004/04/28 5 physical size: 344x 222.0 x 6.5 max. physical size: 344x 222.0 x 6.8 max 21 idd current: 600ma typ. idd current: 500ma typ. 21 add idd current: 600ma max. 25 mechanical drawing updated 0.5 2004/06/28 31 add edid description 1.0 handing precautions 1) since front polarizer is easily damaged, pay attention not to scratch it. 2) be sure to turn off power supply when inserting or disconnecting from input connector. 3) wipe off water drop immediately. long contact with water may cause discoloration or spots. 4) when the panel surface is soiled, wipe it with absorbent cotton or other soft cloth. 5) since the panel is made of glass, it may break or crack if dropped or bumped on hard surface. 6) since cmos lsi is used in this module, take care of static electricity and insure human earth when handling. 7) do not open nor modify the module assembly. 8) do not press the reflector sheet at the back of the module to any directions. 9) in case if a module has to be put back into the packing container slot after once it was taken out from the container, do not press the center of the ccfl reflector edge. instead, press at the far ends of the cfl reflector edge softly. otherwise the tft module may be damaged. 10) at the insertion or removal of the signal interface connector, be sure not to rotate nor tilt the interface connector of the tft module. 11) after installation of the tft module into an enclosure (notebook pc bezel, for example), do not twist nor bend the tft module even momentary. at designing the enclosure, it should be taken into consideration that no bending/twisting forces are applied to the tft module from outside. otherwise the tft module may be damaged. www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 4/34 no reproduction and redistribution allowed. 12) cold cathode fluorescent lamp in lcd contains a small amount of mercury. please follow local ordinances or regulations for disposal. 13) small amount of materials having no flammability grade is used in the lcd module. the lcd module should be supplied by power complied with requirements of limited power source(2.11, iec60950 or ul1950), or be applied exemption. 14) the lcd module is designed so that the cfl in it is supplied by limited current circuit(2.4, iec60950 or ul1950). do not connect the cfl in hazardous voltage circuit. www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 5/34 no reproduction and redistribution allowed. 2.0 general description b154ew01 v1 is a color active matrix liquid crystal display composed of a tft lcd panel, a driver circuit, and backlight system. the screen format is intended to support the wxga (1280(h) x 800(v)) screen and 262k colors (rgb 6-bits data driver). all input signals are lvds interface compatible. inverter card of backlight is not included. b154ew01 v1 is designed for a display unit of notebook style personal computer and industrial machine. . www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 6/34 no reproduction and redistribution allowed. 2.1 display characteristics the following items are characteristics summary on the table under 25 condition: items unit specifications screen diagonal [mm] 391mm active area [mm] 331.2 x 207.0 pixels h x v 1280x3(rgb) x 800 pixel pitch [mm] 0.2588x0.2588 pixel arrangement r.g.b. vertical stripe display mode normally white typical white luminance (icfl=6.0ma) [cd/m 2 ] 195 min (5 point average) 220 typ. (5 point average) luminance uniformity 1.25 max. (5 pts) 1.50 max. (13pts) contrast ratio 300 min 400 typ optical rise time/fall time [msec] 18/7 nominal input voltage vdd [volt] +3.3 typ. typical power consumption (vdd line + vcfl line) [watt] 6.5w max weight [grams] 585g typ. physical size [mm] 344x 222.0 x 6.8 max. electrical interface 1 channel lvds surface treatment glare, harness 2h, haze 41.7%, reflectance 2.5% support color native 262k colors ( rgb 6-bit data driver ) temperature range operating storage (non-operating) [ o c] [ o c] 0 to +50 -20 to +60 www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 7/34 no reproduction and redistribution allowed. 2.2 functional block diagram the following diagram shows the functional block of the 15.4 inches color tft/lcd module: tft array/cell 6bit color data for r/g/b hsync vsync vdd lcd controller lcd drive card backlight unit 1280(r/g/b) x 3 x 800 gnd dc-dc converter ref circuit y - driver x - driver dsptmg (3 pairs lvds) dtclk (1 pair lvds) jae jae fi-xb30sl-hf10 mating type jae fi-s30m lcd connector jst bhsr - 02vs - 1 mating type sm02b-bhss-1 lamp connector www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 8/34 no reproduction and redistribution allowed. 3.0 absolute maximum ratings absolute maximum ratings of the module is as following: item symbol min max unit conditions logic/lcd drive voltage vdd -0.3 +4.0 [volt] input voltage of signal vin -0.3 vdd+0.3 [volt] ccfl current icfl - 6.5 [ma] rms ccfl ignition voltage vs - 1000 vrms operating temperature top 0 +50 [ o c] note 1 operating humidity hop 8 95 [%rh] note 1 storage temperature tst -20 +60 [ o c] note 1 storage humidity hst 5 95 [%rh] note 1 vibration 1.5 10-500 (random) g hz 2hrs/axis, x,y,z shock(non-operating) 220 , 2 g ms half sine wave note 1 : maximum wet-bulb should be 39 and no condensation. www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 9/34 no reproduction and redistribution allowed. 3.1 wet-bulb temperature chart twb=39 c operating range storage range www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 10/34 no reproduction and redistribution allowed. 4.0 optical characteristics the optical characteristics are measured under stable conditions as follows under 25 condition: item conditions typ. note viewing angle [degree] horizontal (right) k = 10 (left) 70 70 note 4, note 6 k: contrast ratio [degree] vertical (upper) k = 10 (lower) 60 60 note 4,note 6 contrast ratio 400 note 4 luminance uniformity 1.25 max. (5 pts) 1.50 max. (13pts) note 1, note 2,note 3, note 4 cross talk % 4% max note 5 response time [msec] rising 18 note 7 (room temp.) [msec] falling 7 note 7 color red x 0.600+/-0.03 chromaticity red y 0.350+/-0.03 coordinates (cie) green x 0.310+/-0.03 green y 0.550+/-0.03 blue x 0.150+/-0.03 blue y 0.115+/-0.03 white x 0.313+/-0.03 white y 0.329+/-0.03 note 4 white luminance (ccfl 6.0 ma) [cd/m 2 ] 195min(5 points average) 220 (5 points average) note 1, note 2, note 4 www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 11/34 no reproduction and redistribution allowed. note 1: 5 points position (display area : 331.2mm x 207.0mm) 12 3 4 5 h/4 h/4 h/4 h/4 h w w/4 w/4 w/4 w/4 note 2: 13 points position w/4 w w/4 h h/4 h/4 h/4 h/4 7 9 10 w/4 1 8 w/4 10 10 10 10 2 3 13 12 45 6 11 note 3: the luminance uniformity of 5 and 13 points is defined by dividing the maximum luminance values by the minimum test point luminance w13 = maximum brightness of th irteen points minimum brightness of thirteen points maximum brightness of five points w5 = minimum brightness of five points www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 12/34 no reproduction and redistribution allowed. note 4: measurement method the lcd module should be stabilized at given temperature for 30 minutes to avoid abrupt temperature change during measuring. in order to stabilize the luminance, the measurement should be executed after lighting backlight for 30 minutes in a stable, windless and dark room. note 5 definition of cross talk (ct) ct = | y b C y a | / y a 100 (%) where y a = luminance of measured location without gray level 0 pattern (cd/m 2 ) y b = luminance of measured location with gray level 0 pattern (cd/m 2 ) center of the screen tft-lcd module 50 cm photodetector ( bm - 5a,bm - 7 or lcd panel field= 2 www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 13/34 no reproduction and redistribution allowed. note 6: definition of response time: the output signals of bm-7 or equivalent are measured when the input signals are changed from black to white (falling time) and from white to black (rising time), respectively. the response time interval between the 10% and 90% of amplitudes. refer to figure as below. note 7. definition of viewing angle viewing angle is the measurement of contrast ratio R 10, at the screen center, over a 180 horizontal and 180 vertical range (off-normal viewing angles). the 180 viewing angle range is broken down as follows; 90 ( ) horizontal left and right and 90 ( ) vertical, high (up) and low (down). the measurement direction is typically perpendicular to the display surface with the screen rotated about its center to develop the desired measurement viewing angle. 5.0 signal interface s i g n a l ( r e l a t i v e v a l u e ) "black" tr tf "white" "white" 0% 10 % 90 % 100 % www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 14/34 no reproduction and redistribution allowed. 5.1 connectors physical interface is described as for the connector on module. these connectors are capable of accommodating the following signals and will be following components. connector name / designation for signal connector manufacturer jae or compatible type / part number fi-xb30sl-hf10 or compatible mating housing/part number fi-x30m, fi-x30c or fi-x30h mating contact/part number fi-c3-a1 connector name / designation for lamp connector manufacturer jst type / part number bhsr-02vs-1 mating type / part number sm02b-bhss-1-tb 5.2 signal pin pin# signal name pin# signal name 1 gnd 2 vdd 3 vdd 4 vedid 5 nc 6 clkedid 7 dataedid 8 rxin0- 9 rxin0+ 10 gnd 11 rxln1- 12 rxln1+ 13 gnd 14 rxin2- 15 rxin2+ 16 gnd 17 rxclkin- 18 rxclkin+ 19 gnd 20 gnd 21 nc 22 nc 23 nc 24 nc 25 nc 26 nc 27 nc 28 nc 29 nc 30 nc www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 15/34 no reproduction and redistribution allowed. 5.3 signal description the module is use a lvds receiver. lvds is a differential signal technology for lcd interface and high speed data transfer device. transmitter shall be sn75lvds86 (negative edge sampling) or compatible. signal name description rxin0-, rxin0+ lvds differential data input(red0-red5, green0) rxin1-, rxin1+ lvds differential data input(green1-green5, blue0-blue1) rxin2-, rxin2+ lvds differential data input(blue2-blue5, hsync, vsync, dsptmg) rxclkin-, rxclkin0+ lvds differential clock input vdd +3.3v power supply gnd ground note: input signals shall be low or hi-z state when vdd is off. internal circuit of lvds inputs are as following. www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 16/34 no reproduction and redistribution allowed. the module uses a 100ohm resistor between positive and negative data lines of each receiver input signal name description red5 red4 red3 red2 red1 red0 red data 5 (msb) red data 4 red data 3 red data 2 red data 1 red data 0 (lsb) red-pixel data red-pixel data each red pixel's brightness data consists of these 6 bits pixel data. green 5 green data 5 (msb) green-pixel data r r r r sn75lvds86 or compatible signal input pin no. 9 11 12 14 15 17 18 8 rxin0+ rxin0- rxin1+ rxin1- rxin2+ rxin2- rxclkin+ rxclkin- www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 17/34 no reproduction and redistribution allowed. green 4 green 3 green 2 green 1 green 0 green data 4 green data 3 green data 2 green data 1 green data 0 (lsb) green-pixel data each green pixel's brightness data consists of these 6 bits pixel data. blue 5 blue 4 blue 3 blue 2 blue 1 blue 0 blue data 5 (msb) blue data 4 blue data 3 blue data 2 blue data 1 blue data 0 (lsb) blue-pixel data blue-pixel data each blue pixel's brightness data consists of these 6 bits pixel data. dtclk data cloc k the typical frequency is 68.9 mhz.. the signal is used to strobe the pixel data and dsptmg signals. all pixel data shall be valid at the falling edge when the dsptmg signal is high. dsptmg display timing this signal is strobed at the falling edge of -dtclk. when the signal is high, the pixel data shall be valid to be displayed. vsync vertical sync the signal is synchronized to -dtclk . hsync horizontal sync the signal is synchronized to -dtclk . note: output signals from any system shall be low or hi-z state when vdd is off. 5.4 signal electrical characteristics input signals shall be low or hi-z state when vdd is off. it is recommended to refer the specifications of sn75lvds86dgg(texas instruments) in detail. signal electrical characteristics are as follows; parameter condition min max unit vth differential input high voltage(vcm=+1.2v) 100 [mv] vtl differential input low voltage(vcm=+1.2v) -100 [mv] lvds macro ac characteristics are as follows: www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 18/34 no reproduction and redistribution allowed. min. max. clock frequency (t) 50mhz 85mhz data setup time (tsu) 1ns data hold time (thd) 1ns 5.5 signal for lamp connector pin # signal name 1 lamp high voltage 2 lamp low voltage thd tsu input clock input data t www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 19/34 no reproduction and redistribution allowed. 6.0 pixel format image following figure shows the relationship of the input signals and lcd pixel format. r g b r g b r g b r g b r g b r g b r g b r g b 0 1 1279 1280 1st line 800th line 7.0 parameter guide line for cfl inverter parameter min dp-1 max units condition white luminance 5 points average - 220 ? [cd/m 2 ] (ta=25 ) ccfl current(icfl) 3.0 6.0 6.5 [ma] rms (ta=25 ) note 2 ccfl frequency(fcfl) 50 60 70 [khz] (ta=25 ) note 3,4 ccfl ignition voltage(vs) 991 [volt] rms (ta= 0 ) note 5 ccfl voltage (reference) (vcfl) 648 720 792 [volt] rms (ta=25 ) note 6 ccfl power consumption (pcfl) 3.87 4.3 4.73 [watt] (ta=25 ) note 6 note 1: dp-1 are auo recommended design points. *1 all of characteristics listed are measured under the condition using the auo test inverter. www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 20/34 no reproduction and redistribution allowed. *2 in case of using an inverter other than listed, it is recommended to check the inverter carefully. sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen. *3 in designing an inverter, it is suggested to check safety circuit very carefully. impedance of cfl, for instance, becomes more than 1 [m ohm] when cfl is damaged. *4 generally, cfl has some amount of delay time after applying kick-off voltage. it is recommended to keep on applying kick-off voltage for 1 [sec] until discharge. *5 cfl discharge frequency must be carefully chosen so as not to produce interfering noise stripes on the screen. *6 reducing cfl current increases cfl discharge voltage and generally increases cfl discharge frequency. so all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high-voltage output of the inverter. note 2: it should be employed the inverter which has duty dimming , if icfl is less than 4ma. note 3: cfl discharge frequency should be carefully determined to avoid interference between inverter and tft lcd. note 4: the frequency range will not affect to lamp life and reliability characteristics. note 5: cfl inverter should be able to give out a power that has a generating capacity of over 1,400 voltage. lamp units need 1,400 voltage minimum for ignition. note 6: calculator value for reference (icfl vcfl=pcfl) 8.0 interface timings basically, interface timings should match the 1280x800 /60hz manufacturing guide line timing. 8.1 timing characteristics parameter symbol min. typ. max. unit condition clock frequency 1/ t clock 50 68.9 85 mhz period t v 803 816 832 active t vd 800 800 800 vertical section blanking t vb 3 16 32 t line period t h 1302 1408 1700 active t hd 1280 1280 1280 horizontal section blanking t hb 22 128 420 t clock end-frame checking period tef 2 t line de checking period tde 6400 t line 8 frames www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 21/34 no reproduction and redistribution allowed. 8.2 timing definition 9.0 power consumption input power specifications are as follows; symble parameter min typ max units condition vdd logic/lcd drive voltage 3.0 3.3 3.6 [volt] load capacitance 20uf pdd vdd power 2 [watt] all black pattern pdd max vdd power max 2 [watt] max pattern note idd idd current 500 ma all black pattern idd max idd current max 600 ma max pattern note i rush inrush current 1800 ma vddrp allowable logic/lcd drive ripple voltage 100 [mv] p-p vddns allowable logic/lcd drive ripple noise 100 [mv] p-p note : vdd=3.3v dotclk de t h t hb t hd de t v t vb t vd input timing definition ( de mode) t clock input data pixel 1 pixel 2 pixel 3 pixel n-1 pixel n invaild data invaild data pixel 1 www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 22/34 no reproduction and redistribution allowed. 10. power on/off sequence vdd power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi-z state or low level when vdd is off. 90% 10% 10% 10% 90% 0-10ms max. 0-50 ms 0-50 ms 0 v 0 v vdd signals 10% 10% 200ms min. 200ms min 0 v lamp on 10% 10% 400ms min. 0-10ms max. www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 23/34 no reproduction and redistribution allowed. 11.0 reliability test condition items required condition note temperature humidity bias 40 /90%,300hr high temperature operation 60 /dry,300hr low temperature operation 0 ,300hr on/off test 25 ,150hrs(on/10 sec. off/10sec., 10,000 cycles) hot storage 60 /35% rh ,250 hours cold storage -20 /50% rh ,250 hours thermal shock test -20 /30 min ,60 /30 min 100cycles hot start test 50 /1 hr min. power on/off per 5 minutes, 5 times cold start test 0 /1 hr min. power on/off per 5 minutes, 5 times shock test (non- operating) 220g, 2ms, half-sine wave vibration test (non- operating) random vibration, 1.5 g zero-to-peak, 10 to 500 hz, 30 mins in each of three mutually perpendicular axes. esd contact : 8kv/ operation air : 15kv / operation note 1 room temperature test 25 , 2000hours, operating with loop pattern note1: some performance degradation allowed. no data lost. self-recoverable. no hardware failures. www..net
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(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 25/34 no reproduction and redistribution allowed. 12. mechanical characteristics 12.1 lcm outline dimension www..net
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(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 27/34 no reproduction and redistribution allowed. 12.2 screw hole depth and center position screw hole minimum depth, from side surface =2.5 mm (see drawing) screw hole center location, from front surface = 3.7 0.2mm (see drawing) screw torque: maximum 2.5 kgf-cm www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 28/34 no reproduction and redistribution allowed. 13. shipping label format note 1: *xxxxxxxxxxxx-xxxxx 04/01 0axxx 83mm 23m hardware : note1 firmware model name week code manufacturing area control code note1 0a 1 v. b154ew01 v1 ic combinationcontrol codeh/w source ic: nt 39360 gate ic: nt 3959a0axxx0a source ic: tsb t6l92a gate ic: nec upd160703 1axxx1a www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 29/34 no reproduction and redistribution allowed. 14. carton package the outside dimension of carton is 455 (l)mm x 380 (w)mm x 355 (h)mm u www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 30/34 no reproduction and redistribution allowed. 15. shipping package of palletizing sequence u top cardboard wooden pallet bottom cardboard corner angle stretch film pe band note : limit of box palletizing = max 3 layers(ship and stock conditions) www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 31/34 no reproduction and redistribution allowed. 16.0 appendix: edid descriptipn b154ew01 edid table address function value value value notes hex hex bin dec 00 header 00 00000000 0 01 ff 11111111 255 02 ff 11111111 255 03 ff 11111111 255 04 ff 11111111 255 05 ff 11111111 255 06 ff 11111111 255 07 00 00000000 0 08 eisa manuf. code lsb 06 00000110 6 ascii data string:b154ew01 09 compressed ascii af 10101111 175 auo 0a product code 0d 00001101 13 13(15b13) 0b hex, lsb first 0f 00001111 15 15(15b13) 0c 32-bit ser # 01 00000001 1 unused 0d 01 00000001 1 0e 01 00000001 1 0f 01 00000001 1 10 week of manufacture 2a 00101010 42 week 42 11 year of manufacture 0d 00001101 13 13(2003-1990=13) 12 edid structure ver. 01 00000001 1 13 edid revision # 03 00000011 3 14 video input definition 80 10000000 128 digital input 15 max h image size 21 00100001 33 33.12cm 16 max v image size 15 00010101 21 20.7cm 17 display gamma 78 01111000 120 gamma 2.2 18 feature support 0a 00001010 10 no dpms,active off,rgb color 19 red/green low bits 47 01000111 71 1a blue/white low bits a0 10100000 160 1b red x/ high bits 99 10011001 153 rx=0.6 1c red y 59 01011001 89 ry=0.35 www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 32/34 no reproduction and redistribution allowed. 1d green x 4f 01001111 79 gx=0.310 1e green y 8c 10001100 140 gy=0.550 1f blue x 26 00100110 38 bx=0.15 20 blue y 1d 00011101 29 by=0.115 21 white x 50 01010000 80 wx=0.313 22 white y 54 01010100 84 wy=0.329 23 established timing 1 00 00000000 0 unused 24 established timing 2 00 00000000 0 25 manufacturer's timing 00 00000000 0 26 standard timing #1 01 00000001 1 unused 27 01 00000001 1 28 standard timing #2 01 00000001 1 29 01 00000001 1 2a standard timing #3 01 00000001 1 2b 01 00000001 1 2c standard timing #4 01 00000001 1 2d 01 00000001 1 2e standard timing #5 01 00000001 1 2f 01 00000001 1 30 standard timing #6 01 00000001 1 31 01 00000001 1 32 standard timing #7 01 00000001 1 33 01 00000001 1 34 standard timing #8 01 00000001 1 35 01 00000001 1 36 pixel clock/10,000 (lsb) ea 11101010 234 timing descriptor #1 37 pixel clock/10,000 (msb) 1a 00011010 26 1280x800 @60_mode:pixel clock=68.9mhz 38 horiz. active pixels(lower 8 bits) 00 00000000 0 horiz active=1280 pixels 39 horiz.blanking (lower 8 bits) 80 10000000 128 horiz blanking=128 pixels 3a horiz. active pixels:horiz. blanking (upper4:4 bits) 50 01010000 80 3b 20 00100000 32 vertcal active=800 lines 3c 10 00010000 16 vertical blanking=16 lines 3d vert. active pixels:vert. blanking (upper4:4 bits) 30 00110000 48 3e 15 00010101 21 horiz sync. offset=21 pixels www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 33/34 no reproduction and redistribution allowed. 3f 20 00100000 32 horiz sync. pulse width=32 pixels 40 vert. sync. offset=xx lines, sync width=xx lines 44 01000100 68 verti sync. offset=4 lines,sync width=4 lines 41 horz. ver. sync/width (upper 2 bits) 00 00000000 0 42 hori. image size (lower 8 bits) 4b 01001011 75 hori image size= 331 mm 43 vert. image size (lower 8 bits) cf 11001111 207 verti image size = 207mm 44 hori. image size : vert. image size (upper 4 bits) 10 00010000 16 45 00 00000000 0 horizontal border = 0 46 00 00000000 0 vertical border = 0 47 18 00011000 24 48 detailed timing/monitor 00 00000000 0 ascii data string:b154ew01 49 descriptor #2 00 00000000 0 4a 00 00000000 0 4b 0f 00001111 15 4c 0 00000000 0 4d 42 01000010 66 b 4e 31 00110001 49 1 4f 35 00110101 53 5 50 34 00110100 52 4 51 45 01000101 69 e 52 57 01010111 87 w 53 30 00110000 48 0 54 31 00110001 49 1 55 0a 00001010 10 56 20 00100000 32 57 20 00100000 32 58 20 00100000 32 59 20 00100000 32 edid version. 5a detailed timing/monitor 00 00000000 0 ascii data string:b154ew01 5b descriptor #3 00 00000000 0 5c 00 00000000 0 5d fe 11111110 254 5e 0 00000000 0 5f 41 01000001 65 a 60 55 01010101 85 u www..net
(c) copyright au optronics, inc. august, 2003 all rights reserved. b154ew01 v1 ver.6 34/34 no reproduction and redistribution allowed. 61 4f 01001111 79 o 62 0a 00001010 10 63 20 00100000 32 64 20 00100000 32 65 20 00100000 32 66 20 00100000 32 67 20 00100000 32 68 20 00100000 32 69 20 00100000 32 6a 20 00100000 32 6b 20 00100000 32 6c detailed timing/monitor 00 00000000 0 monitor name: color lcd 6d descriptor #4 00 00000000 0 6e 00 00000000 0 6f fe 11111110 254 70 00 00000000 0 71 42 01000010 66 b 72 31 00110001 49 1 73 35 00110101 53 5 74 34 00110100 52 4 75 45 01000101 69 e 76 57 01010111 87 w 77 30 00110000 48 0 78 31 00110001 49 1 79 0a 00001010 10 7a 20 00100000 32 7b 20 00100000 32 7c 20 00100000 32 7d 20 00100000 32 7e extension flag 00 00000000 0 7f checksum 44 01000100 68 check sum www..net


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