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NB638 high efficiency , fast transient, 7a , 28v sy nchronous step-down converter in a tiny 3x4mm qfn package NB638 rev.1.16 www.monolithicpower.com 1 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. the future of analog ic technology descri ption the NB638 is a fully int egrated, hig h frequency synchronous rectified step-down switch mode converter. it offers a very compact solution to achieve 7a continuous output cur r ent over a wide input supply range with excelle nt load an d line regulation. the n b 638 operates at high efficiency over a wide ou tput current load range. constant-on-time (cot) co ntrol mod e provides fast transient re sponse and eases loop stabilization. full p r ot ectio n fea t u r e s in clude scp , ocp, ovp, uvp an d t h e r mal sh utd o w n. t h e nb63 8 req u i r es a mi ni mu m n u m b e r of read ily available sta nda rd ext e rn al compo n e n t s and is ava i lab l e in a spa c e-saving qfn2 0 (3x4mm) pa ckage . features ? wide 4.5v to 28v operating input range ? 7a output current ? internal 30 m ? high-si de, 12m ? low-side power mos f ets ? proprietary switching l o ss reduction technique ? 1% reference voltage ? programma ble soft start time ? soft shutdown ? 200khz to 1 m hz switching frequency ? scp, ocp, ovp, uvp protection and thermal sh utdown ? output adjustable from 0.8v to 13v ? availa ble i n a q f n 2 0 ( 3 x 4 m m ) packag e appli c ations ? notebook systems and i/o power ? networking systems ? optical communication systems ? distributed power and pol systems al l m ps pa rts a r e lea d - fr ee an d a d h e r e to t h e ro hs d i rect i v e. f o r m p s g r e e n sta t u s , plea se v isit mps w ebsite under produ cts, quali t y assuran c e page. ?mp s ? a n d ?t he fu ture o f a n a l og ic te ch no lo gy ? a r e re gi stere d tra dem ar ks o f monolithic power systems, inc. typical application 5 6 4 3 2 7 9,10,17,18 1 20 8,19 11-16 in vcc pgood freq en pgnd agnd ss sw fb bst r7 c in c2 c ss 33nf c3 r4 r1 r2 c4 NB638 vi n en v o u t 1 . 05v http://
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 2 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. ordering information part number* package top marking NB638dl qfn20 (3x4mm) NB638 * for tap e & reel, ad d suf f ix ?z (e.g. NB638dl?z ) for rohs co mpliant pa ckaging, ad d su ffix ?lf (e.g. NB638 dl ?lf ?z) package reference t o p view 1 2 3 4 5 6 16 15 14 13 12 agnd freq fb ss en pgood pgnd pgnd pgnd pgnd pgnd pgnd sw sw bst exposed p ad on backside in sw sw vcc in in in in sw sw 789 10 11 20 19 18 17 absolute m a xi mum ratings (1) supply voltage v in ....................................... 30v v sw ........................................ -0.3v to v in + 0.3v v bst ...................................................... v sw + 6v i vin (rms) ........................................................ 3.5a v pgood .................................... -0.3v to v cc +0.6v all other pins .................................. -0.3v to +6v continuous power dissipation (t a = +25c) (2) ???? ? ???? ? ??? ?? ???.2.6 w junction te mperature ............................... 150 c lead temperature .................................... 260 c storage temperature ............... -65 c to +150 c recommended operating conditions (3) supply voltage v in ........................... 4.5v to 28v output voltage v out ......................... 0.8v to 13v maxi mum j unct. temp (t j ) ...... -40 c to +125 c thermal resistance (4) ja jc q f n 2 0 ( 3 x 4 m m ) ...................... 48 ...... 10 ... c/w notes : 1) exceeding these ratings ma y da m age the device. 2) the ma ximum allowable po w e r dissipation is a fun c tion of the maximum junction tempe r ature t j (max), the junction-to- ambient therm a l resistance ja , a nd the a m bient t e mperatu r e t a . the ma ximu m allow able cont inuous po w e r di ssipation at an y ambient tem peratur e is calculated b y p d (max)=(t j (max)- t a )/ ja . excee d ing the maximum allow able po wer dissipation w ill cause ex cessive die temperature, and the reg u l ator w ill go into thermal sh utdo w n . inte rnal thermal shutdo w n circuitr y protects the device from perma ne nt damage. 3) the device is not guarant eed to function outside of its operating conditions. 4) measured on je sd51-7, 4 - la y e r pcb.
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 3 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. electri c al characteristi cs v in = 12v, t a = +25 c, unless otherw ise noted . parameters sy mbol conditio n min t y p max units supply cu rre nt (shutdo wn ) i in v en = 0v 0 a supply curre nt (quie s cent ) i in v en = 2v v fb = 1v 500 a hs s w it ch o n re sist a n c e (5) hs rds-on 30 m ? ls s w it ch on resi st an ce (5 ) ls rds-on 12 m ? switch leaka ge sw lkg v en = 0v v sw = 0v or 1 2 v 0 10 a current limit i li m it 12 a one-s hot on time t on r7 =30 1 k ? v out =1. 2 v 250 ns minimum off time (5) t off 100 ns fold-ba ck off time (5) t fb i li m =1(hig h) 1.4 s ocp hold-off time (5) t oc i li m =1(hig h) 40 s t a =25 c 807 815 823 feedb ack vol t age v fb 0 c NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 4 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. pin functio n s pin # nam e description 1 agnd analog ground. 2 freq frequency set during ccm operation. the on period is determined by the input voltage and the frequency-set resistor conne cted to freq pin. connect a resistor to in for line feed-forward. decouple with a 1nf capacitor. 3 fb feedback. an external resistor divider fr om the output to gnd, tapped to the fb pin, sets the output voltage. 4 ss soft start. conne ct an external ss capa cito r to prog ram the soft start time for the swit ch mod e regul ator. wh en the en pin beco m e s high, an intern al current sou r ce (8.5a) charges up the ss capacitor and the ss voltage slowly ramps up from 0 to v fb smoothly. when the en pin becomes low, an internal current source (8.5 a ) discharges the ss capacitor and the ss voltage slowly ramps down. 5 en en=1 to enable the NB638. for automatic start-up, connect en pin to in with a 100k ? resistor. it includes an internal 1m ? pull-down resistor. 6 pgoo d powe r goo d output. the output of this pin i s an o pen d r ain a n d is hig h if the output voltag e is hig h e r th an 90% of th e nomin al vol t age. the r e i s del ay from fb 90% to pgood hig h , whi c h is 5 0 % of ss time plus 0.5ms. 7 bst bootstrap. a 0.1f-1f capacitor connec ted between sw and bs pins is required to form a floating supply across the high-side switch driver. 8, 19 in supply voltage. the NB638 operates from a +4.5v to +28v input rail. c in is needed to decouple the input rail. use wide pcb traces and multiple vias to make the connection. 9, 10, 17, 18 sw switch output. use wide pcb trac es and multiple vias to make the connection. 11-1 6 pgnd system ground. this pin is the referenc e ground of the regulated output voltage. for this reason care must be taken in pcb layout. 20 vcc internal bias supply. decouple with a 1f capacitor as close to the pin as possible.
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 5 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics v in =12v, v out =1.05v, l=1h, t a =+25c, unless otherwise noted.
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 6 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.05v, l=1h, t a =+25c, unless otherwise noted.
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 7 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.05v, l=1h, t a =+25c, unless otherwise noted.
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 8 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. block diagram figure 1?functional block diagram
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 9 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. operation pwm operation the NB638 is a fu lly integrated synchronous rectified st ep-down switch mode converter. constant-on-time (cot) control is employed t o provide fast transient r e sponse an d easy loo p stabilization. at the beginning of ea ch cycle, th e high-side mosfet (hs-fet) is tur ned on wh en the feedback voltage (v fb ) is below the reference voltage (v ref ), which in dicates insu fficient outp u t voltage. the on period is deter mined by the input voltag e and the f r equency-set resist or a s follows: () ( ) () () on in 6r 7 k tn s 4 0 n s vv 0 . 4 =+ ? (1) after the on period elapses, the hs-fet is turned off, or becomes off state. it is turned on again when v fb drops below v ref . by repeating operation th is way, the converter r egulates th e output voltage. the inte grated low-side mosfet (ls-fet) is turned on w hen the hs-fet is in it s off state to minimize the conduction loss. the re will be a de ad short be tween input and gnd i f both hs-fet and ls-fet are turned on at th e same time. it?s calle d shoot-through. in order to avoid shoot-through, a dead-time (dt) is internally generated between hs-f et off and ls- fet on, or ls-fet off and hs-fet on. heav y - loa d operatio n figure 2?heav y loa d operatio n as figure 2 shows, when the outp u t current is high, the hs-fet and ls-fet repeat on/off a s described a bove. in this operation, the inducto r current will never go to zero. it?s calle d continuous- c onduction- mode (ccm) operation. in ccm operation, the switching frequ ency (f sw ) is fairly consta nt. light-load operation at light loa d or no lo ad conditio n , the outp u t drops very slowly and the NB638 reduces the switching fr equency automatically to maintain high efficien cy. the light load operation is show n in figure 3. the v fb d oes not rea c h v ref when the inductor current is approaching zero. the ls- fet driver t u rns into tri-state (high z) wheneve r the inducto r current reaches zer o. a current modulator takes over the control o f ls-fet and limits the inductor cur r ent to le ss than -1m a . hence, the output capa citors d i sch arge slowly to gnd throug h ls-fet. as a result, the efficien cy at light load condition is greatly improved. at light load condit i on, the hs-fet is not t u rned on as frequently as at heavy load condition. this is called skip mode. figure 3?light load operation as the output current increases from the lig ht load condition, the time period within which t he current modulator regulates beco m es shorter. the hs-fet is t u rne d on more frequently. hence, th e switchin g frequen cy increases correspondingly. the output curren t reaches th e critica l level when the current modulator time is zero. the critical level of the outp u t current is determined as follows: in o u t o u t out sw in (v v ) v i 2l f v ? = ( 2 )
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 10 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. it turns into pwm mode once the output current exceeds the critica l level. after that, the switching frequency stays fairly constant over the output current rang e. sw itching frequenc y constant o n -time (cot) control is used in t h e NB638 and there is no dedicated o scillator in t he ic. the inpu t voltage is f eed-forwarded to the on - time one-shot timer through the resistor r7. the duty ratio is kept as v out /v in . hence, t he switching frequency is fairly con s tant over t h e input voltag e range. the switch ing frequen c y can be set a s follows: () () () () () () 6 sw in deal y in o u t 10 fk h z 6r 7 k v v tn s vv 0 . 4 v v = + ? (3) where t delay is the comparator de lay. it?s about 40ns. 0 200 400 600 800 1000 1200 1400 0 200 400 600 10 00 800 fr e quency (khz) frequency vs. r freq v out =3.3v v out =2.5v v out =1.05v generally, the NB638 is set for 200 khz to 1mhz application . it is optimized to o perate at h i gh switching fr equency with high eff i ciency. hig h switching frequency makes it possible t o utilize small sized lc filter co mponents to save syst em pcb space. jitter and fb ramp sl ope figure 4 and figure 5 show jitter occurring in both pwm mode and s k ip mode. when there is noise in the v fb downwa r d slope, the on time o f hs-fet de viates from its intended location an d produces jitt er. it is necessary to un derstand th at there is a relationship between a system?s stability an d the steep ness of the v fb ripple?s downward slope. the slope steepne ss of the v fb ripple dominates in noise immunit y . the magnitude of the v fb rip p le doesn?t directly affe ct the noise im munity directly. figure 4?jitter in pwm mode figure 5?jitter in skip mode ramp w i th large esr cap in the case of poscap or other types of capacitor with larger esr is applied as output capacitor. t he esr ripple dominates the output ripple, and the slope o n the fb is quite es r related. fig u re 6 shows an equivalent circu i t in pwm mode with the hs-fet off a nd without an external ramp circuit. turn to applicatio n information section for design step s with large esr caps. r1 r2 esr po sc ap sw fb vo l figure 6?simplified circuit in pwm mode w i thout ext e rnal ramp compensation to realize t he stability when no external ramp is used, usually the esr value should be chosen as follow:
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 11 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. sw on esr ou t tt 0.7 2 r c + (4) tsw is the switching period. ramp w i th small esr cap when the output capa citors are ceramic ones, the esr ripple is not high enough t o stabilize t he system, an d external ramp co mpensation is needed. skip to application information sectio n for design st eps with small esr caps. r1 r2 ce r a m i c sw fb vo l r4 c4 i r4 i c4 i fb r9 figure 7?simplified circuit in pwm mode w i th external ramp compensation in pwm mo de, an equivalent circu i t with hs-fet off and the use of an external ramp compensation circuit ( r 4, c4) is simplified in figure 7. t he external ramp is derived from th e inductor rip p le current. if one chooses c4, r9, r1 and r2 to meet the following con d ition: 12 9 sw 4 1 2 rr 11 r 2f c 5 r r ?? < + ?? + ?? (5) where: r4 c4 f b c 4 ii ii =+ ( 6 ) and the ra mp on the v fb can the n be est i mated as: in o 12 ra m p o n 44 12 9 vv r/ / r vt rc r / / r r ? = + (7) the downward slope of the v fb ri p p l e t h en follows ? ? == ou t ra m p sl o pe 1 off 4 4 v v v tr c (8) as can be seen from equation 8, if there is instability in pwm mod e , we can r educe eith e r r4 or c4. if c4 can not be reduced further due to limitation fr om equation 5, then we can only reduce r4. for a stable pwm o peration, th e v slope1 shou ld be design follow equation 9. 3 10 sw o n es r o u t sl ope 1 o u t ou t s w o n tt +- r c io 0.7 ? 2 -v v + 2l c t - t ? (9) io is the loa d current. in skip mode, the downward slope of the v fb ripple is almost the same wheth e r the external ramp is use d or not. fig.9 shows t he simplifie d circuit of th e skip mod e when both the hs-fet and ls-fet are off. r1 r2 cout fb vo ro figure 8?simplified circuit in skip mode the downward slope o f the v fb ripple in skip mode can be determined as follow: () re f slope2 12 o u t v v (r r / / r o ) c ? = + (1 0) where ro is the equivalent load resistor. as describe d in fig.5, v slope2 in the skip mode is lower than that is in t he pwm mode, so it is reasonable that the jitt er in the skip mode is larger. if o ne wants a system wi th less jitte r during ultra light load co ndition, the values of the v fb resistors should not be too big, however, th at will decrease the light lo ad efficien cy. soft start/stop the nb63 8 employs soft start/stop (ss) mechanism to ensure smooth o u tput during power-up and power shutdown. when the en pin becomes high, an internal current source (8.5 a) charges up the ss cap. the ss cap voltag e takes over the ref voltage t o the pwm comparator. the output voltage smoothly ramp s
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 12 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. up with the ss voltage. once the ss voltage reaches the same level as the ref voltage, it keeps ram p ing up w h ile v ref t a kes ov er the pwm comp arator. at this point, t he soft st a r t finishes and it enters int o steady state operation. when the en pin bec omes low, the ss cap voltage is discharged t hrough an 8.5 a internal current sou r ce. once t he ss voltage reache s ref voltage , it takes ov er the pwm comparator. the output voltage will decrease smoothly with ss voltage until zero le vel. the ss cap value can be deter mined as follows: () ( ) ( ) () = ss s s ss re f tm s i a cn f vv (11) if the out pu t capacitors have large capacitance value, it?s n o t recomme nded to set the ss time too small. otherwise, it?s easy to hit the curre nt limit during ss. a minimum value of 4.7nf should be used if the output capacitance value is larger than 330 f. pow e r good (pgood) the NB638 has power-good (pgood) outp u t. the pgood pin is the open drain of a mosfet. it should be connecte d to v cc or other volta ge source thro ugh a resistor (e.g. 10 0k). after t h e input voltage is applied , the mosf et is turned on so that the pgood pin is pulled to gnd before ss i s ready. af ter fb voltage reaches 90% of ref voltage, t he pgood pin is pulle d high after a delay. the pgood delay time is determined as follow s : pgoo d s s t ( ms ) 0 . 5 t ( ms ) 0 . 5 = + (12 ) when the fb voltage drops to 85% of ref voltage, the pgood pin will be pulle d low. over-cu rre nt protection (ocp) and sho r t- circuit protection (scp) the NB638 has cycle- by-cycle over-current limi t control. the inductor cu rrent is monitored durin g the on state. once it detects that the induct o r current is higher than the current limit, the hs- fet is turn ed off. at t he same time, the ocp timer is start ed. the ocp timer is set as 40 s. if in the following 40 s, the current limit is hit for every cycle, then it ?ll trigger ocp latch-off. th e converter needs power cycle to r e start after it triggers ocp. if short circuit happens, then the cu rrent limit will be hit im mediately and the f b voltage will become lower than 50% of the ref voltag e. when the current limit is hit and the fb voltage is lower than 5 0 % of the r e f voltage (0.815v), the device con s iders th is as a dead short on th e output and triggers scp latch-off immediately. this is short circuit pro t e c tion (scp). over/under-voltage protection (ovp/uvp) the NB638 monitors the output voltage through a resistor d i vider feedback (fb) volta ge to dete c t overvoltage and unde rvoltage on the outpu t. when the fb voltage is higher than 125% of th e ref voltag e (0.8v), it?ll trigger ovp latch-off. once it trig gers ovp, the ls-fet is always o n while the hs-fet is always off. it needs power cycle to po wer up again. when the fb voltage is below 50% of the ref voltage (0.815v), it is recognized as uv (under-voltage). usually, uvp accompanies a hit in current limit and results in scp. uvlo p r otection the NB638 has under-voltage lo ck- out protect i o n (uvlo). w hen the inp u t voltage is higher th an the uvlo ri sing thresho l d voltage, the NB638 will be powered up. it shuts off when the input voltage is lo wer than the uvlo falling threshol d voltage. this is non-la tch protection. thermal shutdow n thermal shutdown is employed in the NB638. the junctio n temperature of the i c is interna lly monitored. if the junction tempera t ure exceeds the thresh old value (typically 150oc), the converter sh uts off. this is a non-latch protection . there is about 25oc hysteres is. once the junction te mperature drops to a bout 125oc, it initiates a ss.
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 13 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. appli c ation information setting the output voltage-large esr caps for applications that ele c trolytic cap a citor or pos capacitor with a controlled output o f esr is set as output ca pacitors. th e output volt age is set by feedback re sistors r1 a nd r2. as figure 9 shows. r1 r2 esr po sc ap sw fb vo l figure 9?simplified circuit of pos capacitor first, choo se a value for r2. r2 should be chosen rea s onably, a small r2 will lead to considerable quiescent current lo ss while to o large r2 makes the fb noise sensitive. it is recommend ed to choo se a value within 5k ? - 50k ? for r 2 , using a comparative l y larger r2 when vout is low, etc., 1 .05v, and a smaller r2 when vout is high. th en r1 is d e termined as follow with the output rip p le consid ered: o ut o ut re f 12 re f 1 vv v 2 rr v ' (1 3) ou t v ' is the outpu t ripple dete r mined by equation 21. setting the output voltage-small esr caps r1 r2 cer a m i c sw fb vo l r9 r4 c4 figure 10?simplified circuit of ceramic capacitor when low esr ceramic capacitor is used in the output, an external voltage ramp should be added to fb through resistor r4 and capacit or c4.the output voltage is influenced by ramp voltage v ramp beside s r divider as shown in figure 11. t he v ramp ca n be calcu l a t ed as show n in equation 7. r2 should be chosen reasonably, a small r2 will lead t o considera b le quiesce nt current loss while too large r2 makes the f b noise sensit ive. it is recommended to choose a value within 5k ? -50k ? for r2 , using a comparative l y larger r2 when vo is low, etc.,1.05v, and a smaller r2 when vo is high . and the value of r1 then is determined as follow: 2 1 fb( a v g ) 2 ou t fb(avg) 4 9 r r= v r - (v - v ) r + r ( 14) the v fb(avg ) is the average value on the f b , v fb(avg) varies with t he vin, vo, and load condition, et c., its value on the skip mode would be lower th an that of the pwm mode, which means the load regulation is strict ly related to th e v fb(avg) . also the lin e re gulation is r e lated to th e v fb(avg) ,if o ne wants to gets a bett e r load or line regulation, a lower vra m p is suggested once it meets equation 9. for pwm operation, v fb(avg) value can be deduced fro m equation 15. 12 fb ( avg) ref ramp 12 9 r/ / r 1 vv v 2r / / r r u (15) usually, r9 is set to 0 ? , and it can also be set following equation 16 for a better no ise immunity. it should also set to be 5 timers smaller than r1//r2 to mi nimize its inf l uence on v r amp. 9 4s w 1 r 2c 2 f d su u (16) using equation 14 to calculate the o u tput voltage can be complicated. to simplify the calculat ion of r1 in equat ion 14, a d c -blocking capacitor c d c can be added to filter the dc influ ence from r4 and r9. f i g u re 12 shows a simplifie d circuit with external ramp compen sation and a dc-blocking capacitor. with this ca pacitor, r1 can easily be obtained by using equ ation 17 for pwm mod e operation.
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 14 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. ?? = + out r e f ra mp 12 re f ra m p 1 (v v v ) 2 rr 1 vv 2 (17) cdc is sugg ested to be at least 10 times larger than c4 for better dc blocking perfo rmance, and should also not larger than 0.47 f considerin g start up performance. in case one wants to use larger cdc for a bet ter fb noise immunity, combined with reduced r1 and r2 to limit th e cdc in a re asonable va lue without affecting th e system start up. be noted that even when the cdc is applied, the load and line regulation are still vramp related. r1 r2 cer a m i c sw fb vo l cd c r4 c 4 figure 11?simplified circuit of ceramic capacitor w i th dc blocking capacitor input capacitor the input current to the step-down converter is discontinu o u s. therefor e, a capacit or is require d to supply t he ac current to the step-down converter while maintaining the dc input voltage. ceramic ca pacitors are recommen ded for best performance. in the layout, it?s recommended to put the inpu t capacitor s as close to t he in pin as possible. the capa citance va ries significantly over temperature. capacitors with x 5 r and x 7 r ceramic die l ectrics are recommen ded because they are fairly stable over temperature. the capacit ors must also have a ripple current rating great er than the maxi mum input ripple current of th e converter. the input r i pple curren t can be estimated as follows: ou t ou t ci n o ut in in vv ii ( 1 ) vv = ? (18) the worst-case conditio n occurs at v in = 2v out , where: out ci n i i 2 = (1 9) for simplification, cho o se the in put capacit or whose rms current rating is greate r than half of the maxi mu m load current. the input ca pacitance value determines the inpu t voltage ripple of the co nverter. if there is inp u t voltage ripple requirement in the sy stem design , choose the input cap a citor that meets th e specification the input voltage ripp le can be estimated a s follows: out o u t o u t in sw in in in iv v v( 1 ) fc v v = ? (20) the worst-case condit i o n occurs at v in = 2v out , where: ou t in sw in i 1 v 4f c = ( 21) output cap acitor the output capacitor is required to maintain the dc output voltage. ceramic or poscap capacitors a r e recommended. the o u tput voltag e ripple can b e estimated as: out o u t out e sr sw i n sw out vv 1 v( 1 ) ( r ) fl v 8 f c = ? + (22) in the case of ceramic capacitors, th e impedance at the switching frequency is domi nated by th e capacitan ce . the outpu t voltage rip ple is mainly caused by t he capacita n ce. for sim p lificat ion, th e output voltage ripple ca n be estimated as: ou t ou t ou t 2 sw o u t i n vv v( 1 ) 8f l c v = ? (23) the output voltage ripple caused by esr is very small. therefore, an external ramp is needed to stabilize the system. th e external ramp can be generated through resistor r4 and capacitor c4 following eq uation 5, 8 a nd 9. in the case of poscap capacitor s, the esr dominates the impedance at t he switching frequency. the ramp voltage gene rated from the esr is high enough t o stabilize the system. therefore, an external ramp is n o t needed. a minimu m esr value around 12m ? is required to ensure sta b le operation of the converter. for
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 15 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. simplification, the output ripple can be approximated as: ou t o ut out e s r sw in vv v( 1 ) r fl v = ? ( 2 4 ) inductor the induct o r is re quired to sup p ly constan t current to t he output lo ad while be ing driven by the switch ing input voltage. a larger valu e inductor will result in less ripple cu rrent that wi ll result in lower output ripple voltage. however, a larger value inductor will have a la rger physical size, highe r series r e sistance, and/or low e r saturation current. a good rule for determining the inductor value is to allow the peak-to-pea k ripple curre nt in the ind u ctor to be approximate l y 30~40% of the ma ximum switch current limit. also, make sure that th e peak indu ctor current is below the maxi mum switch current limit. the inductance value can be calcula t ed as: ou t o u t sw l in vv l( 1 ) fi v = ? ( 2 5 ) where i l is the peak-to-peak inductor ripple current. choose an inductor tha t will not sa turate under the maxi mu m inductor peak curren t. the peak inductor curr ent can be calculated a s : ou t ou t lp ou t sw in vv ii ( 1 ) 2f l v =+ ? (26) the induct o rs listed in table 1 are highl y recommend ed for the high efficie n cy they can provide. table 1?inductor selection guide part numb er manufac ture r inducta nce (h ) dc r (m ? ) curre nt ratin g (a ) dimensions l x w x h (m m 3 ) s w i t ching freque nc y (kh z ) pcmc-13 5 t-r68m f cyntec 0.68 1.7 34 13.5 x 12.6 x 4.8 600 fda12 54-1r0m toko 1 2 25.2 13.5 x 12.6 x 5.4 300 ~600 fda12 54-1r2m toko 1.2 2.05 20.2 13.5 x 12.6 x 5.4 300 ~600 t y pical des i gn parameter tables the following tables include r e commende d component values for typical ou tput voltages (1.2v, 2.5v, 3.3v) and switching frequencie s (300khz, 50 0khz, and 7 00khz). refer to table s 2-4 for de sign ca ses without e x ternal ramp compensation and tab les 5-7 for design ca se s with externa l ramp comp ensation. external ramp is not need ed when high-esr capacitors, su ch as electro l ytic or poscaps are used. external ramp is nee ded when low-esr ca pacitors, su ch as ceramic capacitors are used. f or cases n ot listed in this datasheet , a calcu l at or in excel spreadsheet can also be requested through a local sale s representative to assist with the calculat ion. table 2?300khz, 12v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r7 (k ? ) 1.2 2.2 12.1 26.1 750 2.5 2.2 30 14.3 1500 3.3 1 40.2 13.3 1600 table 3?500khz, 12v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r7 (k ? ) 1.2 1 12.1 26.1 442 2.5 1 30 14.3 845 3.3 1 40.2 13.3 1000 table 4?700khz, 12v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r7 (k ? ) 1.2 1 12.1 26.1 316 2.5 1 30 14.3 590 3.3 1 40.2 13.3 806 table 5?300khz, 12v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r7 (k ? ) 1.2 2 .2 12.1 26.1 330 220 750 2.5 2 .2 30 14.3 402 220 1500 3.3 2 .2 40.2 12.4 422 220 1600
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 16 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. table 6?500khz, 12v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r7 (k ? ) 1.2 1 12.1 26.1 374 220 442 2.5 1 30 14.3 412 220 845 3.3 1 40.2 12.4 422 220 1000 table 7?700khz, 12v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r7 (k ? ) 1.2 1 12.1 26.1 240 220 316 2.5 1 30 14.3 412 220 590 3.3 1 40.2 12.4 422 220 806
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 17 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. typical application vin r7 301k 1.05v r5 100k c7 1nf r6 100k c6 33nf 1 4 5 6 20 2 8,19 u1 NB638 in freq vcc pgood en ss agnd pgnd fb sw bst 7 9,10,17,18 3 1 1-16 r2 42.2k r1 12.1k r3 4.7 gnd pgood en vout gnd figure 12 ? t y pical application circuit w i t h no external ramp vin r7 301k 1.05v r5 100k c7 1nf r6 100k c6 33nf 1 4 5 6 20 2 8,19 u1 NB638 in freq vcc pgood en ss agnd pgnd fb sw bst 7 9,10,17,18 3 1 1-16 r2 43.2k r1 12.1k r3 4.7 r4 360k c4 220pf gnd pgood en vout gnd r9 0 figure 13 ? typical application circuit with low esr ceramic capacitor r7 301k 10nf figure 14 ? t y pical application circuit w i t h lo w esr ceramic ca pacitor and dc-blo cking capacitor .
NB638?hi g h efficiency, fast transient synchronous step-down converter NB638 rev.1.16 www.monolithicpower.com 18 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. layout recommendation 1. the high current paths (gnd, in, and sw) should be placed very close to t he device with short, d i rect and wide traces. 2. put the input capacitor s as close to the i n and gnd pi ns as possib l e. 3. put the decoupling cap a citor as close to the v cc and gnd pins as po ssible. 4. keep the switching no de sw short and away from the feedback netw o rk. 5. the external feedback resistor s should be placed next to the fb pin. make sure that there is no via on the fb trace. 6. keep the b s t voltage path (bst, c3, and sw) as shor t as possible . 7. keep the bo ttom in and sw pads c onnected with large copper to achieve better thermal performance. 8. four-layer layout is strongly recommended to achieve better thermal performance. top la y e r inner1 la y e r gnd inner2 la y e r bottom la yer figure 15?pcb la y o u t
NB638?hi g h efficiency, fast transient synchronous step-down converter notice: t he i n formatio n in this docum ent i s subject to chang e w i t h o u t notice. users sh oul d w a rra nt and gu arante e that third part y int e ll ectu al prop ert y r i g h ts are n o t inf r ing ed u p o n w hen i n tegr atin g mps product s into an y ap p licatio n. mps w i ll not assume a n y le gal res pons ib ili t y for an y sai d app licati ons. NB638 rev.1.16 www.monolithicpower.com 19 4/18/2012 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2012 mps. all rights reserved. package informati o n qfn20 (3x4mm)

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