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| HFC0100 quasi resonant controller hfc010 0 rev. 1 .01 www . m o nolithicpow er.co m 1 9/23/2011 mps pr oprietar y info rma t ion. pa tent prot ected. unautho rized phot ocop y a nd duplication prohibited. ? 2011 mps. all rights reserved. the future of analog ic t echnology descri ption the HFC0100 is a peak current mode controller with green mode operation. its high efficiency feature over the entire line and load range meets the stringent world-wide energy efficiency re quirements. the hfc01 00 integrate d with a high voltage current sou r ce, its valley detector ensures minimu m drain-source voltage switching (quasi-resonant oper ation). whe n the outpu t power falls below a given level, the controller enters the b u rst mode. the HFC0100 features variable protections like thermal sh utdown (tsd), vcc un der voltage lockout (uvlo), over load protection (olp), over voltag e protection (ovp). t h e hf c0 10 0 is a v ai lab l e i n th e 8-p in soi c 8 packa ge . features ? universal main input voltage (85~265vac) ? quasi-resonant operation ? valley switching for high efficien cy and emi ? active burst mode for low standby powe r consumptio n ? internal hig h voltage current source ? high level of integration , allows a very low number exte rnal component count ? maxi mum frequency limited ? internal soft start ? internal 250 ns leading edge blanking ? thermal shutdown (auto resta r t with hysteresis) ? vcc under voltage lockout with hysteresis (uvlo) ? over voltag e protection ? over load protection. appli c ations ? battery ch arger: cellular phone, digital camera, video camera, electrical shaver, emergency l i ghting syste m , etc ? standby power supply: crt-tv, projection- tv, lcd-t v , pdp-t v , desk top pc, audio sy stem , etc ? smps: inc jet printer, dvd player/recorder, vcr, cd player, set top box, air conditioner, refrigerator, washing machine, dish washer , adapter for nb, etc for mps green sta t us, plea se v i sit m ps w ebsi t e under quality a ssu rance. ?mp s ? an d ?t he f u ture o f ana l o g ic t e chno lo gy ? ar e re gi ste r ed tr ade ma r ks o f monolithic power systems, inc. http://
HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 .01 www . m o nolithicpow er.co m 2 9/23/2011 mps pr oprietar y info rma t ion. pa tent prot ected. unautho rized phot ocop y a nd duplication prohibited. ? 2011 mps. all rights reserved. typical application rt n * * * t1 vsd 1 2 3 45 6 7 8 cs hv n/ c dr i v e gn d fb vc c + + HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 .01 www . m o nolithicpow er.co m 3 9/23/2011 mps pr oprietar y info rma t ion. pa tent prot ected. unautho rized phot ocop y a nd duplication prohibited. ? 2011 mps. all rights reserved. ordering information part number* package top marking free air temperature (t a ) HFC0100hs soic8 hfc100 -40 c to +125 c *for ta pe & reel, ad d suf f ix ?z (e.g. hfc01 0 0 h s?z ) ; for rohs co mpliant pa ckaging, ad d su ffix ?lf (e.g. hfc010 0hs ?lf?z ) package reference absolute m a xi mum ratings (1) hv break down voltage .............. -0.7v to 700v vcc, drv to gnd ........................... -0.3v to 22v fb, cs, vsd to gnd ........................ -0.3v to 7v continuous power dissipation?(t a = +25c) (2) ??????????????????....1.3 w junction te mperature ............................... 150 c thermal sh ut down .................................. 150 c thermal sh ut down hysteresis .................. 50 c lead temperature .................................... 260 c storage temperature .............. -60c to +150 c esd capa bility human body model (all pin s except hv) ............................................... 2.0kv esd capabi lity machine model ................. 200v recommended operation conditions (3) operating vcc range ........................... 8v to 20v maxi mum j unction temp. (t j ) ............. +125c thermal resistance (4) ja jc soic8 ..................................... 96 ...... 45 ... c/w notes : 1) exceeding these ratings ma y da m age the device. 2) the ma ximum allowable po w e r dissipation is a fun c tion of the maximum junction temperatu r e t j (max), the junction-to- ambient therm a l resistance ja , a nd the a m bient t e mperatu r e t a . the maximu m allow a ble con t inuous po w e r di ssipation at an y ambient te mperatu r e is ca lculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation w ill cause ex cessive die tempe r ature, and t h e regulator w ill g o into thermal shutdo w n . inte rnal thermal shutdo w n circuitr y pr otects the device from permanent damage. 3) the device is not guarant eed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb. vsd vcc nc hv fb gnd cs drive 1 2 3 4 8 7 6 5 t op view HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 .01 www . m o nolithicpow er.co m 4 9/23/2011 mps pr oprietar y info rma t ion. pa tent prot ected. unautho rized phot ocop y a nd duplication prohibited. ? 2011 mps. all rights reserved. electrical characterics for ty pical value t j =25 parameter symbol conditions min typ max unit start-up current source (pin hv) charging current from pin hv i charge vcc=6v;v hv =400v 1.4 2 2.6 ma lea kag e cu rrent from pin hv i leak with auxiliary sup p ly ; v hv = 400v, vcc=13v -- 20 -- a brea k do wn voltage v br 700 -- -- v supply voltage management (pin vcc) vcc up per l e vel at which the intern al high voltag e curre n t source stop s v cch 10.6 11.8 13 v vcc lo we r l e vel at which the internal high voltag e curre n t source tri gge rs v ccl 7.2 8 8.8 v vcc re -cha rge level at which the prote c tion o c curs vccp -- 5.5 -- v internal ic consumption, 1nf lo ad on drive pin, i cc1 fs=100 khz, vcc=12v -- 2.0 -- ma internal ic con s um ption , latch off pha se, icc2 vcc=6v -- 450 -- a feedback management (pin fb) internal pull up res i s t or r fb -- 10 -- k internal pull up voltage vup -- 4.5 -- v fb pin to current limit division ratio i div -- 3 -- -- internal soft-start time tss -- 2.4 -- ms fb decrea si ng level at which the controlle r ent er the burst mode v burl -- 0.5 -- v fb increa sin g level at which the controlle r lea v e the burst mode v burh -- 0.7 -- v over loa d set point v olp -- 3.7 -- v valley switching management (pin vsd) valley switch ing threshold voltage v vsd 40 55 70 mv valley switching hysteresi s v hy s -- 10 -- mv v vsdh high state; ipin2=3.0ma 7 7.5 8 pin vsd cla m p voltage v vsdl low state; ipin2=-2.0ma -0.8 -0.65 -0.5 v valley switching propagation delay t vsd pull down fro m 2v to -100mv 120 160 200 ns minimum off time t min 6.6 7.8 9 s re-s tart time after las t valley detec t tran sition t restart -- 4.6 -- s ovp sampling delay t ovps -- 3.5 -- s pin vsd ovp referenc e level v ovp -- 6 -- v internal impe dan ce rint -- 24 -- k current sampling management (pin cs) leadi ng edg e blankin g t leb -- 250 -- ns driving signal (pin drive) sourcing re sistor r h -- 17 -- sinking re sistor r l -- 7 -- HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 .01 www . m o nolithicpow er.co m 5 9/23/2011 mps pr oprietar y info rma t ion. pa tent prot ected. unautho rized phot ocop y a nd duplication prohibited. ? 2011 mps. all rights reserved. pin functio n s pin # nam e description 1 vsd input from the auxiliary flyback signal, it ensures discontinuous operation and valley switching. it also offers a fixed ovp detection. 2 v cc supply voltage pin. this pin is connected to an external bulk capacitor of typically 22uf and a ceramic capacitor of typically 0.1uf. 3 n/c this pin ensures adequate creepage distance. 4 hv input for the start up current unit. 5 drive output of the driving signal. 6 cs input of t he current sense. 7 gnd ground. 8 fb the pin sets the peak cu rre nt limit, by conne cting an optocoupl er to this pin. a feedback voltage of 3.7 v will trigger an over load prote c tion, an d a feedback voltage of 0.5 v will trigger a burst mode operation. HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 .01 www .mo nolithicpow er.com 6 9/23/2011 mps pr oprietar y info rma t ion. pat ent prot ected. unautho rized photoc op y a nd duplication prohibited. ? 2011 mps. all rights reserved. typical perfo r mance characteristics t a =25 400 500 600 700 800 900 1000 1100 10 11 12 13 14 15 16 17 18 v cc (v) v cc (v) i cc 1 (ua) f s =60khz f s =60khz f s =100khz f s =100khz ic consumption vs vcc (no output load) 1000 1400 1800 2200 2600 3000 3400 10 11 12 13 14 15 16 17 18 i cc 1 (ua) v cch (v) v ccl (v) tempera ture ( o c) temperature ( o c) temperature ( o c) temperature ( o c) 1 1.5 2 2.5 3 -40 -20 0 25 50 85 105 125 icharge (ma) charging current from pin hv (vcc=6v , vhv=400v) vs t emperature ic consumption vs vcc (1nf output load) 11 11.2 11.4 11.6 11.8 12 -40 -20 0 25 50 85 105 125 vcc upper level at which the internal high v oltage current source stops vs t emperature 7.5 7.7 7.9 8.1 8.3 8.5 -40 -20 0 2 5 5 0 85 105 125 vcc lower level at which the internal high v oltage current source t riggers vs t emperature 8 9 10 11 12 -40 -20 0 2 5 5 0 85 105 125 pin fb internal pull up resistor vs t emperature temperature ( o c) temperature ( o c) temperature ( o c) t min (us) v vsd (mv) v olp (v) m i nimum off time vs temperature 7 7.5 8 8.5 9 -40 -20 0 25 50 85 105 125 valley switching threshold voltage vs temperature 30 40 50 60 70 80 -40 -20 0 25 50 85 105 125 ov er load set point vs temperature 3.4 3.6 3.8 4 -40 -20 0 2 5 50 85 105 125 HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 .01 www .mo nolithicpow er.com 7 9/23/2011 mps pr oprietar y info rma t ion. pat ent prot ected. unautho rized photoc op y a nd duplication prohibited. ? 2011 mps. all rights reserved. typical perfo r manc e characteristics (c ontinues) t a =25 600 650 700 750 800 -40 -20 0 25 50 85 105 125 temperature ( o c) temperature ( o c) temperature ( o c) temperature ( o c) temperature ( o c) temperature ( o c) temperature ( o c) v b u r h(mv) v b u r h(mv) v ref (v) t sample (us) fb i n cr easi ng level at w h ich th e co n t ro ller leav e the burst m ode vs temperature fb decreasing level at w h ich th e co n t ro ller enter the burst m o de vs temperature 400 450 500 550 600 -40 -20 0 25 50 85 105 125 0 5 10 15 20 -40 -20 0 25 50 85 105 125 sinking resistor vs temperature sourcing resistor vs temperature 10 15 20 25 30 -40 -20 0 25 50 85 105 125 pin vsd internal impedance vs temperature 20 22 24 26 28 30 -40 -20 0 2 5 5 0 8 5 105 125 pin vsd ovp reference lev e l vs temperature 5.8 5.9 6 6.1 6.2 -40 -20 0 2 5 5 0 85 105 125 ovp sampling delay vs temperature 3 3.2 3.4 3.6 3.8 4 -40 -20 0 25 50 85 105 125 HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 .01 www .mo nolithicpow er.com 8 9/23/2011 mps pr oprietar y info rma t ion. pat ent prot ected. unautho rized photoc op y a nd duplication prohibited. ? 2011 mps. all rights reserved. block diagrame d r i v e ( 5 ) c s ( 6 ) f b ( 8 ) n . c . ( 3 ) g n d ( 7 ) v c c ( 2 ) h v ( 4 ) v s d ( 1 ) s t a r t u p u n i t v a l l e y d e t e c t o r p r o t e c t i o n u n i t p e a k c u r r e n t l i m i t a t i o n p o w e r m a n a g e m e n t b u r s t m o d e c o n t r o l d r i v i n g s i g n a l m a n a g m e n t figure 1? block diagram HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 .01 www . m o nolithicpow er.co m 9 9/23/2011 mps pr oprietar y info rma t ion. pa tent prot ected. unautho rized phot ocop y a nd duplication prohibited. ? 2011 mps. all rights reserved. operation the HFC0100 incorp orates all t he necessa ry features nee ded to a reliable switch mode powe r supply. its valley det ector ensur es minimu m drain-source voltage switching (q uasi-reson ant operation). when the o u tput power falls be low a given level, the regulato r enters the burst mode. an internal minimu m off time limiter prevents the free running frequency to exceed 150khz. start-up initially, the ic is self su pplying from the internal high voltag e current source unit which drawn from the hv pin. the ic starts switchin g and the internal hig h voltage current source u n it is stoppe d as so on a s the voltage on pin vcc reaches t he threshold v cch ?11.8 v . before the supply is ta ken over by the auxiliar y winding of the transfor m er, the vcc capa cito r supplies hf c0100 to maintain vcc. quasi-reso nant opera t ion the HFC0100 opera t es in discontinuous conduction mode (dcm). the valley detector ensures minimu m drain-source voltage switching (quasi-reson ant operatio n) as a result, there are virtually no primary s w itch turn on losses and no secondary diode recovery losses. it en sures the re duction of th e emi noise. figure2 sho w s the valley detector unit. when the voltage: aux ds in pri vsd n 24 k (v v ) x x 5 5 m v n2 4 k r ?< + v ds ?drain source voltage of the p r imary fet v in ?input voltage n aux ?auxiliary winding turns of the transformer n pri ?primary winding turns of the t r ansformer the valley detector se nds out a valley signal to turn on the primary fet . figure3 shows a typi cal drain source voltage waveform wi th valley switching. figure 2?valle y detector v ds 100v/div 4us/div figure 3?valley switching to ensure the switching frequency below the en55022 start limit---150khz, HFC0100 employs an internal minimum off time limiter---7.8 s, shows as figure 4. v ds 100v/div 2us/div figure 4?minimum off time limit valley switching t off HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 .01 www . m o nolithicpow er.co m 10 9/23/2011 mps pr oprietar y info rma t ion. pa tent prot ected. unautho rized phot ocop y a nd duplication prohibited. ? 2011 mps. all rights reserved. v cc under-voltage lock-out when the vcc below th e uvlo threshold-8v, t he HFC0100 stops swit ching and the internal high voltage current source unit re-sta rts, the vcc external bulk capacitor is re-charge d by it. figure 5 shows the typ i cal waveform with vcc under voltage lock out. v cch =1 1 . 8 v v ccl =8v v cc in te r n a l cu r r e n t so u r c e d r ivin g s i g nal on of f t h e a u xilia r y w i ndi n g t ak e ov er figure 5?vcc under-voltage lock out over-voltage protection (ovp) the positive plateau of auxiliary win d ing voltage is proportion al to the output voltage, the ovp us e the auxiliary winding voltage instea d of directly monitoring the output voltage. the figure 6 shows the ovp sampl e unit. if the voltage: 6v r 24k 24k n n v vsd sec aux o > + v o ?output voltage n aux ?auxiliary winding turns of the transformer n sec ?secondary winding tur ns of t h e transformer the ovp ci rcuit is trig g e red, and the hfc010 0 stops the switching cycle and goes into latche d fault condition. the controller stays fully latched in this position until the vcc is decre ased down to 3v, e.g. wh en the user unplugs the power supply from the mai n supply and re-plugs it. figure 6?ovp sample unit to avoid th e mis-trigger due to the oscillat i on of the leakag e inductan c e and the parasitic capacitan ce , the ovp sampling has a t ovp s blanking, ty pical 3.5 s, shows as figure 7. v vs d 0v t ovps sam pl i ng h er e figure 7 over load protection (olp) the maxi mum output power is limited by th e maxi mum switching fr equency and maxi mu m primary pe ak current. if the output consumes more than t he maximu m output po wer, the out put voltage is drawn below t he set point, this reduces the current through the optocouple r led, which also reduces the transistor current, thus increases th e fb voltage. by continuously monitoring the pin fb voltage , when the feedback voltage exceeds the threshold v olp ?3.7v, it shuts off t he switchin g cycle. the HFC0100 e n ters a saf e low power operation th at prevents f r om any lethal thermal o r stress da mage. as soon a s the defa u lt disappears, the power supply resumes operation . during the start up or load transient, the f b voltage will be high en ough temporarily to mis- trigger the olp, to prevent t h is unde sir e d protection, olp circuit is designed t o be trigger ed after vcc is decreased b elow 8.5v. HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 .01 www . m o nolithicpow er.co m 11 9/23/2011 mps pr oprietar y info rma t ion. pa tent prot ected. unautho rized phot ocop y a nd duplication prohibited. ? 2011 mps. all rights reserved. burst ope r ation to minimize the power dissipat ion in no load or light load, the hfc010 0 enters the burst mo de operation. as the load decreases, th e fb voltag e decreases,, the HFC0100 stops the switching cycle when the fb voltage drop s below th e threshold v burl ?0.5v. and the o u tput voltage starts to dr op at a rat e dependen t on the loa d. this cau s es the fb volt age to rise again. once the fb voltage exceeds the threshold v burh ? 0.7v, switching resumes. the fb voltage then falls and rises repeat edly. the burst mode operation alternately enables and disables switching cycle of the mosfet thereby reducing switching loss in the no load or light lo ad conditions. figure 8 shows the typical f b and drive waveform d u ring the bu rst mode. v drive 5v/div v fb 200mv/div 40us/div figure 8?burst mode thermal shutdow n (ts d ) to prevents from any let hal thermal damage. the HFC0100 shuts down switching cycle when th e inner temperature exceeds 150degc. as soon a s the inner te mperature drops below 100degc, th e power supply resumes operation. soft-start to reduce t he stress o n primary mosfet and secondary diode durin g start up, to smoothly establish th e output voltage, the h f c0100 has an internal soft-start circuit that increases t he current co mparator inverting input voltage, together with the mosf et current, slowly after it starts up. t he pulse width to the p o wer switching device is pr ogressively increased to establish th e correct wo rking cond itions for t r ansformers, inductors, a nd capacitor s. current li mit setting the switch current is sensed b y the resistor series betw een the source of the fet and th e ground. and the current limit is deter mined by th e fb signal, 3 v i v v fb div fb limit = = . to limit the maxi mum output power, the current limit is clamped at 1v when v fb is bigger t han 3.3v. leading edge blanking in order to a v oid the pre m ature termination of th e switching p u lse due to the parasitic capacitance, an internal leading edg e blanking (leb) unit is employed b e tween the cs pin and the curre nt comparator input. during the blanking time, the path, cs pi n to the current comparator input, is blocked. figure 9 shows the leading edge blanking. t le b = 250 n s v li mi t t figure 9?leading edge blanking over pow e r compensation in the case of current sensing, sh ows as figure 10, the turn off of the f e t is delayed due to the propagation delay of the control cir c uit, the dela y time is the inherent ch aracteristic of the contr ol circuit, so t de la y can be s een fixed. t h is delay will cause an o v ershoot of the peak cu rrent. i2 is bigger than i1 due to the bigger rising ratio(th e higher input voltage, the bigger rising ratio). v bur l :0.5v v bur h :0.7v HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 .01 www . m o nolithicpow er.co m 12 9/23/2011 mps pr oprietar y info rma t ion. pa tent prot ected. unautho rized phot ocop y a nd duplication prohibited. ? 2011 mps. all rights reserved. the propagation delay is done by means of the feedforward resistor, shown as figure 1 1 . through this method, a dding one o ffset voltage at cs pin ( t he higher input voltage, the big g e r offset voltage.). t delay t delay t delay t delay i li m i t i li m i t 1 i li m i t t i1 i2 i li m i t 2 figure 10?propagation dela y of t h e current limit cs 6 v ref hf c0 1 0 0 current comparator r f eedf or w ar d r s ens e r1 c1 q1 t1 v _bul k figure 11?over pow e r compensation figure 12 sh ows the HFC0100 control flow chart . figure 13 shows the h f c0100 evolution of th e signals in pr esence of fa ults HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 .01 www .mo nolithicpow er.com 13 9/23/2011 mps pr oprietar y info rma t ion. pat ent prot ected. unautho rized photoc op y a nd duplication prohibited. ? 2011 mps. all rights reserved. start vcc>11.8v vcc<8.5v? and olp=logic high internal high voltage current source on toff<7.8us y n soft start monitor v fb monitor vcc v fb >3.7v 0.5v HFC0100 qua s i res o na nt c o ntroll er hfc010 0 rev. 1 . 01 www .mo nolithicpow er.com 14 9/23/2011 mps pr opri e tar y info rma t i on. pat ent prot ected. unautho ri zed photoc op y a nd dupl i c ati on prohi bi ted. ? 2011 mps. al l ri ghts reserved. 11 .8v 8. 5v 5.5v vc c dr i v e r if au lt f l a g ov p f a u l t o ccu r s h er e dr i v e r pl u s e s re gu l a t i o n o c c u rs h e re high voltage current source st a r t u p normal operation normal operation normal operation o l p fa ul t oc c u r s h e r e on of f over voltage occurs here no r m a l operation ot p f a u l t oc c u r s h e r e n o r m al o p e r at i o n u n pl ug f r om m a in i n p u t normal o p er at i o n no r m a l op e r a t i on figure 13?evolution of the signals in presence of faults HFC0100 qua s i res o na nt c o ntroll er notice: t he informatio n in t h is doc ume n t is subject to ch ang e w i th out n o tice. users sh oul d w a rra nt a nd gu ara n tee t hat third part y intell ectu al propert y ri g h ts are not infring ed upo n w hen inte grati n g mps product s into an y ap p licatio n. mps w i ll not assume a n y le gal res pons ib ili t y for an y sai d app licati ons. hfc010 0 rev. 1 . 01 www .m on olithicpow er.com 15 9/23/2011 mps pr opri e tar y info rma t i on. pat ent prot ected. unautho ri zed photoc op y a nd dupl i c ati on prohi bi ted. ? 2011 mps. al l ri ghts reserved. package informati o n soic8 0 . 0 1 6( 0. 4 1) 0 . 0 5 0( 1. 2 7) 0 o -8 o detail "a" 0.01 0 ( 0. 2 5 ) 0.020(0.50) x 45 o se e d e t a il " a " 0. 00 75 ( 0 . 19 ) 0 . 00 98 ( 0 . 25 ) 0. 1 5 0(3.80) 0.157(4.00) pin 1 id 0.050(1.27) bsc 0 . 013( 0 . 33 ) 0 . 020( 0 . 51 ) seating plane 0.004(0.10) 0.010(0.25) 0 . 1 89( 4 . 80 ) 0.197(5.00) 0. 0 53 ( 1 . 35) 0. 0 69 ( 1 . 75) top view front view 0.2 2 8(5 . 8 0 ) 0. 2 4 4(6 . 2 0 ) side view 14 85 recomm e nded land pattern 0.213 ( 5.40) 0.063(1.6 0 ) 0.050(1 . 2 7 ) 0.024(0.6 1 ) note: 1 ) c o nt ro l d i me ns io n is i n inc h e s . d i me ns io n i n br ack et is i n m i l l i me t e rs . 2 ) p a c kage le ngth does n o t inclu d e mold flas h, p r o t ru si on s or g a t e bu rrs . 3 ) p a c kage width doe s n o t inc l ude int e r l ea d flas h o r pro t r u s i o n s . 4) l e a d cop l an arity (bottom of le ads afte r f o r m in g ) s hal l be 0.00 4 " inche s max . 5 ) d rawi n g conforms to jedec ms -012, vari a t i o n a a . 6 ) d rawin g is not to s cale . 0. 01 0 ( 0. 2 5 ) bsc gaug e pla n e |
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