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HT24LC02A cmos 2k 2-wire serial eeprom selection table part no. capacity v dd clock rate (khz) write speed @2.4v(ms) operating current @5.0v(ma) standby current @5.0v(a) package marking HT24LC02A 2568 1.8v~ 5.5v 400 5 5 2 sot23-5 2402a 8sop HT24LC02A block diagram pin assignment rev. 1.00 1 january 29, 2013 features operating voltage: 1.8v~5.5v for temperature 40 cto+85 c low power consumption operation: 5ma max. standby: 2 a max. internal organization: 256 8 2-wire serial interface write cycle time: 5ms max. automatic erase-before-write operation partial page write allowed 8-byte page write modes write operation with built-in timer hardware controlled write protection 40-year data retention 10 6 erase/write cycles per word industrial temperature range ( 40 cto+85 c) package types: 8sop and sot23-5 general description the HT24LC02A is a 2k-bit serial read/write non-volatile memory device using the cmos floating gate process. its 2048 bits of memory are organized into 256 words and each word is 8 bits. the device is opti - mized for use in many industrial and commercial appli - cations where low power and low voltage operation are essential. up to eight HT24LC02A devices may be con - nected to the same 2-wire bus. the HT24LC02A is guaranteed for 1m erase/write cycles and 40-year data retention.

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pin description pin name i/o description sda i/o serial data inputs/output scl i serial clock data input wp i write protect vss negative power supply, ground vcc positive power supply absolute maximum ratings supply voltage ..........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage .............................v ss 0.3v to v cc +0.3v operating temperature........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics t a =40 c ~ +85c symbol parameter test conditions min. typ. max. unit v cc conditions v cc operating voltage 40 cto+85 c 1.8 5.5 v i cc1 operating current 5v read at 100khz 2ma i cc2 operating current 5v write at 100khz 5ma v il input low voltage 1 0.3v cc v v ih input high voltage 0.7v cc v cc +0.5 v v ol output low voltage 2.4v i ol =2.1ma 0.4 v i li input leakage current 5v v in =0 or v cc 1 a i lo output leakage current 5v v out =0 or v cc 1 a i stb1 standby current 5v v in =0 or v cc 2 a i stb2 standby current 1.8v v in =0 or v cc 2 a c in input capacitance (see note) f=1mhz, 25 c 6pf c out output capacitance (see note) f=1mhz, 25 c 8pf note: these parameters are periodically sampled but not 100% tested HT24LC02A rev. 1.00 2 january 29, 2013
a.c. characteristics t a =40 c ~ +85c symbol parameter remark v cc =1.8v~5.0v v cc =2.5v~5.0v unit min. max. min. max. f sk clock frequency 400 1000 khz t high clock high time 600 400 ns t low clock low time 1200 600 ns t r sda and scl rise time note 300 300 ns t f sda and scl fall time note 300 300 ns t hd:sta start condition hold time after this period the first clock pulse is generated 600 250 ns t su:sta start condition setup time only relevant for repeated start condition 600 250 ns t hd:dat data input hold time 0 0 ns t su:dat data input setup time 150 100 ns t su:sto stop condition setup time 600 250 ns t aa output valid from clock 900 600 ns t buf bus free time time in which the bus must be free before a new transmission can start 1200 500 ns t sp input filter time constant (sda and scl pins) noise suppression time 50 50 ns t wr write cycle time 5 5ms endurance 25 c, page mode 5.0v 1,000,000 write cycles note: these parameters are periodically sampled but not 100% tested. for relative timing, refer to timing diagrams HT24LC02A rev. 1.00 3 january 29, 2013
HT24LC02A rev. 1.00 4 january 29, 2013 functional description pin function serial clock scl the scl input is used for positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data sda the sda pin is bidirectional for serial data transfer. the pin is open-drain driven and may be wired-or with any number of other open-drain or open collector devices. write protect wp the HT24LC02A has a write protect pin that provides hardware data protection. the write protect pin allows normal read/write operations when connected to the v ss . when the write protect pin is connected to vcc, the write protection feature is enabled and operates as shown in the following table. wp pin status protect array at v cc full array (2k) at v ss normal read/write operations memory organization HT24LC02A, 2k serial eeprom internally organized with 256 8-bit words, the 2k re- quires an 8-bit data word address for random word ad- dressing. device operations clock and data transition data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in data line while the clock line is high will be interpreted as a start or stop condition. start condition a high-to-low transition of sda with scl high is a start condition which must precede any other command (refer to start and stop definition timing diagram). stop condition a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (re - fer to start and stop definition timing diagram). acknowledge all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero to acknowledge that it has re - ceived each word. this happens during the ninth clock cycle. device addressing the 2k eeprom devices all require an 8-bit device ad - dress word following a start condition to enable the chip for a read or write operation. the device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to the diagram showing the device address). this is common to all the eeprom device. the 8th bit of device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. if the comparison of the device address succeed the eeprom will output a zero at ack bit. if not, the chip will return to a standby state. write operations byte write a write operation requires an 8-bit data word address following the device address word and acknowledg - ment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. after receiving the 8-bit data word, the eeprom will output a zero and the addressing de - vice, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally-timed write cycle to the non-volatile memory. all inputs are disabled during this write cycle and eeprom will not respond until the write is completed (refer to byte write timing). + + , + % , ! 1 + % % & & , + ! 2 % 3 + % ! % + , ! %
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HT24LC02A rev. 1.00 5 january 29, 2013 page write the 2k eeprom is capable of an 8-byte page write. a page write is initiated the same as byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges the receipt of the first data word, the microcontroller can transmit up to seven more data words. the eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write se - quence with a stop condition. the data word address lower three (2k) bits are inter - nally incremented following the receipt of each data word. the higher data word address bits are not incre - mented, retaining the memory page row location (re - fer to page write timing). acknowledge polling to maximise bus throughput, one technique is to allow the master to poll for an acknowledge signal after the start condition and the control byte for a write com - mand have been sent. if the device is still busy imple - menting its write cycle, then no ack will be returned. the master can send the next read/write command when the ack signal has finally been received. write protect the HT24LC02A has a write-protect function and pro- gramming will then be inhibited when the wp pin is connected to vcc. under this mode, the HT24LC02A is used as a serial rom. read operations the HT24LC02A supports three read operations, namely, current address read, random address read and sequential read. during read operation execution, the read/write select bit should be set to 1 . current address read the internal data word address counter maintains the last address accessed during the last read or write op - eration, incremented by one. this address stays valid between operations as long as the chip power is main - tained. the address roll over during read from the last byte of the last memory page to the first byte of the first page. the address roll over during write from the last byte of the current page to the first byte of the same page. once the device address with the read/write se- lect bit set to one is clocked in and acknowledged by the eeprom, the current address data word is seri- ally clocked out. the microcontroller should respond a no ack (high) signal and following stop condition (re- fer to current read timing). * 5 5 5 3 ! , + % % & & % , + % % & & 4 + 4 4 3 ! , + % % & & % , + % % & & , 4 + 4 4 4 , 6 , 6 7 5 3 ! , + % % & & 4 +
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timing diagrams note: the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command. HT24LC02A rev. 1.00 6 january 29, 2013 random read a random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the eeprom. the microcontroller must then generate another start con - dition. the microcontroller now initiates a current ad - dress read by sending a device address with the read/write select bit high. the eeprom acknowl - edges the device address and serially clocks out the data word. the microcontroller should respond with a no ack signal (high) followed by a stop condition. (refer to random read timing). sequential read sequential reads are initiated by either a current ad - dress read or a random address read. after the microcontroller receives a data word, it responds with an acknowledgment. as long as the eeprom receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will roll over and the sequential read continues. the sequential read operation is terminated when the microcontroller responds with a no ack sig - nal (high) followed by a stop condition. 3 ! , + % % & & % , + % % & & 4 + 4
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package information note that the package information provided here is for consultation purposes only. as this information may be updated at regu - lar intervals users are reminded to consult the holtek website ( http://www.holtek.com.tw/english/literature/package.pdf ) for the latest version of the package information. 8-pin sop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.012 0.020 c 0.188 0.197 d 0.069 e 0.050 f 0.004 0.010 g 0.016 0.050 h 0.007 0.010
08 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.30 0.51 c 4.78 5.00 d 1.75 e 1.27 f 0.10 0.25 g 0.41 1.27 h 0.18 0.25
08 HT24LC02A rev. 1.00 7 january 29, 2013 ? a < 0 ) -
5-pin sot23-5 outline dimensions symbol dimensions in inch min. nom. max. a 0.039 0.051 a1 0.004 a2 0.028 0.035 b 0.014 0.020 c 0.004 0.010 d 0.106 0.122 e 0.055 0.071 e 0.075 h 0.102 0.118 l 0.015 09 symbol dimensions in mm min. nom. max. a 1.00 1.30 a1 0.10 a2 0.70 0.90 b 0.35 0.50 c 0.10 0.25 d 2.70 3.10 e 1.40 1.80 e 1.90 h 2.60 3.00 l 0.37 09 HT24LC02A rev. 1.00 8 january 29, 2013 0 ) @
product tape and reel specifications reel dimensions sop 8n symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 12.8 +0.3/-0.2 t2 reel thickness 18.20.2 sot23-5 symbol description dimensions in mm a reel outer diameter 178.01.0 b reel inner diameter 62.01.0 c spindle hole diameter 13.00.2 d key slit width 2.500.25 t1 space between flange 8.4 +1.5/-0.0 t2 reel thickness 11.4 +1.5/-0.0 HT24LC02A rev. 1.00 9 january 29, 2013 -
carrier tape dimensions sop 8n symbol description dimensions in mm w carrier tape width 12.0 +0.3/-0.1 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 5.50.1 d perforation diameter 1.550.10 d1 cavity hole diameter 1.50+0.25 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.40.1 b0 cavity width 5.20.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 9.30.1 sot23-5 symbol description dimensions in mm w carrier tape width 8.00.3 p cavity pitch 4.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 3.500.05 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.5 +0.1/-0.0 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.000.05 a0 cavity length 3.150.10 b0 cavity width 3.20.1 k0 cavity depth 1.40.1 t carrier tape thickness 0.200.03 c cover tape width 5.30.1 HT24LC02A rev. 1.00 10 january 29, 2013 5 ) ? 4 5 - 5 5 , + ! 2 + , , , + % , 1 , , 1 & + , ! + % , , 1 , & + # , & % b * , 0
HT24LC02A rev. 1.00 11 january 29, 2013 copyright 2013 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor (china) inc. building no. 10, xinzhu court, (no. 1 headquarters), 4 cuizhu road, songshan lake, dongguan, china 523808 tel: 86-769-2626-1300 fax: 86-769-2626-1311 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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