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[ak4128a] ms1242-e-00 2010/09 - 1 - general description the ak4128a is an 8ch digital sample rate converter (src). the input sample rate ranges from 8khz to 216khz. the output sample rate is from 8khz to 216khz. the ak4128a has an internal oscillator and does not need any external master clocks. it contribut es simplifying a system c onfiguration. the ak4128a supports master mode and tdm data interface, enabling simultaneous input of asynchronous stereo data. the ak4128a is suitable for the application interfacing to di fferent sample rates such as multi-channel high-end car audio systems and dvd recorders. features ? 8 channels input/output ? asynchronous sample rate converter ? input sample rate range (fsi): 8khz 216khz ? output sample rate range (fso): 8khz 216khz ? input to output sample rate ratio: 1/6 to 6 ? thd+n: ? 130db ? dynamic range: 140db (a-weighted) ? i/f format: msb justified, lsb justified and i 2 s compatible and tdm ? oscillator for internal operation clock ? clock for master mode: 128/256/384/512/768fso ? on-chip x?tal oscillator ? digital de-emphasis filter (32khz, 44.1khz and 48khz) ? soft mute function ? src bypass mode (master/slave) ? p interface: i2c bus ? power supply: avdd, dvdd1-4: 3.0 3.6v (typ. 3.3v) ? ta = ? 20 85 c (AK4128AEQ), ? 40 85 c (ak4128avq) ? package: 64lqfp 8ch 216khz / 24-bit asynchronous src ak4128a
[ak4128a] ms1242-e-00 2010/09 - 2 - output serial a udio i/f dem input serial a udio i/f src1 fir src smute + dither bypass src 0.5 lsb ibick1 sdti1 ilrck1 dem input serial a udio i/f src2 fir src smute + dither bypass src ibick2 sdti2 ilrck2 sdto1 sdto2 dem input serial a udio i/f src3 fir src smute + dither bypass src ibick3 sdti3 ilrck3 sdto3 dem input serial a udio i/f src4 fir src smute + dither bypass src ibick4 sdti4 ilrck4 sdto4 mcko clock div cm2 cm1 cm0 imclk bypass src x?tal osc omclk/xti xto olrck obick obit1 obit2 odif1 odif0 idif2 up i/f sda spb cad0 pdn pm1 pm2 unlock a vdd vss1 scl idif1 idif0 dem1 dem0 inas dvdd1-4 vss2-5 smsemi smute smt1 smt0 dither 0.5 lsb 0.5 lsb 0.5 lsb internal osc internal regulator ref vd18 figure 1. ak4128a block diagram (synchronous mode inas pin = ?l?) output serial a udio i/f dem input serial a udio src1 fir src smute + dither bypass src ibick1 sdti1 ilrck1 dem input serial a udio src2 fir src smute + dither bypass src ibick2 sdti2 ilrck2 sdto1 sdto2 dem input serial a udio i/f src3 fir src smute + dither bypass src ibick3 sdti3 ilrck3 sdto3 dem input serial a udio i/f src4 fir src smute + dither bypass src ibick4 sdti4 ilrck4 sdto4 mcko clock div cm2 cm1 cm0 imclk bypass src x?tal osc omclk/xti xto olrck obick obit1 obit0 scl 0.5lsb odif1 odif0 up i/f sda spb cad0 pdn pm1 pm2 unlock a vdd vss1 idif2 idif1 idif0 dem1 dem0 inas dvdd1-4 vss2-5 smsemi smute smt1 smt0 dither i/f i/f 0.5lsb 0.5lsb 0.5lsb internal osc internal regulator ref vd18 figure 2. ak4128a block diagram (asynchronous mode inas pin = ?h?)
[ak4128a] ms1242-e-00 2010/09 - 3 - compatibility with ak4126 (1) specifications parameter ak4126 ak4128a stereo inputs asynchronous mode not available synchronous mode only available the inas pin controls synchronous and asynchronous modes. internal clock internal pll the pll2-0 pins must be set according to the pll reference clock. #61 pin: a pin for external devices of pll filter. internal regulator + internal oscillator pll reference clock select is not needed since internal oscillator generates the clock. #61 pin: a capacitor pin for the internal regulator. bypass mode not available available controlled by cm2-0 pins or byps bit. master mode for output ports not available available controlled by cm2-0 pins maximum fsi and fso 192khz 216khz maximum ibick and obick frequency 64fs 256fs x?tal oscillator not available available master clock output not available available tdm mode not available available controlled by idif2-0 pins or idif2-0 bits (input) controlled by tdm pin (output) soft mute all channels are controlled together. individual setting available individual setting is available by setting smute4-1 bits in serial control mode. de-emphasis filter all channels are controlled together. individual setting available individual setting is available by dem41-40, 31-30, 21-20, 11-10 bits in serial control mode. audio format for input port. all channels are controlled together. individual setting available individual setting is available by idif42-40, 32-30, 22-20, 12-10 bits in serial control mode. i2c not available available parallel and serial control modes are selected by the spb pin. unlock pin detects pll unlock. fsi:fso ratio change detect detects over-current/voltage of the 1.8v outputs.
[ak4128a] ms1242-e-00 2010/09 - 4 - (2) pins pin# ak4126 ak4128a ak4128a pin 6ch mode ak4126 compatible (pm2/1 pin = ?ll?) 1 nc ibick2 l 2 test0 imclk l 7 tst0 sdti4 l 14 tst1 ilrck3 l 15 tst2 ibick3 l 16 nc ilrck4 l 17 tst3 ibick4 l 18 tst4 inas l 32 tst5 pm2 l 33 nc tdm l 42 tst6 sdto4 l 47 test4 omclk/xti l 48 nc xto l 49 nc mcko l 51 tst8 cad0 l 54 pll2 tst1 l or h 55 pll1 smsemi l or h 56 pll0 tst2 l or h 57 tst9 scl l 58 tst10 sda l 59 nc spb l 61 filt vd18 * 64 nc ilrck2 l *: an external device is needed for the no 61 pin. ak4126 c1 r fi lt c2 ak4128a vd18 1uf figure 3. ak4126 figure 4. ak4128a (please refer to the ak4126 datasheet about external devices.)
[ak4128a] ms1242-e-00 2010/09 - 5 - ordering guide AK4128AEQ ? 20 +85 c 64pin lqfp (0.5mm pitch) ak4128avq ? 40 +85 c 64pin lqfp (0.5mm pitch) akd4128a evaluation board for ak4128a pin layout mcko xto 49 tst0 48 50 cad0 51 dvdd4 52 vss5 53 tst1 54 smsemi 55 tst2 56 scl 57 sda 58 spb omclk/xti 47 olrck 4 6 45 44 vss4 43 sdto4 42 sdto1 41 sdto2 40 sd to3 3 9 odif0 38 ilrck4 1 ibick2 2 imclk 3 ilr ck1 4 ibick1 5 6 vss2 7 sdti4 8 sdti1 9 sdti2 10 sdti3 11 32 31 30 29 28 27 26 25 24 23 22 pm 2 ob it1 ob it0 pm 1 dem1 dem0 sm t1 sm t0 pdn dither sm ute top view dvdd1 obick dvdd3 od if1 3 7 idif0 12 59 av d d 6 0 21 vss3 vd 18 61 vss1 62 tst3 63 ilrck2 64 idif1 13 idif 2 14 ilrck3 15 ibick3 16 cm0 36 cm1 35 cm2 3 4 tdm 33 20 19 18 dvdd2 unlock inas 17 ibick4
[ak4128a] ms1242-e-00 2010/09 - 6 - pin / function no. pin name i/o function 1 ibick2 i audio serial data clock #2 pin when the inas pin = ?l?, this pin should be connected to vss2-5. 2 imclk i master clock input pin for input port 3 ilrck1 i input channel clock #1 pin 4 ibick1 i audio serial data clock #1 pin 5 dvdd1 - digital power supply pin, 3.0 3.6v 6 vss2 - digital ground pin 7 sdti4 i audio serial data input #4 pin 8 sdti1 i audio serial data input #1 pin 9 sdti2 i audio serial data input #2 pin 10 sdti3 i audio serial data input #3 pin 11 idif0 i audio interface format #0 pin for input port ( note 2 ) 12 idif1 i audio interface format #1 pin for input port ( note 2 ) 13 idif2 i audio interface format #2 pin for input port ( note 2 ) 14 ilrck3 i input channel clock #3 pin when the inas pin = ?l?, this pin should be connected to vss2-5. 15 ibick3 i audio serial data clock #3 pin when the inas pin = ?l?, this pin should be connected to vss2-5. 16 ilrck4 i input channel clock #4 pin when the inas pin = ?l?, this pin should be connected tovss2-5. 17 ibick4 i audio serial data clock #4 pin when the inas pin = ?l?, this pin should be connected to vss2-5. 18 inas i asynchronous mode select pin. ?l?(connected to the ground): synchronous mode. ?h?(connected to dvdd1-4) : asynchronous mode. 19 unlock o unlock status pin when the pdn pin= ?l?, this pin outputs ?h?. 20 dvdd2 - digital power supply pin, 3.0 3.6v 21 vss3 - digital ground pin 22 smute i soft mute pin ( note 3 ) ?h?: soft mute, ?l?: normal operation 23 dither i dither enable pin ?h?: dither on, ?l?: dither off 24 pdn i power-down mode pin ?h?: power up, ?l?: power down reset and initializes the control register. the ak4128a should be reset once by bringing pdn pin = ?l? upon power-up. 25 smt0 i soft mute timer select #0 pin 26 smt1 i soft mute timer select #1 pin 27 dem0 i de-emphasis control #0 pin ( note 4 ) 28 dem1 i de-emphasis control #1 pin ( note 4 ) 29 pm1 i channel mode select #1 pin 30 obit0 i bit length select #0 pin for output data 31 obit1 i bit length select #1 pin for output data 32 pm2 i channel mode select #2 pin 33 tdm i tdm format select pin. ?l?(connected to the ground): stereo mode. ?h?(connected to dvdd1-4) : tdm mode.
[ak4128a] ms1242-e-00 2010/09 - 7 - no. pin name i/o function 34 cm2 i clock select or mode select #2 pin for output port 35 cm1 i clock select or mode select #1 pin for output port 36 cm0 i clock select or mode select #0 pin for output port 37 odif1 i audio interface form at #1 pin for output port 38 odif0 i audio interface form at #0 pin for output port 39 sdto3 o audio serial data output #3 pin for output port when the pdn pin = ?l?, the sdro3 pin outputs ?l?. 40 sdto2 o audio serial data output #2 pin for output port when the pdn pin = ?l?, the sdto2 pin outputs ?l?. 41 sdto1 o audio serial data output #1 pin for output port when the pdn pin = ?l?, the sdto1 pin outputs ?l?. 42 sdto4 o audio serial data output #4 pin for output port when the pdn pin = ?l?, the sdro4 pin outputs ?l?. 43 vss4 - digital ground pin 44 dvdd3 - digital power supply pin, 3.0 3.6v 45 obick i/ o audio serial data clock pin for output port when the pdn pin = ?l? in master mode, the obock pin outputs ?l?. 46 olrck i/ o output channel clock pin for output port when the pdn pin = ?l? in master mode, the obock pin outputs ?l?. 47 omclk/xti i external master clock input / x?tal input pin 48 xto o x?tal output pin when the pdn pin = ?l?, xto outputs hi-z. 49 mcko o master clock output pin when the pm2 pin = ?h? and pdn pin = ?l?, the mcko pin outputs ?l?. when the pm2 pin = ?l? and pdn pin = ?l?, the mcko pin outputs hi-z. 50 tst0 i test pin. this pin should be connected to vss2-5. 51 cad0 i chip address 0 pin this pin must be connected to vss2-5 in parallel control mode (spb pin = ?l?). 52 dvdd4 - digital power supply pin, 3.0 3.6v 53 vss5 - digital ground pin 54 tst1 i test pin. this pin should be connected to vss2-5. 55 smsemi i soft mute semi-auto mode setting pin ?h?: semi-auto, ?l?: manual mode 56 tst2 i test pin. this pin should be connected to vss2-5. 57 scl i i 2 c control data clock pin, (when the spb pin= ?h?) since there is a protection diode between this pin and dvdd1-4, connect pulled-up resister to dvdd1-4 + 0.3v or less. this pin must be connected to the vss2-5 in parallel control mode (psb pin= ?l?). 58 sda i/ o i 2 c control data in/out put pin, (when the spb pin= ?h?) since there is a protection diode between this pin and dvdd1-4, connect pulled-up resister to dvdd1-4 + 0.3v or less. this pin must be connected to the vss2-5 in parallel control mode (psb pin= ?l?). 59 spb i parallel/serial control mode select pin ?h?: serial control mode, ?l?: parallel control mode
[ak4128a] ms1242-e-00 2010/09 - 8 - no. pin name i/o function 60 avdd - analog power supply pin, 3.0 3.6v 61 vd18 o digital power output pin, typ 1.8v when the pdn pin= ?l?, the dv18 pin outputs ?l?. current must not be taken from this pin. a 1 f (30%; including the temperat ure characteristics) capacitor should be connected between this pin and dvss. when this capacitor is polarized, the positive polarity pin should be connected to the vd18 pin. 62 vss1 - analog ground pin 63 tst3 i test pin. this pin should be connected to vss2-5. 64 ilrck2 i input channel clock #2 pin when inas pin = ?l?, this pin should be connected to vss2-5. note: all input pins should not be left floating. dvdd1-4 must be connected to the same power supply. note 1. spb, cm2-0, inas, pm2-1, obit1-0, tdm, odif1-0, idif2-0 and cad0 pin must be changed when the pdn pin= ?l?. note 2. in parallel control mode (spb pin = ?l?), idif2- 0 pins control all src1~4 a udio interface input formats. in serial control mode (spb pin = ?h ?), the setting of idif2-0 pins is i gnored. the idif[12:10] bits setting is reflected to src1, the idif[22:20] bits setting is reflected to src2, the idif[32:30] bits setting is reflected to src3, and the idif[42:40] bits setting is reflected to src4. note 3. in parallel control mode (spb pin = ?l?), the smute pin controls all src1~4 soft mute. in serial control mode (spb pin = ?h?), the sumu te pin setting is ignored. the smute1 bit setting is reflected to src1, the smute2 bit setting is reflected to src2, the smute3 bit setting is reflected to src3, and the smute4 bit setting is reflected to src4. note 4. in parallel control mode (spb pin= ?l?), de m1-0 pins control all src1~4 de-emphasis settings. in serial control mode (spb pin= ?h ?), setting of dem1-0 pins is ignored . dem[11:10] bits setting is reflected to src1, dem[21:20] bits setting is reflected to src2, dem[31:30] bits setting is reflected to src3, and dem[41:40] bits setting is reflected to src4. v handling of unused pins the unused i/o pins should be processed appropriately as below. classification pin name setting ibick2, imclk, sdti3-4, ilrck3, ibick3, ilrck4, ibick4, smute, dither, omclk/xti, ilrck2, sda, scl, cad0, tst0-3 these pins must be connected to vss2-5. digital unlock, sdto1-4, mcko, xto these pins must be open.
[ak4128a] ms1242-e-00 2010/09 - 9 - absolute maximum ratings (vss1-5=0v; note 5 ) parameter symbol min max units power supplies: analog digital avdd dvdd1-4 ? 0.3 ? 0.3 4.2 4.2 v v input current, any pin except supplies iin - 10 ma digital input voltage ( note 6 ) vind ? 0.3 dvdd1-4+0.3 v AK4128AEQ ta ? 20 85 c ambient temperature (power applied) ( note 7 ) ak4128avq ta ? 40 85 c storage temperature tstg ? 65 150 c note 5. all voltages with respect to ground. vss1-5 must be connected to the same ground. note 6. imclk, ibick4-1, ilrck4-1, idif2-0, inas, su mte, dither, pdn, smt1-0, dem1-0, pm2-1, obit1-0, tdm, cm2-0, odif1-0, sdto4-1, obick, olrck, omclk/xti, cad0, smsemi, scl, sda and spb pins. note 7. in case that wiring density is 100%. note 8. dvdd1-4 pins must be connected to the same power supply. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1-5=0v; note 5 ) parameter symbol min typ max units power supplies: ( note 9 ) analog digital avdd dvdd1-4 3.0 3.0 3.3 3.3 3.6 3.6 v v difference avdd - dvdd1-4 -0.3 0 +0.3 v note 5. all voltages with respect to ground. vss1-5 must be connected to the same ground. note 8. dvdd1-4 pins must be connected to the same power supply. note 9. the power up sequence between avdd and dvdd1-4 is not critical but the pdn pin must be ?l? until all power supplies are on, then put the pdn pin to ?h?. warning: akm assumes no responsibility for the us age beyond the conditions in this datasheet.
[ak4128a] ms1242-e-00 2010/09 - 10 - src characteristics (ta=25 c; avdd=dvdd1-4=3.3v; vss1-5=0v; signa l frequency = 1khz; data = 24bit; measurement bandwidth = 20hz ~ fso/2; unless otherwise specified.) parameter symbol min typ max units src characteristics: resolution 24 bits input sample rate fsi 8 216 khz output sample rate fso 8 216 khz thd+n (input = 1khz, 0dbfs, note 10 ) fso/fsi = 44.1khz/48khz fso/fsi = 48khz/44.1khz fso/fsi = 48khz/192khz fso/fsi = 192khz/48khz worst case (fso/fsi = 32khz/176.4khz) - - - - - ? 130 ? 124 ? 133 ? 124 - - - - - -91 db db db db db dynamic range (input = 1khz, ? 60dbfs, note 10 ) fso/fsi = 44.1khz/48khz fso/fsi = 48khz/44.1khz fso/fsi = 48khz/192khz fso/fsi = 192khz/48khz worst case (fso/fsi = 48khz/32khz) dynamic range (input = 1khz, ? 60dbfs, a-weighted, note 10 ) fso/fsi = 44.1khz/48khz - - - - 132 - 136 136 136 132 - 140 - - - - - - db db db db db db ratio between input and output sample rate fso/fsi 1/6 6 - note 10. measured by audio precision system two cascade. power consumption (ta= 25 c; avdd=dvdd1-4=3.0~3.6v; vss1-5=0 v; signal frequency=1khz; data =24bit; asynchronous input mode (inas pin = ?h?), output port: master mode, omclk/xti are input via a x?tal. pm2/1 pin = ?h/l? 8ch mode, unless otherwise specified.) parameter min typ max units power supplies power supply current normal operation (pdn pin = ?h?) avdd+dvdd1-4 fsi=fso=48khz: avdd=dvdd1-4=3.3v ( note 12 ) fsi=fso=192khz: avdd=dvdd1-4=3.3v ( note 13 ) : avdd=dvdd1-4=3.6v ( note 14 ) power down (pdn pin = ?l?) ( note 11 ) avdd+dvdd1-4 42 108 109 10 - - 164 100 ma ma ma a note 11. all digital input pins are held to vss2-5. note 12. it is 41 [ma] (typ) when the omclk/xti pin is supplied a 24.576mhz external clock and the output port is in slave mode. note 13. it is 105 [ma] (typ) when the omclk/xti pin is supplied a 24.576mhz external clock and the output port is in slave mode. note 14. it is 106 [ma] (typ) when the omclk/xti pin is supplied a 24.576mhz external clock and the output port is in slave mode.
[ak4128a] ms1242-e-00 2010/09 - 11 - filter characteristics (ta= 25 c; avdd=dvdd1-4=3.0 3.6v) parameter symbol min typ max units digital filter 0.985 fso/fsi 6.000 pb 0 0.4583fsi khz 0.905 fso/fsi < 0.985 pb 0 0.4167fsi khz 0.714 fso/fsi < 0.905 pb 0 0.3195fsi khz 0.656 fso/fsi < 0.714 pb 0 0.2852fsi khz 0.536 fso/fsi < 0.656 pb 0 0.2182fsi khz 0.492 fso/fsi < 0.536 pb 0 0.2177fsi khz 0.452 fso/fsi < 0.492 pb 0 0.1948fsi khz 0.357 fso/fsi < 0.452 pb 0 0.1458fsi khz 0.324 fso/fsi < 0.357 pb 0 0.1302fsi khz 0.246 fso/fsi < 0.324 pb 0 0.0917fsi khz 0.226 fso/fsi < 0.246 pb 0 0.0826fsi khz passband ? 0.01db 0.1667 fso/fsi < 0.226 pb 0 0.0583fsi khz 0.985 fso/fsi 6.000 sb 0.5417fsi khz 0.905 fso/fsi < 0.985 sb 0.5021fsi khz 0.714 fso/fsi < 0.905 sb 0.3965fsi khz 0.656 fso/fsi < 0.714 sb 0.3643fsi khz 0.536 fso/fsi < 0.656 sb 0.2974fsi khz 0.492 fso/fsi < 0.536 sb 0.2813fsi khz 0.452 fso/fsi < 0.492 sb 0.2604fsi khz 0.357 fso/fsi < 0.452 sb 0.2116fsi khz 0.324 fso/fsi < 0.357 sb 0.1969fsi khz 0.246 fso/fsi < 0.324 sb 0.1573fsi khz 0.226 fso/fsi < 0.246 sb 0.1471fsi khz stopband 0.1667 fso/fsi < 0.226 sb 0.1020fsi khz passband ripple pr 0.01 db 0.985 fso/fsi 6.000 sa 121.2 db 0.905 fso/fsi < 0.985 sa 121.4 db 0.714 fso/fsi < 0.905 sa 115.3 db 0.656 fso/fsi < 0.714 sa 116.9 db 0.536 fso/fsi < 0.656 sa 114.6 db 0.492 fso/fsi < 0.536 sa 100.2 db 0.452 fso/fsi < 0.492 sa 103.3 db 0.357 fso/fsi < 0.452 sa 102.0 db 0.324 fso/fsi < 0.357 sa 103.6 db 0.246 fso/fsi < 0.324 sa 103.3 db 0.226 fso/fsi < 0.246 sa 101.5 db stopband attenuation 0.1667 fso/fsi < 0.226 sa 73.2 db group delay ( note 15 ) gd - 64 - 1/fs note 15. this value is the time from the rising edge of ilrck after sdti data is input to rising edge of olrck after the sdti data is output, when olrck data corresponds with ilrck data.
[ak4128a] ms1242-e-00 2010/09 - 12 - dc characteristics (ta= 25 c; avdd=dvdd1-4=3.0 3.6v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%dvdd1-4 - - - - 30%dvdd1-4 v v high-level output voltage except the sda pin (iout= ? 400 a) low-level output voltage except the sda pin (iout=400 a) sda pin (iout=3ma) voh vol vol dvdd1-4 ? 0.4 - - - - 0.4 0.4 v v v input leakage current iin - - 10 a switching characteristics (ta= 25 c; avdd=dvdd1-4=3.0 3.6v; c l =20pf) parameter symbol min typ max units master clock timing crystal oscillator frequency fxtal 11.2896 24.576 mhz imclk input frequency duty feclk declk 1.024 40 50 36.864 60 mhz % omclk input 128 fso : pulse width low pulse width high 256 fso : pulse width low pulse width high 384 fso : pulse width low pulse width high 512 fso : pulse width low pulse width high 768 fso : pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 1.024 13 13 2.048 13 13 3.072 10 10 4.096 13 13 6.144 10 10 27.648 27.648 36.864 27.648 36.864 mhz ns ns mhz ns ns mhz ns ns mhz ns ns mhz ns ns mcko output frequency duty ( note 16 ) fmck dmclk 1.024 40 50 36.864 60 mhz % note 16. this is a value of mcko output duty when the master clock for output ports is supplied by a crystal oscillator.
[ak4128a] ms1242-e-00 2010/09 - 13 - input port lrck for stereo mode (ilrck1-4) frequency duty cycle slave mode fsi duty 8 48 50 216 52 khz % output port lrck for stereo mode (olrck) frequency slave mode master mode omclk input 128fso mode master mode omclk input 256fso mode master mode omclk input 384fso mode master mode omclk input 512fso mode master mode omclk input 768fso mode duty cycle slave mode master mode fso fso fso fso fso fso duty duty 8 8 8 8 8 8 48 50 50 216 216 108 96 54 48 52 khz khz khz khz khz khz % % input port lrck for tdm256 mode (ilrck1) asynchronous inputs mode (inas pin = ?l?) frequency ?h? time (slave mode) ?l? time (slave mode) fsi tlrh tlrl 8 1/256fsi 1/256 fsi 48 khz ns ns output port lrck for tdm256 mode (olrck) frequency ?h? time (slave mode) ?l? time (slave mode) ?h? time (master mode, tdm256 24bit msb justified) ?l? time (master mode, tdm256 24bit i 2 s) fso tlrh tlrl tlrh tlrl 8 1/256 fso 1/256 fso - - 1/8 fso 1/8 fso 48 - - khz ns ns ns ns audio interface timing input port ( stereo slave mode) ibick1-4 period (fsi= 8khz 54khz) (fsi=54khz 108khz) (fsi=108khz 216khz) ibick1-4 pulse width low pulse width high ilrck1-4 edge to ibick1-4 ? ?( note 17 ) ibick1-4 ? ? to ilrck1-4 edge ( note 17 ) sdti1-4 hold time from ibick1-4 ? ? sdti1-4 setup time to ibick1-4 ? ? tbck tbck tbck tbckl tbckh tlrb tblr tsdh tsds 1/256 fsi 1/128 fsi 1/64 fsi 27 27 15 15 15 15 ns ns ns ns ns ns ns ns ns input port (tdm256 slave mode) ibick1 period ibick1 pulse width low pulse width high ilrck1 edge to ibick1 ? ? ( note 17 ) ibick1 ? ? to ilrck1 edge ( note 17 ) sdti1 hold time from ibick1 ? ? sdti1 setup time to ibick1 ? ? tbck tbckl tbckh tlrb tblr tsdh tsds 81 32 32 20 20 20 10 ns ns ns ns ns ns ns output port ( stereo slave mode) obick period (fso= 8khz 54khz) (fso= 54khz 108khz) (fso=108khz 216khz) obick pulse width low pulse width high olrck edge to obick ? ? ( note 17 ) obick ? ? to olrck edge ( note 17 ) olrck to sdto1-4 (msb) (except i 2 s mode) obick ? ? to sdto1-4 tbck tbck tbck tbckl tbckh tlrb tblr tlrs tbsd 1/256 fso 1/128 fso 1/64 fso 27 27 20 20 20 20 ns ns ns ns ns ns ns ns ns
[ak4128a] ms1242-e-00 2010/09 - 14 - output port (tdm256 slave mode) obick period obick pulse width low pulse width high olrck edge to obick ? ? ( note 17 ) obick ? ? to olrck edge ( note 17 ) obick ? ? to sdto1 tbck tbckl tbckh tlrb tblr tbsd 81 32 32 20 20 20 ns ns ns ns ns ns output port (stereo master mode) obick frequency obick duty obick ? ? to olrck edge obick ? ? to sdto1-4 fbck dbck tmblr tbsd ? 20 ? 20 64 fso 50 20 20 hz % ns ns output port (tdm256 master mode) obick frequency obick duty obick ? ? to olrck edge obick ? ? to sdto1 fbck dbck tmblr tbsd - - ? 10 ? 20 256 fso 50( note 19 ) - - - 10 20 hz % ns ns reset timing pdn pulse width ( note 18 ) tpd 150 ns note 17. bick rising edge must not occur at the same time as lrck edge. note 18. the ak4128a can be reset by bringing the pdn pin = ?l?. note 19. when omclk=512fso. if the omclk=256fso, omclk clock is though and output from the obick pin. when omclk = 384fso, dbck= (tclkh)/(tclkh+1/fclk) x100 [%] or (tclkl)/(tclkl+1/fclk) x100 [%]. when omclk=768fso, dbck= (1/fclk)/(3/fclk) x100 [%]. omclk=384fso omclk=768fso omclk pin tclkh tclkl tclkl 1/fclk 1/fclk tclkh tclkl 1/fclk 1/fclk obick pin ouput (tdm256 master mode) omclk pin 1/fclk 3/fclk 3/fclk obick pin output (tdm256 master mode) 1/fclk 1/fclk 1/fclk
[ak4128a] ms1242-e-00 2010/09 - 15 - parameter symbol min typ max units control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 20 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf note 20. data must be held for sufficient tim e to bridge the 300 ns transition time of scl.
[ak4128a] ms1242-e-00 2010/09 - 16 - 1/fclk omclk(i) vih vil 1/fmck tmckl 50%dvdd tmckh mcko(o) tclkl tc lkh 1/feclk te clkl vih teclkh imclk(i) vil declk = teclkh (or teclkl) x feclk x 100 dmclk = tmckh (or tmckl) x fmck x 100 1/fsi lrck1-4(i) vih vil tlrcl tlrch tbck tbckl vih tbckh ibick1-4(i) vil ? stereo mode and slave mode duty = tlrch (or tlrcl) x fsi x 100 1/fsi lr ck1(i) vih vil tlrl tlrh tbck tbckl vih tbckh ibick1(i) vil ? tdm256 mode and slave mode timing diagram figure 5. imclk, omclk, mcko clock timing figure 6. ilrck1-4, ibick1-4 clock timing
[ak4128a] ms1242-e-00 2010/09 - 17 - 1/fso olrck(i) vih vil tlrcl tlrch tbck tbckl vih tbckh obick(i) vil ? stereo mode and slave mode duty = tlrch (or tlrcl) x fso x 100 1/fso olrck(i) vih vil tlrl tlrh tbck tbckl vih tbckh obick(i) vil ? tdm256 mode and slave mode 1/fso olrck(o) 50%dvdd tlrcl tlrch 1/ fbck tbickl 50%dvdd tbickh obick(o) ? stereo mode and master mode duty = tlrch (or tlrcl) x fso x 100 ? tdm256 mode and master mode dbck = tbickh(or tbickl) x fbck x 100 1/fso olrck(o) 24bit msb justified 50%dvdd tlrh 1/ fbck tbickl 50%dvdd tbickh obick(o) dbck = tbickh(or tbickl) x fbck x 100 1/fso olrck(o) 24bit i 2 s 50%dvdd tlrl figure 7. olrck, obick, clock timing (slave mode) figure 8. olrck, obick, clock timing (master mode)
[ak4128a] ms1242-e-00 2010/09 - 18 - figure 9. input port audio interface timing (stereo slave mode a nd tdm256 slave mode) figure 10. output port audio interface timi ng (tdm256 slave mode & stereo slave mode) tlrb ilrck 1 - 4 vih ibick 1 - 4 vil vih vil tblr tsds sdti 1 - 4 vih vil tsdh tlrb o lrck vih o bick vil sdto 1 - 4 50% d vdd vih vil tblr tlrs tbsd
[ak4128a] ms1242-e-00 2010/09 - 19 - thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp olrck obick sdto1-4 tbsd tmblr 50%dvdd 50%dvdd 50%dvdd figure 11. output port audio interface timing (tdm256 master m ode & stereo master mode) tpd pdn vil figure 12. power down timing figure 13. i 2 c bus timing
[ak4128a] ms1242-e-00 2010/09 - 20 - operation overview synchronous and asynchronous modes setting there are two modes of operation: asynchronous and sync hronous modes. the ak4128a is set to synchronous mode when the inas pin is ?l? and it is set to asynchronous mode when the inas pin is ?h?. fsi pin mode data lrck bick sdti1 sdti2 sdti3 l synchro nous sdti4 ilrck1 ( note 21 ) ibick1 ( note 22 ) sdti1 ilrck1 ibick1 sdti2 ilrck2 ibick 2 sdti3 ilrck3 ibick 3 h asynchr onous sdti4 ilrck4 ibick 4 note 21. ilrck2-4 pins must be connected to vss2-5. note 22. ibick2-4 pins must be connected to vss2-5. table 1. input data synchr onous/asynchronous mode setting audio interface format for input port the audio data format of input port is msb first, 2?s complement format. the sdti1, sdti2, sdti3 and sdti4 are latched on the rising edge of ibick1, ib ick2, ibixk3 and ib ick4 respectively. in parallel control mode (spb pin= ?l?), idif2-0 pins control all audio interface fo rmats of src1~4. idif2-0 pins must be set during the pdn pin= ?l?. in serial control mode (spb pin = ?h?), setting of idif2-0 pins is ignored. idif[ 12:10] bits setting is reflected to src1, idif[22:20] bits setting is reflected to src2, idif[32:30] bits setting is reflected to src3, and idif[42:40] bits setting is reflected to src4. idif[12:10] bits should be changed after all sdto1 output codes become zero during soft mute by smute1 bit = ?1? or the smute pin = ?h?. idif[22:20] bits should be changed after all sdto2 output codes become zero during soft mute by smute2 bit = ?1? or the smute pin = ?h?. idif[32:30] bits should be changed after all sdto3 output codes become zero during soft mute by smute3 bit = ?1? or the smute pin = ?h?. idif[42:40] bits should be changed after all sdto4 output codes become zero during soft mute by smute4 bit = ?1? or the smute pin = ?h?. tdm mode (mode 5/6) can be set in synchronous inputs mode (i nas pin = ?l?). serial data for 8channels should be input from the sdti1 pin. in this mode, connect sdti2- 4 pins to vdd2-5 because there pins are ignored. asynchronous inputs mode (inas pin = ?h?) does not support tdm mode. the ak4128a is not able to operate correctly because of sdti1-4 data inputs are in correct. tdm mode is must be off, when using the ak4128a in asynchronous inputs mode (inas pin = ?h?). the maximum input frequency of ibick1-4 is 256fsi.
[ak4128a] ms1242-e-00 2010/09 - 21 - mode idif2 pin ( note 23 ) idif1 pin ( note 23 ) idif0 pin ( note 23 ) sdti1-4 format ilrck 1-4 ibick 1-4 ibick1-4 freq 0 l l l 16bit, lsb justified 32fsi 1 l l h 20bit, lsb justified 40fsi 2 l h l 24bit, msb justified 48fsi 24 or 16bit, i 2 s compatible 48fsi 3 l h h 16bit, i 2 s compatible 32fsi 4 h l l 24bit, lsb justified 48fsi 5 h l h tdm 24bit, msb justified 256fsi 6 h h x tdm 24bit, i 2 s compatible input input 256fsi table 2. input port audio interface format (para llel control mode, spb pin= ?l?) (x= don?t care) note 23. in serial control mode (spb pi n = ?h?), setting of idif2-0 pins is ignored . idif[12:10] bits setting is reflected to src1, idif[22:20] bits setting is reflected to src2, idif[32:30] bits setting is reflected to src3, and idif[42:40] bits setting is reflected to src4. ilrck ibick(32fs) 0 110 2 3 9 1112131415 0 12 3 1 0 10 9 1112131415 sdti(i) don't care 1 0 15 14 13 210 15 14 13 12 12 don't care 15:msb, 0:lsb sdti(i) 15 14 13 76543 210 15 14 13 15 76543 210 ibick(64fs) 0 118 2 3 19 20 31 0 1 2 3 1 0 18 19 20 31 17 17 lch data rch data figure 14. mode 0 timing (16bit, lsb justified) ilrck ibick(64fs) 0 1 224310 12 1 0 31 24 sdti(i) don't care 0 8 10 19:msb, 0:lsb lch data rch data 19 8 don't care 19 1 12 13 13 12 figure 15. mode 1 timing (20bit, lsb justified) ilrck ibick(64fs) 0 1 2202124310 12 1 0 22 20 21 31 24 22 23 23 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data don't care 4321 23 22 23 22 23 1 2 3 4 figure 16. mode 2 timing (24bit, msb justified)
[ak4128a] ms1242-e-00 2010/09 - 22 - ilrck ibick(64fs) 0 1 225 21 24 0 12 1 0 22 25 21 24 22 23 23 3 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data don't care 4321 23 22 23 22 1 2 3 4 figure 17. mode 3 timing (24bit i 2 s) ilrck ibick(64fs) 0 1 224310 12 1 0 31 24 89 89 sdti(i) don't care 0 8 10 23:msb, 0:lsb lch data rch data 23 8 don't care 23 1 figure 18. mode 4 timing (24bit, lsb justified) note: sdti is identified as sdti1, sdti2, sdti3 and sdti4, ilrck is identified as ilrck1, ilrck2, ilrck3 and ilrck4, ibick is identified as ibic k1, ibick2, ibick3 and ibick4. 23 ilrck1( i) ibick1 (i: 256fsi) sdti1(i) 22 0 l1 32 ibick 256 ibic k 22 0 r1 32 ibick 22 23 23 23 22 0 l2 32 ibick 22 0 r2 32 ibick 23 23 22 0 l3 22 0 r3 23 23 22 0 l4 22 0 r4 23 32 ibick 32 i bick 32 i bick 32 i bick figure 19. mode 5 timing (tdm, 24bit, msb justified, sdti2-4: don?t care) ilrck1( i) ibick1(i: 256fsi) sdti1(i) 23 0 l1 256 ibic k 23 0 r1 23 23 0 l2 23 0 r2 23 0 l3 23 0 r3 23 0 l4 23 0 r4 32 ibick 32 ibick 32 ibick 32 ibick 32 ibick 32 ibick 32 ibick 32 ibick figure 20. mode 6 timing (tdm, i 2 s, sdti2-4: don?t care)
[ak4128a] ms1242-e-00 2010/09 - 23 - system clock for output port the output ports work in master mode and slave mode. the cm2-0 pins select the master/slave mode. mode cm2 pin cm1 pin cm0 pin master / slave omclk/xti input mcko output fso fso with x?tal 0 l l l master 256fso 256fso 8k 108khz 44.1~96khz 1 l l h master 384fso 384fso 8k 96khz 29.4~64khz 2 l h l master 512fso 512fso 8k 54khz 22.05~48khz 3 l h h master 768fso 768fso 8k 48khz 14.7~32khz 4 h l l slave not used. ( note 24 ) omclk input clock 8k 216khz - 5 h l h master 128fso ( note 25 ) 128fso 8k 216khz 88.2~192khz 6 h h l slave(bypass) 7 h h h master(bypass) not used. ( note 24 ) imclk input clock 8k 216khz - note 24. use for a clock input or connect to vss2-5 pin. in mode 4, the mcko pin outputs ?l? if the omclk/xti pin is connected to vss2-5. when a clock is input to the omclk/xti pin, the clock is through and output from the mcko pin. in mode 6-7, omclk/xti input is ignored internally. note 25. output ports do not support tdm mode in this mode. table 3. output port master/slave/ bypass mode control (spb pin = ?l?) in serial control mode (spb pin = ?h?), the byps bit selects src bypass mode and src mode. the default value of the byps bit is ?0? (src mode). mode cm2 pin cm1 pin cm0 pin byps bit master / slave omclk/xti input mcko output fso fso with x?tal 0 l l l 0 master 256fso 256fso 8 108khz 44.1~96khz 1 l l h 0 master 384fso 384fso 8 96khz 29.4~64khz 2 l h l 0 master 512fso 512fso 8 54khz 22.05~48khz 3 l h h 0 master 768fso 768fso 8k~48khz 14.7~32khz 4 h l l 0 slave not used. ( note 26 ) omclk input clock 8 216khz - 5 h l h 0 master 128fso ( note 25 ) 128fso 8 216khz 88.2~192khz 6 h h l 0 slave (bypass) 7 h h h 0 master (bypass) 8 l l l 1 master (bypass) 9 l l h 1 master (bypass) 10 l h l 1 master (bypass) 11 l h h 1 master (bypass) 12 h l l 1 slave (bypass) 13 h l h 1 master (bypass) 14 h h l 1 slave (bypass) 15 h h h 1 master (bypass) not used. ( note 26 ) imclk input clock 8 216khz - note 26. use for a clock input or connect to vss2-5 pin. in mode 4, the mcko pin outputs ?l? if the omclk/xti pin is connected to vss2-5. when a clock is input to the omclk/xti pin, the clock is through and output from the mcko pin. in mode 6-15, omclk/xti input is ignored internally. table 4. output port master/slave/ bypass mode control (spb pin = ?h?)
[ak4128a] ms1242-e-00 2010/09 - 24 - (1) master mode the olrck pin and obick pin are output pins in master mode. master clock is supplied from the omclk/xti pin. the clock for the omclk/xti pin can be ge nerated by the following methods: conn ect a crystal oscillator between the omclk/xti and xto pins, or input a clock to the omclk/xti pin. in bypass mode, the mcko pin outputs imclk data. a. x?tal xti xto ak4128a 460k c c (typ) note: refer to table 5 for the capacitor and resistor values of the x?tal oscillator. figure 21. x?tal mode nominal frequency [mhz] 11.2896 12.288 24.576 equivalent series resistance r1[ ? ] max 60 external capacitance c[pf] max 15 table 5. equivalent series resistor and external capacitor for external x?tal oscillator in x?tal mode at 256fso omclk input, fso ranges from 44.1khz to 96khz. in x?tal mode at 384fso omclk input, fso ranges from 29.4khz to 64khz. in x?tal mode at 512fso omclk input, fso ranges from 22.05khz to 48khz. in x?tal mode at 768fso omclk input, fso ranges from 14.7khz to 32khz. in x?tal mode at 128fso omclk input, fso ranges from 88.2khz to 192khz. b. external clcok - note: do not input the clock over dvdd1-4. xti xto ak4128a 460k external clock (typ) figure 22. external clock (omclk) mode (2) slave mode the olrck pin and obick pin are input pins in slave mode. the omclk/xti pin is pulled down when the pdn pin= ?l?.
[ak4128a] ms1242-e-00 2010/09 - 25 - (3) src bypass mode src bypass mode can be set in synchronous inputs mode (inas pin = ?l?). asynchronous inputs mode (inas pin = ?h?) does not supports src bypass mode, so that the data is not transferred correctly on sdti1 sdto1, sdti2 sdto2, sdti3 sdto3 and sdti4 sdto4 lines. in asynchronous inputs mode (inas pin = ?h?), the ak4128a should be used in src mode. when the ak4128a is in slave mode, sdti1-4 data are input by the ilrck1 and ibick1 clocks in src bypass mode ( table 2 ). the sdti1-4 data are output from the olrck and obick pins in a format shown in table 6 and table 7 . ibick and obick must be synchronized but the phase is not critical. ilrck and olrck must be synchronized but the phase is not critical. output serial a udio i/f dem input serial a udio i/f src1 fir src smute + dither bypass src 0.5 lsb ibick1 sdti1 ilrck1 dem input serial a udio i/f src2 fir src smute + dither bypass src ibick2 sdti2 ilrck2 sdto1 sdto2 dem input serial a udio i/f src3 fir src smute + dither bypass src ibick3 sdti3 ilrck3 sdto3 dem input serial a udio i/f src4 fir src smute + dither bypass src ibick4 sdti4 ilrck4 sdto4 mcko clock div cm2 cm1 cm0 imclk bypass src x?tal osc omclk/xti xto olrck obick obit1 obit2 odif1 odif0 idif2 up i/f sda spb cad0 pdn pm1 pm2 unlock a vdd vss1 scl idif1 idif0 dem1 dem0 inas dvdd1-4 vss2-5 smsemi smute smt1 smt0 dither 0.5 lsb 0.5 lsb 0.5 lsb internal osc internal regulator ref vd18 figure 23. bypass mode in slave mode (synchronous mode inas pin = ?l?)
[ak4128a] ms1242-e-00 2010/09 - 26 - when the ak4128a is in master mode, sdti1-4 data are input by the ilrck1 and ibick1 clocks in src bypass mode ( table 2 ). the sdti1-4 output data are output by the ilrck1 and ibick1 clocks in a format shown in table 6 and table 7 . the ilrck1 clock bypasses the src and it is output from th e olrck pin. the ibick1 clock bypasses the src and it is output from the obick pin. output serial a udio i/f dem input serial a udio i/f src1 fir src smute + dither bypass src 0.5 lsb ibick1 sdti1 ilrck1 dem input serial a udio i/f src2 fir src smute + dither bypass src ibick2 sdti2 ilrck2 sdto1 sdto2 dem input serial a udio i/f src3 fir src smute + dither bypass src ibick3 sdti3 ilrck3 sdto3 dem input serial a udio i/f src4 fir src smute + dither bypass src ibick4 sdti4 ilrck4 sdto4 mcko clock div cm2 cm1 cm0 imclk bypass src x?tal osc omclk/xti xto olrck obick obit1 obit2 odif1 odif0 idif2 up i/f sda spb cad0 pdn pm1 pm2 unlock a vdd vss1 scl idif1 idif0 dem1 dem0 inas dvdd1-4 vss2-5 smsemi smute smt1 smt0 dither 0.5 lsb 0.5 lsb 0.5 lsb internal osc internal regulator ref vd18 figure 24. bypass mode in master mode (synchronous mode inas pin = ?l?)
[ak4128a] ms1242-e-00 2010/09 - 27 - audio interface format for output port the odif1-0 pins and obit1-0 pi ns select the audio interface format for the out put port. the audio data is msb first, 2?s complement format. the sdto1-4 is clocked out on the falli ng edge of obick. select th e audio interface format for output port when the pdn pin = ?l?. if the ak4128a is in slave mode at bypass mode, ibick1 and obick must be synchronized but the phase is not critical. ilrck1 and olrck must be synchronized but the phase is not critical. the audio interface format of sdto1, sdto2, sdto3 and sdto4 are controlled together by odif1-0 pins, obit1-0 pins and tdm pin. output ports become tdm mode when the tdm pin = ?h?. in tdm mode, the sdti1 pin outputs serial data for 8channels and the sdti2-4 pins output ?l?. mode tdm pin odif1 pin odif0 pin sdto1-4 format 0 l l l lsb justified 1 l l h reserved 2 l h l msb justified 3 l h h i 2 s compatible 4 h l l reserved 5 h l h reserved 6 h h l tdm256 mode 24bit msb justified 7 h h h tdm256 mode 24bit i 2 s compatible table 6. output port audio interface format 1 obick frequency mode tdm pin master / slave setting obit1 pin obit0 pin sdto 1-4 olrc k obick msb justified, i 2 s lsb justified 0 l l 16bit 32fso 1 l h 18bit 36fso 2 h l 20bit 40fso 3 slave (cm2-0 = ?hll? or ?hhl?) h h 24bit input input 48fso 64fso 4 l l 16bit 5 l h 18bit 6 h l 20bit 7 l master (not cm2-0 = ?hll?/?hhl?) h h 24bit output output 64fso 8 9 10 11 slave (cm2-0 = ?hll? or ?hhl?) * * tdm256 mode 24bit input input 256fso 12 13 14 15 h master (not cm2-0 = ?hll?/?hhl?) * * tdm256 mode 24bit output output 256fso table 7. output port audio interface format 2 (* the data length for 1channel is 24bit fixed in tdm mode. the obit1-0 pin settings are ignored. connect these pins to vss2-5.)
[ak4128a] ms1242-e-00 2010/09 - 28 - olrck obick(64fs) 0 1 lch data rch data 89 sdto(o) 15:msb, 0:lsb sdto(o) 17:msb, 0:lsb sdto(o) 19:msb, 0:lsb sdto(o) 23:msb, 0:lsb 1 0 12 13 14 11 10 16 17 15 20 21 22 29 23 31 30 10 9 8 11 15 14 2 1 0 10 9 8 11 15 14 2 1 0 17 16 10 9 8 11 15 14 2 1 0 17 16 19 18 10 9 8 11 15 14 2 1 0 17 16 19 18 21 20 23 22 12 13 14 11 8 9 10 16 17 15 20 21 22 29 23 31 30 0 1 2 10 9 2 11 15 14 0 1 8 2 8 15 14 11 0 1 17 16 10 9 2 8 15 14 9 0 1 17 16 19 18 11 10 2 8 15 11 10 9 0 1 17 16 19 18 21 20 23 22 14 figure 25. stereo mode lsb justified timing olrck obick(64fs) 0 1 2 lch data rch data 34 sdto(o) sdto(o) sdto(o) sdto(o) 23:msb, 0:lsb 34 15:msb, 0:lsb 17:msb, 0:lsb 19:msb, 0:lsb 321 4 8765 0 10 9 21 20 23 22 321 4 65 0 17 16 19 18 321 4 15 14 0 17 16 15 14 13 12 2 1 0 321 4 8765 0 10 9 21 20 23 22 321 4 65 0 17 16 19 18 321 4 15 14 0 17 16 15 14 13 12 2 1 0 0 31 1 2 0 31 1 2 19 18 17 24 13 14 16 15 20 21 23 22 19 18 17 24 13 14 16 15 20 21 23 22 23 22 19 18 17 16 15 14 figure 26. stereo mode msb justified timing olrck obick(64fs) 0 1 2 lch data rch data 34 sdto(o) sdto(o) sdto(o) sdto(o) 23:msb, 0:lsb 34 15:msb, 0:lsb 17:msb, 0:lsb 19:msb, 0:lsb 012 0 31 1 2 19 18 17 24 14 16 15 20 21 23 22 19 18 17 24 14 16 15 20 21 23 22 23 19 17 15 15 14 13 12 2 1 0 321 4 15 14 0 17 16 321 4 65 0 17 16 19 18 321 4 8765 0 10 9 21 20 23 22 15 14 13 12 2 1 0 321 4 15 14 0 17 16 321 4 65 0 17 16 19 18 321 4 8765 0 10 9 21 20 23 22 figure 27. stereo mode i 2 s compatible timing note: sdto is identified as sd to1, sdto2, sdto3 and sdto4.
[ak4128a] ms1242-e-00 2010/09 - 29 - 23 o bick(o) (2 56fso ) sdto 1 (o) 22 0 l1 32 obick 256 obick 22 0 r1 32obick 22 23 23 23 22 0 l2 32obick 22 0 r2 32 obick 23 23 22 0 l3 22 0 r3 23 23 22 0 l4 22 0 r4 23 o lrck(o) 1/ 8fso 32obick 32 obick 32 obick 32obick figure 28. tdm 256 mode 24bit msb justified timing at master mode. (sdto2-4: ?l? outputs) 23 olrck(i) obick(i) (256fso) s dto 1 (o) 22 0 l1 32 obick 256 obick 22 0 r1 32 obick 22 23 23 23 22 0 l2 32 obick 22 0 r2 32 ob ic k 23 23 22 0 l3 22 0 r3 23 23 22 0 l4 22 0 r4 23 mi n. 1/ 256fso 32 obick 32 obick 32 obick 32 obick figure 29. tdm 256 mode 24bit msb justified timing at slave mode. (sdto2-4: ?l? outputs) obick (o: 2 56fs o) sdto 1 (o) 23 0 l1 32 obick 256 obick 23 0 r1 32 ob ick 23 23 0 l2 32 obick 23 0 r2 32 obick 23 0 l3 23 0 r3 23 0 l4 23 0 r4 olrck(o) 1/8 fso 32 obick 32 obick 32 obick 32 obic k figure 30. tdm 256 mode 24bit i 2 s compatible timing at master mode (sdto2-4: ?l? outputs) olrck(i) obick ( i: 256fso) sdto 1 (o) 23 0 l1 32 obick 256 obick 23 0 r1 32 obick 23 23 0 l2 32 obick 23 0 r2 32 obick 23 0 l3 23 0 r3 23 0 l4 23 0 r4 32 obick 32 obick 32 obick 32 obick min. 1/ 256fso figure 31. tdm 256 mode 24bit i 2 s compatible timing at slave mode (sdto2-4: ?l? outputs)
[ak4128a] ms1242-e-00 2010/09 - 30 - 6/4channel mode the ak4128a has 6-channel and 4-channel modes to reduce pow er supply current when not using all eight channels. when the pm2 and pm1 pins are se t to ?l/l?, six channels (sdti1 ? sdto1, sdti2 ? sdto2 and sdti3 ? sdto3) are powered-up and the other two channels (sdti4 ? sdto4) are powered-down (?l? output). when the pm2 and pm1 pins are set to ?l/h?, four channels (sdti1 ? sdto1 and sdti2 ? sdto2) are powered-up and the other four channels (sdti3 ? sdto3 and sdti4 ? sdto4) are powered-down (?l? output). in 6-channel and 4-channel modes, the x?tal oscillator circuit and the mcko output are powered-down and the xto pin and mcko pin output hi-z. pm2 pin pm1 pin pdn pin mode x?tal oscillator xti pin xto pin mcko pin l l l pull down to vss2-5 (note) l l h 6-channel mode power-down input hi-z l h l pull down to vss2-5 (note) l h h 4-channel mode power-down input hi-z hi-z h l l power-down pull down to vss2-5 (note) hi-z l h l h 8-channel mode normal operation input output normal operation h h l - - - - h h h not available - - - - note: pull down (460k ? typ.) to vss2-5. table 8. channel mode setting soft mute operation 1. manual mode the soft mute operation is performed in the digital domain of the src output. src1-4 soft mutes are controlled together by the smute pin in parallel control mode (spb pin = ?l?). in serial control mode (spb pin = ?h?), setting of the smute pin is ignored. src1 reflects smute1 b it setting, src2 reflects smute2 bit setti ng, src3 reflects smute3 bit setting, and src4 reflects smute4 bit setting. when the smute pin goes ?h? or smute1-4 bits becomes ?1?, all the outputs data are attenuated by f during 1024 olrck cycles (@ smt1 pin = ?l? and smt0 pin = ?l?). when the smute pin goes ?l? or smute1-4 bits becomes ?0?the mute is cancelled and the output attenuation gradually changes to 0db during 1024 olrck cycles (@ smt1 pin = ?l? and smt0 pin = ?l?). if the soft mu te is cancelled before attenuating to - ? , the attenuation is discontinued and returned to 0db by the same cycles. the soft mute is effective for changing the signal source without stopping the signal transmission. soft mute cycle is set by smt1-0 pins. smt1-0 pins must not be changed during soft mute transition. smt1pin smt0 pin period fso=48khz fso=96khz fso=192khz l l 1024/fso 21.3ms 10.7ms 5.3ms l h 2048/fso 42.7ms 21.3ms 10.7ms h l 4096/fso 85.3ms 42.7ms 21.3ms h h 8192/fso 170.7ms 85.3ms 42.7ms table 9. soft mute cycle setting (parallel mode)
[ak4128a] ms1242-e-00 2010/09 - 31 - smute pin, smute1-4 bit attenuation 0db - (1) (2) sdto (1) a ll ?0? code note: sdto is identified as sd to1, sdto2, sdto3 and sdto4. (1) the soft mute cycle is se lected by smt1-0 pins. ( table 9 ) the output data is attenuated by ? during the soft mute cycle. (2) if the soft mute is cancelled before attenuating to ? , the attenuation is discontinued and returned to 0db by the same clock cycles. figure 32. soft mute function (manual mode) 2. semi-auto mode when power down of the ak4128a is released (pdn pin = ?l? ?h?) with the smsemi pin= ?h?, the ak4128a enters semi-auto mode. in this mode, soft mute is cancelled automatically 4410/fso after a rising edge of pdn (100ms @fso=44.1khz). the soft mute is on after releasing power down if the smute pin = ?h?. the smsemi pin must be set during the pdn pin = ?l?. pdn pin attenuation 0db - sdto 4410/fso (1 ) smute pin don?t care ?l ? ?l? all ?0? code (2 ) note: sdto is identified as sd to1, sdto2, sdto3 and sdto4. (1) the output data is attenuated by ? during the soft mute cycle ( table 9 ) (2) when it is 0db by a soft mute release after 4410/fso, it is able to mute or release the mute by the soft mute cycle in table 9 . figure 33. soft mute function (semi-auto mode)
[ak4128a] ms1242-e-00 2010/09 - 32 - dither the ak4128a includes a dither circuit. the dither circuit adds a dither signal after the lowest bit of all the output data set by the obit1-0 pins when the dither pin = ?h?, regardless of src and src bypass modes. if the output bit is 24bit length in src bypass mode, the output code doe s not change by the dither pin setting. de-emphasis filter the ak4128a includes a digital de-emphasis filter (tc = 50/15 s) by an iir filter. this filter corresponds to three frequencies (32khz, 44.1khz and 48khz). in parallel control m ode (spb pin = ?l?), de-em phasis setting of src1-4 are controlled together by dem1-0 pins. in serial control mode (psb pin = ?h?), the setting of dem1-0 pins is ignored. src1 reflects the dem[11:10] bits setting, src2 reflects the dem[21:20] bits setting, src3 reflects the dem[31:30] bits setting, and src4 reflects the dem[41:40] bits setting. dem11pin dem10 pin mode(sdti1-4) l l 44.1khz l h off h l 48khz h h 32khz table 10. de-emphasis filter setting (parallel control mode (spb pin= ?l?)) dem11bit dem10 bit mode(sdti1) l l 44.1khz l h off h l 48khz h h 32khz table 11. de-emphasis filter setting for sdti1 (serial control mode (spb pin = ?h?)) dem21 bit dem20 bit mode(sdti2) l l 44.1khz l h off h l 48khz h h 32khz table 12. de-emphasis filter setting for sdti2 (serial control mode (spb pin= ?h?)) dem31 bit dem30 bit mode(sdti3) l l 44.1khz l h off h l 48khz h h 32khz table 13. de-emphasis filter setting for sdti3 (serial control mode (spb pin = ?h?)) dem41 bit dem40 bit mode(sdti4) l l 44.1khz l h off h l 48khz h h 32khz table 14. de-emphasis filter setting for sdti4 (serial control mode (spb pin = ?h?))
[ak4128a] ms1242-e-00 2010/09 - 33 - regulator the ak4128a has an internal regulator which suppresses the voltage to 1.8v from dvdd1-4 voltage. the generated 1.8v power is used as power supply for internal circuit. when over-current is flowed to the regulator output, over-current detection circuit works. when over-voltage is flowed to th e regulator output, over-voltage detection circuit works. the regulator block is powered-down and the ak4128a becomes reset state when over-current detection circuit or over-voltage detection circuit is operated. the ak4128a does not return to normal operation without a reset by the pdn pin when these detection circuits are worked. when over-cu rrent or over-voltage is detected, the pdn pin should be brought into ?l? at once, and should be set to ?h? again to recover normal operation. the unlock pin indicate the internal status of the device, and outputs ?l? in src normal operation, and outputs ?h? when over-current or over-voltage are detected. system reset bringing the pdn pin = ?l? sets the ak4128a power-down m ode and initializes the digital filters. the ak4128a should be reset once by bringing the pdn pin = ?l? upon power-up. when pdn pin = ?l?, the sdto1-4 output is ?l?. it takes 23ms (max) for sdto output enable after power-down state is released by a clock input. until then, the sdto1-4 outputs ?l?. the internal src circuit is powered-up on an edge of ilrck1-4 after a power-up time period of the internal regulator. (sdto is identified as sdto1, sdto2, tdto3 and sdto4. sdti is identified as sdti1, sdti2, sdti3 and sdti4.) figure 34. system reset 1 case 1: system reset with clock inputs external clocks (input port) sdti don?t care sdto4 (internal state) power-down normal operation normal data input clocks 1 external clocks (output port) don?t care don?t care pdn power-down don?t care don?t care don?t care ?0 ? data normal operati on 23ms(max) normal data pd input data 1 output clocks 1 input clocks 2 input data 2 output clocks 2 ?0? data ?0 ? data unlock 23 ms(m ax) (1) sdto3 normal data ?0 ? data normal data ?0? data ?0? data sdto2 normal data ?0 ? data normal data ?0? data ?0? data sdto1 normal data ?0 ? data normal data ?0? data ?0 ? data (1)
[ak4128a] ms1242-e-00 2010/09 - 34 - figure 35. system reset 2 note 27. spb, cm2-0, inas, pm2-1, obit1-0, tdm, odif1-0, idif2-0 and cad0 pin must be changed when the pdn pin= ?l?. note 28. the unlock pin outputs ?h? when the pdn pin= ?l?. src data is output from sdto1-4 pins, which corresponds to the each sampling frequency ratio detected src, after a rising edge ? ? of pdn if the internal regulator is in normal operation. in 8-channel m ode, the unlock pin outputs ?l? when sampling frequency ratio detection is completed at all src?s. the unlock pin keeps outputting ?h? if there is one src which does not finished sampling frequency ratio detection. note 29. (1) is the total time of ?internal circuit power-up + fso/fsi ratio detection + clock detection + internal circuit group delay?. note 30. (2) is the total time of ?fso/fsi ratio detection + clock detection + internal circuit group delay?. case 2: system reset without clock inputs external clocks (input port) sdti sdto4 (internal state) power-down normal o per ation 21m s(ma x) normal data (n o clock) external clocks (output port) pdn power-down don?t care don?t care don?t care ?0? data internal circuit power-up time input clocks input d ata output clocks ?0? data (don?t care) (do n? t c are) ilrck1- 4 inpu t wa it (2) sdto3 normal data ?0? data ?0? data sdto2 normal data ?0? data ?0? data sdto1 normal data ?0? data ?0? data unlock
[ak4128a] ms1242-e-00 2010/09 - 35 - internal reset function for clock change clock change timing is shown in figure 36 and figure 37 . sdto is identified as sdto1, sdto2, sdto3 and sdto4. when changing the clock, the ak4128a should be reset by the pdn pin in parallel control m ode and it should be reset by the pdn pin or rstn bit in serial control mode ( figure 36 ). sdto means sdto1-4 in this figure. (3) power-down external clock s (input port or output port) clocks 1 sdto (internal state) normal operation normal operation clocks 2 don?t care max 23ms smute (note32, recommended) 1024/fso att.level 0db - db normal data normal data 1024/fso pdn pin note 31 note 31. the data on sdto may cause a clicking noise. to preven t this, set ?0? to the sdti more than 1024/fs (gd) before the pdn pin changes to ?l?. it makes the data on sdto remain as ?0?. note 32. smute can also remove the clicking noise ( note 31 ). note 33. (3) is the total time of ?internal circuit power-up + fso/fsi ratio detection + internal circuit group delay?. figure 36. clock change sequence in parallel control mode (spb pin = ?l?) note 34. the data on sdto may cause a clicking noise. to prevent this, set ?0? to the sdti from gd before the pdn pin changes to ?l?. it makes the data on sdto remain as ?0?. note 35. smute can also remove the unknown data at note 26 note 36. the digital block except serial control interface and registers is power ed-down. the internal oscillator and regulator are not powered-down. note 37. (4) is the total time of ?0.5/fsi+8/fsi(o)+156/fso? or ?1.5/fsi+8/fsi(o)+156/fso?. (fsi(o) is lower frequency between fsi and fso). figure 37. clock change sequence in serial control mode (spb pin = ?h?) reset (note 28) external clocks (input port or output port) clocks 1 sdto (internal state) normal operation normal operation clocks 2 d on?t care smute (note35,recommended) 1024/fso att.level 0db - db normal data normal data 1024/fso rstn bit note 34 (4 )
[ak4128a] ms1242-e-00 2010/09 - 36 - 1. when the frequency of ilrckx (x=1, 2, 3, 4) at input port is changed without a reset by the pdn pin or rstn bit. when the difference of internal oscillator (min. 59.4 mhz, typ. 73.5 mhz) clock number in one ilrckx cycle between before an ilrckx frequency change (fso/fsi ratio is stabilized) and after the change is more than 100 for 8cycles, an internal reset is made automatically and sampling frequency ratio detection is executed again. sdtox outputs ?l? when the internal reset is made, and src data is output after ?0.5/fsi+8/fsi(o)+156/fso or 1.5/fsi+8/fsi(o)+156/fso? (fsi(o) is lower frequency between fsi and fso). if the difference of internal oscillator clock number in one ilrckx cycle between before an ilrckx frequency change and after the change is less than 100 or more than 100 but shorter than 8cycles, the internal reset is not executed. in both cases; when ilrckx frequency is changed immediately without transiti on time or with transition time which is not long enough for an internal reset, it takes 5148/fso (max. 643.5ms @fso=8khz) ( note 38 )to output normal src data. distorted data may be output until normal src output. when ilrckx is stopped, an internal reset is executed automatically. it takes ?0.5/fsi+8/fsi(o)+156/fso or 1.5/fsi+8/fsi(o)+156/fso? (fsi(o) is lower frequency be tween fsi and fso) [s] to output normal src data after ilrckx is input again. 2. when the frequency of olrck at output port is changed without a reset by the pdn pin or rstn bit. when the difference of internal oscillator clock number in one olrck cycle between before an olrck frequency change (fso/fsi ratio is stabilized) and after the change is more than 100 for 8cycles, an internal reset is made automatically and sampling frequency ratio detection is ex ecuted again. sdtox (x=1, 2, 3, 4)outputs ?l? when the internal reset is made, and src data is output afte r ?0.5/fsi+8/fsi(o)+156/fso or 1.5/fsi+8/fsi(o)+156/fso? (fsi(o) is lower frequency between fsi and fso). if the difference of internal oscillator clock number in one olrck cycle between before an olrck frequency change and after the change is less than 100 or more than 100 but shorter than 8cycles, the internal reset is not executed. it takes 5148/fso (max. 643.5ms @fso=8khz) ( note 38 ) to output normal src data. distorted data may be output until normal src output. when olrck is stopped, an internal reset is executed automatically. it takes ?0.5/fsi+8/fsi(o)+156/fso or 1.5/fsi+8/fsi(o)+156/fso? (fsi(o) is lower frequency be tween fsi and fso) [s] to output normal src data after ilrckx is input again. note 38. when fso=8khz and fso/fsi ratio is changed from 1/6 to 1/5.99. it is 160.9ms when fso=32khz and fso/fsi ratio is changed from 1/6 to 1/5.99.
[ak4128a] ms1242-e-00 2010/09 - 37 - internal status pin the unlock pin indicates internal status of the device. this pin outputs ?h? when the pdn pin = ?l?. src data is output from sdto1-4 pins, which corresponds to the each sampling frequency ratio detected src, after a rising edge ? ? of pdn if the internal regulator is in normal operation. in 8-ch annel mode, the unlock pin outputs ?l? when sampling frequency ratio detection is completed at all src?s (src1-4). the unlock pin keeps outputting ?h? if there is one src which does not finished sampling frequency ratio detection. in 6-channel mode, the unlock pin outputs ?l? when sampli ng frequency ratio detection is completed at src1-3. it keeps outputting ?h? if there is one src which does not finish sampling frequency ratio detection. in 4-channel mode, the unlock pin outputs ?l? when sampli ng frequency ratio detection is completed at src1-2. it keeps outputting ?h? if there is one src which doe s not finish sampling frequency ratio detection. when over-current/voltage is flowed at the internal regulator, the unlcok pin outputs ?h?. an or?ed result of the flags between over-current/voltage detection at the internal regul ator and src sampling frequency detection complete is output from this pin. figure 38. internal flags and unlock pin output in parallel control mode, if the ak4128a is set in src bypass mode by cm2-0 pins during the pdn pin = ?l? and powered-up, the unlock pin outputs ?l? after the power-up time of the internal regulator (max. 1.4ms) from a rising edge ? ? of the pdn pin. in serial control mode, if byps bit is set to ?1?while rstn bit = ?0?, the unlock pin immediately outputs ?l? afte r the register writing. over-current/voltage limit flag (?l? normal, ?h? over-current/voltage detect) src sampling frequency ratio complete flag unlock pin
[ak4128a] ms1242-e-00 2010/09 - 38 - serial control interface the ak4128a supports fast-mode i 2 c-bus system (max: 400khz). pull-up resistors at sda and scl pins should be connected to (dvdd1-4 + 0.3)v or less voltage. 1. data transfer all commands are preceded by a start condition. after th e start condition, a slave address is sent. after the ak4128a recognizes the start condition, the device interfaced to the bus waits of the slave address to be transmitted over the sda line. if the transmitted slave address matches an address for one of the devices, the designated slave device pulls the sda line to low (acknowledge). the data transfer is always terminat ed by a stop condition generated by the master device. 1-1. data validity the data on the sda line must be stable during a high period of the clock. the high or low state of the data line can only be changed when the clock signal on the scl line is low except for the start and the stop condition. scl sda data line stable : data valid change of data a llowed figure 39. data transfer 1-2. start and stop condition a high to low transition on the sda line while scl is high indicates a start condition. all sequences start from the start condition. a low to high transition on the sda line while scl is high defines a stop condition. all sequences end by the stop condition. s scl sda stop condition start condition figure 40. start and stop conditions
[ak4128a] ms1242-e-00 2010/09 - 39 - 1-3. acknowledge acknowledge is a software convention used to indicate successful data transfer s. the transmitter will release the sda line (high) after transmitting eight bits . the receiver must pull down the sda lin e during the acknowledge clock pulse so that that it remains stable ?l? during ?h? period of this clock pulse. the ak4128a genera tes an acknowledge after each byte is received. in read mode, the slave, the ak4128a transmits eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue transmitting data. if an acknowledge is not de tected, the slave will terminate further data transmissions and await the stop condition. scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge figure 41. acknowledge on the i 2 c-bus 1-4. first byte the first byte, which includes seven bits of slave address and one bit of r/w bit, is sent after a start condition. if the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the sda line. the first six bits of the slave address are fixed as ?001001?. the next (seventh) bit is cad0 (device address bits). it is ?0? when the cad0 pin = ?l?, and ?1? when the cad pin = ?h?. this bit identifie s the specific device on the bus. when the slave address is input, the matched device generates an acknowledge and executes a command. the eighth bit (r/w bit) of the first byte defines whether the master requests a write or r ead condition. a ?1? indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. 0 0 1 0 0 1 cad0 r/w figure 42. the first byte
[ak4128a] ms1242-e-00 2010/09 - 40 - 2. write operations set r/w bit = ?0? for the write operation of the ak4128a. after receipt of a start condition and th e first byte, the ak4128a generates an acknowledge, and awaits the second byte (register address). the second byte consists of the address fo r control registers of ak4128a. the format is msb first, and first 6bits must be fixed to ?0?. 0 0 0 0 0 0 a1 a0 (*: don?t care) figure 43. the second byte after receipt the second byte, the ak4128a generates an acknowledge, and awaits the third byte. those data after the second byte contain control data. the format is msb first, 8bits. d7 d6 d5 d4 d3 d2 d1 d0 figure 44. byte structure after the second byte the ak4128a is capable of more than one byte write operation by one sequence. after receipt of the third byte, the ak4128a generates an ac knowledge, and awaits the next data again. the master can transmit more than one word inst ead of terminating the write cycle after the firs t data word is transferred. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 03h prior to generating a stop condition, th e address counter will ?roll over? to 00h and the previous data will be overwritten. sd a s t a r t a c k a c k s slave a ddr ess a c k re gister a ddr ess(n) data(n) p s t o p data(n+x) a c k da ta( n+ 1) figure 45. write operation
[ak4128a] ms1242-e-00 2010/09 - 41 - 3. read operations set r/w bit = ?1? for the read operation of the ak4128a. after transmission of the data, the master can read next addr ess?s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatica lly. if the address exceeds 03h prior to generating a stop condition, the address counter will ?roll over? to 00h and th e previous data will be overwritten. the ak4128a supports two basic read operati ons: current address read and random read. 3-1. current address read the ak4128a contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address ?n?, the next current read operation would access data from the address ?n+1?. after receipt of the slave address with r/w bit set to ?1?, the ak4128a genera tes an acknowledge, transmits 1byte data which address is set by the internal address counter and increm ents the internal address counter by 1. if the master does not generate an acknowledge but gene rate the stop condition, the ak 4128a discontinues transmission. sd a s t a r t a c k a c k s slave a ddr ess a c k data(n) data(n+1) p s t o p data(n+x) a c k da ta( n+ 2) figure 46. current address read 3-2. random read random read operation allows the master to access any memory location at random. prior to i ssuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start condition, slav e address (r/w=?0?) and then the register address to read. after the register address?s acknowledge, the master immediat ely reissues the start condition and the slave address with the r/w bit set to ?1?. then the ak4128a generates an acknowledge, 1byte data a nd increments the internal address counter by one. if the master does not generate an acknowle dge but generate the stop condition, the ak4128a discontinues transmission. sd a s t a r t a c k a c k s s s t a r t slave a ddress wo rd a ddress( n) slave a ddress a c k da ta( n) a c k p s t o p data(n+x) a c k data(n+1) figure 47. random read
[ak4128a] ms1242-e-00 2010/09 - 42 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h reset & mute smute4 smu te3 smute2 smute1 0 byps 0 rstn 01h de-emphasis dem41 dem40 dem31 dem30 dem21 dem20 dem11 dem10 02h input audio data format 1 0 idif22 idif21 idif20 0 idif12 idif11 idif10 03h input audio data format 2 0 idif42 idif41 idif40 0 idif32 idif31 idif30 note 39. all register values are initialized by the pdn pin = ?l?. note 40. writing to the address 00h ~ 03h are inhabited. the addresses defined as 0 must contain ?0? data. byps bit and idif12-10, 22-20, 32-30, 42-40 bits should be written when rstn bit = ?0?. note 41. i 2 c access becomes valid after 1.4ms (max) from pdn pin ? ?. register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h reset & mute smute4 smute3 smute2 smute1 0 byps 0 rstn r/w r/w r/w r/w r/w rd r/w rd r/w default 0 0 0 0 0 0 0 1 rstn: digital reset control 0: reset 1: reset release (default) when this bit is set to ?0?, some digital blocks of the ak4128a are powered-down. in this case src1-4 can not operate. control re gister settings are not initialized becau se i2c serial control interface and control register blocks are not powered-down. control register writings are available. the internal oscillator for the clocks, the regulator and the reference voltage generation circuit are not powered-down. byps: bypass mode control 0: src mode (default) 1: src bypass mode refer to table 3 . smute1: src1 soft mute control 0: soft mute release (default) 1: soft mute in serial control mode (spb pin= ?h?), the smute pin setting is ignored. src1 reflects the smute1 bit setting. smute2: src2 soft mute control 0: soft mute release (default) 1: soft mute in serial control mode (spb pin= ?h?), the smute pin setting is ignored. src2 reflects the smute2 bit setting. smute3: src3 soft mute control 0: soft mute release (default) 1: soft mute in serial control mode (spb pin= ?h?), the smute pin setting is ignored. src3 reflects the smute3 bit setting.
[ak4128a] ms1242-e-00 2010/09 - 43 - smute4: src4 soft mute control 0: soft mute release (default) 1: soft mute in serial control mode (spb pin= ?h?), the smute pin setting is ignored. src4 reflects the smute4 bit setting. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h de-emphasis dem41 dem40 dem31 dem30 dem21 dem20 dem11 dem10 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 0 1 0 1 0 1 dem11/10: src1 de-emphasis control default: ?01? de-emphasis=off dem21/20: src2 de-emphasis control default: ?01? de-emphasis=off dem31/30: src3 de-emphasis control default: ?01? de-emphasis=off dem41/40: src4 de-emphasis control default: ?01? de-emphasis=off in serial control mode (spb pin= ?h?), the setting of dem1-0 pins is ignored. the dem[11:10] bits setting is reflected to src1, the dem[21:20] bits setting is reflected to src2, the dem[31:30] bits setting is reflected to src3, and the dem[41:40] bits setting is reflected to src4. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h input audio data format 1 0 idif22 idif21 idif20 0 idif12 idif11 idif10 r/w rd r/w r/w r/w rd r/w r/w r/w default 0 0 0 0 0 0 0 0 addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h input audio data format 2 0 idif42 idif41 idif40 0 idif32 idif31 idif30 r/w rd r/w r/w r/w rd r/w r/w r/w default 0 0 0 0 0 0 0 0 idif12/11/10: src1 audio data interface mode sel ect for input ports default: ?000? mode 0 (refer table 2 ) idif22/21/20: src2 audio data inte rface mode select for input ports default: ?000? mode 0 (refer table 2 ) idif32/31/30: src3 audio data inte rface mode select for input ports default: ?000? mode 0 (refer table 2 ) idif42/41/40: src4 audio data inte rface mode select for input ports default: ?000? mode 0 (refer table 2 ) in serial control mode (spb pin = ?h ?), the setting of idif2-0 pins is i gnored. the idif[12:10] bits setting is reflected to src1, the idif[22:20] bits setting is reflected to src2, the idif[32:30] bits setting is reflected to src3, and the idif[42:40] bits setting is reflected to src4.
[ak4128a] ms1242-e-00 2010/09 - 44 - system design figure 48 and figure 49 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. ? parallel control mode (spb pin = ?l?). ? synchronous mode (inas pin = ?l?). ? omclk/xti input = x?tal mode ? input port: slave mode, ibick1 lock mode (64fsi), 24 bit msb justified ? output port: slave mode, 24 bit msb justified ? dither = off, dem=off, pm2/1 pin= ?h/l? (8ch mode) c1= 0.1 f c2=10 f c3=1 f 30% ibick2 1 2 3 4 5 6 7 8 9 10 11 imclk ilrck1 ibick1 dvdd1 vss2 sdti4 sdti1 sdti2 sdti3 idif0 top view ilrck2 64 63 62 tst3 vss1 61 60 58 57 59 55 54 56 53 vd18 avdd spb sda scl tst2 smsemi tst1 vss5 12 idif1 13 idif2 14 ilrck3 15 ibick3 16 ilrck4 52 dvdd4 51 cad0 50 tst0 49 mcko ibick4 17 inas 18 unlock 19 dvdd2 20 vss3 21 smute 22 dither 23 pdn 24 smt0 25 smt1 26 dem0 27 dem1 28 pm1 29 obit0 30 obit1 31 pm2 32 44 43 42 41 40 39 38 37 36 35 34 33 dvdd3 vss4 sdto4 sdto1 sdto2 sdto3 odif0 odif1 cm0 cm1 cm2 tdm 45 obick 46 olrck 47 xti/omclk 48 xto dsp1 up 3.3v c2 c1 c1 c1 + + dsp2 c1 c1 c2 + c2 fsi 64fsi fso 64fso c3 + cc notes: - all digital input pins should be not left floating. - vss1 -5 must be connected to the same ground plane. - dvdd1-4 pins must be connected to the same power supply. - connect a 1 f ( 30%; including temperature characteristics) capacitor between the vd18 pin and dvss. when this capacitor is polarized, th e positive polarity pin should be connected to the vd18 pin. - refer to table 5 for the equivalent series resistance r1 and capacitance c values of the x?tal oscillator. figure 48. typical connection diagram (parallel control mode)
[ak4128a] ms1242-e-00 2010/09 - 45 - ? serial control mode (spb pin = ?h?). ? asynchronous inputs mode (inas pin = ?h?). ? omclk/xti input= 256fso, x?tal ? input port: slave mode, ibick1~4 lock mode (64fsi) input audio interface format can be set by registers. ? output port: master mode, 24 bit msb justified. ? dither = off, de-emphasis filter can be set by registers. pm2/1 pin= ?h/l? (8ch mode) c1= 0.1 f c2=10 f c3=1 f 30% notes: - all digital input pins should be not left floating. - vss1 -5 must be connected to the same ground plane. - dvdd1-4 pins must be connected to the same power supply. - connect a 1 f ( 30%; including temperature characteristics) capacitor between the vd18 pin and dvss. when this capacitor is polarized, th e positive polarity pin should be connected to the vd18 pin. - refer to table 5 for the equivalent series resistance r1 and capacitance c values of the x?tal oscillator. figure 49. typical connection diagram (serial control mode) ibick2 1 2 3 4 5 6 7 8 9 10 11 imclk ilrck1 ibick1 dvdd1 vss2 sdti4 sdti1 sdti2 sdti3 idif0 top view ilrck2 64 63 62 tst3 vss1 61 60 58 57 59 55 54 56 53 vd18 avdd spb sda scl tst2 smsemi tst1 vss5 12 idif1 13 idif2 14 ilrck3 15 ibick3 16 ilrck4 52 dvdd4 51 cad0 50 tst0 49 mcko ibick4 17 inas 18 unlock 19 dvdd2 20 vss3 21 smute 22 dither 23 pdn 24 smt0 25 smt1 26 dem0 27 dem1 28 pm1 29 obit0 30 obit1 31 pm2 32 44 43 42 41 40 39 38 37 36 35 34 33 dvdd3 vss4 sdto4 sdto1 sdto2 sdto3 odif0 odif1 cm0 cm1 cm2 tdm 45 obick 46 olrck 47 xti/omclk 48 xto dsp1 up 3.3v c2 c1 c1 c1 + + dsp5 c1 c1 c2 + c2 fsi 64fsi fso 64fso dsp2 dsp3 dsp4 c3 + cc
[ak4128a] ms1242-e-00 2010/09 - 46 - 1. grounding and power supply decoupling the ak4128a requires careful attention to power suppl y and grounding arrangements. alternatively if avdd and dvdd1-4 are supplied separately, th e power up sequence is not critical . vss1-5 must be connected to the same ground plane. decoupling capacitors should be as near to the ak4128a as possible, with the small value ceramic capacitor being the nearest. 2. jitter tolerance figure 50 shows the jitter tolerance to ilrck1-4 and ibick. the jitter quantity is defined by the jitter frequency and the jitter amplitude shown in figure 50 . when the jitter amplitude is 0.02ui pp or less, the ak4128a operates normally regardless of the jitter frequency. figure 50. jitter tolerance (1) normal operation (2) there is a possibility that the output data is lost. note ? y axis is the jitter amplitude of ilrck1-4 just before thd+n degradation starts. 1ui (unit interval) is one cycle of ibick. when fsi = 48khz, 1[uipp]=1/48khz=20.8 s a
[ak4128a] ms1242-e-00 2010/09 - 47 - 3. digital filter response example table 15 shows the examples of digital filte r response performed by the ak4128a. ratio fso/fsi [khz] passband [khz] stopband [khz] stopband attenuation [db] gain [db] 4.000 192/48.0 22.000 26.000 ? 121.2 ? 0.01@ 20k 1.000 48.0/48.0 22.000 26.000 ? 121.2 ? 0.01@ 20k 0.919 44.1/48.0 20.000 24.100 ? 121.4 ? 0.01@ 20k 0.725 32.0/44.1 14.088 17.487 ? 115.3 ? 0.01@ 14.5k 0.667 32.0/48.0 13.688 17.488 ? 116.9 ? 0.19@ 14.5k 0.544 48.0/88.2 19.250 26.232 ? 114.6 ? 0.03@ 20k 0.500 48.0/96.0 20.900 27.000 ? 100.2 ? 0.01@ 20k 0.500 44.1/88.2 19.202 24.806 ? 100.2 ? 0.08@ 20k 0.459 44.1/96.0 18.700 25.000 ? 103.3 ? 0.23@ 20k 0.363 32.0/88.2 12.863 18.665 ? 102.0 ? 0.75@ 14.5k 0.333 32.0/96.0 12.500 18.900 ? 103.6 ? 1.07@ 14.5k 0.250 48.0/192.0 17.600 30.200 ? 104.0 ? 0.18@ 20k 0.250 44.1/176.4 16.170 27.746 ? 104.0 ? 1.34@ 20k 0.230 44.1/192.0 15.860 28.240 ? 103.3 ? 1.40@ 20k 0.167 32.0/192.0 11.200 19.600 ? 73.2 ? 2.97@ 14.5k 0.181 32.0/176.4 10.278 17.987 ? 73.2 ? 7.88@ 14.5k 0.167 8/48.0 2.800 4.900 ? 73.2 ? 2.97@ 3.625k 0.181 8/44.1 2.5695 4.4968 ? 73.2 ? 7.88@ 3.625k table 15. digital filter example 4. i 2 c bus connection scl and sda pins should be connected to dvdd1-4 through the resistor based on i 2 c standard. as there is a protection between each pin and dvdd1-4, the pulled up voltage must be dvdd1-4 or lower ( figure 51 ). vss2-5 dvdd1-4 ak4128a +3.3v s da pin figure 51. sda pin output
[ak4128a] ms1242-e-00 2010/09 - 48 - package 12.0 10.0 32 33 48 49 64 1 16 17 0.2 0.1 0.10 m 0.5 12.0 0.10 0.50 0.25 0 ~10 max 1.85 1.40 0.00~0.25 0.09~0.25 64pin lqfp(unit: mm) material & lead finish package molding compound: epoxy, halogen (bromine and chlorine) free lead frame material: cu lead frame surface treatme nt: solder (pb free) plate
[ak4128a] ms1242-e-00 2010/09 - 49 - marking (AK4128AEQ) 1 akm AK4128AEQ xxxxxxx xxxxxxx: date code identifier marking (ak4128avq) 1 akm ak4128avq xxxxxxx xxxxxxx: date code identifier
[ak4128a] ms1242-e-00 2010/09 - 50 - date (yy/mm/dd) revision reason page contents 10/09/13 00 first edition important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. revision history

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