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eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 general description the austin semiconductor, inc. as8e128k32 is a 4 megabit eeprom module organized as 128k x 32 bit. user configurable to 256k x16 or 512kx 8. the module achieves high speed access, low power consumption and high reliability by employing advanced cmos memory technology. the military grade product is manufactured in compliance to the smd and mil-std 883, making the as8e128k32 ideally suited for military or space applications. the module is offered in a 1.075 inch square ceramic pin grid array substrate. this package design provides the optimum space saving solution for boards that accept through hole packaging. the module is also offered as a 68 lead 0.990 inch square ceramic quad flat pack. it has a max. height of 0.200 inch. this package design is targeted for those applications which require low profile smt packaging. features ? access times of 120, 140, 150, 200, 250, and 300 ns ? built in decoupling caps for low noise operation ? organized as 128k x32; user configurable as 256k x16 or 512k x8 ? operation with single 5 volt supply ? low power cmos ? ttl compatible inputs and outputs ? operating temperature ranges: military: -55 o c to +125 o c industrial: -40 o c to +85 o c options markings ? timing 120 ns -120 140 ns -140 150 ns -150 200 ns -200 250 ns -250 300 ns -300 ? package ceramic quad flat pack q no. 703 pin grid array- 8 series p no. 904 pin grid array- 8 series pn no. 904 available as military specifications ? smd 5962-94585 ? mil-std-883 pin assignment (top view) 66 lead pga (pins 8, 21, 28, 39 are no connects on the pn package) 68 lead cqfp 66 lead pga (pins 8, 21, 28, 39 are grounds on the p package) 128k x 32 eeprom eeprom memory array for more products and information please visit our web site at www.austinsemiconductor.com 3 4
eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 of the last byte written will result in the complement of the written data to be presented on i/o7. once the write cycle has been com- pleted, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at anytime during the write cycle. toggle bit in addition to data polling the module provides another method for determining the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 of the accessed die toggling between one and zero. once the write has completed, i/o6 will stop toggling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. data protection if precautions are not taken, inadvertent writes may occur during transitions of the host power supply. the e 2 module has incorpo- rated both hardware and software features that will protect the memory against inadvertent writes. hardware protection hardware features protect against inadvertent writes to the mod- ule in the following ways: (a) vcc sense - if vcc is below 3.8 v (typical) the write function is inhibited; (b) vcc power-on delay - once vcc has reached 3.8 v the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit - holding any one of oe\ low, ce\ high or we\ high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the we\ or ce\ inputs will not initiate a write cycle. software data protection a software controlled data protection feature has been imple- mented on the memory module. when enabled, the software data protection (sdp), will prevent inadvertent writes. the sdp feature may be enabled or disabled by the user and is shipped with sdp disabled, sdp is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to software data protection algorithm). after writing the three byte command sequence and after t wc the entire module will be protected from inadvertent write operations. it should be noted, that once protected the host may still perform a byte of page write to the module. this is done by preceding the data to be written by the same three byte command sequence used to enable sdp. once set, sdp will remain active unless the disable command sequence is issued. power transitions do not disable sdp and sdp will protect the 128k x 32 eeprom during power-up and power-down condi- tions. all command sequences must conform to the page write timing specifications. the data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. after setting sdp, any attempt to write to the device without the three byte command sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , read operations will effectively be polling operations. device identification an extra 128 bytes of eeprom memory is available on each die for user identification. by raising a9 to 12v + 0.5v and using address locations 1ff80h to 1ffffh the bytes may be written to or read from in the same manner as the regular memory array. device operation the 128k x 32 eeprom memory solution is an electrically erasable and programmable memory module that is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 128-byte-page register to allow writing of up to 128 bytes of data simultaneously. during a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected a new access for a read or write can begin. read the memory module is accessed like a static ram. when ce\ and oe\ are low and we\ is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the module can be read as a 32 bit, 16 bit or 8 bit device. the outputs are put in the high impedance state when either ce\ or oe\ is high. this dual-line control gives designers flexibility in preventing bus contention in their system. byte write a low pulse on the we\ or ce\ input with ce\ or we\ low (respectively) and oe\ high initiates a write cycle. the address is latched on the falling edge of ce\ or we\, whichever occurs last. the data is latched by the first rising edge of ce\ or we\. once a bwdw (byte, word or double word) write has been started it will automati- cally time itself to completion. page write the page write operation of the 128k x 32 eeprom allows 1 to 128 bwdws of data to be written into the device during a single internal programming period. each new bwdw must be written within 150- m sec (t blc ) of the previous bwdw. if the t blc limit is exceeded the memory module will cease accepting data and commence the internal programming operation. for each we high to low transi- tion during the page write operation, a7-a16 must be the same. the a0-a6 inputs are used to specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are speci- fied for writing will be written; unnecessary cycling of other bytes within the page does not occur. data polling this memory module features data polling to indicate the end of a write cycle. during a byte or page write cycle an attempted read
eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. **junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity (plas- tics). absolute maximum ratings* voltage on vcc supply relative to vss vcc ..............................................................................-.5v to +7.0v storage temperature ....................... ....................-65 c to +150 c short circuit output current (per i/o).............................20ma voltage on any pin relative to vss.....................-.5v to vcc+1 v max junction temperature**.............................................+150 c thermal resistance junction to case ( q jc ): package type q...............................................11.3 c/w package type p & pn.......................................2.8 c/w electrical characteristics and recommended dc operating conditions (-55 o c
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eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 ac test conditions test specifications input pulse levels...........................................v ss to 3v input rise and fall times...........................................5ns input timing reference levels.................................1.5v output reference levels.........................................1.5v output load................................................see figure 1 oh ol i i current source current source vz = 1.5v (bipolar supply) device under test ceff = 50pf -+ + notes: vz is programmable from -2v to + 7v. i ol and i oh programmable from 0 to 16 ma. vz is typically the midpoint of v oh and v ol . i ol and i oh are adjusted to simulate a typical resistive load circuit. truth table mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z note: 1. this parameter is guaranteed but not tested. capacitance table 1 (v in = 0v, f = 1 mhz, t a = 25 o c) symbol parameter max units c add a0 - a16 capacitance 40 pf c oe oe\ capacitance 40 pf c we, c ce we\ and ce\ capacitance 10 pf c io i/o 0- i/o 31 capacitance 12 pf figure 1 notes: 1. x can be v il or v ih 2. refer to ac programming waveforms
eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 ac read waveforms (1,2,3) notes : 1. ce\ may be delayed to t acc -t ce after the address transition without impact on t acc . 2. oe\ may be delayed to t ce -t oe after the falling edge of ce\ without impact on t ce or by t acc -t oe after an address change without inpact on t acc . 3. t df is specified from oe\ or ce\ whichever occurs first (c l = 5pf). electrical characteristics and recommended ac operating conditions (-55 o c < t a < +125 o c or -40 o c to +85 o c; vcc = 5v +10%) min max min max min max min max min max min max address to output delay t acc 120 140 150 200 250 300 ns ce\ to output delay t ce 120 140 150 200 250 300 ns oe\ to output delay t oe 0 50 0 55 0 55 0 55 0 55 0 55 ns ce\ or oe\ to output float t df 55 55 55 55 55 55 ns output hold from oe\, ce\ or address, whichever comes first t oh 0 0 0 0 0 0 ns units 200 250 300 description 140 120 150 symbol tacc toh toe tdf tce trc trc output valid address valid address ce/ oe\ dq t ce t oe t acc t oh t df
eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 write cycle no 1. (chip enable controlled) write cycle no 2. (write enable controlled) electrical characteristics and recommended ac write characteristics (-55 o c < t a < +125 o c; vcc = 5v +10%) symbol parameter min max units t wc write cyce time 10 ms t as address set-up time 4 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 10 ns t wp write pulse width 100 ns t blc byte load cycle time 150 m s t wph write pulse width high 50 ns tdh tds twph twph twp twp tch tcs twc tah twc tas toeh toes data valid address valid oe\ address we\ ce\ dq t oes t as t cs t wp t ds t dh t wph t ch t oeh t wc t ah tdh tds twph twph twp twp tch tcs tah tas toeh toes data valid oe\ address ce\ we\ dq t oes t as t cs t wp t ah t ds t dh t wph t ch t oeh
eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 page mode write waveforms (1,2) notes: 1. a7 through a16 must specify the page address during each high to low transition of we\ (or ce\). 2. oe\ must be high only when we\ and ce\ are both low. 3. vd - valid data 4. va - valid address page mode characteristics symbol parameter min max unit t as , t oes address, oe\ set-up time 4 ns t ah address, hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we\ or ce\) 100 ns t ds data set-up time 50 ns t dh , t oeh data, oe\ hold time 10 ns chip erase waveforms t s = 5 msec (min.) t w = th = 10 msec (min.) v h = 12.0v + 0.5v vih vil vh vih vih vil ce\ oe\ we\ t w t s t h twc tdh tds tah tas tblc tblc twph twph twp twp byte 0 byte 1 byte 2 byte 3 byte127 byte 126 va va va va va va vd vd vd vd vd vd vd va vd vd oe ce\ we\ a0 - a16 data t wp t ah t as t ds t dh t wph t blc t wc
eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 software data protection enable algorithm (1) software data protection disable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex) 2. write protect state will be active at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of period even if no other data is loaded. 4. 1 to 128 bytes of data are loaded. load data 55 to address 2aaa writes enabled (2) enter data protect state load data aa to address 5555 load data xx to any address (4) load data a0 to address 5555 load last byte to last address exit data protect state (3) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 20 to address 5555 load data xx to any address (4) load last byte to last address 1. a0-a14 of the selected i/o bytes must conform to the addressing sequence for the first three bytes as shown above. 2. after the command sequence has been issued and a page write operation follows, the page address inputs (a7-a16) of the selec ted i/o bytes must be the same for each high to low transition of we\ (or ce\). 3. oe must be high only when we\ and ce\ are both low. software protected program cycle waveform (1)(2)(3) byte address page address we\ a0-a6 a7-a16 data t wc byte 127 byte 126 byte 0 a0 55 aa t dh t ds 5555 2aaa 5555 t as t ah t blc t wph t wp oe\ ce\
eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 data polling characteristics (1) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. data polling waveforms toggle bit waveforms (1,2,3) notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. toggle bit characteristics (1) we\ ce\ oe\ i/o7 a0 - a16 t oeh t dh t oe t wr high-z an an an an an symbol parameter min max units t dh data hold time 10 ns t oeh oe\ hold time 10 ns t oe oe\ to output delay (2) 100 ns t wr write recovery time 0 ns symbol parameter min max units t dh data hold time 10 ns t oeh oe\ hold time 10 ns t oe oe\ to output delay (2) 100 ns t oeph oe\ high pulse 150 ns i cc write recovery time 0 ns t wr t oehp twr twr toe tdh toeh high z we\ ce\ oe\ i/o 6 t oeh t dh t oe t wr t oehp
eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 asi case #703 (package designator q) smd 5962-94585, case outline m mechanical definitions* *all measurements are in inches. min max a 0.123 0.200 a1 0.000 0.020 b 0.013 0.017 b d d1 0.870 0.890 d2 0.980 1.000 d3 0.936 0.956 e r 0.005 l1 0.035 0.045 symbol 0.010 ref 0.050 bsc smd specifications 0.800 bsc 4 x d2 4 x d1 4 x d b e pin 1 detail a l1 0 o - 7 o r b a1 see detail a a d3
eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 mechanical definitions* *all measurements are in inches. asi case #904 (package designator p & pn) smd 5962-94585, case outline 4 and 5 min max a 0.135 0.181 a1 0.025 0.035 f b 0.016 0.020 f b1 0.045 0.055 f b2 0.065 0.075 d 1.065 1.085 d1/e1 d2 e l 0.132 0.155 0.600 bsc 0.100 bsc symbol 1.000 bsc smd specifications a a1 l f b e f b1 4 x d d1 d2 e1 pin 66 e pin 11 pin 1 (identified by 0.060 square pad) pin 56 66 x f b2
eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c 883c = full military processing -55 o c to +125 o c package notes p = pins 8, 21, 28, and 39 are grounds. pn = pins 8, 21, 28, and 39 are no connects. ordering information device number package type speed ns process as8e128k32 q -120 /* as8e128k32 q -140 /* as8e128k32 q -150 /* as8e128k32 q -200 /* as8e128k32 q -250 /* as8e128k32 q -300 /* device number package type speed ns process as8e128k32 as8e128k32 p pn -120 -120 /* /* as8e128k32 as8e128k32 p pn -140 -140 /* /* as8e128k32 as8e128k32 p pn -150 -150 /* /* as8e128k32 as8e128k32 p pn -200 -200 /* /* as8e128k32 as8e128k32 p pn -250 -250 /* /* as8e128k32 as8e128k32 p pn -300 -300 /* /* example: as8e128k32q-250/xt example: as8e128k32p-200/883c
eeprom as8e128k32 austin semiconductor, inc. as8e128k32 rev. 5.5 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 13 asi to dscc part number cross reference* asi package designator q asi part # smd part # as8e128k32q-120/883c 5962-9458506hma as8e128k32q-120/883c 5962-9458506hmc as8e128k32q-140/883c 5962-9458505hma as8e128k32q-140/883c 5962-9458505hmc as8e128k32q-150/883c 5962-9458504hma as8e128k32q-150/883c 5962-9458504hmc as8e128k32q-200/883c 5962-9458503hma as8e128k32q-200/883c 5962-9458503hmc as8e128k32q-250/883c 5962-9458502hma as8e128k32q-250/883c 5962-9458502hmc as8e128k32q-300/883c 5962-9458501hma as8e128k32q-300/883c 5962-9458501HMC asi package designator p & pn asi part # smd part # as8e128k32p-120/883c 5962-9458506h5a as8e128k32p-120/883c 5962-9458506h5c as8e128k32p-140/883c 5962-9458505h5a as8e128k32p-140/883c 5962-9458505h5c as8e128k32p-150/883c 5962-9458504h5a as8e128k32p-150/883c 5962-9458504h5c as8e128k32p-200/883c 5962-9458503h5a as8e128k32p-200/883c 5962-9458503h5c as8e128k32p-250/883c 5962-9458502h5a as8e128k32p-250/883c 5962-9458502h5c as8e128k32p-300/883c 5962-9458501h5a as8e128k32p-300/883c 5962-9458501h5c as8e128k32pn-120/883c 5962-9458506h4a as8e128k32pn-120/883c 5962-9458506h4c as8e128k32pn-140/883c 5962-9458505h4a as8e128k32pn-140/883c 5962-9458505h4c as8e128k32pn-150/883c 5962-9458504h4a as8e128k32pn-150/883c 5962-9458504h4c as8e128k32pn-200/883c 5962-9458503h4a as8e128k32pn-200/883c 5962-9458503h4c as8e128k32pn-250/883c 5962-9458502h4a as8e128k32pn-250/883c 5962-9458502h4c as8e128k32pn-300/883c 5962-9458501h4a as8e128k32pn-300/883c 5962-9458501h4c * asi part number is for reference only. orders received referencing the smd part number will be processed per the smd.

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