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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
1/23 ? semiconductor msm65512a/65p512a general description the msm65512a is a high-performance 8-bit microcontroller that employs oki original nx-8/ 50 cpu core. with a minimum instruction execution time of 400 ns (10mhz clock), the msm65512a is capable of high-speed processing, and includes 8k bytes of program memory, 256 bytes of data memory, timers and serial ports. also available are the msm65p512a, which replaces the msm65512's built-in program memory with one-time prom, and the msm65x512a, which uses external program memory. features ? operating range operating frequency : 0 to 10 mhz (v dd =4.5 to 5.5 v) 0 to 5 mhz (v dd =2.7 to 5.5 v) operating voltage : 2.7 to 5.5 v operating temperature : C40 to +85 c (operation at +125 c is assured by the other specification.) ? memory space : 64k bytes internal program memory : 8k bytes internal data memory : 256 bytes ? minimum instruction execution time : 400 ns @ 10 mhz ? powerful instruction set : 83 basic instructions 8/16-bit operation instructions bit manipulation instructions compound function instructions ? abundant addressing modes ? multiplication/division operation functions : 8 8 ? 16 16/8 ? 16 ... 8 ? i/o ports input-output port : 4 ports 8 bits ? timers : 8-bit auto-reload timer 2 16-bit auto-reload timer 1 watchdog timer 1 ? counters : time base counter 1 16-bit free-running counter 1 ? capture input : 1 channel ? compare output : 2 channels ? serial ports : shift register 1 serial port with baud rate generator (uart/synchronous) 1 ? external interrupts : 3 ? interrupt sources : 15 ? package 40-pin plastic dip (dip40-p-600-2.54) : (msm65512a- rs, msm65p512a- rs) 44-pin plastic qfp (qfp44-p-910-0.80-2k) : (msm65512a- gs-2k, msm65p512a-xxxgs-2k) 44-pin plastic qfj (plcc) (qfj44-p-s650-1.27): (msm65512a- js, msm65p512a- js) indicates the code number. ? semiconductor msm65512a/65p512a high performance 8-bit microcontroller e2e1011-27-y4 this version: jan. 1998 previous version: nov. 1996
2/23 ? semiconductor msm65512a/65p512a block diagram osc 0 osc 1 reset hstop* v dd gnd osc cont. rom (8k bytes) ext.mem. cont. cpu core inst. dec. t/c ir alu gmar pc ar br psw sp lmar bus cont. i/o port ram (256 bytes) tbc wdt 16-bit timer 16-bit frc cap 1, cmp 2 sio ad0-7* a8-15* rd wr * ale ea t2ck* gate* cap* cmp0* cmp1* txd* rxd* p0 p1 p2 p3 * secondary functions of ports. ** one timer is used for the sio baud rate generator 8 8 8 8 8 8-bit timer 3** t1out* t0ck* 8-bit shift-reg. interrupt cont. sfto* sfti* sftck* int0* int1* int2* mul/div
3/23 ? semiconductor msm65512a/65p512a pin configuration (top view) 40-pin plastic dip 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 gnd p3.0/t2ck p3.1/cap p3.2/cmp0 p3.3/cmp1 p3.4/int2 p3.5/sfto p3.6/sfti p3.7/sftck reset p2.0/rxd p2.1/txd p2.2/int0 p2.3/int1/gate p2.4/t0ck p2.5/ hstop p2.6/ wr p2.7/t1out osc1 osc0 p1.0/a8 v dd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea ale rd p1.7/a15 p1.6/a14 p1.5/a13 p1.4/a12 p1.3/a11 p1.2/a10 p1.1/a9 21 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
4/23 ? semiconductor msm65512a/65p512a pin configuration (top view) (continued) 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 nc p3.5/sfto p3.6/sfti p3.7/sftck reset p2.0/rxd p2.1/txd p2.2/int0 p2.3/int1/gate p2.4/t0ck p2.5/ hstop p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea ale rd p1.7/a15 p1.6/a14 p1.5/a13 nc 44 43 42 41 40 39 38 37 36 35 34 p3.4/int2 p3.3/cmp1 p3.2/cmp0 p3.1/cap p3.0/t2ck v dd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 nc 12 13 14 15 16 17 18 19 20 21 22 p2.6/ wr p2.7/t1out osc1 osc0 gnd *v dd p1.0/a8 p1.1/a9 p1.2/a10 p1.3/a11 p1.4/a12 * no-connection pin for msm65p512a nc: no-connection pin 44-pin plastic qfp
5/23 ? semiconductor msm65512a/65p512a pin configuration (top view) (continued) p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 v dd p3.0/t2ck p3.1/cap p3.2/cmp0 p3.3/cmp1 p3.4/int2 nc p1.4/a12 p1.3/a11 p1.2/a10 p1.1/a9 p1.0/a8 gnd osc0 osc1 p2.7/t1out p2.6/ wr p3.5/sfto p3.6/sfti p3.7/sftck reset p2.0/rxd p2.1/txd p2.2/int0 p2.3/int1/gate p2.4/t0ck p2.5/ hstop p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea ale rd p1.7/a15 p1.6/a14 p1.5/a13 nc nc nc 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 28 27 26 25 24 23 22 21 20 19 18 39 38 37 36 35 34 33 32 31 30 29 nc: no-connection pin 44-pin plastic qfj (plcc)
6/23 ? semiconductor msm65512a/65p512a pin descriptions basic functions function symbol type description power supply v dd +5v power supply gnd 0v digital ground osc0 crystal oscillation input/external clock input osc1 crystal oscillation output i o reset system reset input (program starts from address 0040h); internal pull-up resistor i ea program memory select input pin. "l" level input for external program memory; "h" level input for internal program memory. i rd read strobe signal during external memory access o ale address latch signal during external memory access o port 0 8-bit input-output port during external memory access, becomes address/data bus for address output, instruction fetch or data read/write along with ale, rd and wr pins i/o port 1 8-bit input/output port address bus during external memory access i/o port 2 port 3 8-bit input/output port 2. secondary functions shown in following table are added for ports 2 and 3. i/o oscillation control port
7/23 ? semiconductor msm65512a/65p512a secondary functions symbol type description int0 p2.2 secondary function external interrupt 0 input pin. i int1/gate p2.3 secondary functions external interrupt 1 input pin. also used as input pin for gate signal for timer 0 count enable/disable. i t0ck p2.4 secondary function timer 0 external clock input pin. i hstop p2.5 secondary function hard stop mode input pin; stops system clock oscillation with "l" level input. i wr p2.6 secondary function write strobe signal output pin during external data memory access. o t1out p2.7 secondary function output pin for signal obtained by dividing timer overflow by 2. o sfto p3.5 secondary function shift register data output pin. o sfti p3.6 secondary function shift register data input pin. i sftck p3.7 secondary function shift register synchronizing clock input/output pin. i/o rxd p2.0 secondary functions uart: input pin for serial port receive data. synchronous: input/output pin for serial port transmit/receive data. i/o txd o t2ck p3.0 secondary function timer 2 external clock input pin. i cap p3.1 secondary function capture trigger input pin. i cmp0 p3.2 secondary function compare output channel 0 output pin. o cmp1 p3.3 secondary function compare output channel 1 output pin. o int2 p3.4 secondary function external interrupt 2 input pin i p2.1 secondary functions uart: output pin for serial port transmit data. synchronous: output pin for serial port synchronizing clock.
8/23 ? semiconductor msm65512a/65p512a port circuit configuration type port electrical characteristics (v dd =5v) p0.0/ad0- p0.7/ad7 1 "h" input voltage: ? v ih =2.4v "l" input voltage: ? v il =0.8v "h" output voltage: ? v oh =3.75v ? i oh =C400 m a "l" output voltage: ? v ol =0.4v ? i ol =3.2ma circuit configuration p1.0/a8- p1.7/a15 2 "h" input voltage: ? v ih =2.4v "l" input voltage: ? v il =0.8v "h" output voltage: ? v oh =3.75v ? i oh =C200 m a "l" output voltage: ? v ol =0.4v ? i ol =1.6ma p0d p0 dir data bus external memory control port0 p1d p1 dir data bus external memory control port1 data bus pxd px dir secondary output function (x=2 to 5) px mod portx secondary input function 3 "h" input voltage: ? v ih =2.4v "l" input voltage: ? v il =0.8v p2.6/ wr "h" output voltage: ? v oh =3.75v ? i oh =C400 m a "l" output voltage: ? v ol =0.4v ? i ol =3.2ma excluding p2.6/ wr "h" output voltage: ? v oh =3.75v ? i oh =C200 m a "l" output voltage: ? v ol =0.4v ? i ol =1.6ma p2.0/rxd, p2.1/txd, p2.6/ wr , p2.7/t1out, p3.2/cmp0, p3.3/cmp1, p3.5/sft0, p3.7/sftck
9/23 ? semiconductor msm65512a/65p512a pxd px dir data bus (x=2 to 5) portx secondary input function type port electrical characteristics (v dd =5v) 4 "h" input voltage: ? v ih =2.4v "l" input voltage: ? v il =0.8v "h" output voltage: ? v oh =3.75v ? i oh =C200 m a "l" output voltage: ? v ol =0.4v ? i ol =1.6ma circuit configuration p2.2/int0, p2.3/int1/gate, p2.4/t0ck, p2.5/ hstop , p3.0/t2ck, p3.1/cap, p3.4/int2, p3.6/sfti port circuit configuration (continued)
10/23 ? semiconductor msm65512a/65p512a absolute maximum ratings recommended operating conditions parameter unit supply voltage v dd C0.3 to 7.0 symbol condition rating ta=25c input voltage v i C0.3 to v dd +0.3 output voltage v o C0.3 to v dd +0.3 power dissipation p d 400 ta=25c per package 50 ta=25c per output storage temperature t stg C55 to +150 v mw c *1 this is due to the standard of a crystal oscillator or ceramic resonator. memory maps 100h 80h 40h 30h 20h 10h 0 0ffffh 2000h 100h 80h 40h 20h internal memory local memory space sfr data memory local register set 3 local register set 2 local register set 1 local register set 0 general memory space external memory program memory vector call table area program memory interrupt vector table area vector call table area 0 17fh data memory page 1 page 0 parameter unit supply voltage v dd 2.7 to 5.5 symbol condition range refer to figure 1. memory hold voltage v ddmh 2.0 to 5.5 f osc =0 hz oscillation operating frequency * 1 f osc 1 to 10 refer to figure 1. external clock operating frequency f extclk 0 to 10 refer to figure 1. operating temperature t op C40 to +85 v mhz mhz c
11/23 ? semiconductor msm65512a/65p512a figure 1. operating frequency vs. power supply voltage 2 5 4 6 8 10 23456 1 2.7 5.5 ta=C40 to +85c f osc , f extclk (mhz) * oscillates at 1mhz or more. v dd (v)
12/23 ? semiconductor msm65512a/65p512a electrical characteristics dc characteristics 1 (v dd =4.5 to 5.5v) (gnd=0v, ta=C40 to +85c) parameter symbol condition min. typ. max. unit "h" input voltage 1 *1 v ih1 2.4 v dd +0.3 "h" input voltage 2 *2 v ih2 0.7v dd v dd +0.3 "l" input voltage v il C0.3 0.8 "h" output voltage 1 *3 v oh1 i oh =C200 m a 0.75v dd "h" output voltage 2 *4 v oh2 i oh =C400 m a 0.75v dd "l" output voltage 1 *3 v ol1 i ol =1.6ma 0.4 "l" output voltage 2 *4 v ol2 i ol =3.2ma 0.4 input leakage current 1 *5 i li1 v i =v dd /0v 1 input leakage current 2 *6 i li2 v i =v dd /0v 10 "l" input current *7 i il v i =0v C40 C200 C400 input capacitance c i f=1mhz, ta=25c 5 current consumption i dds 5v, stop mode *8 50 10mhz, 5v, no load *9 v m a pf m a 20 40 i dds ma *1 excluding osc0 and reset *2 osc0 and reset *3 excluding p0, ale, rd , p2.6/ wr *4 p0, ale, rd , p2.6/ wr *5 ea *6 excluding reset , ea *7 reset *8 the ports configured as inputs should be coupled to v dd or 0v. other ports should not be loaded. *9 refer to figure 2.
13/23 ? semiconductor msm65512a/65p512a dc characteristics 2 (2.7 v dd < 4.5v) *1 excluding osc0 and reset *2 osc0 and reset *3 excluding p0, ale, rd , p2.6/ wr *4 p0, ale, rd , p2.6/ wr *5 ea *6 excluding reset , ea *7 reset *8 the ports configured as inputs should be coupled to v dd or 0v. other ports should not be loaded. *9 refer to figure 2. (gnd=0v, ta=C40 to +85c) parameter symbol condition min. typ. max. unit "h" input voltage 1 *1 v ih1 0.5v dd +0.2 v dd +0.3 "h" input voltage 2 *2 v ih2 0.6v dd +0.4 v dd +0.3 "l" input voltage v il C0.3 0.15v dd +0.1 "h" output voltage 1 *3 v oh1 i oh =C10 m a 0.75v dd "h" output voltage 2 *4 v oh2 i oh =C20 m a 0.75v dd "l" output voltage 1 *3 v ol1 i ol =10 m a 0.1 "l" output voltage 2 *4 v ol2 i ol =20 m a 0.1 input leakage current 1 *5 i li1 v i =v dd /0v 1 input leakage current 2 *6 i li2 v i =v dd /0v 10 "l" input current *7 i il v dd =2.7 to 3.3v, v i =0v C40 C120 C240 input capacitance c i f=1mhz, ta=25c 5 current consumption i dds 3v, stop mode *8 25 i dd 5mhz, 3v, no load *9 6 15 v m a pf m a ma
14/23 ? semiconductor msm65512a/65p512a 10 20 30 40 50 i dd (ma) 23456 v dd (v) 10 20 30 40 50 i dd (ma) 23456 v dd (v) 10 20 30 40 50 i dd (ma) 23456 v dd (v) 10mhz max. typ. max. typ. max. typ. 6mhz 2mhz ta=C40 to +85c , no load figure 2. operating current consumption vs. power supply voltage
15/23 ? semiconductor msm65512a/65p512a ac characteristics ? external memory control (v dd =2.7 to 5.5v, gnd=0v, ta=C40 to +85c) parameter symbol condition min. max. unit clock cycle t c v dd =4.5 to 5.5v 100 "l" clock pulse width t clw v dd =2.7 to 5.5v 45 "h" clock pulse width t chw c l =100pf 45 clock cycle t c 200 "l" clock pulse width t clw 90 "h" clock pulse width t chw 90 ale pulse width t aw t c +t chw C20 ale pulse delay time 1 t ald1 t clw C20 ale pulse delay time 2 t ald2 t clw C20 rd pulse width t rw t c +t chw C40 rd pulse delay time t rd t clw C40 t clw +20 wr pulse width t ww t c +t chw C40 wr pulse delay time t wd t clw C20 t clw +40 "l" address setup time t las t c C40 "h" address setup time t has t c C40 "l" address hold time t lah t clw C20 bus float time t laz 20 "h" address hold time t hahr t c C20 "h" address hold time t hahw t c C20 read data access time t rdaa t c +t clw C15 read data access time t rdar t chw +10 read data hold time t rdh 0 write data setup time t wds t c +t clh C40 write data hold time t wdh t clw C20 ns
16/23 ? semiconductor msm65512a/65p512a osc0 t chw t c t aw t clw t rd t rdar t las t laz t rdaa t has t wd t wds t hahw t rw t ald1 t lah t rdh t hahr t ww t ald2 t wdh address l inst or data in address h address l data out address h ale rd p0 p1 wr p0 p1
17/23 ? semiconductor msm65512a/65p512a ? cpu control *1 excluding power on, stop mode and hard stop mode. *2 during power on, in stop mode and hard stop mode. *3 oscillation stabilization time depends on resonator. (v dd =2.7 to 5.5v, gnd=0v, ta=C40 to +85c) parameter symbol condition min. max. unit reset pulse width * 1 t resw1 20 ns reset pulse width * 2 t resw2 * 3 reset pulse width t resw1 , 2 reset ? peripheral control 1 * t t0clk : timer 0 count clock cycle selected by t0con. (v dd =2.7 to 5.5v, gnd=0v, ta=C40 to +85c) parameter symbol condition min. max. unit clock cycle t c 100 ns external interrupt pulse width t exiw 4 t c external clock pulse width t t0cw 4 t c gate pulse width t t0gw 1 t toclk * osc exi t0 external clock pulse width t t2cw 4 t c t2 cap pulse width t capw 12 t c cap v dd =4.5 to 5.5v 200 v dd =2.7 to 5.5v
18/23 ? semiconductor msm65512a/65p512a 1) exi pulse width 2) t0 3) t2 4) cap osc0 t c t clw t0ck t t0cw gate t t0gw t2ck t t2cw cap t capw int0-2 t exiw
19/23 ? semiconductor msm65512a/65p512a ? peripheral control 2 (v dd =2.7 to 5.5v, gnd=0v, ta=C40 to +85c) parameter symbol condition min. max. unit clock cycle t c 100 ns sftck cycle t sfc 8 t c sftck "l" pulse width t sfclw 4 t c C20 sftck "h" pulse width t sfchw 4 t c C20 osc sft sftck setup time t sfos t sfclw C100 sfto hold time t sfoh t sfchw C100 sfti setup time t sfis 100 sfti hold time t sfih 100 c l =100pf synchronous clock cycle t sic 8 t c synchronous clock "l" pulse width t siclw 4 t c C20 synchronous clock "h" pulse width t sichw 4 t c C20 output data setup time t sios 6 t c C100 output data hold time t sioh 2 t c C100 input data setup time t siis t c +t clw +100 input data hold time t siih 0 sio (clock syn- chro- nous) v dd =4.5 to 5.5v 200 v dd =2.7 to 5.5v
20/23 ? semiconductor msm65512a/65p512a 1) sft 2) sio (clock synchronous mode) t sfclw t sfchw t sfc t sfos t sfoh t sfis t sfih sftck sfto sfti t siclw t sichw t sic t sios t sioh t siis t siih txd rxd (transmission) rxd (reception)
21/23 ? semiconductor msm65512a/65p512a (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). dip40-p-600-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 6.10 typ.
22/23 ? semiconductor msm65512a/65p512a (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.41 typ. qfp44-p-910-0.80-2k mirror finish
23/23 ? semiconductor msm65512a/65p512a (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfj44-p-s650-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin cu alloy solder plating 5 m m or more 2.00 typ. mirror finish

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