_______________general description maxim's redesigned dg401/dg403/dg405 analog switches now feature guaranteed low on-resistance matching between switches (2 ? max) and guaranteed on-resistance flatness over the signal range (3 ? max). these low on-resistance switches (20 ? typ) conduct equally well in either direction and are guaranteed to have low charge injection (15pc max). the new design offers lower off leakage current over temperature (less than 5na at +85?). the dg401/dg403/dg405 are dual, high-speed switches. the single-pole/single-throw dg401 and double-pole/single-throw dg405 are normally open dual switches. the dual, single-pole/double-throw dg403 has two normally open and two normally closed switches. switching times are 150ns max for t on and 100ns max for t off , with a maximum power consump- tion of 35?. these devices operate from a single +10v to +30v supply, or bipolar supplies of ?.5v to ?0v. maxim's improved dg401/dg403/dg405 are fabricated with a 44v silicon-gate process. ________________________applications sample-and-hold circuits test equipment guidance and control systems heads-up displays communications systems pbx, pabx battery-operated systems audio signal routing military radios ______________________new features plug-in upgrade for industry-standard dg401/dg403/dg405 improved r ds(on) match between channels (2 ? max) guaranteed r flat(on) over signal range (3 ? max) improved charge injection (15pc max) improved off leakage current over temperature (<5na at +85?) __________________existing features low r ds(on) (30 ? max) single-supply operation +10v to +30v bipolar-supply operation 4.5v to 20v low power consumption (35 w max) rail-to-rail signal handling capability ttl/cmos-logic compatible ______________ordering information ordering information continued on last page. *contact factory for dice specifications. dg401/dg403/dg405 improved, dual, high-speed analog switches ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 s1 in1 v- gnd n.c. n.c. n.c. d1 top view dg401 v l v+ in2 s2 d2 n.c. n.c. n.c. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 s1 in1 v- gnd s3 d3 n.c. d1 dg403 v l v+ in2 s2 d2 n.c. d4 s4 dip/so dip/so 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 s1 in1 v- gnd s3 d3 n.c. d1 dg405 v l v+ in2 s2 d2 n.c. d4 s4 dip/so dg401 logic switch 0 1 off on dg403 logic switches 1, 2 0 1 off on dg405 logic switch 0 1 off on switches 3, 4 on off switches shown for logic "0" input n.c. = not internally connected lcc packages on last page. _____________________pin configurations/functional diagrams/truth tables 19-4727; rev 2; 6/99 part temp. range pin package dg401 cj 0? to +70? 16 plastic dip dg401cy 0? to +70? 16 narrow so dg401c/d 0? to +70? dice* for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769.
t a = t min to t max v+ = 16.5v, v- = -16.5v, v d = 15.5v, v s = ?5.5v, v+ = 16.5v, v- = -16.5v, v d = ?5.5v, v s = 15.5v improved, dual, high-speed analog switches 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = 15v, v- = -15v, v l = +5v, gnd = 0v, v inh = +2.4v, v inl = +0.8v, t a = t min to t max , unless otherwise noted.) dg401/dg403/dg405 note 1: signals on s, d or in exceeding v+ or v- are clamped by internal diodes. limit forward current to maximum current rating. stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage referenced to v- v+.......................................................................................44v gnd ...................................................................................25v v l .................................................(gnd - 0.3v) to (v+ + 0.3v) digital inputs, v s , v d (note 1) .......(v- - 2v) to (v+ + 2v) or 20ma (whichever occurs first) continuous current (any terminal) ......................................30ma continuous current, s or d .................................................20ma peak current, s or d (pulsed at 1ms, 10% duty cycle max) ..........................100ma continuous power dissipation (t a = +70?) 16-pin plastic dip(derate 10.53mw/? above +70?)...842mw 16-pin narrow so (derate 8.70mw/? above +70?) ...696mw 16-pin cerdip (derate 10.00mw/? above 70?) .......800mw 20-pin lcc (derate 9.09mw/? above +70?) ............727mw operating temperature ranges dg40_c_ .............................................................0? to +70? dg40_d_ ..........................................................-40? to +85? dg40_a_ ........................................................-55? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10sec) .............................+300? parameter symbol conditions temp. range min typ max (note 2) units analog signal range v analog (note 3) -15 +15 v c,d 20 45 a 20 30 c,d 55 drain-source on-resistance r ds(on) v+ = 13.5v, v- = -13.5v, i s = -10ma, v d = ?0v, v inh = 2.4v, v inl = 0.8v a 45 ? 0.5 2 drain-source on-resistance match between channels (note 4) ? r ds(on) v+ = 15v, v- = -15v, i s = -10ma, v d = ?0v c, d, a ? on-resistance flatness (note 4) r flat(on) v+ = 15v, v- = -15v, i s = -10ma, v d = ?v, 0v c, d, a 3 ? c, d -0.50 -0.01 0.50 a -0.25 -0.01 0.25 c, d -5 5 source-off leakage current (note 7) i s(off) a -10 10 na c, d -0.50 -0.01 0.50 a -0.25 -0.01 0.25 c, d -5 5 drain-off leakage current (note 7) i d(off) a -10 10 na c, d -1.0 -0.04 1.0 a -0.4 -0.04 0.4 c, d -10 10 drain-on leakage current (note 7) i d(on) or i s(on) v+ = 16.5v, v- = -16.5v, v d = ?5.5v, v s = ?5.5v a -20 20 na t a = +25? t a = t min to t max t a = +25? t a = +25? t a = +25? t a = t min to t max t a = +25? t a = t min to t max t a = +25? t a = t min to t max t a = t min to t max 3 6 switch
dg401/dg403/dg405 improved, dual, high-speed analog switches _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = 15v, v- = -15v, v l = +5v, gnd = 0v, v inh = +2.4v, v inl = +0.8v, t a = t min to t max , unless otherwise noted.) note 2: this data sheet uses the algebraic convention, where the most negative value is a minimum and the most positive value is a maximum. note 3: guaranteed by design. note 4: ? r on = ? r on (max) - ? r on (min). on-resistance match between channels and flatness are guaranteed only with specified voltages. flatness is defined as the difference between the maximum and minimum value of on-resistance as measured at the extremes of the specified analog signal range. note 5: off isolation = 20log (v s /v d ), v d = output, v s = input to off switch. note 6: between any two switches. note 7: leakage parameters i s(off) , i d(off) , and i d(on) are 100% tested at the maximum rated hot temperature and guaranteed by correlation at +25?. parameter symbol conditions min typ max (note 2) units input current with input voltage high i inh v in = 2.4v, all others = 0.8v -1.0 0.005 1.0 ? input current with input voltage low i inl v in = 0.8v, all others = 2.4v -1.0 0.005 1.0 ? power-supply range ?.5 ?0 v positive supply current i+ all channels on or off, v+ = 16.5v, v- = -16.5v, v in = 0v or 5v t a = +25? -1.0 0.01 1.0 ? negative supply current i- all channels on or off, v+ = 16.5v, v- = -16.5v, v in = 0v or 5v t a = +25? -1.0 0.01 1.0 ? logic supply current i l all channels on or off, v+ = 16.5v, v- = -16.5v, v in = 0v or 5v t a = +25? -1.0 0.01 1.0 ? ground current i gnd all channels on or off, v+ = 16.5v, v- = -16.5v, v in = 0v or 5v t a = +25? -1.0 0.01 1.0 ? turn-on time t on figure 2 t a = +25? 100 150 ns turn-off time t off figure 2 t a = +25? 60 100 ns break-before-make delay (note 3) t d dg403 only, figure 3 t a = +25? 10 20 ns charge injection (note 3) q c l = 1.0nf, v gen = 0v, r gen = 0 ? , figure 4 t a = +25? 10 15 pc off isolation (note 5) oirr r l = 100 ? , c l = 5pf, f = 1mhz, figure 5 t a = +25? 72 db crosstalk (note 6) r l = 50 ? , c l = 5pf, f = 1mhz, figure 6 t a = +25? 90 db source-off capacitance c s(off) f = 1mhz, figure 7 t a = +25? 12 pf drain-off capacitance c d(off) f = 1mhz, figure 7 t a = +25? 12 pf channel-on capacitance c d(on) or c s(on) f = 1mhz, figure 8 t a = +25? 39 pf t a = t min to t max t a = t min to t max t a = t min to t max t a = t min to t max -5.0 5.0 -5.0 5.0 -5.0 5.0 -5.0 5.0 input supply dynamic
dg401/dg403/dg405 improved, dual, high-speed analog switches 4 _______________________________________________________________________________________ __________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.) 50 55 20 -20 on-resistance vs. v d (dual supplies) 25 45 max401-1 v d (v) r ds (on) ( ? ) 10 35 30 -10 0 20 40 15 10 5 a: v+ = 5v, v- = -5v b: v+ = 10v, v- = -10v c: v+ = 15v, v- = -15v d: v+ = 20v, v- = -20v a b c d 35 5 -20 on-resistance vs. v d and temperature (dual supplies) 10 30 max401-2 v d (v) r ds (on) ( ? ) 20 20 15 -10 10 25 0 v+ = 15v, v- = -15v t a = +125? t a = +85? t a = +25? t a = -55? 140 20 0 on-resistance vs. v d (single supply) 40 120 max401-3 v d (v) r ds (on) ( ? ) 20 80 60 515 100 10 v+ = 5v v- = 0v v+ = 10v v+ = 15v v+ = 20v 70 10 0 on-resistance vs. v d and temperature (single supply) 20 60 max401-4 v d (v) r ds (on) ( ? ) 20 40 30 515 50 10 v+ = 12v, v- = 0v t a = +125 c t a = +85 c t a = +25 c 60 -60 -20 20 charge injection vs. analog voltage -40 40 max401-7 v d (v) q (pc) 10 0 -20 -10 0 20 v+ = 15v, v- = -15v 100 0.0001 -55 125 supply current vs. temperature 0.001 10 max401-8 temperature (?) i+, i-, i l ( a) 0.1 0.01 25 1 i+ at v+ = 16.5v i- at v- = -16.5v i l at v l = 5v 100 0.0001 -55 125 off leakage currents vs. temperature 0.001 10 max401-5 temperature ( c) off leakage (na) 0.1 0.01 25 1 v+ = 16.5v v- = -16.5v v d = 15v v s = 15v 100 0.0001 -55 125 on leakage currents vs. temperature 0.001 10 max401-6 temperature ( c) on leakage (na) 0.1 0.01 25 1 v+ = 16.5v v- = -16.5v v d = 15v v s = 15v
dg401/dg403/dg405 improved, dual, high-speed analog switches _______________________________________________________________________________________ 5 __________applications information _____________________pin description figure 1. overvoltage protection using external blocking diodes operation with supply voltages other than 15v the dg401/dg403/dg405 switches operate with ?.5v to ?0v bipolar supplies or with a +10v to +30v single supply. in either case, analog signals ranging from v+ to v- can be switched. the typical operating characteristics graphs illustrate typical analog-signal and supply-voltage on-resistance variations. the usual on-resistance temperature coefficient is 0.5%/? (typ). logic inputs these devices operate with a single positive supply or with bipolar supplies. they maintain ttl compatibility with supplies anywhere in the ?.5v to ?0v range as long as v l = +5v. if v l is connected to v+ or another supply at voltages other than +5v, the devices will operate at cmos-logic-level inputs. overvoltage protection proper power-supply sequencing is recommended for all cmos devices. do not exceed the absolute maximum ratings because stresses beyond the listed ratings may cause permanent damage to the devices. always sequence v+ on first, followed by v l , v-, and logic inputs. if power-supply sequencing is not possible, add two small, external signal diodes in series with supply pins for overvoltage protection (figure 1). adding diodes reduces the analog-signal range to 1v below v+ and 1v below v-, without affect- ing low switch resistance and low leakage characteristics. device operation is unchanged, and the difference between v+ and v- should not exceed +44v. dg401 dip/so lcc name function 1, 8 2, 10 d1, d2 drain (analog signal) 2-7 1, 3-9, 11, 16 n.c. not internally connected 9, 16 12, 20 s2, s1 source (analog signal) 10, 15 13, 19 in2, in1 digital logic inputs 11 14 v+ positive supply-voltage input?onnected to substrate 12 15 v l logic supply-voltage input 13 17 gnd ground 14 18 v- negative supply-voltage input dg403 dip/so lcc name function 1, 8, 3, 6 2, 10, 4, 8 d1-d4 drain (analog signal) 2, 7 1, 3, 6, 9, 11, 16 n.c. not internally connected 11 14 v+ positive supply-voltage input?onnected to substrate 12 15 v l logic supply-voltage input 13 17 gnd ground 14 18 v- negative supply-voltage input dg405 dip/so lcc name function 1, 8, 3, 6 2, 10, 4, 8 d1-d4 drain (analog signal) 2, 7 1, 3, 6, 9, 11, 16 n.c. not internally connected 11 14 v+ positive supply-voltage input?onnected to substrate 12 15 v l logic supply-voltage input 13 17 gnd ground 14 18 v- negative supply voltage v+ d v- s v g 16, 9, 4, 5 20, 12, 5, 7, s1-s4 source (analog signal) 10, 15 13, 19 in2, in1 digital logic inputs 16, 9, 4, 5 20, 12, 5, 7, s1-s4 source (analog signal) 10, 15 13, 19 in2, in1 digital logic inputs
dg401/dg403/dg405 improved, dual, high-speed analog switches 6 _______________________________________________________________________________________ ______________________________________________timing diagrams/test circuits 50% t off tr < 20ns t f < 20ns v out v out t on 0.9 x v out 0.9 x v out +3v 0v 0v logic input switch output logic input waveform is inverted for switches that have the opposite logic sense control. +5v +15v v out r l = 1000 ? c l = 35pf -15v repeat test for in2 and s2 0v gnd logic input v d = +10v (for t on ) v d = -10v (for t off ) for load conditions, see electrical characteristics. c l includes fixture and stray capacitance. v out = v d r l r l + r ds(on) v+ v l v- d in s ( ) dg401 dg403 dg405 v gen gnd c l 10nf v out 0v -15v v- v l v+ r gen v out in on off on ? v out q = ( ? v out ) (c l ) +5v +15v sd dg401 dg403 dg405 50% v out1 v out2 0.9 x v out +3v 0v 0v logic input switch output 1 switch output 2 +5v v l +15v v+ v- -15v c l includes fixture and stray capacitance. 0v gnd logic input 0v 0.9 x v out t d t d in r l2 c l2 v out2 r l1 v out1 c l1 r l = 1000 ? c l = 35pf d d s s +10v +10v dg401 dg403 dg405 figure 2. switching time figure 4. charge injection figure 3. break-before-make interval
dg401/dg403/dg405 improved, dual, high-speed analog switches _______________________________________________________________________________________ 7 _________________________________timing diagrams/test circuits (continued) in 0v or 2.4v signal generator +15v +5v c c v+ v l analyzer ch a ch b s r l 100 ? gnd d c -15v c = 5pf frequency tested 1mhz signal generator automatic synthesizer analyzer tracking spectrum analyzer off isolation = 20log v s v d v- dg401 dg403 dg405 figure 5. off isolation figure 6. crosstalk in2 0v or 2.4v signal generator +15v +5v c c v l analyzer ch a ch b r l 100 ? gnd c v- -15v c = 5pf frequency tested 1mhz signal generator automatic synthesizer analyzer tracking spectrum analyzer 0v or 2.4v in1 50 ? v+ d d s s dg401 dg403 dg405 v- capacitance meter gnd c -15v in 0v or 2.4v c c +15v +5v v+ v l s d dg401 dg403 dg405 figure 7. channel-off capacitance v- capacitance meter gnd c -15v in 0v or 2.4v c c +15v +5v v+ v l s d dg401 dg403 dg405 figure 8. channel-on capacitance
___________________chip topography d1 s1 d2 s2 in1 v- gnd v l v+ in2 0.102 (2.59mm) d3 (dg403/dg405) s3 (dg403/dg405) s4 (dg403/dg405) d4 (dg403/dg405) 0.070 (1.78mm) dg401/dg403/dg405 improved, dual, high-speed analog switches _ordering information (continued) ____pin configurations (continued) * contact factory for dice specifications. * *contact factory for availability and processing to mil-std-883b. dg401 lcc dg403 14 15 16 17 18 5 6 7 8 3 2 1 20 19 9 10 11 12 13 s3 d3 4 n.c. s4 d4 v- gnd n.c. v l v+ n.c. d1 n.c. s1 in1 n.c. d2 n.c. s2 in2 14 15 16 17 18 4 5 6 7 8 3 2 1 20 19 9 10 11 12 13 n.c. n.c. n.c. n.c. n.c. v- gnd n.c. v l v+ n.c. d1 n.c. s1 in1 n.c. d2 n.c. s2 in2 top view dg405 14 15 16 17 18 4 5 6 7 8 3 2 1 20 19 9 10 11 12 13 d3 s3 n.c. s4 d4 v- gnd n.c. v l v+ n.c. d1 n.c. s1 in1 n.c. d2 n.c. s2 in2 20 lcc** -55? to +125? dg401az 16 cerdip** -55? to +125? dg401ak 16 cerdip -40? to +85? dg401dk 16 narrow so -40? to +85? dg401dy 16 plastic dip -40? to +85? dg401dj 20 lcc** -55? to +125? dg405az 16 cerdip** -55? to +125? dg405ak 16 cerdip -40? to +85? dg405dk 16 plastic dip -40? to +85? dg405dj 16 narrow so -40? to +85? dg405dy dice* 0? to +70? dg405c/d 16 narrow so 0? to +70? dg405cy 16 plastic dip 0? to +70? dg405 cj 20 lcc** -55? to +125? dg403az 16 cerdip** -55? to +125? dg403ak 16 cerdip -40? to +85? dg403dk 16 narrow so -40? to +85? dg403dy 16 plastic dip -40? to +85? dg403dj dice* 0? to +70? dg403c/d 16 narrow so 0? to +70? dg403cy 16 plastic dip 0? to +70? dg403 cj pin package temp. range part transistor count: 66 substrate connected to v+ n.c. = not internally connected maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1999 maxim integrated products printed usa is a registered trademark of maxim integrated products.
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