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preliminary 32m (2m x 16) sram cy81u032x16a7a mobl3? cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05312 rev. ** revised september 11, 2002 features very high speed: 70 ns advanced low-power mobl ? architecture wide voltage range: ? v cc range: 2.3v ? 3.1v ? v ccq range (i/o): 1.7v ? v cc ultra-low active, standby power easy memory expansion with ce and oe features 1t sram memory cell automatic power-down when deselected cmos for optimum speed/power functional description [1] the mobl3 ? is a high-performance cmos static ram organized as 2m words by 16 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life ? (mobl) in portable applications such as cellular telephones. the device can be put into standby mode when deselected (ce high, or both ble and bhe high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce high, or both ble and bhe high), outputs are disabled (oe high), or during a write operation (ce low and we low). writing to the device is accomplished by taking chip enable (ce ) low and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 20 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 20 ). reading from the device is accomplished by taking chip enable (ce ) low and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this datasheet for a complete description of read and write modes. this sram has multiple power down functions. the zz pin will put the sram into a deep sleep mode, where the data is not retained in the sram. the variable address mode allows the user to retain data in a section of the sram and reduce the standby current. the cy81u032x16a7a has the deep sleep mode enabled on power-up. the var register can be used to disable the deep sleep mode. the mobl3 is available in a 48-ball fbga package. note: 1. for best practice recommendations, please refer to the cy application note ? system design guidelines ? on http://www.cypress.com. logic block diagram 2m x 16 ram array i/o 0 ? i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ? i/o 15 ce we ble bhe a 10 a 16 a 0 a 1 a 17 a 9 a 18 a 20 a 19 power-down circuit bhe ble ce refresh/power-down circuit zz
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 2 of 14 notes: 2. dnu pins are to be connected to v ss or left open. 3. v ssq is the ground pin for the i/o drivers. it should be connected to v ss . pin configuration [2, 3] fbga we v cc a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ssq a 9 a 8 oe v ss a 7 i/o 0 bhe zz a 17 a 2 a 1 ble v ccq i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 a 20 3 2 6 5 4 1 d e b a c f g h top view a 16 dnu
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 3 of 14 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage to ground potential-v25 ....... ? 0.2v to +3.3v dc voltage applied to outputs in high-z state [4, 5, 6] .............................. ? 0.2v to v cc + 0.3v dc input voltage [4, 5, 6] .......................... ? 0.2v to v cc + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage.......................................... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma power-up characteristics the 32m needs to have a initialization time before accesses can be started on the device. the initialization sequence is shown in the figure below. chip select (ce) should be high for at least 200 us after v cc has reached a stable value. no access must be attempted during this period of 200 us. operating range ambient temperature v cc v ccq ? 25 c to +85 c 2.3 to 3.1v 1.7v to vcc product portfolio product v cc range cycle time t aa power dissipation operating (icc) standby (i sb2 ) f = 1 mhz f = f max min. typ. max. typ. [7] max. typ. [7] max. typ. [7] max. cy81u032x16a7a-85 2.3v 2.5v 3.1v 85 ns 85 ns 2 ma 18 ma 100 a cy81u032x16a7a-70 70 ns 70 ns 21 ma parameter description min. typ. max. unit tpu chip enable low after stable vcc 200 s note: 4. overshoot: v cc + 0.2v, pulse width < 20 ns. 5. undershoot: ? 0.2v, pulse width < 20 ns. 6. overshoot and undershoot specifications are characterized and are not 100% tested. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c. tpu ce vcc first access stable power
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 4 of 14 variable address refresh description the variable address mode allows customers to turn off sections of the die to save standby current. the 32m mobl3 is divided into four 8m sections allowing certain sections to be active (i.e., refreshed). the variable address mode also allows a customer to go into a low-power mode with zz tied low and keep the data in a certain section of memory. function at power up, all four sections of the die are activated and the sram enters into its default state of full memory size and refresh space. mobl3 provides three distinct operation modes for reducing standby power: a. reduced memory size operation b. partial array refresh c. deep sleep mode. in the reduced memory size (rms) operation, the sram can be operated as a reduced size sram. for example, one could operate the 32m sram as an 8m, 16m, or a 32m memory block. the protocol to turn on/off the sections of the memory is given in the following pages. the rms mode is enabled after zz goes high and remains in rms mode after zz goes high. to revert back to a complete 32m sram, the protocol outlined on the next page will have to be followed, along with the bit pattern definitions shown on page 6. in the partial array refresh (par), the sram will only refresh certain portions of the memory, as configured by the user. this mode is only for standby and is applicable as long as zz remains low. once zz returns high in this mode, the sram goes back to operating in full address refresh. the protocol shown on the next page will have to be followed to turn on/off this mode of operation. once the variable address (va) register is updated, all future par accesses will use the contents of the va register when zz returns low. if the customer wants to change the par space, the va register must be updated per next figure. if the variable address (va) register is not updated after power up, the sram will be in its default state. in the default state the whole memory array will be refreshed and driving zz low places the sram into a deep sleep mode after 1us. once in the deep sleep mode, data integrity in the sram is not guaranteed. if the customer updates the va register, then address bit 4 (a4) must be set to 1, indicating to the sram that the deep sleep mode is disabled. at any point of time, one could drive zz low and change the va register ? s a4 bit back to 0. then the sram enters deep sleep when zz is driven low and remains in deep sleep mode until zz is driven high. once the sram enters into deep sleep mode the content of the va register is destroyed and the part returns to its default state. note: 8. oe and the data pins are in a don ? t care state while the device is in variable address mode. variable address refresh swishing diagrams variable address mode ? register update [8] address t wc ce bhe / ble we zz t aw t pwe t bw t sa t zzwe t ha lower-order address (a0-a4) define power save variable address mode ce or ble / bhe t cdr 1 us suspend t r variable address mode ? entry/exit zz
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 5 of 14 variable address space timings [ 9 ] parameter description min. max. unit t zzwe zz low to we low 1000 ns t cdr chip deselect to zz low 0 ns t r [10] operation recovery time (deep sleep mode only) 200 s t zzmin deep sleep mode time 10 s variable address space ? register variable address space ? address patterns partial array refresh mode (a3=0, a4=1) a2 a1, a0 refresh section address size density 0 11 one-fourth of the die 00000h ? 07ffffh (a20=a19=0) 512k x 16 8m 0 10 half of the die 00000h ? 0fffffh (a20=0, a19=0 or 1) 1m x 16 16m 0 01 three-fourths of the die 00000h ? 17ffffh (a20:a19 != 11) 1.5m x 16 24m 1 11 one-fourth of the die 180000h ? 1fffffh (a20=a19=1) 512k x 16 8m 1 10 half of the die 100000h ? 1fffffh (a20=1, a19=0 or 1) 1m x 16 16m 1 01 three-fourths of the die 080000h ? 1fffffh (a20:a19 != 00) 1.5m x 16 24m reduced memory size mode (a3=1, a4=1) 0 11 one-fourth of the die 00000h ? 07ffffh (a20=a19=0) 512k x 16 8m 0 10 half of the die 00000h ? 0fffffh (a20=0, a19=0 or 1) 1m x 16 16m 0 01 three-fourths of the die 00000h ? 17ffffh (a20:a19 != 11) 1.5m x 16 24m 0 00 full die 00000h ? 1fffffh 2m x 16 32m 1 11 one-fourth of the die 180000h ? 07ffffh (a20=a19=0) 512k x 16 8m 1 10 half of the die 100000h ? 0fffffh (a20=0, a19=0 or 1) 1m x 16 16m 1 01 three-fourths of the die 080000h ? 17ffffh (a20:a19 != 00) 1.5m x 16 24m 1 00 full die 000000h ? 1fffffh 2m x 16 32m notes: 9. all other timing parameters are as shown in the data sheets. 10. t r applies only in the deep sleep mode. a0 a1 a2 a3 a4 a20 ? a5 memory array selection 11 ? 8m 10 ? 16m 01 ? 24m 00 ? 32m (default) top/bottom half selection 0 ? bottom (default) 1 ? to p array on/off on zz 0 ? par mode (default) 1 ? rms mode zz enable/disable 0 ? deep sleep enabled 1 ? deep sleep disabled reserved
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 6 of 14 memory block split 18 18 18 18 18 18 18 18 17 17 18 18 18 18 18 18 19 19 19 19 19 19 19 19 1/4 address space refresh active address space: a0-a18 a<19,20> = <0,0> 1/2 address space refresh active address space: a0-a19 a<20>=<0> 3/4 address space refresh active address space: a0-a20 a<19,20> = <0,0>,<1,0>,<0,1> full address space refresh active address space: a0-a20 a<19,20> = 0 1 0 1 a<19>=ra11 a<20>=ra12 0 1 0 1 a<19>=ra11 a<20>=ra12 0 1 0 1 a<19>=ra11 a<20>=ra12 0 1 0 1 a<19>=ra11 a<20>=ra12 0 1 0 1 a<19>=ra11 a<20>=ra12 0 1 0 1 a<19>=ra11 a<20>=ra12 0 1 0 1 a<19>=ra11 a<20>=ra12 0 1 0 1 a<19>=ra11 a<20>=ra12 1/4 address space refresh active address space: a0-a18 a<19,20> = <1,1> 1/2 address space refresh active address space: a0-a19 a<20>=<1> 3/4 address space refresh active address space: a0-a20 a<19,20> = <1,0>,<0,1>,<1,1> full address space refresh active address space: a0-a20 a<19,20> = top address range bottom address range
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 7 of 14 capacitance [13] electrical characteristics over the operating range [4,5,6] parameter description test conditions cy81u032x16a7a unit min. typ. [7] max. v oh [11] output high voltage i oh = ? 0.1 ma v ccq ? 0.2 v v ol [11] output low voltage i ol = 0.1 ma 0.2 v v ih [12] input high voltage 1.4 v cc +0.2v v v il [12] input low voltage ? 0.2 0.4 v i ix input leakage current gnd < v i < v cc ? 1+1 a i oz output leakage current gnd < v o < v cc , output disabled ? 1+1 a i cc v cc operating supply current i out = 0 ma, f = f max = 1/t rc , v cc = max cmos levels t aa = 85 ns 18 ma t aa = 70 ns 21 ma i out = 0 ma, f = 1 mhz, cmos levels, v cc = max 2ma i sb1 automatic ce power-down current ? cmos inputs ce > v cc ? 0.3v or ce < 0.3v v in > v cc ? 0.3v or v in < 0.3v, f = f max (address and data only), f=0 (oe , we , bhe , ble ) v cc = max 100 a i sb2 automatic ce power-down current ? cmos inputs ce > v cc ? 0.3v or ce < 0.3v v in > v cc ? 0.3v or v in < 0.3v, f=0, v cc = max 100 a parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc(typ) 6 pf c out output capacitance 8 pf thermal resistance parameter description test conditions bga unit ja thermal resistance (junction to ambient) [13] still air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board 55 c/w jc thermal resistance (junction to case) [13] 16 c/w ac test loads and waveforms notes: 11. for i oh = ? 0.4 ma, v oh = 0.8 x v ccq ; for i ol = 0.4 ma, v ol = 0.2 x v ccq . 12. for v ccq = 1.7 ? 2.25v: v ih = higher of (1.4v, 0.8 x v ccq ); v il = lower of (0.4v, 0.2 x v ccq ). 13. tested initially and after any design or process changes that may affect these parameters. v cc typ v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% output v equivalent to: th venin equivalent all input pulses r th r1 rise time: 1 v/ns fall time: 1 v/ns
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 8 of 14 parameters 2.5v i/o 1.8v i/o unit r1 21000 14000 ohms r2 21000 14000 ohms r th 10500 7000 ohms v th 1.25 0.9 volts deep sleep mode [14] parameter description conditions min. typ. [7] max. unit i ccds deep sleep current ce > v cc ? 0.2v, zz < v il, v in > v cc ? 0.2v or v in < 0.2v no input may exceed v cc + 0.2v 7 10 a t cdr [14] chip deselect to data retention time 0 ns t r operation recovery time 200 s t zzmin deep sleep mode time 10 s deep sleep waveform [15] switching characteristics over the operating range [16] parameter description 85 ns 70 ns unit min. max. min. max. read cycle t rc read cycle time 85 70 ns t aa address to data valid 85 70 ns t oha data hold from address change 10 10 ns t ace ce low to data valid 85 70 ns t doe oe low to data valid 35 35 ns t lzoe [20] oe low to low-z [17] 5 5 ns t hzoe [20] oe high to high-z [17, 18] 25 25 ns t lzce [20] ce low to low-z [17] 10 10 ns t hzce [20] ce high to high-z [17, 18] 25 25 ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 85 70 ns t dbe ble / bhe low to data valid 85 70 ns t lzbe [20] ble / bhe low to low-z [17] 5 5 ns t hzbe [20] ble / bhe high to high-z [17,18] 25 25 ns notes: 14. this mode does not retain the data in the sram. all data will be lost in the mode of operation. this is the default mode of operation on the cy81u032x16a7a device. 15. bhe .ble is the and of both bhe and ble . chip can be deselected by either disabling the chip enable signal (ce high) or by disabling both bhe and ble (both high). 16. test conditions assume signal transition time of 3ns or less, timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh and 30 pf load capacitance. t cdr deep sleep mode t r ce or zz bhe .ble t zzmin 1 us suspend
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 9 of 14 write cycle [19] t wc write cycle time 85 70 ns t sce ce low to write end 75 60 ns t aw address set-up to write end 75 60 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 65 1000 50 1000 ns t bw ble / bhe low to write end 75 60 ns t sd data set-up to write end 30 30 ns t hd data hold from write end 0 0 ns t hzwe [20] we low to high-z [17, 18] 25 25 ns t lzwe [20] we high to low-z [17] 10 10 ns switching characteristics over the operating range [16] (continued) parameter description 85 ns 70 ns unit min. max. min. max. switching waveforms notes: 17. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , t hzbe is less than t lzbe and t hzwe is less than t lzwe for any given device. 18. t hzoe , t hzce , t hzbe and t hzwe transitions are measured when the output enters a high impedance state. 19. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble =v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edg e of the signal that terminates the write. 20. high-z and low-z parameters are guaranteed by design and are not tested. 21. device is continuously selected. oe , ce = v il , bhe and/or ble = v il 22. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha read cycle no. 1(address transition controlled) [21, 22]
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 10 of 14 notes: 23. address valid prior to or coincident with ce transition low. 24. data i/o is high impedance if oe = v ih . 25. if ce goes low simultaneously with we high, the output remains in a high-impedance state. 26. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) read cycle no. 2 (oe controlled) [22, 23] 50% 50% data valid t rc t ace t lzbe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current t hzbe bhe /ble t lzoe address t doe t dbe t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 26 write cycle no. 1 (we controlled) bhe /ble t bw [19, 24, 25]
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 11 of 14 switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 26 write cycle no. 2 (ce controlled) bhe /ble t bw [19, 24, 25] t sa data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 26 write cycle no. 3 (we controlled, oe low) t bw bhe /ble [25]
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 12 of 14 switching waveforms (continued) write cycle no. 4 (bhe /ble controlled, oe low) [25] data i/o address t hd t sd t sa t ha t aw t wc ce we data in valid note 26 t bw bhe /ble t sce t pwe t hzwe t lzwe truth table ce zz we oe bhe ble inputs/outputs mode power x h x x h h high-z deselect/power-down standby (i sb ) h h x x x x high-z deselect/power-down standby (i sb ) x l x x x x high-z deep sleep mode deep sleep current (iccds) [27] l h h l l l data out (i/o0 ? i/o15) read active (i cc ) l h h l h l data out (i/o0 ? i/o7); high-z (i/o8 ? i/o15) read active (i cc ) l h h l l h data out (i/o8 ? i/o15); high-z (i/o0 ? i/o7) read active (i cc ) l h x h l l high-z output disabled active (i cc ) l h l x l l data in (i/o0 ? i/o15) write active (i cc ) l h l x h l data in (i/o0 ? i/o7); high-z (i/o8 ? i/o15) write active (i cc ) l h l x l h data in (i/o8 ? i/o15); high-z (i/o0 ? i/o7) write active (i cc ) ordering information speed (ns) ordering code package name package type operating range 70 cy81u032x16a7a-7n4fi bv48a 6 x 8 x 1 48-ball fine pitch bga industrial 85 CY81U032X16A7A-8N4FI note: 27. this assumes that the deep sleep mode is enabled in the var register.
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 13 of 14 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. mobl is a registered trademark, and mobl3 and more battery life are trademarks, of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams 48-ball vfbga (6 x 8 x 1 mm) bv48a 51-85150-*a
preliminary cy81u032x16a7a mobl3 ? document #: 38-05312 rev. ** page 14 of 14 document history page document title : cy81u032x16a7a mobl3 ? 32m (2m x 16) sram document number : 38-05312 rev. ecn no. issue date orig. of change description of change ** 117419 09/16/02 hrt new data sheet

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