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ps014401-1001 product specification z86e61/z86e63 cmos z8 16k/32k eprom microcontroller copyright ?2008 by zilog ? , inc. all rights reserved. www.zilog.com
ps014401-1001 do not use in life support life support policy zilog's products are not authorized fo r use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. a critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. document disclaimer ?2008 by zilog, inc. all rights reserved. information in this pu blication concerning the devices, applications, or technology describe d is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained within this document has been verified according to the general pr inciples of electrical and mechanical engineering. z8, z8 encore!, z8 encore! xp, z8 encore! mc, crim zon, ez80, and zneo are trademarks or registered trademarks of zilog, inc. all other product or servi ce names are the property of their respective owners. warning:
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 iii table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 romless (input, active low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ds (output, active low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 as (output, active low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 xtal2, xtal1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 r/w (output, write low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 reset (input, active low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 port 0 (p07-p00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 port 1 (p17-p10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 uart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 z86e61/e63 user modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 z86e63 signal description for eprom program/read . . . . . . . . . . . . . . . 27 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 z8 control register diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 instruction set notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 instruction formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 iv
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 v list of figures figure 1. z86e61/e63 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. 40-pin dip pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. 44-pin plcc pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. 40-pin dip pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. 44-pin plcc pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. port 0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. port 1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. port 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. port 3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. serial data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11. program memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. data memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13. register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 14. register pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 15. counter/timers block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 16. interrupt block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 17. oscillator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 18. eprom read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 19. eprom program and verity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 20. programming eprom, ram protect, and 4k size selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 21. programming eprom, ram protect, and 16k size selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22. intelligent programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23. test load diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 24. external i/o or memory read/write timing . . . . . . . . . . . . . . . . . . . 36 figure 25. additional timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 26. input handshake timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 27. output handshake timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 28. serial i/o register (f0h: read/write) . . . . . . . . . . . . . . . . . . . . . . . 41 figure 29. timer mode register (f1h: read/write) . . . . . . . . . . . . . . . . . . . . . 41 figure 30. counter/timer 1 register (f2h: read/write) . . . . . . . . . . . . . . . . . 42 figure 31. prescaler 1 register (f3h: write only) . . . . . . . . . . . . . . . . . . . . . . 42 figure 32. counter/timer 0 register (f4h: read/write) . . . . . . . . . . . . . . . . . 42 figure 33. prescaler 0 register (f5h: write only) . . . . . . . . . . . . . . . . . . . . . . 43 figure 34. port 2 mode register (f6h: write only) . . . . . . . . . . . . . . . . . . . . . 43
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 vi figure 35. port 3 mode register (f7h: write only) . . . . . . . . . . . . . . . . . . . . . 44 figure 36. port 0 and 1 mode register (f8h: write only) . . . . . . . . . . . . . . . . 45 figure 37. interrupt priority register (f9h: write only) . . . . . . . . . . . . . . . . . . 46 figure 38. interrupt request register (fah: read/write) . . . . . . . . . . . . . . . . 46 figure 39. interrupt mask register (fbh: read/write) . . . . . . . . . . . . . . . . . . . 47 figure 40. flag register (fch: read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 41. register pointer register (fdh: read/write) . . . . . . . . . . . . . . . . . 48 figure 42. stack pointer register (feh: read/write) . . . . . . . . . . . . . . . . . . . 48 figure 43. stack pointer register (ffh: read/write) . . . . . . . . . . . . . . . . . . . . 48 figure 44. typical icc vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 45. typical icc1 vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 46. instruction formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 47. opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 48. 40-pin dip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 49. 44-pin plcc package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 50. 44-pin lqfp package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 vii list of tables table 1. 40-pin dip pin identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2. 44-pin plcc pin identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. 40-pin dip pin identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. 44-pin plcc pin identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. port 3 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. otp programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 7. timing of programming waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 10. external i/o or memory read and write timing . . . . . . . . . . . . . . . . 36 table 11. clock dependent formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 12. additional timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 13. handshake timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 14. instruction set notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 15. condition codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 16. instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 viii
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 - 1 features ? 8-bit cmos microcontroller 40-pin dip, 44-pin plcc, 44-pin l qfp style packages 4.5v to 5.5v operating range clock speeds: 16 and 20 mhz low power consumption: 275 mw (max) fast instruction pointer: 1.0 ms 0 12 mhz two standby modes: stop and halt 32 input/output lines full-duplex uart all digital inputs are ttl levels auto latches high voltage protection on high voltage inputs ram and eprom protect eprom: ? 16 kbytes z86e61 ? 32 kbytes z86e63 256 bytes register file ? 236 bytes of general-purpose ram ? 16 bytes of control and status registers ? 4 bytes for ports two programmable 8-bit counter/timers. each with 6-bit programmable pres- caler six vectored, priority interrupts from eight different sources on-chip oscillator that accepts a crystal, ceramic resonator, lc, or external clock drive
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 2 general description the z86e61/e63 microcontrollers are members of the z8 ? single-chip microcon- troller family with 16k/32 kbytes of eprom and 236 bytes of general-purpose ram. offered in 40-pin dip, 44-pin plcc or 44-pin l qfp package styles, these devices are pin-compatible eprom versions of the z86c61/ 63. the romless pin option is available on the 44-pin versions only. with 4 kbytes of rom and 236 bytes of general-purpose ram, the z86e61/e63 offers fast execution, efficient use of memory, sophisticated interrupts, input/out- put bit manipulation capabilities, and easy hardware/software system expansion. for applications demanding powerful i/o capabilities, the z86e61/e63 offers 32 pins dedicated to input and output. these lines are grouped into four ports. each port consists of eight lines, and is configurable under software control to provide timing, status signals, serial or parallel i/o with or without handshake, and an address/data bus for interfacing external memory. the z86e61/e63 can address both external memory and preprogrammed rom, making it well suited for high-volume applications or where code flexibility is required. there are three basic address spaces available to support this configu- ration: program memory, data memory, and 236 general-purpose registers. to unburden the system from coping with real-time tasks such as counting/timing and serial data communication, the z86e61/e63 offers two on-chip counter/timers with a large number of user selectable modes (figure 1). power connections follow conventional descriptions below: connection circuit device power v cc v dd ground gnd v ss
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 3 figure 1. z86e61/e63 functional block diagram i/o (bit programmable) address or i/o (nibble programmable) address/data or i/o (byte programmable) port 2 port 0 port 1 port 3 uart counter/ timers (2) interrupt control alu flags register pointer register file 256 x 8-bit machine timing and instruction control 44 output input v cc gnd prg. memory 16k/32k program counter xtal as ds r/w reset 8
nc a12 a11 a10 a9 a8 vpp nc d7 d6 d5 reset nc nc nc nc gnd epm a0 a1 a2 nc a 3 a 4 a 5 a 6 a 7 d 0 d 1 d 2 d 3 d 4 c n c n c e n c x a 1t l x a 2t l vc c n c o e p mg a41 a31 1 11 12 22 23 33 34 44 z86e61/e63 lqfp eprom programming mode z86e61/e63 cmos z8 16k/32k eprom microcontroller 4 pin description - standard mode xtal2 crystal oscillator clock output xtal1 crystal oscillator clock input reset reset input r/w read/write output ds data strobe output as address strobe output p00-p07 port 0 8 bit genaral io input/output p10-p17 port 1 8 bit genaral io input/output p20-p27 port 2 8 bit genaral io input/output p30-p33 port 3 4 bit input input p34-p37 port 3 4 bit output output r/rl rom/romless ctrl input gnd ground input vcc power supply input pin description - eprom programming mode xtal2 crystal oscillator clock output xtal1 crystal oscillator clock input ce chip enable input reset reset input epm eprom prog mode input a0-a14 15-bit address bus input d7-d0 8-bit data bus input/output vpp prog voltage input pgm prog mode input oe output enable input nc not connected input gnd ground input vcc power supply input nc p24 p23 p22 p21 p20 p33 p34 p17 p16 p15 reset r/w ds as p35 gnd p32 p00 p01 p02 r/rl p 3 0 p 04 p 5 0 p 6 0 p 07 p 0 1 p 1 1 p 2 1 p 3 1 p 41 nc p 30 p 37 1 x ta l 2 x ta l vc c 6 p 3 1 p 3 7 p 2 6 p 2 5 p 2 1 11 12 22 23 33 34 44 z86e61/e63 lqfp standard mode ps14401-1001 nc
1 28 29 39 40 6 7 17 18 1 28 29 39 40 6 7 17 18 z86e61/e63 cmos z8 16k/32k eprom microcontroller 5 nc a12 a11 a10 a9 a8 vpp nc d7 d6 d5 reset nc nc nc nc gnd epm a0 a1 a2 nc a 3 a 4 a 5 a 6 a 7 d 0 d 1 d 2 d 3 c 4 n c c n c e n c x a 1 t l x a 2 t l v c c n c o e p m g a 4 1 a 3 1 z86e61/e63 plcc eprom programming mode nc p24 p23 p22 p21 p20 p33 p34 p17 p16 p15 reset r/w ds as p35 gnd p32 p00 p01 p02 r/rl p 0 3 p 4 0 p 0 5 p 0 6 7 p 0 p 1 0 p 1 1 p 1 2 p 3 1 4 p 1 n c n c p 3 0 p 3 7 1 x t a l 2 x t a l v c c 6 p 3 1 p 3 7 p 2 6 p 2 5 p 2 z86e61/e63 plcc standard mode ps14401-1001 pin description - standard mode xtal2 crystal oscillator clock output xtal1 crystal oscillator clock input reset reset input r/w read/write output ds data strobe output as address strobe output p00-p07 port 0 8 bit genaral io input/output p10-p17 port 1 8 bit genaral io input/output p20-p27 port 2 8 bit genaral io input/output p30-p33 port 3 4 bit input input p34-p37 port 3 4 bit output output r/rl rom/romless ctrl input gnd ground input vcc power supply input pin description - eprom programming mode xtal2 crystal oscillator clock output xtal1 crystal oscillator clock input ce chip enable input reset reset input epm eprom prog mode input a0-a14 15-bit address bus input d7-d0 8-bit data bus input/output vpp prog voltage input pgm prog mode input oe output enable input nc not connected input gnd ground input vcc power supply input
1 21 40 20 z86e61/e63 cmos z8 16k/32k eprom microcontroller 6 nc a12 a11 a10 a9 a8 vpp d7 d6 d5 nc nc nc nc gnd epm a0 a1 a2 a3 a4 a5 a6 a7 0d 1d 2d 3d 4d nc cn xa2 tl xa1 tl vcc a14 a13 1 21 40 20 reset ec oe pgm z86e61/e63 pdip eprom programming mode p24 p23 p22 p21 p20 p33 p34 p17 p16 p15 p35 gnd p32 p00 p01 p02 p30 p40 p50 p60 p70 p01 p11 p21 p13 p14 p30 p73 xtal1 2xtal vcc p63 p13 p72 p62 p52 reset ds r/w as z86e61/e63 pdip standard mode ps014401-1001 pin description - standard mode xtal2 crystal oscillator clock output xtal1 crystal oscillator clock input reset reset input r/w read/write output ds data strobe output as address strobe output p00-p07 port 0 8 bit genaral io input/output p10-p17 port 1 8 bit genaral io input/output p20-p27 port 2 8 bit genaral io input/output p30-p33 port 3 4 bit input input p34-p37 port 3 4 bit output output gnd ground input vcc power supply input pin description - eprom programming mode xtal2 crystal oscillator clock output xtal1 crystal oscillator clock input ce chip enable input reset reset input epm eprom prog mode input a0-a14 15-bit address bus input d7-d0 8-bit data bus input/output vpp prog voltage input pgm prog mode input oe output enable input nc not connected input gnd ground input vcc power supply input
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 11 pin functions romless (input, active low). connecting this pin to gnd disables the internal rom and forces the device to function as a z86c91 romless z8 (see the z86c91 product specification for more information). when pulled high to v cc , the device functions as a normal z86e61/e63 eprom version. this pin is only available on the 44-pin versions of the z86e61/ e63. ds (output, active low). data strobe is activated once for each external memory transfer. for a read operation, data must be available prior to the trailing edge of ds . for write operations, the falling edge of ds indicates that output data is valid. as (output, active low). address strobe is pulsed once at the beginning of each machine cycle. address output is through port 1 for all external programs. memory address transfers are valid at the trailing edge of as . under program control, as can be placed in the high-impedance state along with ports 0 and 1, data strobe, and read/write. xtal2, xtal1 crystal 2, crystal 1 (time-based input and output, respectively) . these pins con- nect a parallel-resonant crystal, ceramic resonator, lc, or any external single- phase clock to the on-chip oscillator and buffer. r/w (output, write low). the read/write signal is low when the mcu is writing to the external program or data memory. reset (input, active low). to avoid asynchronous and noisy reset problems, the z86e61/e63 is equipped with a reset filter of four external clocks (4tpc). if the external reset signal is less than 4tpc in duration, no reset occurs. note:
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 12 on the fifth clock after the reset is detected, an internal rst signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external reset , whichever is longer. during the reset cycle, ds is held active low while as cycles at a rate of tpc/2. when reset is deactivated, program execution begins at location 000c (hex). power-up reset time must be held low for 50 ms, or until v cc is stable, whichever is longer. port 0 (p07-p00) port 0 is an 8-bit, nibble programmable, bidirectional, ttl compatible port. these eight i/o lines can be configured under software control as a nibble i/o port, or as an address port for interfacing external memory. when used as an i/o port, port 0 may be placed under handshake control. in this configuration, port 3, lines p32 and p35 are used as the handshake control dav0 and rdy0 (data available and ready). handshake signal assignment is dictated by the i/o direction of the upper nibble p07-p04. the lower nibble must have the same direction as the upper nib- ble to be under handshake control. for external memory references, port 0 can provide address bits a11-a8 (lower nibble) or a15-a8 (lower and upper nibbles) depending on the required address space. if the address range requires 12 bits or less, the upper nibble of port 0 can be programmed independently as i/o while the lower nibble is used for address- ing. if one or both nibbles are needed for i/o operation, they must be configured by writing to the port 0 mode register. in romless mode, after a hardware reset, port 0 lines are defined as address lines a15-a8, and extended timing is set to accommodate slow memory access. the initialization routine can include reconfiguration to eliminate this extended tim- ing mode (figure 8). port 1 (p17-p10) port 1 is an 8-bit, byte programmable, bidirectional, ttl compatible port. it has multiplexed address (a7-a0) and data (d7-d0) ports. for z86e61/e63, these eight i/o lines can be programmed as input or output lines or are configured under software control as an address/data port for interfacing external memory. when used as an i/o port, port 1 can be placed under handshake control. in this config- uration, port 3 lines, p33 and p34, are used as the handshake controls rdy1 and dav1 . memory locations greater than 16384 (e61) or 32768 (e63) are referenced through port 1. to interface external memory, port 1 must be programmed for the multiplexed address/ data mode. if more than 256 external locations are required, port 0 must output the additional lines.
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 13 port 1 can be placed in high-impedance state along with port 0, as , ds , and r/w , allowing the mcu to share common resources in multiprocessor and dma appli- cations. data transfers are controlled by assigning p33 as a bus acknowledge input, and p34 as a bus request output (figure 7). figure 6. port 0 configuration z86e61 /e63 mcu port 0 (i/o) handshake controls dav0 and rdy0 (p32 and p35) pad auto latch r = 500 k ? ttl level shifter in out oen 4 4
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 14 figure 7. port 1 configuration port 2 (p27-p20). port 2 is an 8-bit, bit programmable, bi-directional, cm0s com- patible port. each of these eight i/0 lines can be independently programmed as an input or output, or globally as an open-drain output. port 2 is always available for i/ 0 operation. when used as an i/0 port, port 2 can be placed under handshake control. in this configuration, port 3 lines p31 and p36 are used as the handshake control lines dav2 and rdy2. the handshake signal assignment for port 3 lines, p31 and p36, is dictated by the direction (input or output) assigned to p27 (figure 8 and table 21 on page 16). z86e61 /e63 mcu port 1 handshake controls dav1 and rdy1 (p33 and p34) pad auto latch r = 500 k ? ttl level shifter in out oen 8 (ad7-ad0)
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 15 figure 8. port 2 configuration port 3 (p37-p30). port 3 is an 8-bit, cmos compatible four-fixed input and four- fixed output port. these eight i/o lines have four-fixed (p33-p30) input and four- fixed (p37-p34) output ports. port 3, when used as serial i/o, is programmed as serial in and serial out, respectively (figure 9). z86e61 /e63 mcu port 2 (i/o) handshake controls dav2 and rdy2 (p31 and p36) pad auto latch r = 500 k ? ttl level shifter in out oen open-drain
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 16 figure 9. port 3 configuration port 3 is configured under software control to provide the following control func- tions: handshake for ports 0 and 2 (dav and rdy); four external interrupt request signals (irq3-irq0); timer input and output signals (tin and tout) data mem- ory select (/dm) and eprom control signals (p30 = ce , p31 = oe , p32 = epm and p33 = vpp). 1. hs = handshake signals d = data available r = ready table 21. port 3 pin assignments pin i/o ctci int. p0 hs p1 hs p2 hs uart ext eprom p30 in t in irq3 serial in ce p31 in t in irq2 d/r oe p32 in t in irq0 d/r epm p33 in t in irq1 d/r v pp p34 out t out r/d dm p35 out t out r/d p36 out t out r/d p37 out t out serial out t0 irq4 t1 irq5 z86e61 /e63 mcu port 3 (i/o or control)
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 17 uart operation port 3 lines, p37 and p30, are programmed as serial i/0 lines for full-duplex serial asynchronous receiver/transmitter operation. the bit rate is controlled by counter/ timer0. the z86e61/e63 automatically adds a start bit and two stop bits to transmitted data (figure 10). odd parity is also available as an option. eight data bits are always transmitted, regardless of parity selection. if parity is enabled, the eighth bit is the odd parity bit. an interrupt request (irq4) is generated on all transmitted characters. received data must have a start bit, eight data bits, and at least one stop bit. if parity is on, bit 7 of the received data is replaced by a parity error flag. received characters generate the irq3 interrupt request. figure 10. serial data formats auto latch the auto latch puts valid cmos levels on all cmos inputs that are not externally driven. this reduces excessive supply current flow in the input buffer when it is not driven by any source. p33-p30 inputs differ from the z86c61/c63 in that there is no clamping diode to v cc because of the eprom high voltage detection circuits. exceeding the vih maximum specification during standard operating mode may cause the device to enter eprom mode. sp d7 d6 d5 d4 d3 d2 d1 d0 st sp transmitted data (no parity) start bit eight data bits two stop bits sp p d6d5d4d3d2d1d0st sp transmitted data (with parity) start bit seven data bits two stop bits odd parity sp d7 d6 d5 d4 d3 d2 d1 d0 st received data (no parity) start bit eight data bits one stop bit sp p d6 d5 d4 d3 d2 d1 d0 st received data (with parity) start bit one stop bit parity error flag note:
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 18 address space program memory. the z86e61/e63 can address 48 kbytes (e61) or 32 kbytes (e63) of external program memory (figure 11). the first 12 bytes of program memory are reserved for the interrupt vectors. these locations contain six 16-bit vectors that correspond to the six available interrupts. for eprom mode, byte 13 to byte 16383 (e61) or 32767 (e63) consists of on-chip eprom. at addresses 16384 (e61) or 32768 (e63) and above, the z86e61/e63 executes external pro- gram memory fetches. in romless mode, the z86e61/e63 can address up to 64 kbytes of program memory. program execution begins at external location 000c (hex) after a reset. figure 11. program memory configuration data memory ( dm ) the eprom version can address up to 48 kbytes (e61) or 32 kbytes (e63) of external data memory space beginning at location 16384 (e61) or 32768 (e63). the romless version can address up to 64 kbytes of external data memory. external data memory may be included with, or separated from, the external pro- gram memory space. dm , an optional i/0 function that can be programmed to appear on pin p34, is used to distinguish between data and program memory interrupt vector (upper byte) interrupt vector (lower byte) location of first byte of instruction executed after reset 65535 16384 (e61) 32768 (e63) 16383 (e61) 32767 (e63) 12 11 10 9 8 7 6 5 4 3 2 1 0 irq5 irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 external rom and ram on-chip prom
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 19 space (figure 12). the state of the dm signal is controlled by the type instruction being executed. an ldc opcode references program (dm inactive) memory, and an lde instruction references data (dm active low) memory. register file the register file consists of four i/0 port registers, 236 general-purpose registers, and 16 control and status registers (figure 13). the instructions can access regis- ters directly or indirectly through an 8-bit address field. the z86e61/e63 also allows short 4-bit register addressing using the register pointer (figure 14). in the 4-bit mode, the register file is divided into 16 working register groups, each occu- pying 16 continuous locations. the register pointer addresses the starting loca- tion of the active working register group. stack the z86e61/e63 has a 16-bit stack pointer (r255-r254) used for external stacks that reside anywhere in the data memory for the romless mode, but only from 16384 (e61) or 32768 (e63) to 65535 in the eprom mode. an 8-bit stack pointer (r255) is used for the internal stack that resides within the 236 general-purpose registers (r239-r4). the high byte of the stack pointer (sph bits 15-8) can be use as a general purpose register when using internal stack only.
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 20 figure 12. data memory configuration 65535 16384 (e61) 32768 (e63) 16383 (e61) 32767 (e63) 0 external data not addressable memory
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 21 figure 13. register file location identifiers r255 r254 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 r240 r239 r4 r3 r2 r1 r0 general purpose registers port 3 port 2 port 1 port 0 serial i/o timer mode timer/counter1 t1 prescaler timer/counter0 t0 prescaler port 2 mode port 3 mode port 0-1 mode stack pointer (bits 7-0) stack pointer (bits 15-8) register pointer program control flags interrupt mask register interrupt request register interrupt priority register spl sph rp flags imr irq ipr p01m p3m p2m pre0 t0 pre1 t1 tmr sio p3 p2 p1 p0
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 22 figure 14. register pointer functional description counter/timers there are two 8-bit programmable counter/timers (t0-t1), each driven by its own 6-bit programmable prescaler. the t1 prescaler is driven by internal or external clock sources; however, the to prescaler is driven by the internal clock only (fig- ure 15). the 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. when both the counters and prescalers reach the end of the count, a timer interrupt request, irq4 (t0) or irq5 (t1), is generated. the counter is programmed to start, stop, restart to continue, or restart from the initial value. the counters can also be programmed to stop upon reaching zero r253 r7 r6 r5 r4 r3 r2 r1 r0 (register pointer) the upper nibble of the register file address provided by the register pointer specifies the active working-register group. r15 to r0 the lower nibble of the register file address provided by the instruction points to the specified register. r15 to r0 r15 to r4 r3 to r0 ff f0 2f 20 1f 10 0f 00 i/o ports register group 0 register group 1 specified working register group
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 23 (single pass mode) or to automatically reload the initial value and continue count- ing (modulo-n continuous mode). the counter, but not the prescalers, are read at any time without disturbing their value or count mode. the clock source for t1 is user-definable and is either the internal microprocessor clock divided-by-four, or an external signal input through port 3. the timer mode register configures the external timer input (p31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. port 3 line p36 also serves as a timer output (tout) through which t0, t1, or the internal clock can be output. the counter/ timers are cascaded by connecting the to output to the input of t1. figure 15. counter/timers block diagram interrupts the z86e61/e63 has six different interrupts from eight different sources. the interrupts are maskable and prioritized. the eight sources are divided as follows: four sources are claimed by port 3 lines p33-p30, one in serial out, one in serial in, and two in the counter/timers (figure 16). the interrupt mask register globally +4 +4 +2 +2 osc internal clock external clock internal clock gated clock triggered clock t in p31 clock logic write read write internal data bus t1 initial value register pre1 initial value register t1 current value register 6-bit down counter 8-bit down counter 6-bit down counter 8-bit down counter t0 initial value register pre0 initial value register t0 current value register write read write internal data bus irq4 serial i/o clock irq5 t out p36
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 24 or individually enables or disables the six interrupt requests. when more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the interrupt priority register (refer to table 21 on page 16). all z86e61/e63 interrupts are vectored through locations in the program memory. when an interrupt machine cycle is activated, an interrupt request is granted. thus, this disables all of the subsequent interrupts, saves the program counter and status flags, and then branches to the program memory vector location reserved for that interrupt. this memory location and the next byte contain the 16- bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests need service. software initialized interrupts are supported by setting the appropri- ate bit in the interrupt request register (irq). internal interrupt requests are sampled on the falling edge of the last cycle of every instruction, and the interrupt request must be valid 5tpc before the falling edge of the last clock cycle of the currently executing instruction. figure 16. interrupt block diagram for the romless mode, when the device samples a valid interrupt request, the next 48 (external) clock cycles are used to prioritize the interrupt, and push the two pc bytes and the flag register on the stack. the following nine cycles are used to fetch the interrupt vector from external memory. the first byte of the inter- rupt service routine is fetched beginning on the 58th tpc cycle following the inter- global interrupt enable irq0-irq5 irq imr ipr priority logic vector select 6 interrupt request
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 25 nal sample point, which corresponds to the 63rd tpc cycle following the external interrupt sample point. clock the z86e61/e63 on-chip oscillator has a high gain, parallel resonant amplifier for connection to a crystal, lc, ceramic resonator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal should be at cut, 1 mhz to 16 mhz max; series resistance (rs) is less than or equal to 100 ohms. the crys- tal should be connected across xtal1 and xtal2 using the recommended capacitors (10 pf < cl < 100 pf) from each pin to ground (figure 17). actual capacitor value specified by crystal manufacturer. figure 17. oscillator configuration halt turns off the internal cpu clock but not the xtal oscillation. the counter/timers and external interrupts irq0, irq1, irq2, and irq3 remain active. the devices are recovered by interrupts, either externally or internally generated. an interrupt request must be executed (enabled) to exit halt mode. after the interrupt service routine, the program continues from the instruction after the halt. stop this instruction turns off the internal clock and external crystal oscillation, and reduces the standby current to 5 u a (typical) or less. the stop mode is termi- nated by a reset, which causes the processor to restart the application program at address 000ch . in order to enter stop (or halt) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. to do this, the user note: xtal1 xtal2 xtal1 xtal2 external clock lc clock pin 11 pin 11 c1 c2 pin 11 c1 c2 pin 11 l ceramic resonator or crystal xtal1 xtal2
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 26 must execute a nop (opcode = 0ffh ) immediately before the appropriate sleep instruction. i.e., ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode programming z86e61/e63 user modes the z86e61/e63 uses separate ac timing cycles for the different user modes available. table 22 on page 27 shows the z86e61/e63 user modes. table 23 on page 28 shows the timing of the programming waveforms. user mode 1 eprom read the z86e61 /e63 eprom read cycle is provided so that the user may read the z86e61 /e63 as a standard 27128 (e61) or 27256 (e63) eprom. this is accom- plished by driving the epm pin (p32) to vh and activating ce and oe . pgm remains inactive. this mode is not valid after execution of an eprom protect cycle. timing for the eprom read cycle is shown in figure 18. user mode 2 eprom program the z86e61/e63 program function conforms to the intelligent programming algo- rithm. the device is programmed with v cc , at 6.0v and v pp = 12.5v. programming pulses are applied in 1 ms increments to a maximum of 25 pulses before proper verification. after verification, a programming pulse of three times the duration of the cycles necessary to program the device is issued to ensure proper program- ming. after all addresses are programmed, a final data comparison is executed and the programming cycle is complete. timing for the z86e61/e63 programming cycle is shown in figure 18. user mode 3: prom verify the program verify cycle is used as part of the intelligent programming algorithm to insure data integrity under worst-case conditions. it differs from the eprom read cycle in that vpp is active and v cc must be driven to 6.0v. timing is shown in figure 18.
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 27 user modes 4 and 5: eprom and ram protect to extend program security, eprom and ram protect cycles are provided for the z86e61/e63. execution of the eprom protect cycle prohibits proper execution of the eprom read, eprom verify, and eprom programming cycles. execution of the ram protect cycle disables accesses to the upper 128 bytes of register memory (excluding mode and configuration registers), but first the user ? s program must set bit 6 of the imr (r251). timing is shown in figure 20 and figure 21. user modes. table 6 shows the programming voltage of each mode of the z86e61/e63. z86e63 signal description for eprom program/read the following signals are required to correctly program or read the z86e63 device. addr the address must remain stable throughout the program read cycle. data the i/o data bus must be stable during programming (oe high, pgm low, vpp high). during read the data bus outputs data. table 22. otp programming a a. i pp during programming = 40 ma maximum. i cc during programming, verify, or read = 40 ma maximum. user/test mode device pin no. user modes device pins port 1 cnfg data p33 p32 p30 p31 p20 v pp epm ce oe pgm addr v cc eprom read v ih v h c c. v h = 12.0 0.5 v v il d d. v il = 0 v v il v ih addr 5.0v out program v pp b b. v pp = 12.0 0.5 v. xv il v ih e e. v ih = 5 v. v il addr 6.0v in program verify v pp b xv il v il v ih addr 6.0v out eprom protect v pp b v h v h v ih v il xx f f. xx = irrelevant. 6.0v xx ram protect v pp xv h v ih v il xx f 6.0v xx
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 28 xclk a clock is required to clock the reset signal into the registers before program- ming. a constant clock can be applied, or the xclk input can be toggled a minimum of 12 cycles before any programming or verify function begins. the maximum clock frequency to be applied when in the eprom mode is 12 mhz. reset the reset input can be held to a constant low or high value throughout normal programming. it must be held high to program the eprom protect option bit. also, any time the reset input changes state the xclk must be clocked a mini- mum of 12 times to clock the reset through the reset filter. oe when the device is placed in eprom mode, the oe input also serves as the pre- charge for the sense amp. the precharge signal should be low for the first half of the stable address and high for the second half. the prechg signal is inverted from the oe signal so the oe should be high on the first half and low on the sec- ond half, or stable address. the eprom output data should be sampled during the second half of stable address. the access time of the eprom is defined in later sections. this two part calcula- tion of access time is required because this is a precharged sense amp with a pre- charge clock. table 23. timing of programming waveforms parameters name min max units 1address setup time2 s 2 data setup time 2 s 3v pp setup 2 s 4v cc setup time 2 s 5 chip enable setup time 2 s 6 program pulse width 0.95 ms 7 data hold time 2 s 8oe setup time 2 s 9 data access time 200 ns 10 data output float time 100 ns
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 29 figure 18. eprom read 11 over program pulse width 2.85 ms 12 epm setup time 2 s 13 pgm setup time 2 s 14 address to oe setup time 2 s 15 option program pulse width 78 ms table 23. timing of programming waveforms (continued) parameters name min max units address address stable address stable vih vil vih vil data invalid 0 min valid valid invalid vpp epm vh vil vh vil vih vil vih vil vih vil 0 min vcc 4.5 v ce oe pgm 5.5 v 12 9 3
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 30 figure 19. eprom program and verity address stable data stable data out valid 10 1 2 7 3 4 5 8 9 program cycle verify cycle 6 11
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 31 figure 20. programming eprom, ram protect, and 4k size selection address 003 5 address vil data vpp epm vih vil vcc ce oe pgm 12 rom protect programming ram protect programming 12 15 15 vih vih vh vil vih vh vih vh 6 v 4.5 v 14 3 4 vih vh vih vih vil
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 32 figure 21. programming eprom, ram protect, and 16k size selection address 008 5 address vil data vpp epm vih vil vcc ce oe pgm 12 rom protect programming ram protect programming 12 15 15 vih vih vh vil vih vh vih vh 6 v 4.5 v 14 3 4 vih vh vih vih vil
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 33 figure 22. intelligent programming flowchart absolute maximum ratings table 24. absolute maximum ratings symbol description min max units v cc supply voltage a -0.3 + 7.0 v t stg storage temp -65 +150 c device passed device failed start verify all bytes pass fail verify byte pass fail fail increment address verify all bytes fail yes addr = first location vcc = 6.0 v vpp = 12.5 v n = 0 program 1 ms pulse increment n n = 25? no pass yes verify one byte no prog. one pulse 3xn ms duration last addr? vcc=vpp=4.5v vcc=vpp=5.5v
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 34 stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for an extended period may affect device reliability. standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (figure 23). figure 23. test load diagram t a operating ambient temperature note b c a. voltages on all pins with respect to gnd. b. see see ? ordering information ? on page 62. table 24. absolute maximum ratings (continued) symbol description min max units i 150 pf from output under test
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 35 dc characteristics table 25. dc characteristics sym parameter t a = 0 c to +70 c typical @ 25 c units conditions min max max input voltage 7 v i in 250 a max input voltage 13 v p33-p30 only v ch clock input high voltage 3.8 v cc + 0.3 v driven by external clock generator v cl clock input low voltage -0.3 0.8 v driven by external clock generator v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage -0.3 0.8 v v oh output high voltage 2.4 v i oh = -2.0 ma v ol output low voltage 0.4 v i ol = +2.0 ma v rh reset input high voltage 3.8 v cc + 0.3 v v ri reset input low voltage -0.3 0.8 v i il input leakage -10 10 a0 v v in + 5.25 v i ol output leakage -10 10 a0 v v in + 5.25 v i ir reset input current -50 av cc = + 5.25 v, v rl = 0 v i cc supply current 50 25 ma @ 16 mhz 60 35 ma @ 20 mhz i cc1 standby current 15 5 ma halt mode v in = 0 v, v cc @ 16 mhz 20 10 ma halt mode v in = 0 v, v cc @ 20 mhz i cc2 a a. icc2 requires loading tmr (f1hh) with any value prior to stop execution. use this sequence: ld tmr,#00 nop stop standby current 20 5 a stop mode v in = 0 v, v cc @ 16 mhz 20 5 a stop mode v in = 0 v, v cc @ 20 mhz
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 36 figure 24. external i/o or memory read/write timing 9 d7-d0 in 10 15 11 13 3 16 8 6 7 d7-d0 out 14 17 17 2 12 18 1 4 a7-a0 a7-a0 ds (write) port 1 ds (read) as port 1 port 0, dm r/w
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 37 ac characteristics table 26. external i/o or memory read and write timing no symbol parameter ta = 0 c to +70 c units notes 16 mhz a a. all timing references use 2.0v for a logic 1 and 0.8v for a logic 0. 20 mhz min max min max 1 tda(as) address valid to as rise delay 20 26 ns note b,c b. timing numbers given are for minimum tpc. c. see table 11 2 tdas(a) as rise to address float delay 30 28 ns note b , c 3tdas(dr) as rise to read data req ? d valid 180 160 ns note b , c ,d d. when using extended memory timing add 2 tpc. 4twas as low width 35 36 ns note b , c 5 tdaz(ds) address float to ds fall00ns 6 twdsr ds (read) low width 135 130 ns note b , c , d 7 twdsw ds (write) low width 80 75 ns note b , c , d 8tddsr(dr) ds fall to read data req ? d valid 75 100 ns note b , c , d 9 thdr(ds) read data to ds rise hold time00nsnote b , c 10 tdds(a) ds rise to address active delay 35 48 ns note b , c 11 tdds(as) ds rise to as fall delay 30 36 ns note b , c 12 tdr/w(as) r/w valid to as rise delay 20 32 ns note b , c 13 tdds(r/w) ds rise to r//w not valid 30 36 ns note b , c 14 tddw(dsw) write data valid to ds fall (write) delay 25 40 ns note b , c 15 tdds(dw) ds rise to write data not valid delay 30 40 ns note b , c 16 tda(dr) address valid to read data req ? d valid 200 200 ns note b , c , d 17 tdas(ds)as as rise to ds fall delay 40 48 ns note b , c 18 tddm(as) dm valid to as fall delay 30 36 ns note b , c
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 38 table 27. clock dependent formulas number symbol equation 1 tda(as) 0.40 tpc + 0.32 2 tdas(a) 0.59 tpc - 3.25 3 tdas(dr) 2.83 tpc + 6.14 4 twas 0.66 tpc - 1.65 6 twdsr 2.33 tpc - 10.56 7 twdsw 1.27 tpc + 1.67 8 tddsr(dr) 1.97 tpc - 42.5 10 tdds(a) 0.8 tpc 11 tdds(as) 0.59 tpc - 3.14 12 tdr/w(as) 0.4 tpc 13 tdds(r/w ) 0.8 tpc - 15 14 tddw(dsw) 0.4 stpc 15 tdds(dw) 0.88 tpc - 19 16 tda(dr) 4 tpc - 20 17 tdas(ds) 0.91 tpc - 10.7 18 tddm(as) 0.9 tpc - 26.3
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 39 figure 25. additional timing 8 clock tin irqn 9 6 5 4 7 2 2 3 3 1 7
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 40 ac characteristics table 28. additional timing no symbol parameter ta = 0 c to +70 c units notes 16 mhz 20 mhz min max min max 1 tpc input clock period 62.5 1000 50 1000 ns note a a. clock timing references use 3.8v for a logic 1 and 0.8v for a logic 0. 2 trc,tfc clock input rise & fall times 10 15 ns note a 3 twc input clock width 21 37 ns note a 4 twtinl timer input low width 50 75 ns note b b. timing references use 2.0v for a logic 1 and 0.8v for a logic 0. 5 twtinh timer input high width 5tpc 5tpc note b 6 tptin timer input period 8tpc 8tpc note b 7 trtin,tftin timer input rise & fall times 100 100 ns note b 8a twil interrupt request input low times 70 50 ns note b ,c c. interrupt request through port 3 (p33-p31). 8b twil interrupt request input low times 5tpc 5tpc note b ,d d. interrupt request through port 30. 9 twih interrupt request input high times 5tpc 5tpc note b ,e e. interrupt references request through port 3.
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 41 figure 26. input handshake timing figure 27. output handshake timing table 29. handshake timing no symbol parameter t a = 0 c to +70 c data direction 16 mhz 20 mhz min max min max 1 tsdi(dav) data in setup time 0 0 in 2 thdi(dav) data in hold time 145 145 in 3 twdav data available width 110 110 in 4 tddavi(rdy) dav fall to rdy fall delay 115 115 in 5 tddavid(rdy) dav rise to rdy rise delay 115 115 in 6 tdrdy0(dav) rdy rise to dav fall delay 0 0 in 7 tdd0(dav) data out to dav fall delay tpc tpc out delayed dav next data in valid delayed rdy data in valid rdy (output) dav (input) data in 56 4 1 2 3 next data out valid data out valid delayed dav delayed rdy rdy (input) dav data out (output) 11 10 9 8 7
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 42 z8 control register diagrams figure 28. serial i/o register (f0 h : read/write) 8 tddav0(rdy) dav fall to rdy fall delay 0 0 out 9 tdrdy0(dav) rdy fall to dav rise delay 115 115 out 10 twrdy rdy width 110 110 out 11 tdrdy0d(dav) rdy rise to dav fall delay 115 115 out table 29. handshake timing (continued) no symbol parameter t a = 0 c to +70 c data direction 16 mhz 20 mhz min max min max r240 sio d7 d6 d5 d4 d3 d2 d1 d0 serial data (d0 = lsb)
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 43 figure 29. timer mode register (f1 h : read/write) figure 30. counter/timer 1 register (f2 h : read/write) r241 tmr d7 d6 d5 d4 d3 d2 d1 d0 0 no function 1 load t0 0 disable t0 count 1 enable t0 count 0 no function 1 load t1 0 disable t1 count 1 enable t1 count t in modes 00 external clock input 01 gate input 10 trigger input (non-retriggerable) 11 trigger input (regriggerable) t out modes 00 not used 01 t0 out 10 t1 out 11 internal clock out r242 t1 d7 d6 d5 d4 d3 d2 d1 d0 t1 intial value (when written) (range: 1-256 decimal 01-00 hex) t1 current value (when read)
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 44 figure 31. prescaler 1 register (f3 h : write only) figure 32. counter/timer 0 register (f4 h : read/write) figure 33. prescaler 0 register (f5 h : write only) r243 pre1 d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 t1 single pass 1 t1 modulo n clock source 1 t1 internal 0 t1 external timing input (t in ) mode prescaler modulo (range: 1-64 decimal 01-00 hex) r244 t0 d7 d6 d5 d4 d3 d2 d1 d0 t0 initial value (when written) (range: 1-256 decimal 01-00 hex) t0 current value (when read) r245 pre0 d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 t0 single pass 1 t0 modulo n reserved (must be 0) prescaler modulo (range: 1-64 decimal 01-00 hex)
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 45 figure 34. port 2 mode register (f6 h : write only) figure 35. port 3 mode register (f7 h : write only) r246 p2m d7 d6 d5 d4 d3 d2 d1 d0 p20 - p27 i/o definition 0 defines bit as output 1 defines bit as input r247 p3m d7 d6 d5 d4 d3 d2 d1 d0 0 port 2 pull-ups open drain 1 port 3 pull-ups active reserved (must be 0) 0 p32 - input p35 = output 1 p32 = dav 0/rdy0 p35 = rdy0/dav 0 00 p33 = input p34 = output 01 p33 = input 10 p34 = dm 11 p33 = dav 1/rdy1 p34 = rdy1/dav 1 0 p31 = input (tin) p36 = output (tout) 1 p31 = dav 2/rdy2 p36 = rdy2/dav 2 0 p30 = input p37 = output 1 p30 = serial in p37 = serial out 0 parity off 1 parity on
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 46 figure 36. port 0 and 1 mode register (f8 h : write only) r248 p01m d7 d6 d5 d4 d3 d2 d1 d0 po0 - po0 mode 00 output 01 input 1x a11-a8 stack selection 0 external 1 internal p17 - p10 mode 00 byte output 01 byte input 10 ad7 - ad0 11 high-impedance ad7 - da0, as , ds , r /w , a11-a8 a15- a12, if selected external memory timing 0 normal 1 extended p07 - p04 mode 00 output 01 input 1x a15 - a12
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 47 figure 37. interrupt priority register (f9 h : write only) figure 38. interrupt request register (fa h : read/write) r249 ipr d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority reserved = 00 c > a > b = 001 a > b > c = 010 a > c > b = 011 b > c > a = 100 c > b > a = 101 b > a > c = 110 reserved = 111 irq1, irq4 priority (group c) 0 irq1 > irq4 1 irq4 > irq1 irq0, irq2 priority (group b) 0 irq2 > irq0 1 irq0 > irq2 irq3, irq5 priority (group a) 0 irq5 > irq3 1 irq3 > irq5 reserved (must be 0) r250 irq d7 d6 d5 d4 d3 d2 d1 d0 irq0 = p32 input (d0 = irq0) irq1 = p33 input irq2 = p31 input irq3 = p30 input, serial input irq4 = t0 serial output irq5 = t1 reseserved (must be 0)
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 48 figure 39. interrupt mask register (fb h : read/write) figure 40. flag register (fc h : read/write) r251 imr d7 d6 d5 d4 d3 d2 d1 d0 1 enables irq5-irq0 (d0 = irq0) 1 enables ram protect 1 enables interrupts r252 spl flags d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 49 figure 41. register pointer register (fd h : read/write) figure 42. stack pointer register (fe h : read/write) figure 43. stack pointer register (ff h : read/write) r253 spl d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) register pointer 0 f4 r5 r6 r7 r254 spl d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp15 - sp8) r255 spl d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp7 - sp0)
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 50 dc characteristics supply current figure 44. typical i cc vs. frequency 40 30 20 10 0 2 4 6 8 10 12 14 16 18 20 frequency (mhz) i cc (ma) legend: a ? vcc = 5.6v c ? vcc = 4.4v a b c b ? vcc = 5.0v
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 51 standby current figure 45. typical i cc1 vs. frequency 12 10 8 6 4 2 i cc1 (ma) 0 2 4 6 8 10 12 14 16 18 20 frequency (mhz) legend: a ? vcc = 5.6v c ? vcc = 4.4v b ? vcc = 5.0v a b c
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 52 instruction set notation addressing modes. the following notation is used to describe the addressing modes and instruction operations as shown in the instruction summary (table 14). symbols. the following symbols are used in describing the instruction set. table 30. instruction set notation symbol meaning irr indirect register pair or indirect working register pair address irr indirect working register pair only x indexed address da direct address ra relative address im immediate r register or working register address r working register address only ir indirect register or indirect working register address ir indirect working register address only rr register pair or working register pair address symbol meaning dst destination location or contents src source location or contents cc condition code @ indirect address prefix sp stack pointer pc program counter flags flag register (control register 252) rp register pointer (r253) imr interrupt mask register (r251)
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 53 flags. control register (r252) contains the following six flags: affected flags are indicated by: condition codes symbol meaning c carry flag z zero flag s sign flag voverflow flag d decimal-adjust flag hhalf-carry flag symbol meaning 0clear to zero 1 set to one * set to clear according to operation - unaffected x undefined table 31. condition codes value mnemonic meaning flags set 1000 always true 0111 c carry c = 1 1111 nc no carry c = 0 0110 z zero z = 1 1110 nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 eq equal z = 1 1110 ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 54 0001 lt less than (s xor v) = 1 1010 gt greater than [z or (s xor v)] = 0 0010 le less than or equal [z or (s xor v)] = 1 1111 uge unsigned greater than or equal c = 0 0111 ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 0000 f never true (always false) table 31. condition codes (continued) value mnemonic meaning flags set
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 55 instruction formats figure 46. instruction formats ccf, di, ei, iret, nop, rcf, ret, scf one-byte instructions clr, cpl, da, dec, decw, inc, incw, pop, push, rl, rlc, rr, rrc, sra, swap jp, call (indirect) srp adc, add, and, cp, or, sbc, sub, tcm, tm, xor ld, lde, ldei, ldc, ldci ld ld djnz, jr stop/halt two-byte instructions three-byte instructions opc mode dst/src opc dst opc value src dst dst/src src/dst src/dst dst/src opc opc opc opc opc mode mode dst mode value dst/cc ra ffh 6fh 7fh or or or or or or or or 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 opc opc opc opc opc opc mode mode mode dst dst dst src src dst/src x address cc dau dal dau dal ld ld jp call dst/src dst dst dst dst src src adc, add, and, cp ld, or, sbc, sub, tcm, tm, xor adc, add, and, cp ld, or, sbc, sub, tcm, tm, xor value src opc opc dst
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 56 instruction summary note: assignment of a value is indicated by the symbol ? ? . for example: dst dst + src indicates that the source data is added to the destination data and the result is stored in the destination location. the notation ? addr (n) ? is used to refer to bit (n) of a given operand location. for example: dst (7) refers to bit 7 of the destination operand table 32. instruction summary instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh adc dst, src note a 1[ ] ****0* dst dst + src +c add dst, src note a 0[ ] ****0* dst dst + src and dst, src note a 5[ ] - * * 0 - - dst dst and src call dst da 06 ------ sp sp-2 irr d4 @sp pc, pc dst ccf ef *----- c not c clr dst r b0 ------ dst 0ir b11 com dst r 60 - * * 0 - - dst not dst ir 61 cp dst, src note a a[ ] ****-- dst - src da dst r 40 * * * x - - dst da dst ir 41
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 57 dec dst r 00 -***-- dst dst -1 ir 01 decw dst rr 80 -***-- dst dst-1 ir 81 di 8f ------ imr(7) 0 djnz r, dst ra ra ------ r r -1 r = 0-f if r 0 pc pc + dst range: +127, -128 ei 9f ------ imr(7) 1 halt 7f ------ inc dst r re -***-- dst dst + 1 r = 0 - f r20 ir 21 incw dst rr a0 -***-- dst dst + 1 ir a1 iret bf ****** flags @sp; sp sp + 1 pc @sp; sp sp + 2; imr(7) 1 jp cc, dst da cd ------ table 32. instruction summary (continued) instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 58 if cc is true, c = 0 - f pc dst irr 30 jr cc, dst ra cb ------ if cc is true, c = 0 - f pc pc + dst range: +127, -128 ld dst, src r im rc ------ dst src r r r8 rr r9 r = 0-f rxc7 xr d7 rire3 ir r f3 rre4 rire5 rime6 ir im e7 ir r f5 ldc dst, src r irr c2 ------ dst src ldci dst, src ir irr c3 ------ dst src r r + 1; rr rr + 1 nop ff ------ or dst, src note a 4[ 1 - * * 0 - - table 32. instruction summary (continued) instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 59 dst dst or src pop r 50 ------ dst @sp; ir 51 sp sp + 1 push src r 70 ------ sp sp-1; ir 71 @sp src rcf cf 0----- c 0 ret af ------ pc @sp; sp sp +2 rl dst r 90 ****-- ir 91 rlc dst r 10 ****-- ir 11 rr dst r e0 ****-- ir e1 rrc dst r c0 ****-- ir c1 sbc dst, src note a 3[ ] ****1* dst dst src c scf df 1----- c 1 sra dst r d0 ***0-- ir d1 srp dst im 31 ------ table 32. instruction summary (continued) instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh c 70 c 70 c 70 c 70 c 70
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 60 rp src stop 6f 1----- sub dst, src note a 2[ ] [[[[1[ dst dst src swap dst r f0 x * * x - - ir f1 tcm dst, src note a 6[ ] - * * 0 - - (not dst) and src tm dst, src note a 7[ ] - * * 0 - - dst and src xor dst, src note a b[ ] - * * 0 - - dst dst xor src a. these instructions have an identical set of addressing modes, which are encoded for brevity. the first op code nibble is found in the instruction set table above. the second nibble is expressed symbolically by a ? [ ] ? in this table, and its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the addressing modes r (destination) and ir (source) is 13. address mode lower opcode nibble dst src rr[2] rir[3] rr[4] rir[5] rim[6] ir im [7] table 32. instruction summary (continued) instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh 70 70
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 61 opcode map figure 47. opcode map 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 1234 678 abcde f 59 2 3 2 3 1 lower nibble (hex) upper nibble (hex) bytes per instruction 6.6 dec r1 6.5 dec ir1 8.5 add r1, ir2 10.5 add r1, 1m 6.5 rlc r1 6.5 add r1, r2 10.5 add ir2, r1 10.5 add r1, 1m 10.5 adc r1, 1m 10.5 adc r1, 1m 10.5 adc r2, r1 10.5 adc ir2,r1 6.5 adc r1, r2 6.5 adc r1, ir2 6.5 rlc ir1 6.5 ld r1,r2 6.5 ld r2, r1 10.5 add r2, r1 6.5 inc r1 8.5 da r1 6.6 wc ir1 6.5 sub r1, r2 0.5 sub r1, ir2 10.5 sub ir2, r1 10.5 sub r2, r1 10.5 sub r2, 1m 10.5 bub ir1, 1m 12/10.5 djnz r1, ra 12/0.0 ja cc, ra 6.5 ld r1, 1m 12/10.0 jp cc, da 6.5 inc r1 6.5 jp irr1 6.1 srp 1m 6.5 sbc r1, r2 6.5 sbc r1, ir2 10.5 sbc r2, r1 10.5 sbc ir2, r1 10.5 sbc ir1, 1m 10.5 sbc r1, 1m 8.5 da ir1 6.5 or r1, r2 6.5 or r1, ir2 10.5 or ir2, r1 10.5 or r2, r1 10.5 or r1, 1m 10.5 pop r1 10.5 pop ir1 6.5 and r1, r2 6.5 and r1, ir2 10.5 and r2, r1 10.5 and ir2, r1 10.5 and r1, 1m 10.5 and ir1, 1m 6.5 com r1 6.5 com ir1 6.5 tcm r1, r2 6.5 tcm r1, ir2 10.5 tcm r2, r1 10.5 tcm ir2, r1 10.5 tcm r1, 1m 10.5 tcm ir1, 1m 10/12.1 push r2 10/12.1 push ir2 6.5 tm r1, r2 10.5 tm ir1, 1m 6.5 tm r1, ir2 10.5 tm r2, r1 10.5 tm ir2, r1 10.5 tm r1, 1m 10.5 decw rr1 10.5 decw ir1 18.0 ldei r1, irr2 12.0 lde r1, irr2 18.0 ldei r1, irr2 12.0 lde r1, irr2 6.5 rl ir1 6.5 rl r1 10.5 incw ir1 10.5 incw rr1 6.5 cp r1, r2 6.5 cp r1, ir2 10.5 cp r2, r1 10.5 cp ir2, r1 10.5 cp r1, 1m 10.5 cp ir1, 1m 6.5 clr r1 6.5 clr ir1 6.5 xor r1, r2 6.5 xor r1, ir2 10.5 xor r2, r1 10.5 xor ir2, r1 10.5 xor r1, 1m 6.0 nop 10.5 xor ir1, 1m 8.5 swap ir1 6.5 rrc r1 6.5 rrc ir1 12.0 ldc r1, irr2 18.0 ldc ir1, irr2 10.5 ld r1, x, r2 6.5 sra r1 12.0 ldc r1, irr2 6.5 sra ir1 18.0 ldci ir1, irr2 20.0 call* irr1 20.0 call da 10.5 ld r2, x, r1 6.5 rr ir1 6.5 rr r1 10.5 ld r2, ir1 6.5 ld r1, ir2 10.5 ld ir2, r1 10.5 ld r2, r1 10.5 ld ir1, 1m 10.5 ld r1, 1m 8.5 swap r1 6.5 ld ir1, r2 6.0 stop 7.0 halt 6.1 di 6.1 ei 14.0 ret 16.0 iret 6.5 rcf 6.5 scf 6.5 ccf pipeline cycles execution cycles mnemonic first operand upper opcode nibble lower opcode nibble second operand 10.5 cp r1, r2 a 4 legend: r = 8-bit address r = 4-bit address r1 or r1 = dst address r2 or r2 = src address sequence: opcode, first operand, second operand note: blank areas not defined *2-byte instruction appears as a 3-byte instruction
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 62 package information figure 48. 40-pin dip package diagram figure 49. 44-pin plcc package diagram
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 63 figure 50. 44-pin lqfp package diagram ordering information for fast results, contact your local zilog sales office for assistance in ordering the part desired. z86e61 16 mhz 20 mhz 40-pin dip 44-pin plcc 40-pin dip 44-pin plcc z86e6116psc Z86E6116VSC z86e6120psc z86e6120vsc z86e63 16 mhz 20 mhz 40-pin dip 44-pin plcc 40-pin dip 44-pin plcc z86e6316psc z86e6316vsc z86e6320psc z86e6320vsc
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 64 codes preferred package p = plastic dip v = plastic chip carrier temperature s = 0 c to +70 c speeds 12 = 16 mhz 16 = 20 mhz environmental c = plastic standard example: environmental flow temperature package speed product number zilog prefix is a z86e61, 16 mhz, plcc, 0 c to +70 c, plastic standard flow z 86e61 16 p s c
z86e61/e63 cmos z8 16k/32k eprom microcontroller ps014401-1001 65

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