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? integrated circuits group id 242 se rie s fla sh m emo ry card (model n umb ers : id 242 xx x ) spec no.: c ps 00 0 2- 00 2 issue date: ma y , 199 8 p r oduct overview
sharp id242 series product overview l handle this document carefully for it contains material protected by international copyright law. any repro- duction, full or in part, of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2). even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). * office electronics * instrumentation and measuring equipment * machine tools * audiovisual equipment * home appliances * communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibil- ity for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * control and safety devices for airplanes, trains, automobiles, and other transportation equipment * mainframe computers * traffic control systems * gas leak detectors and automatic cutoff devices * rescue and security equipment * other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. * aerospace equipment * communications equipment for trunk lines * control equipment for the nuclear power industry * medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. cpsoooz-002 8 may.
shari= id242 series product overview 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. contents introduction.. ............................................................................................................... p. features ....................................................................................................................... p. block diagram ............................................................................................................ p. pin connections ........... ............................................................................................... p. signal description ...................................................................................................... p. functions.. ................................................................................................................... p. 6. 1 common memory.. ......................................................................................... p. 6. 2 attribute memory ........................................................................................... p. 6. 3 function table ................................................................................................ p. card information structure (cis) ............................................................................... p. card control ............................................................................................................... p. 8. 1 reset ............................................................................................................. p. 8. 2 status register ................................................................................................ p. 8. 3 write protect switch.. ..................................................................................... p. 8. 4 identifier codes.. ........ . . ................................................................................... p. component management register (cmr) ................................................................. p. command definitions.. ............................................................................................... p. electrical specifications ............................................................................................. p? 11. 1 absolute maximum ratings ........................................................................... p. 11. 2 recommended operating conditions.. ........................................................... p. 11. 3 capacitance ..................................................................................................... p. 11. 4 ac input/output test conditions .................................................................. p. 12. dc characteristics ...................................................................................................... p. 13. ac characteristics ...................................................................................................... p. 13. 1 common memory read operations.. ............................................................. p. 13. 2 command write operations : common memory.. ........................................ p. 13. 3 attribute memory read operations ............................................................... p. 13. 4 attribute memory write operations .............................................................. p. 13. 5 power-up/power down .................................................................................. p. 14. specification changes ................................................................................................ p. 15. other precautions.. ...................................................................................................... p. 16. external diagrams ...................................................................................................... p. 3 3 4 5 6 7 7 8 9 9 12 12 12 12 12 14 16 17 17 17 17 17 18 20 20 22 28 29 30 31 31 32
shari= id242 series product overview 3 - 1. introduction this datasheet is for sharp?s id242 series flash memory card. this datasheet provides all ac and dc character- istics (including timing waveforms) and a convenient reference for the device command set and the card?s inte- grated registers(including the flash memory?s status registers). this datasheet provides description of the meth- ods which are very helpful for customer to use the card. 2. features 2.1 type flash memory card 2.2 overview erase unit program/erase cycles external dimensions 250ns(@vcc=3.3v) 64k word blocks 100,000cycles/block pcmcia type 1 54.0x 85.6x 3.3mm tloso-01 2.3 interface parallel i/o interface 2.4 function table see function table in page. 9 2.5 pin connections see pin connections in page. 6 2.6 type of connector conforms to pcmcia pc card standard 95 card use connector (card connector: jc20-j68s-nb3 jae or fcn-568j068-g/o fujitsu) 2.7 operating temperature 0 to 60c 2.8 storage temperature -20 to 65c 2.9 not designed for rated radiation hardened. - cps0002.002bmay,19!
sharp id242 series product overview 4 3. block diagram ,r d<15:0> a<25:0> reg# cel# , ce2# 1 1 we# , oe# rdpsyk reset, : ? wp a+ control logic vppx vcc ii,t t? cl flash memory data add ce# i t4 rp# we# ry/ry# oe# t ii, t vpp2 vcc vppl vcc t t flash memory data *i * ce# add +- + we# rp# -- + oe# ryrby# --( vppl vcc t t flash memory data c = + ce# add + - + we# rp# -- + oe# ryiby# +? . ii. i , i : i i ii i =rlc vppl b vpp2 b vpp1 vcc vpp2 vcc i i i i t :lash memory data 4 add + - 4 rp# -- ry/by# - i i i i ry/by# oe# i i __*1 oe# eeprom - ce# data m b we# - oe# add v . cdl#, cdl% i i i i * i i i , i * i 9 i i , i i i i i i i i i i i i i figure 1. block giagrarn
shari= id242 series product overview 5 4. pin connections table 1. pin connections ;,? signal i/o function active low high 1 35 ignd 1 iground 1 39 id,, i i/o i data bit 13 i 43 ivs,# i i 0 voltage sense 1 i 44 irfu 1 1 reserved 1 1 reserved i i 1 address bit 17 i 45 irfu 1 46 ia,, 54 43 55 a74 i address bit 23 i address bit 24 1 56 ia,, i i 1 address bit 25 1 i i reset 0 voltage sense 2 i 58 ireset 57 vs,# i 62 ibvd, i 0 battery boltage detect 2 63 bvd, 0 battery boltage detect 1 data bit 8 64 dr i/o 65 dq i/o data bit 9 66 i/o data bit 10 d,ll 67 cd,# i - 68 ignd 0 card detect 2 1 ground cpsooo2-002 @ may.1 998
sharp id242 series product overview 5. signal description table 2. signal description symbol l/o electrical interface function address inputs: ao-azs du-d15 1 pull-down these are address bus lines which enable direct addressing of memory (250k q @ vcc=sv) on the card. signal ai) is not used in word access mode. the system should not access memory beyond the card?s density. because the upper addresses are not decoded. data input/output: 1/o pull-down (2?0k ? @vcc=?v) de through dls constitute the bi-directional data bus. dig is the most significant bit, cei#,cez# oe# we# 1 pull-up card enable i & 2: (250k q @vcc=sv) cei# enables do-d7, ce2# enables dx-dig. 1 pull-up output enable: (250k q @ vcc=sv) active low signal gating read data from the memory card. 1 pull-up wrlte enable: (250k 52 @ vcc=sv) active low signal gating write data to the memory c?ard. ready/busy output: indicates status of internally timed erase or write activities. ld242 series has two types of ready/busy output mode; pcmcla mode and high-performance mode. rdy/bsy# 0 in pcmcla mode, a high output indicates the memory card is ready to accept accesses. a low output indicates that a device in the memory c,ard is busy. in high-performance mode, the card outputs low when the card is in default state. a high output indicates at least one of flash memory devices in the card comes to be ready to accept accesses. card detect 1 & 2: these signals provide for card insertion detection. the signals are cdt#, cd2# 0 pull-down ow connected to ground internally on the memory card, and will be forced low whenever a card is placed in the socket. the host socket interface circuitry shall supply 10k or larger pull-up resistors on these signal pins. o lowpull-down ow wrlte protect: wp high:pull-up 1ookw write protect reflects the status of the write protect switch on the memory card. wp set to high = write protected. vppi, vw2 write/erase power supply 1 & 2: vcc card power supply: gnd ground: reg# 1 pull-up reglster select: (250kw @vcc=sv) provides access to attribute memory when reg# is low. reset 1 pull-up reset: (250kw @vcc=sv) active high signal for placing card in power-on default state. bvdt, bvd2 0 pull-up 1ookw battery voltage detect 1 & 2: these signals are pulled high to maintain sram card compatibility. voltage sense 1 & 2: vsi#: pull-down or notifies the host socket of the cls?s vcc requirements. vs i# is pulled- vsi#, vs2# 0 n.c. down to ground when using the standard cls, that indicate 3.3v vsb: n.c. operating is available. and when using the eeprom for cls, the vs2# is open. that indicate the available operation voltage is 5v only. rfu reserved for future use cpsoooz-002@mav.1991
sharp id242 series product overview 7 6. functions 6.1 common memory 6. 1. 1 common memory architecture figure 2 shows common memory architecture of id242 series flash memory card. device pair is consisted of two pieces of flash memory devices. each device has individually erasable and lockable blocks. all blocks are divided into odd bytes and even bytes. each device pair and block is selected by address bits. table 3 shows definitions of address bits. cps0002-002omay.1991 3 f100'2.0: (a) for 2, 4, 8, 1omb f10580' (b) for 16mb, 20mb figure 2. common memory architecture table 3. address difinitions address pifinitions 2mb - iomb 16mb ,20mb select even / odd byte in the byte access mode. a0 1 select address in the block. i a16-al i select a block. 1 a20-a17 1 a21-a17 1 1 select a device pair. 1 a25-a21 1 a25-a22 1 t1051-01 -
sharp id242seriesproductoverview 8 6. 1. 2 erase erase is executed one block at a time. erasable block size is 64k bytes in byte access mode and 128k bytes in word access mode. 6. 1. 3 address decoding the higher address area of id242 series flash memory card which goes beyond common memory area is not decoded in common memory access. it means that the system will access to random memory address of the memory card even if system will try to access to the memory address which exceeds memory capacity of the card. please do not access to the memory address which goes beyond memory capacity of the card. as an enhanced function, the memory card enables to output invalid data (either of ooooh or ffffh) when system will access to the memory address which exceeds memory capacity of the card. please contact our sales & market- ing support to find concrete way of setting. 6.2 attribute memory figure 3 shows attribute memory map of id242 series flash memory card. attribute memory is contained within the card control logic. attribute memory contains the card information structure (cis) and component man- agement registers (cmrs). the cis contains tuple information and is located at even byte addresses beginning with address ooooh (please refer to section 7). the standard cis of id242 series flash memory card is hardwired and is for read only. as an enhanced function, the hardwired cis area is switchable to eeprom so that customer can program required cis. please contact our sales & marketing support to find concrete way of setting. the cmrs are located at even byte addresses beginning with address 4000h (please refer to section 9). address r-------------, i i i i i i ' 004200h r------ i component i management i i registers c------ _ 004000h i i i i i r------ i 000200h i card i i information i structure ooooooh ------- odd even f1003-01 figure 3. attribute memory map cpsoooz-002@ may. 1998
shari= id242seriesproductoverview 6.3 function table 6.3.1 common memory access table 4. common memory access 6.3.2 attribute memory access table 5. attribute memory access xxx:output data is invalid. the standard cis is for read only. write operation is only for cmrs and cis on eeprom 7. card information structure (cis) the cis is contained within attribute memory (please refer to section 6.2). table 6 shows standard cis tuples, but it is for read only. as an enhanced function, the hardwired cis area is switchable to eeprom so that customer can program required cis. please contact our sales & marketing support to find concrete way of setting.
sharp id242 seriesproductoverview 10 table 6. standard cis address value description 46h 53h s :product info 48h 48h h 52h 54h 56h 58h ah 5ch 5eh 60h 62h 64h 49h i 44h d 32h 2 34h 4 53h s 52h r 20h space ooh end text 53h s :maker info 48h h 66h 1 41h ia 68h 52h r 6ah 1 50h ip 6ch 20h space 6eh 43h c 70h 4fh 0 cps0002.002@may.i9i 84h i ooh iend text 86h 88h ffh end of tuple 1ah configuration info last index of configuration table 92h i 40h icmrs base adress(msb) i configuration table entry 1 -
sharp id242 series product overview table 8. standard cis (continued) address 1 value 1 description 1 address 1 value 1 description i i a4h 1 och ]icc static 1.2ma t 1oh tuple link 04h iindex 104h io6h a6h a8h 06h icc average looma 06h icc peak looma 02h vcc & vpp 79h iparameter selection 108h ioah ioch i oeh , aah 1 23h ~icc powerdown 5oma t i i ach 1 79h [parameter selection t i i aeh i d5h ivpp voltage 5v t 1loh boh b2h 7dh nc ok 1bh ipp static 15oma 7dh iicc average 90ma 7dh ~icc peak 90ma 112h il4h b4h b6h 75h ipp average 80ma 75h ipp peak 80ma 116h 1bh icc powerdown 15oma 79h parameter selection i i b8h i 52h 11pppowerdown 50ma t 118h 1lah i 8eh lvpp voltage 12v bah bch 1bh configuration table entry 2 ofh tuple link 1lch 7dh nc ok 1bh ipp static 15oma i i beh i 02h iindex 1leh 120h 122h 124h 126h 128h 12ah 12ch 12eh 130h 35h ipp average 30ma 35h ipp peak 30ma 52h ipp powerdown 50ma ooh null ooh null 1eh device geometry 06h tuple link 02h bus: 2bytes 1 lh erase block: 64kbvtes i i cah i 06h iicc peak looma cch ceh 23h icc powerdown 50ma 79h parameter selection doh d2h d4h 8eh vpp voltage 12v 7dh ncok 1bh ipp static 1xhna 132h 1 olh read size: lbyte 134h i olh iwrite size: lbyte i d6h i 35h 11pp average 30ma i 136h 138h 13ah 13ch 13eh 14oh olh partation: lblock olh non-interleaved 20h manufacturer id 04h tuple link l boh manufacturer code ooh d8h dah dch deh eoh e2h 35h ipp peak 30ma 52h ipp powerdown 50ma 1bh configuration table entry 3 1 lh tuple link 03h index 02h vcc & vpp manufacturer info: 06h 2mb 07h 4mb 09h 8mb oah 1omb odh 16mb oeh 20mb 33h manufacturer info: dvo e4h e6h e8h 79h parameter selection b5h 1eh vcc voltage 3.3v 142h 144h 146h 21h function identification 02h tuple link olh ifunction: memory ooh isystem init: none 148h 14ah i f4h f6h fah b5h 9eh vpp voltage 3.3v 1bh ipp static 15oma i 14ch 14eh ffh end of cis i fch 75h ipp average 80ma i feh 75h ipp peak 80ma iooh 52h ipp powerdown 5orna 102h 1bh configuration table entry 4 i. cpsoooz-002 0 may. 199
sharp id242 series product overview 12 8. card control 8. 1 reset the card is in initial state directly after power-up. but we recommend to do reset operation after power-up to make sure to initialize the card. during block erase, byte write, or lock-bit configuration modes, an active reset will abort the operation. rdyi bsy# remains low until the reset operation completes. memory contents being altered are no longer valid; the data may be partially erased or written. the host must wait after reset goes to logic-low (vu) before it can write another command, as determined by tphwl. it is important to assert reset to the card during a system reset. if a cpu reset occurs without a card reset, the host will not be able to read from the card if that card is in a different mode when the system reset occurs. for example, if an end-user initiates a host reset when the card is in read status register mode, the host will attempt to read code from the card, but will actually read status register data. sharp?s id242 series flash memory card allows proper card reset following a system reset through the use of the reset input. 8. 2 status register each flash memory device in the card has status register. the status register may be read to determine when a write, block erase, or lock-bits configuration is complete, and whether that operation completed successfully (please refer to table 10). it may be read at any time by writing the read status register command (70h, 7070h) into the cui. in word access mode, the status register data of even byte devices are output to d7-0,and the status register data of odd byte devices are output to d15-8. 8. 3 write protect switch the id242 series flash memory card has a write protect switch on the back of the card. when the switch is in the write protect position, the card blocks all writes to the common and attribute memory without card management registers region (see figure 5). 8. 4 read identifier codes / lock bits information manufacture code and device code are contained within each flash memory device in the memory card. the identifier code operation is initiated by writing the read identifier codes command (90h, 9090h) into the cui of each memory device. the specific address of each device is necessary to be selected to read these codes (table 8). i f1005-01 m writeble position i i i write protz&ition note: the write protect switch is shown by the black square. figure 4. write protect switch cps0002.002@may.1998
sharp id242 series product overview 13 table 7. status register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sr.7 wsms sr.6 ess sr.5 eclbs sr.4 bwslbs sr.3 vpps sr.2 bwss sr.l dps sr.0 rfu sr.7 =write state machine status notes: i = ready 0 = busy chech rdy/bsy# or sr.7 to determine block erase, sr.6 =erase-suspend status word/byte write, or lock-bit configuration completion. sr.6-0 are invalid while sr.7=?0?. i = erase suspended 0 = erase in progress/completed if both sr.5 and sr.4 are ? 1 ?s after a block erase or lock- sr.5 =erase and clear lock-blts status bit configuration attempt, an improper command 1 = error ln block erasure or clear lock-bits sequence was entred. 0 = successful block erase or clear lock-bits sr.3 does not provide a continuous indication of v,, sr.4 =byte write and set lock-bit status level. the wsm interrogates and indicates the v,, level 1 = error in byte write or only after block erase, word/byte write, set set block/master lock-bit block/master lock-bit, or clear lock-bits command 0 = successful byte write or sequences. sr.3 is not guaranteed to reports accurate set block/master lock-bit feedback only when v,,=v,,,,,,,,. sr.3 =vpp status 1 = vpp low detect, operation abort sr. 1 does not provide a continuous indication of master 0 = vpp ok and block lock-bit values. the wsm interrogates the master lock-bit, block lock-bit. and rp# only after block sr.2 =byte write suspend status erase, word/byte write, or lock-bit configuration 1 = byte write suspended command sequences. if informs the system, depending 0 = byte write in progress/completed on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or rp# is not 12v. reading sr. 1 =device protect status the block lock and master lock configuration codes after 1 = master lock-bit,block lock-bit and/or writing the read identifier codes commnad indicates rp# lock detected, operation abort master and block lock-bit status. 0 = unlock sr.0 =reserved for future enhancements sr.0 is reserved for future use and should be masked out when polling the status register. table 8. identifier codes / lock bits block lock configuration (x: select block) d7-d i: reserved note: a0 is ignored in word access mode. and d15-d8 outputs the odd byte data. dpa: address as select device pair blkd: block lock configuration data mlkd: master lock configuration data t1052-01 cpsooo2-0028 may. 1999
shari= id242 series product overview 9. component management registers (cmr) component management registers (cmr) are mapped at even byte locations beginning at address 4000h in attribute memory. 9. 1 9. 2 9. 3 9. 4 configuration option register (address4000h) address bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit. 1 bit.0 4000h sreset reserved sreset: l=reset state o=end reset cycle card configuration register (address:4002h) address 4002h bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit. 1 bit.0 reserved pwdn reserved pwdn: l=power-down device pairs that apointed by sleep control register(4118h-411ah) are in power- down. o=power-up socket and copy register (address:4006h) address bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit.1 bit.0 4006h reserved copy no. soket no. soket no.: socket number copy no.: copy number the card may use to distinguish between similar cards installed in a system. tlo53.01 card status register (address:41 ooh) address 41ooh bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit. 1 bit.0 adm ads sreset cmwp pwdn ciswp wp rdy/bsy adm: ored value of the ready/busy mask register. 1 = any device is masked. 0 = all devices are not masked. ads: ored value of the sleep control register. i = any device-pair is controled power-down by bit.2 of the card configuration register. sreset: reflects the bit.7 of the configuration option register. cmwp: reflects the bit.1 of the write protection register. pwdn: reflects the bit.2 of the card configuration register. ciswp: reflects the bit.0 of the write protection register. wp: indicates the write protect switch status. i = write protect switch: on i = write protect switch: off rdy/bsy: reflects the ready/busy status register. 1 = all devices are ready. 0 = any device is busy. cpsooo2.002 @ may. 1991
shari= id242 series product overview 15 9. 5 write protection register (address:41 04h) address bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit.1 bit.0 4104h reserved blkbn cmwp ciswp blkbn: block locking enable 1 = enable block locking 0 = all blocks unlocked cmwp: common memory write protect 1 = common memory without cis region in write protect status ciswp: common memory cis write protect i = common memory cis in write protect status note: id242 series ignores blkbn bit. block locking is always enable. 9. 6 sleep control register (address:41 18h-411 ah) address 4llah 4118h bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit. 1 bit.0 reserved reserved devlo/ll dev8/9 dev6/7 dev4/5 dev2/3 devo/l 1= select sleep mode device-pair if set to ?l?, the corresponding device-pairs are putted into deep power-down mode by pwdn bit of configuration status register. tl047.01 9. 7 ready/busy mask register (address:41 20h-4122h) address 412231 4120h bit.7 dev7 bit.6 bit.5 bit.4 bit.3 bit.2 bit. 1 bit.0 reserved devll devlo dev9 dev8 dev6 dev5 dev4 dev3 dev2 devl devo 1 =mask the rdylbsy# the corresponding device?s rdy/bsy# signals to set bit are ignored for card?s rdy/bsy# output. t1040.01 9. 8 ready/busy status register (address:41 30h-4132h) address 4132h 4130h bit.7 dev7 bit.6 bit.5 bit.4 bit.3 bit.2 bit. 1 bit.0 reserved devll devlo dev9 dev8 dev6 dev5 dev4 dev3 dev2 devl devo 1 =ready o=busy each bit indicates the corresponding device?s rdy/bsy# signal. tl041.01 9. 9 ready/busy mode register (address:4140h) address 4140h bit.7 bit.6 bit.5 bit.4 reserved rack: ready acknowledge bit bit.3 bit.2 bit. 1 bit.0 rack mode must-clear this bit after receiving ready status to prepare for next device?s ready transition. mode: rdy/bsy# mode 1 = high-performance mode 0 = pcmcia mode t1055.01 cps0002-002@may.l99i
sharp id242seriesproductoverview io. command definitions device operations are determined by writing specific commands to the command user interface. table 9 defines the commands. table 9. command definitions -r 1 command second bus cycle gate first bus cycle address 1 data operation write 1 write e 2 write write 3peration address data da ffh (pfl+) da da da wa ba da 90h (9090h) 70h (707oh) 50h (5050h) 40h (4040h) or 1oh (1010h) 20h (2020h) boh (boboh) da doh (dodoh) ba da da 60h (6060h) 60h (6060h) 60h (6060h) ( read array / reset read identifier codes read read read status register zlear status register wa 1 wd wordlbyte write read 3 write i write block erase 3 write 3 write 3 write write 4 write write data block erase and word/byte write suspend block erase and word/byte write resume set block lock-bit write set master lock-bit write write clear block lock-bit address ia =identifier code address wa =write address id wd =identifier codes =write data ba da =block address =device address srd =data from status register note: 1. following the read identifier codes command, read operations access manufacture, device, block lock, and master lock codes. 2. status register may be read to determine when a write, block erase, or lock bit configuration is complete, and whether that operation completed successfully. 3. if the block is locked, block erase or write operations are desabled. 4. this command is not available. cpsoooz-002@ may.1991
sharp id242 series product overview 11. electrical specifications 11. 1 absolute maximum ratings notes: 1. operating temperature is for commercial product defined by this specification. 2. all specified voltages are with respect to gnd. during transitions, this level may undershoot to -2.0~ for periods 4!0ns or overshoot to vcc+2.ov for periods <20ns. il. 2 recommended operating conditions 11.3 capacitance parameter input capacitance input/output capacitance symbol min cm - c,? - typ max 15 - 25 - unit pf pf ta=25?c, f=lmhz condition v,,=o.ov vo,,=o.ov 11. 4 ac input/output test conditions vcc=3.3v-+q.3v ;oy)lp$iq+~ vcc=5vk5% 3s or vcc=5vs-lo% 1,5 t$q$=xt f,008-0, figure 5. transient input/output reference waveform figure 8 shows input/output level and test level for ac test. input rise and fall times (10% to 90%) < 10ns. ws""uz-owdmay.199<
sharp id242 series product overview 18 12. dc characteristics (ta = 0 to 60c) no- te -i- iym bol ri2 joli vtohi doh2 ccs ccd ccr ccw i i i 4 4 4 \ 1 ?ce 679 tws ?xs ?lko test condition t1042-01 parameter nput low voltage nput high voltage nput low current nput high current jutput low voltage jutput high voltage ?cc stand-by current \, ?cc deep power-down c hrrent \ ?cc read current v ?cc word write or set l .ock-bit current v cc block erase or c lear lock-bit current lock erase suspend :ontinue to next page i 2 3 3 2 4,5 4 5 68 69 6 cpsoooz-0028 may. 199.9
shari= id242seriesproductoverview dc characteristics (continued) (ta = 0 to 60c: t/+kaivic ick , bol , te , ry min max , ;i;., v k;; 1 unit 1 test condition i i vrrs vcc \ t,,stmd-by or read c :urrent \ ipp deep power-down c :urrent 6 4mb 1 i 0.8 i 8mb 1.6 1.6 ma vpf>vcc 1omb 2.0 2.0 ma 16mb 1.6 1.6 ma 20mb 1 i 2.0 i i 2.0 ua ---i ua 6 ? \ word write or set l zk-bit current 6.9 vrr=5.0v* 10% \ i,,,, block erase or c blear lock-bit current v i,+, word write or b lock erase suspend c ?urren t v 6.9 40 40 ma ivrr=5.0vt 10% 32 32 ma i vrr=l2.ovf 5% 2mb 400 400 ua 4mb 430 430 ---i ua 8mb 500 500 ua 4 vw5 vcc 1omb 530 530 ba 16mb 500 500 ua 20mb 1 i 530 i i 530 ua i 6 2mb i i 0.4 i i 0.4 4mb 1 i 0.8 i 1 0.8 8mb 1 i 1.6 i i 1.6 vpp>vcc 1omb 2.0 2.0 16mb 1.6 1.6 20mb 2.0 2.0 ipp lockout voltage vrtlk 7,9 i 1 1.5 1 1 1.5 1 v 1 71048-01 note: 1. these parameters are applied to all input pins and all i/put/output pins in input mode. 2. these parameters are applied to an-az5 and do-d,, in input mode. 3. these parameters are applied to ce,#.cez#,we#,oe#,reg# and reset. 4. these parameters are applied to rdy/bsy#. 5. these parameters are applied to do-d,, in output mode. 6. all currents are in rms unless otherwise notes. 7. block erase, word/byte write, and lock-bit configurations are inhibited when v,,, 5 vfplk, and guaranteed in the vpp voltage is vpi?i, vfpz or vfi.i. 8. automatic power savings(aps) reduces typical i cck to 30ma at vcc=sv and 20ma at vcc=3.3v in static operation. 9. sampled. cpsooo2.002@ may. 1998
id242 series product overview 20 13. ac characteristics testing conditions : 1) input pulse level 2) input rise/fall time 3) input/output timing reference level 4) output load (including scope and jig capacitance) 13. 1 common memory read operations parameter read cycle time address access time ce# access time oe# access time output disable time from cel#,ce2# * output disable time from oe# * output enable time from cei#,ce2# output enable time from oe# data valid time from address change +:time until output become 1.5 to 3.w (@vcc=5v~5%,vcc=5v+10%) 0 to 3.ov (@vcc=3.3+0.3v) ions 2.5v (@vcc=5v~5%,vcc=sv~lo%) 1.5v (@vcc=3.3v+o.3v) lttl+loopf (@vcc=~v+~%,vcc=~v+io%) lttl+sopf (@vcc=3.3v+o.3v) (ta = 0 tc symbol vcc=3.3vi on vcc=sv~ 5% vcc=w-t 10% ieee jeida/ pcmcia min max min max min max t avav tcr 250 - 150 - 160 - t avqv t,(a) - 250 - 150 - 160 t elqv t,(ce) - 250 - 150 - 160 . . . 1 t,(oe) 1 - 1 125 1 - 1 75 1 - 1 80 khqz itdidce) 1 - 1 100 1 - 1 75 i - 1 80 t - - - 80 ghqz qoe) 100 75 te lqnz tc,,( ce) 5 - 5 - 5 - wv 0 - 0 - 0 - , floating. (the output voltage is not defined.) 60c) - ~ unit ns rio43ai cps0002.002@may.1991 9
sharp id242 series product overview address cel#, ce2# oe# dout figure 6. ac waveforms for read operations note) 1. we# = ?high?, during a read cycle. 2. either ?high? or ?low? in diagonal areas. 3. the output data becomes valid when last interval, ta (a), ta (ce) or ta (oe) have concluded. cps0002-002qmay.199
sharp id242 series product overview 22 13.2 command write operations : common memory 13. 2. 1 we# controlled write operations parameter write cycle time address setup time write recovery time data setup time for we# data hold time oe# hold time from we# ce# setup time for we# address setup time for we# write pulse width we# high to rdy/bsy# going low reset recovery time vpp setup time vpp hold time word/byte write time block erase time jet lock-bit time zlear block lock-bits rime nor-d i byte suspend latency rime to read gase suspend latency time o read (vcc=3.3vi 0.3vta=o to 60c) t\ ?hrh i t whrhz vw=3.3v k 0.3% vpp=w+ 10% vw= 12v -t 5% vpp=3.3vi- 0.3% vpp=5vt 10% vrr=12v* 5% 10.0 ps 9.3 p s 10.4 ps 21.1 ps 17.2 l-1 s 17.2 i-is t1044.01 cpsoooz-0028 may. 199
shari= id242 series product overview parameter write cycle time address setup time write recovery time data setup time for we# data hold time oe# hold time from we# ce# setup time for we# address setup time for we# write pulse width we# high to rdy/bsy# going low reset recovery time vpp setup time vpp hold time word/byte write time block erase time set lock-bit time clear block lock-bits time word i byte suspend latency time to read erase suspend latency time to read (vcc=5vi 5%, vcc=5vi losta = 0 i 60c) unit ns ns ns ns ns ns ns ns ns ns ps ns ns ps ps s s ps r1049-oi cpsoooz-0026may.199
sharp id242 series product overview 1. 2. 3. 4. 5. 6. vih address vn. vih ce#, ce2# vil hh oe# vtl ?valid data ~ sm tphwl hvml voh rdyib sy# vol i , i vih reset vil it tqvvl -- vpp i .zj vpp fl figure 7. ac waveforms for write operations (we# controlled) note) while the data signal is in output mode, do not apply an opposite phase input signal. cps0002.0020may.199
sharp id242seriesproductoverview 13. 2. 2 ce# controlled write operations parameter write cycle time address setup time write recovery time data setup time for ce# data hold time oe# hold time from ce# we# setup time for ce# address setup time for ce# write pulse width ce# high to rdy/bsy# going low reset recovery time vpp setup time vpp hold time word/byte write time block erase time set lock-bit time clear block lock-bits time word i byte suspend latency time to read erase suspend latency time to read (vcc=3.3vt- 0.3\(ta = oto 60c) t ehrhi t ehrh2 vpp4v~ 10% vpp=lzv* 5% vpp=3.3v-t 0.3v vpr=5vik 10% vpp=lzvk 5% 9.3 !js 10.4 ps 21.1 i-1 s 17.2 ps 17.2 ps t1045-01 cps0002.002@may.199 j a
shari= id242 series product overview 26 1 parameter write cycle time address setup time write recovery time data setup time for ce# data hold time oe# hold time from ce# we# setup time for ce# address setup time for ce# write pulse width ce# high to rdy/bsy# going low reset recovery time vpp setup time vpp hold time word/byte write time block erase time set lock-bit time clear block lock-bits time word i byte suspend latency time to read erase suspend latency time to read (vcc=5v& 5%, vcc=sv& io%, ta=o to 60c t1046-01
sharb= id242 series product overview 27 address we# oe# ce#, ce2# data 1. 2. 3. 4. 5. 6. k,(a) tcw 1 1 tsu(a-ceh) k&e)/ k?hel tehrhl.2 tehrl voh rdylbsy# vol i / vm reset rl 1 %%22 vpp fl 1. v,, tag~zizgs9~~//y v,, power-up and standby 2. /cl~~~~4tvm~~.17~~~~aj;/~~~~~~m~~.~~~f~p~~q write data write or erase setup command 3. 7j;?lx++j (,y~p~~~)?bfil;f;)?~~il~~7~~~~~~~ write valid address and data or erase comfirm command 4. $1/yi-~~~~~filf$~)a~;c~aa~~ automated data write or erase delay 5. x~-~jz.b-%7b~~~~~xl read status register data 6. ~-f-~%~~z+?~w~&a& write read array command figure 8. ac waveforms for write operations (ce# controlled) note) while the data signal is in output mode, do not apply an opposite phase input signal.
sharp id242 series product overview 13.3 attribute memory read operation (ta=o-60c) parameter * : time until becomes floating. (the output voltage is not defined) t1056-01 note) when the cis constructed by eeprom, this card requires 5v voltage for vcc. address :el#, ce2# \ t,(a) e w h(a) 1 c \ / \ / ta(ce) w oe# \\\\\\\\a i/ ? / ? ? ? ? ?/ ? / / / t&w l&e) i tdoe) ~ t&w e a t f-%%hms dout r q&y-&t data output is valid high-inpedance f1009-0; i figure 9. attribute memory read operation cpsoooz-00263may.1996
sharp id242 series product overview 13.4 attribute memory write operation (ta=o-60c) i symbol vcc=3.3v* 0.3v 1 vcc=.wi 10% 1 parameter pcmcia i unit max min max i i i - ns write pulse width setup time for oe# 1 hold time for oe# setup time for ce# _....- i .-\-- it 1.lllr.t 1 t, (oe-\i hold time for ce# i.. . ..l ?.?\- - -- - t wlwh ?w(we) 300 150 ns t 35 10 ns chwi twioe-we) w 35 10 ns , ???~i. , ii. t f1 u/h ilfcf.~ 0 0 ns 35 20 ns ll.... i .?? \ - -/ t cheh t,, w i i t1057-01 note) when the cis constructed by eeprom, this card requires 5v voltage for vcc. address cel#, ce;?# oe# we# data vih vih \ ain t,,(oe-we) vih f1057-01 figure 10. attribute memory write operation
sharp id242 series product overview 13.5 power-up/power down parameter symbol pcmcia notes min max units ce# signal level (o.ov < vcc < 2.ov) vi (ce) 1 0 vimax v ce# signal level (2.ov < vcc < vin) 1 vcco. i vimax v ce# signal level (vtu < vcc) 1 vih vimax v ce# setup time tsu wcc) - 20 - ms i i i i i reset setup time tau wset) - 20 - ms ce# recover time tree wcc) - 1.0 - ijs vcc rising time b 2 0.1 300 ms vcc falling time tpf 2 3.0 300 ms 1 reset width tw (reset) i - i 10 i - i us -i reset width reset width th (hi-z reset) ts (hi-z reset) - - 1 - ms 0 - ms notes: 1. vimax means absolute maximum voltage for input in the period of o.ov < vcc < 2.0 v, vi (ce#) is only o.oov-vimax 2. the tpr and tpr are defined as ?linear waveforms? in the period of 10% to 90%, or vice-versa. even if the waveform is not a ?liner waveform,? its rising and falling time must meet this specification. e e tpr tpr -c- tsu wcc) - -c- tsu wcc) - vcc vcc -)- tsu (reset) -)- tsu (reset) = = -- -- th (hi-z reset) th (hi-z reset) hi-z -3 reset n tw (hi-z reset) + :et#, cea# at- ts (hi-z reset) hi-z flolz-01 figure 11. power- up/uown liming cpsooo2.002 0 may. 1991
shari= id242 series product overview 31 14. specification changes this datasheet is for id242 series product overview, and final specifications will be submitted for qualification of the memory card. please note that contents of this datasheet may be revised without announcement beforehand. please do not finalize a system design with this information. 15. other precautions permanent damage occurs if the memory card is stressed beyond absolute maximum ratings. operation beyond the recommended operating conditions is not recommended and extended exposure beyond the recommended operating conditions may affect device reliability. writing to the memory card can be prevented by switching on the write protect switch on the end of the memory card. avoid allowing the memory card connectors to come in contact with metals and avoid touching the connec- tors, as the internal circuits can be damaged by static electricity. avoid storing in direct sunlight, high temperatures (do not place near heaters or radiators), high humidity and dusty areas. avoid subjecting the memory card to strong physical abuse. dropping, bending, smashing or throwing the card can result in loss of function. when the memory card is not being used, return it to its protective case. do not allow the memory card to come in contact with fire.
id242seriesproductoverview 16. external diagrams 1 0 a enlargemeht of the write-protect switch - - protected (substrdtc aped) front back a--p r- scale unit a,ppliciill l/l mm ch- date revise chargl thickness mater1 al flnisk memory card nat7e external diagram i oate ,997. 9. 8 i bltla* olly triefci(ecr a,rn.l wd matngaa p~vi*rt team pcmcia ret. 2. 0 type1 \ku~uydtia ic group sharp corporation oe*v?rc morn imc026-a103 cpsooo2-002 by.199

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