vn10k features ? free from secondary breakdown ? low power drive requirement ? ease of paralleling ? low c iss and fast switching speeds ? excellent thermal stability ? integral source-drain diode ? high input i mpedance and high gain applications ? motor controls ? converters ? amplifers ? switches ? power supply circuits ? drivers (relays, ha mmers, solenoids, lamps, memories, displays, bipolar transistors, etc.) general description this enhancement-mode (normally-off) transistor utilizes a vertical dmos structure and supertexs well-proven, silicon- gate manufacturing process. this combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coeffcient inherent in mos devices. characteristic of all mos structures, this device is free from thermal runaway and thermally-induced secondary breakdown. supertexs vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. n-channel enhancement-mode vertical dmos fet ordering information device package bv dss /bv dgs (v) r ds(on) (max) () i d(on) (min) (ma) to-92 vn10k vn10kn3-g 60 5.0 750 pin confguration to-92 (n3) gate source drain yy = year sealed ww = week sealed = ?green? packaging sivn 10k yyww to-92 (n3) product marking package may or may not include the following marks: si or parameter value drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 30v operating and storage temperature -55 o c to +150 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. absolute maximum ratings for packaged products, -g indicates package is rohs compliant (green). consult factory for die / wafer form part numbers. refer to die specifcation vf21 for layout and dimensions. supertex inc. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
2 vn10k electrical characteristics (t a = 25 o c unless otherwise specifed) sym parameter min typ max units conditions bv dss drain-to-source breakdown voltage 60 - - v v gs = 0v, i d = 100a v gs(th) gate threshold voltage 0.8 - 2.5 v v gs = v ds , i d = 1.0ma v gs(th) change in v gs(th) with temperature - -3.8 - mv/ o c v gs = v ds , i d = 1.0ma i gss gate body leakage - - 100 na v gs = 15v, v ds = 0v i dss zero gate voltage drain current - - 10 a v gs = 0v, v ds = 45v - - 500 v gs = 0v, v ds = 45v, t a = 125c i d(on) on-state drain current 0.75 - - a v gs = 10v, v ds = 10v r ds(on) static drain-to-source on-state resistance - - 7.5 v gs = 5.0v, i d = 200ma - - 5.0 v gs = 10v, i d = 500ma r ds(on) change in r ds(on) with temperature - 0.7 - %/ o c v gs = 10v, i d = 500ma g fs forward transductance 100 - - mmho v ds = 10v, i d = 500ma c iss input capacitance - 48 60 pf v gs = 0v, v ds = 25v, f = 1.0mhz c oss common source output capacitance - 16 25 c rss reverse transfer capacitance - 2.0 5.0 t (on) turn-on time - - 10 ns v dd = 15v, i d = 600ma, r gen = 25 t (off) turn-off time - - 10 v sd diode forward voltage drop - 0.8 - v v gs = 0v, i sd = 500ma t rr reverse recovery time - 160 - ns v gs = 0v, i sd = 500ma notes: 1. all d.c. parameters 100% tested at 25 o c unless otherwise stated. (pulse test: 300s pulse, 2% duty cycle.) 2. all a.c. parameters sample tested. notes: ? i d (continuous) is limited by max rated t j . (vn0106n3 can be used if an i d (continuous) of 500ma is needed.) thermal characteristics package i d (continuous) ? (ma) i d (pulsed) (a) power dissipation @t c = 25 o c (w) jc ( o c/w) ja ( o c/w) i dr ? (ma) i drm (a) to-92 310 1.0 1.0 125 170 310 1.0 switching waveforms and test circuit 90% 10% 90% 90% 10% 10% pulse generator v dd r l output d.u.t . t (on) t d(on) t (off) t d(off) t r input input output 10v vdd r gen 0v 0v t f supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
3 vn10k typical performance curves output characteristics 1.0 0.8 0.6 0.4 0.2 0 v ds (volts) i d (amperes) saturation characteristics 1.0 0.8 0.6 0.4 0.2 0 maximum rated safe operating area 1.0 10 100 1000 10 1.0 0.1 0.01 v ds (volts) switching waveform 10 5.0 0 15 10 5.0 0 0 10 20 30 40 50 t ? time (ns) transconductance vs. drain current 250 200 150 100 50 0 0 200 400 600 800 1000 g fs (m ) i d (ma) power dissipation vs. case temperature 0 25 50 75 100 125 150 2.0 1.0 0 t c ( o c) p d (watts) to-92 v ds = 10v 300s, 2% duty cycle, pulse test to-92 (dc) 0 10 20 30 40 50 6v 5v 4v 2v 0 2.0 4.0 6.0 8.0 10 6v 4v 2v 3v output voltage (volts) 5v 3v 9v 8v 7v t c = 25 o c v ds (volts) i d (amperes) v gs = 10v input voltage (volts) i d (amperes) v gs = 10v 7v 8v supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
4 vn10k typical performance curves (cont.) transconductance vs gate-source voltage gfs (m ) i d (amperes) g fs (mhos) output conductance vs drain current on-resistance vs. gate-to-source voltage r ds(on) (ohms) bv dss (normalized) t j ( o c) transfer characteristics i d (amperes) capacitance vs. drain-to-source voltage 50 40 30 20 10 0 c (picofarads ) v ds (volts) v gs (volts) bv dss variation with temperature 0 10 20 30 40 50 0 2.0 4.0 6.0 8.0 10 -50 0 50 100 150 1.1 1.0 0.9 100 10 1.0 1.0 10 100 1.0 0.8 0.6 0.4 0.2 0 250 200 150 100 50 0 v gs (volts) 1.0 0.1 0.01 0.01 0.1 1. 0 v ds = 0.1v reduction due to heating v ds = 25v 80s, 1% duty cycle, pulse test v ds = 10v 3000s, 2% duty cycle pulse test c iss c os s c rss v gs (volts) v ds = 10v 300s, 2% duty cycle, pulse test 0 2.0 4.0 6.0 8.0 10 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
5 vn10k (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-vn10k b031411 3-lead to-92 package outline (n3) symbol a b c d e e1 e e1 l dimensions (inches) min .170 .014 ? .014 ? .175 .125 .080 .095 .045 .500 nom - - - - - - - - - max .210 .022 ? .022 ? .205 .165 .105 .105 .055 .610* jedec registration to-92. * this dimension is not specifed in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc.#: dspd-3to92n3, version e041009. seating plane 1 2 3 front v iew side v iew bottom v iew e1 e d e1 l e c 1 2 3 b a supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?201 1 supertex inc. a ll rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
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