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| DS1820 1wire tm digital thermometer DS1820 030598 1/27 features ? unique 1wire tm interface requires only one port pin for communication ? multidrop capability simplifies distributed temperature sensing applications ? requires no external components ? can be powered from data line ? zero standby power required ? measures temperatures from 55 c to +125 c in 0.5 c increments. fahrenheit equivalent is 67 f to +257 f in 0.9 f increments ? temperature is read as a 9bit digital value. ? converts temperature to digital word in 200 ms (typ.) ? userdefinable, nonvolatile temperature alarm set- tings ? alarm search command identifies and addresses devices whose temperature is outside of pro- grammed limits (temperature alarm condition) ? applications include thermostatic controls, industrial systems, consumer products, thermometers, or any thermally sensitive system pin assignment 3 2 1 dallas ds2434 gnd dq vdd dallas DS1820 3 2 1 DS1820s 16pin ssop DS1820 pr35 package 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 nc nc nc nc nc nc nc gnd nc nc nc nc nc nc vdd dq bottom view see mech. drawings section see mech. drawings section pin description gnd ground dq data in/out v dd optional v dd nc no connect description the DS1820 digital thermometer provides 9bit tem- perature readings which indicate the temperature of the device. information is sent to/from the DS1820 over a 1wire interface, so that only one wire (and ground) needs to be connected from a central microprocessor to a DS1820. power for reading, writing, and performing temperature conversions can be derived from the data line itself with no need for an external power source. because each DS1820 contains a unique silicon serial number, multiple DS1820s can exist on the same 1wire bus. this allows for placing temperature sen- sors in many different places. applications where this feature is useful include hvac environmental controls, sensing temperatures inside buildings, equipment or machinery, and in process monitoring and control.
DS1820 030598 2/27 detailed pin description pin 16pin ssop pin pr35 symbol description 9 1 gnd ground. 8 2 dq data input/output pin. for 1wire operation: open drain. (see aparasite powero section.) 7 3 v dd optional v dd pin . see aparasite powero section for details of connection. DS1820s (16pin ssop): all pins not specified in this table are not to be connected. overview the block diagram of figure 1 shows the major compo- nents of the DS1820. the DS1820 has three main data components: 1) 64bit lasered rom, 2) temperature sensor, and 3) nonvolatile temperature alarm triggers th and tl. the device derives its power from the 1wire communication line by storing energy on an internal capacitor during periods of time when the signal line is high and continues to operate off this power source during the low times of the 1wire line until it returns high to replenish the parasite (capacitor) supply. as an alternative, the DS1820 may also be powered from an external 5 volts supply. communication to the DS1820 is via a 1wire port. with the 1wire port, the memory and control functions will not be available before the rom function protocol has been established. the master must first provide one of five rom function commands: 1) read rom, 2) match rom, 3) search rom, 4) skip rom, or 5) alarm search. these commands operate on the 64bit lasered rom portion of each device and can single out a specific device if many are present on the 1wire line as well as indicate to the bus master how many and what types of devices are present. after a rom function sequence has been successfully executed, the memory and control functions are accessible and the master may then provide any one of the six memory and control function commands. one control function command instructs the DS1820 to perform a temperature measurement. the result of this measurement will be placed in the DS1820's scratch- pad memory, and may be read by issuing a memory function command which reads the contents of the scratchpad memory. the temperature alarm triggers th and tl consist of one byte eeprom each. if the alarm search command is not applied to the DS1820, these registers may be used as general purpose user memory. writing th and tl is done using a memory function command. read access to these registers is through the scratchpad. all data is read and written least significant bit first. DS1820 block diagram figure 1 64bit rom scratchpad memory and control logic and 1wire port temperature sensor 8bit crc generator power supply sense dq v dd internal v dd high temperature trigger, th low temperature trigger, tl +5v +5v DS1820 i/o 4.7k m p v dd gnd DS1820 030598 3/27 parasite power the block diagram (figure 1) shows the parasite pow- ered circuitry. this circuitry astealso power whenever the i/o or v dd pins are high. i/o will provide sufficient power as long as the specified timing and voltage require- ments are met (see the section titled a1wire bus sys- temo). the advantages of parasite power are twofold: 1) by parasiting off this pin, no local power source is needed for remote sensing of temperature, and 2) the rom may be read in absence of normal power. in order for the DS1820 to be able to perform accurate temperature conversions, sufficient power must be pro- vided over the i/o line when a temperature conversion is taking place. since the operating current of the DS1820 is up to 1 ma, the i/o line will not have sufficient drive due to the 5k pullup resistor. this problem is particu- larly acute if several DS1820's are on the same i/o and attempting to convert simultaneously. there are two ways to assure that the DS1820 has suffi- cient supply current during its active conversion cycle. the first is to provide a strong pullup on the i/o line whenever temperature conversions or copies to the e 2 memory are taking place. this may be accomplished by using a mosfet to pull the i/o line directly to the power supply as shown in figure 2. the i/o line must be switched over to the strong pullup within 10 m s maxi- mum after issuing any protocol that involves copying to the e 2 memory or initiates temperature conversions. when using the parasite power mode, the v dd pin must be tied to ground. another method of supplying current to the DS1820 is through the use of an external power supply tied to the v dd pin, as shown in figure 3. the advantage to this is that the strong pullup is not required on the i/o line, and the bus master need not be tied up holding that line high during temperature conversions. this allows other data traffic on the 1wire bus during the conversion time. in addition, any number of DS1820's may be placed on the 1wire bus, and if they all use external power, they may all simultaneously perform temperature conversions by issuing the skip rom command and then issuing the convert t command. note that as long as the external power supply is active, the gnd pin may not be floating. the use of parasite power is not recommended above 100 c, since it may not be able to sustain communica- tions given the higher leakage currents the DS1820 exhibits at these temperatures. for applications in which such temperatures are likely, it is strongly recom- mended that v dd be applied to the DS1820. for situations where the bus master does not know whether the DS1820's on the bus are parasite powered or supplied with external v dd , a provision is made in the DS1820 to signal the power supply scheme used. the bus master can determine if any DS1820's are on the bus which require the strong pullup by sending a skip rom protocol, then issuing the read power supply com- mand. after this command is issued, the master then issues read time slots. the DS1820 will send back a0o on the 1wire bus if it is parasite powered; it will send back a a1o if it is powered from the v dd pin. if the master receives a a0o, it knows that it must supply the strong pullup on the i/o line during temperature conversions. see amemory command functionso section for more detail on this command protocol. strong pullup for supplying DS1820 during temperature conversion figure 2 DS1820 030598 4/27 using v dd to supply temperature conversion current figure 3 +5v DS1820 i/o 4.7k m p v dd to other 1wire devices external +5v supply operation measuring temperature the DS1820 measures temperature through the use of an onboard proprietary temperature measurement technique. a block diagram of the temperature mea- surement circuitry is shown in figure 4. the DS1820 measures temperature by counting the number of clock cycles that an oscillator with a low tem- perature coefficient goes through during a gate period determined by a high temperature coefficient oscillator. the counter is preset with a base count that corre- sponds to 55 c. if the counter reaches zero before the gate period is over, the temperature register, which is also preset to the 55 c value, is incremented, indicat- ing that the temperature is higher than 55 c. at the same time, the counter is then preset with a value determined by the slope accumulator circuitry. this cir- cuitry is needed to compensate for the parabolic behav- ior of the oscillators over temperature. the counter is then clocked again until it reaches zero. if the gate period is still not finished, then this process repeats. the slope accumulator is used to compensate for the nonlinear behavior of the oscillators over temperature, yielding a high resolution temperature measurement. this is done by changing the number of counts neces- sary for the counter to go through for each incremental degree in temperature. to obtain the desired resolution, therefore, both the value of the counter and the number of counts per degree c (the value of the slope accumu- lator) at a given temperature must be known. internally, this calculation is done inside the DS1820 to provide 0.5 c resolution. the temperature reading is provided in a 16bit, signextended two's complement reading. table 1 describes the exact relationship of out- put data to measured temperature. the data is trans- mitted serially over the 1wire interface. the DS1820 can measure temperature over the range of 55 c to +125 c in 0.5 c increments. for fahrenheit usage, a lookup table or conversion factor must be used. note that temperature is represented in the DS1820 in terms of a 1 / 2 c lsb, yielding the following 9bit format: msb lsb 1 1 1 0 0 1 1 1 0 = 25 c the most significant (sign) bit is duplicated into all of the bits in the upper msb of the twobyte temperature reg- ister in memory. this asignextensiono yields the 16bit temperature readings as shown in table 1. higher resolutions may be obtained by the following procedure. first, read the temperature, and truncate the 0.5 c bit (the lsb) from the read value. this value is temp_read. the value left in the counter may then be read. this value is the count remaining (count_remain) after the gate period has ceased. the last value needed is the number of counts per degree c (count_per_c) at that temperature. the actual temperature may be then be calculated by the user using the following: temperature = temp_read 0.25 (count_per_c count_remain) count_per_c DS1820 030598 5/27 temperature measuring circuitry figure 4 slope accumulator preset preset counter counter =0 =0 stop inc compare temperature register low temperature coefficient oscillator high temperature coefficient oscillator set/clear lsb temperature/data relationships table 1 temperature digital output (binary) digital output (hex) +125 c 00000000 1 1111010 00fa +25 c 00000000 00110010 0032h + 1 /2 c 00000000 00000001 0001h +0 c 00000000 00000000 0000h 1 / 2 c 11111111 11111111 ffffh 25 c 11111111 1 1001110 ffceh 55 c 11111111 10010010 ff92h operation alarm signaling after the DS1820 has performed a temperature conver- sion, the temperature value is compared to the trigger values stored in th and tl. since these registers are 8bit only, the 0.5 c bit is ignored for comparison. the most significant bit of th or tl directly corresponds to the sign bit of the 16bit temperature register. if the result of a temperature measurement is higher than th or lower than tl, an alarm flag inside the device is set. this flag is updated with every temperature measure- ment. as long as the alarm flag is set, the DS1820 will respond to the alarm search command. this allows many DS1820s to be connected in parallel doing simul- taneous temperature measurements. if somewhere the temperature exceeds the limits, the alarming device(s) can be identified and read immediately without having to read nonalarming devices. DS1820 030598 6/27 64bit lasered rom each DS1820 contains a unique rom code that is 64bits long. the first eight bits are a 1wire family code (DS1820 code is 10h). the next 48 bits are a unique serial number. the last eight bits are a crc of the first 56 bits. (see figure 5.) the 64bit rom and rom function control section allow the DS1820 to operate as a 1wire device and follow the 1wire proto- col detailed in the section a1wire bus systemo. the functions required to control sections of the DS1820 are not accessible until the rom function protocol has been satisfied. this protocol is described in the rom function protocol flowchart (figure 6). the 1wire bus master must first provide one of five rom function commands: 1) read rom, 2) match rom, 3) search rom, 4) skip rom, or 5) alarm search. after a rom functions sequence has been successfully executed, the func- tions specific to the DS1820 are accessible and the bus master may then provide and one of the six memory and control function commands. crc generation the DS1820 has an 8bit crc stored in the most signif- icant byte of the 64bit rom. the bus master can com- pute a crc value from the first 56bits of the 64bit rom and compare it to the value stored within the DS1820 to determine if the rom data has been received errorfree by the bus master. the equivalent polynomial function of this crc is: crc = x 8 + x 5 + x 4 + 1 the DS1820 also generates an 8bit crc value using the same polynomial function shown above and pro- vides this value to the bus master to validate the transfer of data bytes. in each case where a crc is used for data transfer validation, the bus master must calculate a crc value using the polynomial function given above and compare the calculated value to either the 8bit crc value stored in the 64bit rom portion of the DS1820 (for rom reads) or the 8bit crc value com- puted within the DS1820 (which is read as a ninth byte when the scratchpad is read). the comparison of crc values and decision to continue with an operation are determined entirely by the bus master. there is no cir- cuitry inside the DS1820 that prevents a command sequence from proceeding if the crc stored in or calcu- lated by the DS1820 does not match the value gener- ated by the bus master. the 1wire crc can be generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 7. additional information about the dallas 1wire cyclic redundancy check is available in application note 27 entitled aunderstanding and using cyclic redundancy checks with dallas semiconductor touch memory productso. the shift register bits are initialized to zero. then start- ing with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. shifting in the eight bits of crc should return the shift register to all zeros. 64bit lasered rom figure 5 8bit crc code 48bit serial number 8bit family code (10h) msb lsb msb lsb msb lsb n y y y DS1820 t x presence pulse 33h read rom command 55h match rom command f0h search rom command cch skip rom command DS1820 t x family code 1 byte bit 0 match? bit 0 match? bit 1 match? bit 1 match? bit 63 match? bit 63 match? DS1820 t x serial number 6 bytes DS1820 t x crc byte n nn y y y nn y n n y y y DS1820 t x bit 0 DS1820 t x bit 0 DS1820 t x bit 1 DS1820 t x bit 1 DS1820 t x bit 63 DS1820 t x bit 63 master t x bit 1 master t x bit 0 master t x bit 0 master t x bit 1 master t x bit 63 master t x bit 63 master t x reset pulse master t x rom function command master t x memory or control function command n n y ech alarm search command alarm condition ? y n n DS1820 030598 7/27 rom functions flow chart figure 6 DS1820 030598 8/27 1wire crc code figure 7 (msb) (lsb) xor xor xor input memory the DS1820's memory is organized as shown in figure 8. the memory consists of a scratchpad ram and a nonvolatile, electrically erasable (e 2 ) ram, which stores the high and low temperature triggers th and tl. the scratchpad helps insure data integrity when com- municating over the 1wire bus. data is first written to the scratchpad where it can be read back. after the data has been verified, a copy scratchpad command will transfer the data to the nonvolatile (e 2 ) ram. this pro- cess insures data integrity when modifying the memory. the scratchpad is organized as eight bytes of memory. the first two bytes contain the measured temperature information. the third and fourth bytes are volatile copies of th and tl and are refreshed with every pow- eron reset. the next two bytes are not used; upon reading back, however, they will appear as all logic 1's. the seventh and eighth bytes are count registers, which may be used in obtaining higher temperature resolution (see aoperationmeasuring temperatureo section). there is a ninth byte which may be read with a read scratchpad command. this byte contains a cyclic redundancy check (crc) byte which is the crc over all of the eight previous bytes. this crc is implemented in the fashion described in the section titled acrc genera- tiono. DS1820 memory map figure 8 temperature lsb temperature msb th/user byte 1 tl/user byte 2 reserved reserved count remain crc byte 0 1 2 3 4 5 6 7 8 th/user byte 1 tl/user byte 2 scratchpad e 2 ram count per c DS1820 030598 9/27 1wire bus system the 1wire bus is a system which has a single bus mas- ter and one or more slaves. the DS1820 behaves as a slave. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1wire signaling (signal types and tim- ing). hardware configuration the 1wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1wire bus must have open drain or 3state outputs. the 1wire port of the DS1820 (i/o pin) is open drain with an internal circuit equivalent to that shown in figure 9. a multidrop bus consists of a 1wire bus with multiple slaves attached. the 1wire bus requires a pullup resistor of approximately 5k w . hardware configuration figure 9 +5v 4.7k r x t x r x t x 1oo ohm mosfet DS1820 1wire port bus master 5 m a typ. r x = receive t x = transmit the idle state for the 1wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. infinite recovery time can occur between bits so long as the 1wire bus is in the inactive (high) state during the re- covery period. if this does not occur and the bus is left low for more than 480 m s, all components on the bus will be reset. transaction sequence the protocol for accessing the DS1820 via the 1wire port is as follows: ? initialization ? rom function command ? memory function command ? transaction/data initialization all transactions on the 1wire bus begin with an initial- ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the DS1820 is on the bus and is ready to operate. for more details, see the a1wire signalingo section. rom function commands once the bus master has detected a presence, it can issue one of the five rom function commands. all rom function commands are 8bits long. a list of these com- mands follows (refer to flowchart in figure 6): DS1820 030598 10/27 read rom [33h] this command allows the bus master to read the DS1820's 8bit family code, unique 48bit serial num- ber, and 8bit crc. this command can only be used if there is a single DS1820 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired and result). match rom [55h] the match rom command, followed by a 64bit rom sequence, allows the bus master to address a specific DS1820 on a multidrop bus. only the DS1820 that exactly matches the 64bit rom sequence will respond to the following memory function command. all slaves that do not match the 64bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single drop bus sys- tem by allowing the bus master to access the memory functions without providing the 64bit rom code. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will pro- duce a wired and result). search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1wire bus or their 64bit rom codes. the search rom com- mand allows the bus master to use a process of elimina- tion to identify the 64bit rom codes of all slave devices on the bus. alarm search [ech] the flowchart of this command is identical to the search rom command. however, the DS1820 will respond to this command only if an alarm condition has been encountered at the last temperature measurement. an alarm condition is defined as a temperature higher than th or lower than tl. the alarm condition remains set as long as the DS1820 is powered up, or until another tem- perature measurement reveals a nonalarming value. for alarming, the trigger values stored in eeprom are taken into account. if an alarm condition exists and the th or tl settings are changed, another temperature conversion should be done to validate any alarm condi- tions. example of a rom search the rom search process is the repetition of a simple 3step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus mas- ter performs this simple, 3step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be identified by additional passes. the following example of the rom search process assumes four different devices are connected to the same 1wire bus. the rom data of the four devices is as shown: rom1 00110101... rom2 10101010... rom3 11110101... rom4 00010001... the search process is as follows: 1. the bus master begins the initialization sequence by issuing a reset pulse. the slave devices respond by issuing simultaneous presence pulses. 2. the bus master will then issue the search rom command on the 1wire bus. 3. the bus master reads a bit from the 1wire bus. each device will respond by placing the value of the first bit of their respective rom data onto the 1wire bus. rom1 and rom4 will place a 0 onto the 1wire bus, i.e., pull it low. rom2 and rom3 will place a 1 onto the 1wire bus by allowing the line to stay high. the result is the logical and of all devices on the line, therefore the bus master sees a 0. the bus master reads another bit. since the search rom data command is being executed, all of the devices on the 1wire bus respond to this second read by placing the complement of the first bit of their respective rom data onto the 1wire bus. rom1 and rom4 will place a 1 onto the 1wire, allowing the line to stay high. rom2 and rom3 will place a 0 onto the 1wire, thus it will be pulled low. the bus master again observes a 0 for the complement of the first rom data bit. the bus master has determined that there are some devices on the 1wire bus that have a 0 in the first position and others that have a 1. DS1820 030598 11/27 the data obtained from the two reads of the 3step routine have the following interpretations: 00 there are still devices attached which have conflicting bits in this position. 01 all devices still coupled have a 0bit in this bit position. 10 all devices still coupled have a 1bit in this bit position. 11 there are no devices attached to the 1wire bus. 4. the bus master writes a 0. this deselects rom2 and rom3 for the remainder of this search pass, leaving only rom1 and rom4 connected to the 1wire bus. 5. the bus master performs two more reads and receives a 0bit followed by a 1bit. this indicates that all devices still coupled to the bus have 0's as their second rom data bit. 6. the bus master then writes a 0 to keep both rom1 and rom4 coupled. 7. the bus master executes two reads and receives two 0bits. this indicates that both 1bits and 0bits exist as the third bit of the rom data of the attached devices. 8. the bus master writes a 0bit. this deselects rom1 leaving rom4 as the only device still connected. 9. the bus master reads the remainder of the rom bits for rom4 and continues to access the part if desired. this completes the first pass and uniquely identifies one part on the 1wire bus. 10. the bus master starts a new rom search sequence by repeating steps 1 through 7. 11. the bus master writes a 1bit. this decouples rom4, leaving only rom1 still coupled. 12. the bus master reads the remainder of the rom bits for rom1 and communicates to the underlying logic if desired. this completes the second rom search pass, in which another of the roms was found. 13. the bus master starts a new rom search by repeat- ing steps 1 through 3. 14. the bus master writes a 1bit. this deselects rom1 and rom4 for the remainder of this search pass, leaving only rom2 and rom3 coupled to the system. 15. the bus master executes two read time slots and receives two zeros. 16. the bus master writes a 0bit. this decouples rom3, and leaving only rom2. 17. the bus master reads the remainder of the rom bits for rom2 and communicates to the underlying logic if desired. this completes the third rom search pass, in which another of the roms was found. 18. the bus master starts a new rom search by repeat- ing steps 13 through 15. 19. the bus master writes a 1bit. this decouples rom2, leaving only rom3. 20. the bus master reads the remainder of the rom bits for rom3 and communicates to the underlying logic if desired. this completes the fourth rom search pass, in which another of the roms was found. note the following: the bus master learns the unique id number (rom data pattern) of one 1wire device on each rom search operation. the time required to derive the part's unique rom code is: 960 m s + (8 + 3 x 64) 61 m s = 13.16 ms the bus master is therefore capable of identifying 75 dif- ferent 1wire devices per second. i/o signaling the DS1820 requires strict protocols to insure data integrity. the protocol consists of several types of signaling on one line: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. all of these signals, with the exception of the presence pulse, are initiated by the bus master. the initialization sequence required to begin any com- munication with the DS1820 is shown in figure 11. a reset pulse followed by a presence pulse indicates the DS1820 is ready to send or receive data given the cor- rect rom command and memory function command. the bus master transmits (tx) a reset pulse (a low sig- nal for a minimum of 480 m s). the bus master then releases the line and goes into a receive mode (rx). the 1wire bus is pulled to a high state via the 5k pullup resistor . after detecting the rising edge on the DS1820 030598 12/27 i/o pin, the DS1820 waits 1560 m s and then transmits the presence pulse (a low signal for 60240 m s). memory command functions the following command protocols are summarized in table 2, and by the flowchart of figure 10. write scratchpad [4eh] this command writes to the scratchpad of the DS1820, starting at address 2. the next two bytes written will be saved in scratchpad memory, at address locations 2 and 3. writing may be terminated at any point by issuing a reset. DS1820 030598 13/27 memory functions flow chart figure 10 4eh write scratchpad ? master t x memory or control command DS1820 sets address counter to 2 master t x data byte to scratchpad master t x reset ? address =3 ? DS1820 increments address master t x reset ? beh read scratchpad ? DS1820 sets address counter to 0 master r x data from scratchpad master t x reset ? address =7 ? DS1820 increments address master r x 8bit crc of data DS1820 t x presence pulse master t x reset ? master r x a1so n n n n n n n n y y y y y y y y DS1820 030598 14/27 memory functions flow chart figure 10 (cont'd) 48h copy scratchpad ? 44h convert temperature ? parasite power ? master enables strong pullup nn y y y DS1820 converts temperature master disables strong pullup DS1820 begins conversion master t x reset ? device busy converting temperature ? master r x a1os master r x a0os master t x reset ? nonvolatile memory busy ? master r x a1os master r x a0os n ny n y n y n y parasite power ? master enables strong pullup for 10 ms master disables strong pullup ny DS1820 030598 15/27 memory functions flow chart figure 10 (cont'd) b8h recall e 2 ? DS1820 recalls from e 2 prom master t x reset ? b4h read power supply ? nn y y master t x reset ? n y y parasite powered ? master r x a0os ny master r x a1os master t x reset ? n y device busy converting temperature ? master r x a0os master r x a1os y n DS1820 030598 16/27 initialization procedure areset and presence pulseso figure 11 master t x areset pulseo 480 m s minimum 960 m s maximum master r x 480 m s minimum v cc gnd DS1820 waits 15 - 60 m s DS1820 t x apresence pulseo 60 - 240 m s line type legend: bus master active low both bus master and DS1820 active low DS1820 active low resistor pullup 1wire bus DS1820 command set table 2 instruction description protocol 1wire bus after issuing protocol notes temperature conversion commands convert t initiates temperature conversion. 44h DS1820 030598 17/27 read scratchpad [beh] this command reads the contents of the scratchpad. reading will commence at byte 0, and will continue through the scratchpad until the 9th (byte8, crc) byte is read. if not all locations are to be read, the master may issue a reset to terminate reading at any time. copy scratchpad [48h] this command copies the scratchpad into the e 2 memory of the DS1820, storing the temperature trigger bytes in nonvolatile memory. if the bus master issues read time slots following this command, the DS1820 will output a0o on the bus as long as it is busy copying the scratchpad to e 2 ; it will return a a1o when the copy pro- cess is complete. if parasite powered, the bus master has to enable a strong pullup for at least 10 ms immedi- ately after issuing this command. convert t [44h] this command begins a temperature conversion. no further data is required. the temperature conversion will be performed and then the DS1820 will remain idle. if the bus master issues read time slots following this com- mand, the DS1820 will output a0o on the bus as long as it is busy making a temperature conversion; it will return a a1o when the temperature conversion is complete. if par- asite powered, the bus master has to enable a strong pullup for 500 ms immediately after issuing this com- mand. recall e2 [b8h] this command recalls the temperature trigger values stored in e 2 to the scratchpad. this recall operation hap- pens automatically upon powerup to the DS1820 as well, so valid data is available in the scratchpad as soon as the device has power applied. with every read data time slot issued after this command has been sent, the device will output its temperature converter busy flag a0o=busy, a1o=ready. read power supply [b4h] with every read data time slot issued after this com- mand has been sent to the DS1820, the device will sig- nal its power mode: a0o=parasite power, a1o=external power supply provided. read/write time slots DS1820 data is read and written through the use of time slots to manipulate bits and a command word to specify the transaction. write time slots a write time slot is initiated when the host pulls the data line from a high logic level to a low logic level. there are two types of write time slots: write one time slots and write zero time slots. all write time slots must be a mini- mum of 60 m s in duration with a minimum of a one m s recovery time between individual write cycles. the DS1820 samples the i/o line in a window of 15 m s to 60 m s after the i/o line falls. if the line is high, a write one occurs. if the line is low, a write zero occurs (see figure 12). for the host to generate a write one time slot, the data line must be pulled to a logic low level and then released, allowing the data line to pull up to a high level within 15 m s after the start of the write time slot. for the host to generate a write zero time slot, the data line must be pulled to a logic low level and remain low for 60 m s. read time slots the host generates read time slots when data is to be read from the DS1820. a read time slot is initiated when the host pulls the data line from a logic high level to logic low level. the data line must remain at a low logic level for a minimum of one m s; output data from the DS1820 is valid for 15 m s after the falling edge of the read time slot. the host therefore must stop driving the i/o pin low in order to read its state 15 m s from the start of the read slot (see figure 12). by the end of the read time slot, the i/o pin will pull back high via the external pullup resistor. all read time slots must be a minimum of 60 m s in duration with a minimum of a one m s recovery time between indi- vidual read slots. figure 13 shows that the sum of t init , t rc , and t sample must be less than 15 m s. figure 14 shows that system timing margin is maximized by keeping t init and t rc as small as possible and by locating the master sample time towards the end of the 15 m s period. DS1820 030598 18/27 read/write timing diagram figure 12 1wire bus master write a0o slot master write a1o slot 60 m s DS1820 030598 19/27 detailed master read a1o timing figure 13 v cc gnd 15 m s t init >1 m s t rc master samples 1wire bus v ih of master recommended master read a1o timing figure 14 v cc gnd 15 m s master samples t rc = small t init = small 1wire bus v ih of master line type legend: bus master active low both bus master and DS1820 active low DS1820 active low resistor pullup DS1820 030598 20/27 related application notes the following application notes can be applied to the DS1820. these notes can be obtained from the dallas semiconductor aapplication note booko, via our web- site at http://www.dalsemi.com/, or through our faxback service at (214) 4500441. application note 27: aunderstanding and using cyclic redundancy checks with dallas semiconductor touch memory producto application note 55: aextending the contact range of touch memorieso application note 74: areading and writing touch memories via serial interfaceso application note 104: aminimalist temperature control demoo application note 105: ahigh resolution temperature measurement with dallas directtodirect temperature sen- sorso application note 106: acomplex microlanso application note 108: amicrolan in the long runo sample 1wire subroutines that can be used in conjunction with an74 can be downloaded from the website or our anonymous ftp site. DS1820 030598 21/27 memory function example table 3 example: bus master initiates temperature conversion, then reads temperature (parasite power assumed). master mode data (lsb first) comments tx reset reset pulse (480960 m s). rx presence presence pulse. tx 55h issue amatch romo command. tx <64bit rom code> issue address for DS1820. tx 44h issue aconvert to command. tx i/o line is held high for at least 500 ms by bus master to allow conversion to complete. tx reset reset pulse. rx presence presence pulse. tx 55h issue amatch romo command. tx <64bit rom code> issue address for DS1820. tx beh issue aread scratchpado command. rx <9 data bytes> read entire scratchpad plus crc; the master now recal- culates the crc of the eight data bytes received from the scratchpad, compares the crc calculated and the crc read. if they match, the master continues; if not, this read operation is repeated. tx reset reset pulse. rx presence presence pulse, done. DS1820 030598 22/27 memory function example table 4 example: bus master writes memory (parasite power and only one DS1820 assumed). master mode data (lsb first) comments tx reset reset pulse. rx presence presence pulse. tx cch skip rom command. tx 4eh write scratchpad command. tx <2 data bytes> writes two bytes to scratchpad (th and tl). tx reset reset pulse. rx presence presence pulse. tx cch skip rom command. tx beh read scratchpad command. rx <9 data bytes> read entire scratchpad plus crc. the master now recal- culates the crc of the eight data bytes received from the scratchpad, compares the crc and the two other bytes read back from the scratchpad. if data match, the master continues; if not, repeat the sequence. tx reset reset pulse. rx presence presence pulse. tx cch skip rom command. tx 48h copy scratchpad command; after issuing this command, the master must wait 6 ms for copy operation to complete. tx reset reset pulse. rx presence presence pulse, done. DS1820 030598 23/27 memory function example table 5 example: temperature conversion and interpolation (external power supply and only one DS1820 assumed). master mode data (lsb first) comments tx reset reset pulse. tr presence presence pulse. tx cch skip rom command. tx 44h convert t command. rx <1 data byte> read busy flag eight times. the master continues reading one byte (or bit) after another until the data is ffh (all bits 1). tx reset reset pulse. rx presence presence pulse. tx cch skip rom command. tx beh read scratchpad command. rx <9 data bytes> read entire scratchpad plus crc. the master now recal- culates the crc of the eight data bytes received from the scratchpad and compares both crcs. if the crcs match, the data is valid. the master saves the temperature value and stores the contents of the count register and count per c register as count_remain and count_per_c, respectively. tx reset reset pulse. rx presence presence pulse, done. cpu calculates temperature as described in the data sheet for higher resolution. DS1820 030598 24/27 absolute maximum ratings* voltage on any pin relative to ground 0.5v to +7.0v operating temperature 55 c to +125 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions parameter symbol condition min typ max units notes supply voltage v dd i/o functions 1 / 2 c accurate temperature conversions 2.8 4.3 5.0 5.5 5.5 v 1, 2 data pin i/o 0.5 +5.5 v 2 logic 1 v ih 2.0 v cc +0.3 v 2, 3 logic 0 v il 0.3 +0.8 v 2, 4 dc electrical characteristics (55 c to +125 c; v dd =3.6v to 5.5v) parameter symbol condition min typ max units notes thermometer error t err 0 c to +70 c 55 cto0 c 1 / 2 c 55 c t o 0 c and +70 c to +125 c see typical curve 1, 9, 10 input logic high v ih 2.2 5.5 v 2, 3 input logic low v il 0.3 +0.8 v 2, 4 sink current i l v i/o =0.4v 4.0 ma 2 standby current i q 200 350 na 8 active current i dd 1 1.5 ma 5, 6 input load current i l 5 m a 7 DS1820 030598 25/27 ac electrical characteristics: (55 c to +125 c; v dd =3.6v to 5.5v) parameter symbol min typ max units notes temperature conversion time t conv 200 500 ms time slot t slot 60 120 m s recovery time t rec 1 m s write 0 low time r low0 60 120 m s write 1 low time t low1 1 15 m s read data valid t rdv 15 m s reset time high t rsth 480 m s reset time low t rstl 480 4800 m s presence detect high t pdhigh 15 60 m s presence detect low t pdlow 60 240 m s capacitance c in/out 25 pf notes: 1. temperature conversion will work with 2 c accuracy down to v dd = 3.4 volts. 2. all voltages are referenced to ground. 3. logic one voltages are specified at a source current of 1 ma. 4. logic zero voltages are specified at a sink current of 4 ma. 5. i dd specified with v cc at 5.0 volts. 6. active current refers to either temperature conversion or writing to the e 2 memory. writing to e 2 memory con- sumes approximately 200 m a for up to 10 ms. 7. input load is to ground. 8. standby current specified up to 70 c. standby current typically is 5 m a at 125 c. 9. see typical curve for specification limits outside the 0 c to 70 c range. thermometer error reflects sensor accu- racy as tested during calibration. 10. typical accuracy curve valid for 4.3v v dd 5.5v. 1wire write one time slot start of next cycle t rec t low1 t slot DS1820 030598 26/27 1wire write zero time slot start of next cycle t rec t slot t low0 1wire read zero time slot start of next cycle t rec t slot t rdv 1wire reset pulse reset pulse from host presence detect 1wire presence detect t rstl t rsth t pdhigh t pdlow DS1820 030598 27/27 typical performance curve 55 35 15 5 25 45 65 85 105 125 5 4 3 2 1 1 2 3 upper limit specification typical lower limit specification DS1820 digital termometer and thermostat temperature reading error error (deg. c) temperature (deg. c) error |
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