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1 www.fairchildsemi.com fm25c040u rev. a fm25c040u 4k-bit spi interface serial cmos eeprom fm25c040u 4k-bit spi? interface serial cmos eeprom block diagram april 2001 ?2001 fairchild semiconductor corporation instruction decoder control logic and clock generators high voltage generator and program timer instruction register program enable data in/out register 8 bits data out buffer non-volatile status register decoder address counter/ register eeprom array read/write amps /cs /hold sck v cc v ss v pp /wp si so general description the fm25c040u is a 4k (4,096) bit serial interface cmos eeprom (electrically erasable programmable read-only memory). this device fully conforms to the spi 4-wire protocol which uses chip select (/cs), clock (sck), data-in (si) and data- out (so) pins to synchronously control data transfer between the spi microcontroller and the eeprom. in addition, the serial interface allows a minimal pin count, packaging designed to simplify pc board layout requirements and offers the designer a variety of low voltage and low power options. this spi eeprom family is designed to work with the 68hc11 or any other spi-compatible, high-speed microcontroller and offers both hardware (/wp pin) and software ("block write") data protec- tion. for example, entering a 2-bit code into the status regis- ter prevents programming in a selected block of memory and all programming can be inhibited by connecting the /wp pin to v ss ; allowing the user to protect the entire array or a selected section. in addition, spi devices feature a /hold pin, which allows a temporary interruption of the datastream into the eeprom. fairchild eeproms are designed and tested for applications requiring high endurance, high reliability, and low power con- sumption for a continuously reliable non-volatile solution for all markets. functions spi mode 0 interface 4,096 bits organized as 512 x 8 extended 2.7v to 5.5v operating voltage 2.1 mhz operation @ 4.5v - 5.5v self-timed programming cycle "programming complete" indicated by status register polling /wp pin and block write protection features sequential read of entire array 4 byte "page write" mode to minimize total write time per byte /wp pin and block write protection to prevent inadvert- ent programming as well as programming enable and disable opcodes. /hold pin to suspend data transfer typical 1 a standby current (i sb ) for "l" devices and 0.1 a standby current for "lz" devices. endurance: up to 1,000,000 data changes data retention greater than 40 years spi is a trademark of motorola corporation
2 www.fairchildsemi.com fm25c040u rev. a fm25c040u 4k-bit spi interface serial cmos eeprom connection diagram dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e (n), m08a (m8), and mtc08 (mt8) pin names /cs chip select input so serial data output /wp write protect v ss ground si serial data input sck serial clock input /hold suspends serial data v cc power supply ordering information fm 25 c xx u lz e xx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 a standby current ultralite cs100ul process density/mode 040 4k, mode 0 c cmos technology interface 25 spi fm fairchild nonvolatile memory prefix /cs so /wp v ss v cc /hold sck si 8 7 6 5 1 2 3 4 fm25c040u
3 www.fairchildsemi.com fm25c040u rev. a fm25c040u 4k-bit spi interface serial cmos eeprom standard voltage 4.5 v cc 5.5v specifications absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature fm25c040u 0 c to +70 c fm25c040ue -40 c to +85 c fm25c040uv -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v (unless otherwise specified) symbol parameter conditions min max units i cc operating current /cs = v il 3ma i ccsb standby current /cs = v cc 50 a i il input leakage v in = 0 to v cc -1 +1 a i ol output leakage v out = gnd to v cc -1 +1 a v il cmos input low voltage -0.3 v cc * 0.3 v v ih cmos input high voltage 0.7 * v cc v cc + 0.3 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = -0.8 ma v cc - 0.8 v f op sck frequency 2.1 mhz t ri input rise time 2.0 s t fi input fall time 2.0 s t clh clock high time (note 2) 190 ns t cll clock low time (note 2) 190 ns t csh min /cs high time (note 3) 240 ns t css /cs setup time 240 ns t dis data setup time 100 ns t hds /hold setup time 90 ns t csn /cs hold time 240 ns t din data hold time 100 ns t hdn /hold hold time 90 ns t pd output delay c l = 200 pf 240 ns t dh output hold time 0 ns t lz /hold to output low z 100 ns t df output disable time c l = 200 pf 240 ns t hz /hold to output high z 100 ns t wp write cycle time 1 16 bytes 10 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 4) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200 pf input pulse levels 0.1 * v cc 0.9 * v cc timing measurement reference level 0.3 * v cc - 0.7 * v cc note 1: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, for a f op of 2.1mhz, the period equals 476ns. in this case if t c lh = is set to 190ns, then t cll must be set to a minimum of 286ns. note 3: /cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 4: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com fm25c040u rev. a fm25c040u 4k-bit spi interface serial cmos eeprom low voltage 2.7v v cc 4.5v specifications absolute maximum ratings (note 5) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature fm25c040ul/lz 0 c to +70 c fm25c040ule/lze -40 c to +85 c fm25c040ulv -40 c to +125 c power supply (v cc ) 2.7v 4.5v dc and ac electrical characteristics 2.7v v cc 4.5v (unless otherwise specified) 25c040ul/le 25c040ulv 25c040ulz/ze symbol parameter part conditions min. max. min max units i cc operating current /cs = v il 33ma i ccsb standby current l /cs = v cc 10 10 a lz 1 n/a a i il input leakage v in = 0 to v cc -1 1 -1 1 a i ol output leakage v out = gnd to v cc -1 1 -1 1 a v il input low voltage -0.3 v cc * 0.3 -0.3 v cc * 0.3 v v ih input high voltage v cc * 0.7 v cc + 0.3 v cc * 0.7 v cc + 0.3 v v ol output low voltage i ol = 0.8 ma 0.4 0.4 v v oh output high voltage i oh = 0.8 ma v cc - 0.8 v cc - 0.8 v f op sck frequency 1.0 1.0 mhz t ri input rise time 2.0 2.0 s t fi input fall time 2.0 2.0 s t clh clock high time (note 6) 410 410 ns t cll clock low time (note 6) 410 410 ns t csh min. /cs high time (note 7) 500 500 ns t css /cs setup time 500 500 ns t dis data setup time 100 100 ns t hds /hold setup time 240 240 ns t csn /cs hold time 500 500 ns t din data hold time 100 100 ns t hdn /hold hold time 240 240 ns t pd output delay c l = 200 pf 500 500 ns t dh output hold time 0 0 ns t lz /hold output low z 240 240 ns t df output disable time c l = 200 pf 500 500 ns t hz /hold to output hi z 240 240 ns t wp write cycle time 1-16 bytes 15 15 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 8) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200pf input pulse levels 0.1 * v cc - 0.9 * v cc timing measurement reference level 0.3 * v cc - 0.7 * v cc note 5: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposur e to absolute maximum rating conditions for extended periods may affect device reliability. note 6: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, for a f op of 1mhz, the period equals 1000ns. in this case if t clh = is set to 410ns, then t cll must be set to a minimum of 590ns. note 7: /cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 8: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com fm25c040u rev. a fm25c040u 4k-bit spi interface serial cmos eeprom figure 1. synchronous data timing diagram t css t clh t cll t csh t df t pd t dis t dih t dh t csi sck si so /cs valid input valid output high z mode 3 mode 3 mode 0 mode 0 sck cs so /hold output (n+1) output (n) output (n) output (n+2) t hds t hz t lz t hdh t hds t hdh t dis high z si input (n+1) input (n) input (n) input (n+2) don't care low state ( /cs = 0) don't care figure 3. hold timing figure 2. spi protocol sck si so /cs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 don't care high z mode 3 mode 3
6 www.fairchildsemi.com fm25c040u rev. a fm25c040u 4k-bit spi interface serial cmos eeprom pin description chip select (/cs) this is an active low input pin to the eeprom and is generated by a master that is controlling the eeprom. a low level on this pin selects the eeprom and a high level deselects the eeprom. all serial communications with the eeprom is enabled only when this pin is held low. serial clock (sck) this is an input pin to the eeprom and is generated by the master that is controlling the eeprom. this is a clock signal that synchronizes the communication between a master and the eeprom. all input information (si) to the eeprom is latched on the rising edge of this clock input, while output data (so) from the eeprom is driven after the falling edge of this clock input. serial input (si) this is an input pin to the eeprom and is generated by the master that is controlling the eeprom. the master transfers input information (instruction opcodes, array addresses and data) serially via this pin into the eeprom. this input information is latched on the rising edge of the sck. serial output (so) this is an output pin from the eeprom and is used to transfer output data via this pin to the controlling master. output data is serially shifted out on this pin after the falling edge of the sck. hold (/hold) this is an active low input pin to the eeprom and is generated by the master that is controlling the eeprom. when driven low, this pin suspends any current communication with the eeprom. the suspended communication can be resumed by driving this pin high. this feature eliminates the need to re-transmit the entire sequence by allowing the master to resume the communication from where it was left off. this pin should be tied high if this feature is not used. refer hold function description for additional details. write protect (/wp) this is an active low input pin to the eeprom. this pin allows enabling and disabling of writes to memory array and status register of the eeprom. when this pin is held low, writes to the memory array and status register are disabled. when this pin is held high, writes to the memory array and status register are enabled. status of this pin does not affect operations other than array write and status register write. /wp signal going low at any time will inhibit programming, except when an internal write has already begun. if an internal write cycle has already begun, /wp signal going low will have no effect on the write. refer table1 for write protection matrix. functional description the serial peripheral interface (spi) of fm25c040u consists of an 8-bit instruction register to decode a specific instruction to be executed. six different instructions (opcodes) are incorporated on fm25c040u for various operations. table2 lists the instruc- tions set and the format for proper operation. all opcodes, array addresses and data are transferred in msb first-lsb last fashion. detailed information is provided under individual instruc- tion descriptions. table 2. instruction set instruction instruction operation name opcode wren 00000110 write enabled wrdi 00000100 write disabled rdsr 00000101 read status register wrsr 00000001 write status register read 0000a011 read data from memory array write 0000a010 write data to memory array note: as the fm25c040u requires 9 address bits (4,096 8 = 512 bytes = 2 9 ), the 9th bit (for r/w instructions) is inputted in the instruction set byte in bit i 3 . this convention only applies to 4k spi protocol. in addition to the instruction register, fm25c040u also contains an 8-bit status register that can be accessed by rdsr and wrsr instructions. only the least significant (lsb) 4 bits are defined at present and the most significant (msb) 4 bits are undefined (don t care). the lsb 4 bits define block write protection levels (bp1and bp0), write-enable status (wen) and busy/rdy status (/rdy) of the eeprom. table 3 illustrates the format: table 3. status register format bit bit bit bit bit bit bit bit 76543210 x x x x bp1 bp0 wen rdy refer rdsr and wrsr instruction descriptions for additional information on status register operations. table1. write protection matrix protected blocks /wp pin wen bit status register (by bp1-bp0) unprotected blocks low x write protected write protected write protected high 0 write protected write protected write protected high 1 write allowed write protected write allowed
7 www.fairchildsemi.com fm25c040u rev. a fm25c040u 4k-bit spi interface serial cmos eeprom functional description (continued) spi communication as mentioned before, serial communication with the eeprom is enabled when the /cs pin is held low and the /hold pin is held high. input data (instruction opcodes, array addresses and data) on the si pin is latched in on the rising edges of sck clock signal, starting from the first rising edge after the /cs pin goes low. during the time the si data is input into the eeprom, the so pin remains in high impedance state. if the intended instruction is of read nature (array read and status register read), then data from the eeprom is driven out actively on the so pin from every falling edge of the sck after the last input data (si) is latched in. during the time the so data is output from the eeprom, the data on the si pin is ignored. figure 2 illustrates the above. refer figure 1 for timing information. hold function an active communication with the eeprom can be temporarily suspended by bringing the /hold pin low when a eeprom is selected (/cs pin should be low) and a serial sequence with the eeprom is currently underway. to suspend the communication, /hold pin must be driven low while sck is low, otherwise the hold function will not be invoked until the next sck high to low transition. the eeprom must remain selected during this se- quence. transitions on the sck and si pins are ignored during the time the part is suspended and the so pin will be in high impedance state. releasing the /hold pin back to high state will allow the operation to resume from the point it was suspended. /hold pin must be driven high while the sck pin is low, otherwise serial communication will not resume until the next sck high to low transition. asserting a low on the /hold pin at any time will tri- state the so pin. figure 3 illustrates hold timing. system configuration when multiple spi peripherals (for e.g. eeproms) are present on the bus, the si, so and the sck signals can be tied together. figure 4 illustrates a typical system configuration with respect to /cs, sck, si and so pins. figure 4. system configuration si so sck /cs data out (mosi) data in (miso) serial clock (spick) ss0 ss1 ss2 ss3 si so sck /cs si so sck /cs si so sck /cs spi chip selection master mcu fm25cxxx spi modes 0 and 3 (00 and 11) fm25c040u supports both mode 0 and mode 3 of operations. the difference between mode 0 and mode 3 is determined by the state of the sck clock signal when a spi cycle starts (when /cs is driven low) as well as when the spi cycle ends (when /cs is driven high). under mode 0 of operation, the sck signal is held low both at the start and at the end of a spi cycle. under mode 1 of operation, the sck signal is held high both at the start and at the end of a spi cycle. however in both of these two modes, the input data (si) is sampled (latched in) at the rising edge of the sck clock signal and the output data (so) is driven after the falling edge of the sck clock signal. see figure 1 and figure 2. read sequence (read) reading the memory via the serial spi link requires the following sequence. the /cs pin is pulled low to select the eeprom. the read opcode is transmitted on the si pin followed by the byte address (a7 a0) to be read. after this is done, data on the si pin becomes don t care. the data (d7 d0) at the address specified is then shifted out on the so pin. if only one byte is to be read, the /cs pin can be pulled back to the high level. it is possible to continue the read sequence as the byte address is automatically incremented and data will continue to be shifted out as clock pulses are continuously applied. when the end of memory array is reached (last byte location), the address counter rolls over to the start of memory array (first byte location) allowing the entire memory to be read in one continuous read cycle. see figure 5. figure 5. read sequence / cs si so read opcode byte addr data (1) data (2) data (n) read status register (rdsr): the read status register (rdsr) instruction provides read access to the status register. as mentioned before, of the 8bits of data, only the lsb 4bits are valid and they indicate block protec- tion information (bp1 and bp0), write enable status (wen) and busy/ready status (/rdy) of the eeprom. msb 4bits of are invalid (don t cares) following is the format of rdsr data: table 3. status register format bit bit bit bit bit bit bit bit 76543210 x x x x bp1 bp0 wen rdy bit3 (bp1) and bit2 (bp0) together indicate block write protection previously set on the eeprom. refer table 2. bit1 (wen) indicates the write enable status of the eeprom. this bit is a read-only bit and is read by executing rdsr instruction. if this bit is 1 then the eeprom is write enabled. if this bit is 0 then the eeprom is write disabled. bit0 (/rdy) indicates the busy/ready status of the eeprom. this bit is a read-only bit and is read by executing rdsr instruction. if this bit is 1 then the eeprom is busy doing a program cycle. if this bit is 0 then the eeprom is ready. note that if a rdsr instruction is executed when an internal programming cycle is in progress, only the /rdy bit is valid. all other bits are dont cares.
8 www.fairchildsemi.com fm25c040u rev. a fm25c040u 4k-bit spi interface serial cmos eeprom the rdsr command requires the following sequence. the /cs pin is pulled low to select the eeprom and then the rdsr opcode is transmitted on the si pin. after this is done, data on the si pin becomes don t care. the data from the status register is then shifted out on the so pin starting with d7 bit first and d0 last. see figure 6. figure 6. read status register table 4. block write protection levels level status register bits array address bp1 bp0 protected 0 0 0 none 1 0 1 180-1ff 2 1 0 100-1ff 3 1 1 000-1ff a write command requires the following sequence. the /cs pin is pulled low to select the eeprom, then the write opcode is transmitted on the si pin followed by the byte address (a7-a0) and followed by the data (d7-d0) to be written. see figure 9 . figure 9. byte write / cs si so rdsr op-code rdsr data write enable (wren): when v cc is applied to the eeprom, it powers up in a write- disabled state. therefore, all programming modes (write to memory array and status register), must be preceded by a write en- able (wren) instruction. see figure 7. figure 7. write enable /cs si so wren op-code write disable (wrdi): executing this instruction disables all programming modes (write to memory array and status register), preventing the eeprom from accidental writes. once wrdi instruction is executed, wren instruction should be executed to re-enable all program- ming modes. see figure 8. figure 8. write disable /cs si so wrdi op-code write sequence (write): write to the array is enabled only when /wp pin is held high and the eeprom is write enabled previously (via wren instruction). also, the address of the memory location(s) to be programmed must be outside the protected address field selected by the block write protection level. see table 4. /cs si so write op-code byte addr data high z internally, the programming will start after the /cs pin is brought back to a high level. note that the low to high transition of the /cs pin must occur during the sck low time immediately after clocking in the d0 data bit. see figure 10. figure 10. start of programming sck si so /cs d0 d1 d2 high z start of internal programming programming status (busy/ready) of the eeprom can be deter- mined by executing a read status register (rdsr) in- struction after a write command. upon executing the rdsr instruction, if bit 0 of the rdsr data is 1 , it indicates the write cycle is still in progress. if it is 0 then the write cycle has ended. note that while the internal programming is still in progress (bit 0 = 1), only the rdsr instruction is enabled. it is recommended that no other instruction be issued till the internal programming is complete.
9 www.fairchildsemi.com fm25c040u rev. a fm25c040u 4k-bit spi interface serial cmos eeprom the fm25c040u is also capable of a 4 byte page write operation. page write is performed similar to byte write operation described above. during a page write operation, after the first byte of data, additional bytes (up to 3 bytes) can be input, before bringing the /cs pin high to start the programming. after receipt of each byte of data, the eeprom internally increments the two low order address bits (a1-a0) by one. the high order address bits (a8-a2) will remain constant. if the master should transmit more than 4 bytes of data, the address counter (a1-a0) will roll over and the previously loaded data will be reloaded. see figure 11. figure 11. page write /cs si so write op-code byte addr data (1) data (2) data (3) data (4) /cs si so wrsr op-code sr data xxxxbp1bp0xx figure 12. write status register bp0 sck si so /cs /cs si so invalid code at the completion of a write cycle the eeprom is automatically returned to the write disabled state. note that if the eeprom is not write enabled (wen=0) before issuing the write instruction, the eeprom will ignore the write instruction and return to the standby state when /cs is brought high. write status register (wrsr): the write status register (wrsr) instruction provides write access to the status register. this instruction is used to set block write protection to a portion of the array as defined under table 4. during a wrsr instruction only bit3 (bp1) and bit2 (bp0) can be written with valid information while other bits are ignored. following is the format of wrsr data: status register write data bit bit bit bit bit bit bit bit 76543210 x x x x bp1 bp0 x x x = don t care note that the first four bits are don t care bits followed by bp1 and bp0 and two more don t care bits. wrsr instruction is enabled only when /wp pin is held high and the eeprom is write enabled previously (via wren instruction). wrsr command requires the following sequence. the /cs pin is pulled low to select the eeprom and then the wrsr opcode is transmitted on the si pin followed by the data to be programmed. see figure 12. programming will start after the /cs pin is forced back to a high level. as in the write instruction the low to high transition of the /cs pin must occur during the sck low time immediately after clocking in the last don t care bit. see figure 13. figure 13. start wrsr condition at the completion of this instruction the eeprom is automatically returned to write disabled state. invalid opcode if an invalid code is received, then no data is shifted into the eeprom, and the so data output pin remains high impedance state until a new /cs falling edge reinitializes the serial communi- cation. see figure 14. figure 14. invalid op-code
10 www.fairchildsemi.com fm25c040u rev. a fm25c040u 4k-bit spi interface serial cmos eeprom molded small out-line package (m8) package number m08a molded dual-in-line package (n) package number n08e 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.004 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident
11 www.fairchildsemi.com fm25c040u rev. a fm25c040u 4k-bit spi interface serial cmos eeprom 8-pin molded tssop, jedec (mt8) package number mtc08 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0118 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x physical dimensions inches (millimeters) unless otherwise noted note: metal mask option for 16-byte page size. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841

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