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1 features ? transformerless 2w to 4w conversion ? controls battery feed to line ? programmable line impedance ? programmable network balance impedance ? off-hook and dial pulse detection ? protects against gnd short circuit ? programmable gain ? programmable constant current mode with constant voltage fold over ? transformerless balanced ringing with automatic ring trip circuit. no mechanical relay ? supports low voltage ringing ? line polarity reversal ? on-hook transmission ? power down and wake up capability ? meter pulse injection ? ground key detection applications line interface for: ? pabx ? intercoms ? key telephone systems ? control systems description the zarlink MT91610, with an external bipolar driver (figure 4), provides an interface between a switching system and a subscriber loop. the functions provided by the MT91610 include battery feed, programmable constant current with constant voltage fold over for long loops, 2w to 4w conversion, off-hook and dial pulse detection, direct balance ringing with built in ring tripping, unbalance detection, user definable line and network balance impedance?s and gain, and power down and wake up. the device is fabricated as a cmos circuit in a 36 pin qsop package. figure 1 - functional block diagram td ring tip drive controller audio gain & network balance circuit 2 w to 4 w conversion & line impedance line reverse line sense over-current protection circuit ring drive controller loop supervision tip rc vr z3 z2 cp5 lr v e e g n d v d d c p 3 c p 2 s h k v r e f gtx1 gtx0 vx cp6 driver rv rd u d d c r i v b a t pd esi ese cp4 cp7 c p 1 ringing controller tf rf z1 package information MT91610aq 36 pin qsop package -40 c to +85 c MT91610 programmable ringing slic preliminary information ds5181 issue 6 july 2001
MT91610 preliminary information 2 figure 2 - pin connections pin description pin # name description 1 vdd positive supply rail, +5v. 2 td tip drive (output). controls the tip transistor. connects 330nf cap to gnd. 3 tf tip feed (output). connects to the tip transistor and to tip via the tip feed resistor. 4 nc no connection. left open. 5 tip tip. connects to the tip lead of the telephone line. 6 vref reference voltage (input). used to set the subscribers loop constant current. a 0.1uf cap should be connected between this pin and gnd for noise decoupling. 7 lr line reverse (input). this pin should be set to 0v for normal polarity. setting the pin to +5v reverses the polarity of tip and ring. 8 ring ring. connects to the ring lead of the telephone line. 9 rf ring feed (output). connects to the ring lead via the ring feed resistor. 10 nc no connection. left open. 11 rd ring drive (output). controls the ring transistor. connects 330nf cap to gnd. 12 cp1 cp1 . a 100nf capacitor should be connected between this pin and pin 13. 13 cp2 cp2. a 220nf capacitor for loop stability is connected between this pin and pin 14. 14 cp3 cp3. a 220nf capacitor for loop stability is connected between this pin and pin 13. 15 cp4 cp4 . a 100nf cap should be connected between this pin and gnd. 16 ese external signal enable (input) . a logic ?1? enables the mpi (meter pulse input) to tip / ring. this pin should be set to logic ?0? when not used. 17 pd power down (input) . a logic ?1? power down the device. this pin should be set to logic ?0? for normal operation. 18 dcri dc voltage for ringing input (input) the positive voltage supply for balance ringing. the input dc voltage range is from 0v to +72v. 19 agnd analog ground. 4 wire ground, normally connected to system ground. vx vr vref cp7 vee ring rv gtx0 lr tip nc rf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 36 35 34 33 32 31 30 29 28 27 26 25 24 23 tf vdd td nc rd cp1 cp2 cp3 shk vbat ud rc cp6 gtx1 esi z3 cp4 ese pd dcri 15 16 17 18 22 21 20 19 cp5 z1 z2 agnd
preliminary information MT91610 3 20 z1 line impedance node 1 . a resistor of scaled value "k" is connected between z1 and z2. this connection can not be left open circuit. 21 cp5 line impedance ac couple. a 330 nf cap must be connected between this pin and z1 (pin 20). 22 z2 line impedance node 2 . this is the common connection node between z1 and z3. 23 z3 line impedance node 3 . a resistive or complex network of scaled value "k" is connected between z3 and z2. this connection can not be left open circuit. 24 gtx0 gain node 0 . this is the common node between z3 and vx where resistors are connected to set the 2w to 4w gain. 25 vx transmit audio . 4w analog signal from the slic. 26 esi external signal input . 12 / 16 khz signal input. 27 gtx1 gain node 1 . the common node between vr and the audio input from the codec or switching network where resistors are fitted to set the 4w to 2w gain. 28 vr receive audio . 4w analog signal to the slic. 29 cp6 ringing cap. a 0.47uf cap should be connected between this pin and gnd to filter out the ringing signal. 30 rc ringing control. an active high (+5v) on this pin will set up the dc feed and gain of the slic to apply 20 hz ringing. when low (0v) set the slic in normal constant current mode of operation. 31 ud unbalance detect. logic high (+5v) indicates an offset current between tip and ring. 32 vbat vbat. the negative battery supply, typically at -48v. 33 shk switch hook. this pin indicates the line state of the subscribers telephone. the output can also be used for dial pulse monitoring. logic high (+5v) indicates off hook condition. 34 cp7 deglitching cap. a 33nf should be connected between this pin and gnd. 35 rv ringing voltage. 20 hz sinusoidal or square wave ac in for balance ringing. 36 vee negative supply rail, -5v. pin description (continued) pin # name description functional description refer to figure 4 for MT91610 components designation. the MT91610, with external bipolar transistors, functions as an analog line slic for use in a 4 wire switched system. the slic performs all of the borsh functions while interfacing to a codec or switching system. 2 wire to 4 wire conversion the slic performs 2 wire to 4 wire conversion by taking the 4 wire signal from an analog switch or voice codec, and converting it to a 2 wire differential signal at tip and ring. the 2 wire signal applied to tip and ring by the phone is converted to a 4 wire signal, which is the output from the slic to the analog switch or voice codec. gain control it is possible to set the transmit and receive gains by the selection of the appropriate external components. the gains can be calculated by the following formulae: 2w to 4w gain gain 2 - 4 = 20 log [ r8 / r7] 4w to 2w gain gain 4 - 2 = 20 log [0.891 * [r10 / r9)]
MT91610 preliminary information 4 impedance programming the MT91610 allows the designer to set the device?s impedance across tip and ring, (z tr ), and network balance impedance, (z nb ), separately with external low cost components. the impedance (z tr ) is set by r4, r5, while the network balance, (z nb ), is set by r6, r8, (see figure 4.) the network balance impedance should be calculated once the 2w - 4w gain has been set. line impedance for optimum performance, the characteristic impedance of the line, (z o ), and the device?s impedance across tip and ring, (z tr ), should match. therefore: z o = z tr the relationship between z o and the components that set z tr is given by the formula: z o / ( ra+rb) = kz o / r4 where kz o = r5 ra = rb the value of k can be set by the designer to be any value between 500 and 2000. r4 and r5 should be greater than 100k w. network balance impedance the network balance impedance, (z nb ), will set the transhybrid loss performance for the circuit. the transhybrid loss of the circuit depends on both the 4 - 2 wire gain and the 2 - 4 wire gain. the method of setting the values for r6 (or z6... it can be a complex impedance) is given as below: r6 = r7 * (r9 / r10) * 2.2446689 * ( z nb / z nb + z o ) please note that in the case of z o not equal to z nb (the thl compromized case) r6 is a complex impedance. in the general case of z o matched to z nb (the thl optimised case), r6 is just a single resistor. loop supervision the loop supervision circuit monitors the state of the phone line and when the phone goes ?off hook" the shk pin goes high to indicate this state. this pin reverts to a low state when the phone goes back "on hook" or if the loop resistance is too high (>2.3k w ) when loop disconnect dialling is being used, shk pulses to logic 0 indicate the digits being dialled. this output should be debounced. constant current control & voltage fold over mode the slic employs a feedback circuit to supply a constant feed current to the line. this design is accomplished by sensing the sum of the voltages across the feed resistors, ra and rb, and comparing it to the input reference voltage, vref, that determines the constant current feed current. by using a resistive divider network, (figure 3), it is possible to generate the required voltage to set the loop current, i loop . this voltage can be calculated using the following formula: i loop = [v dd * g] * 3 (ra +rb) where, g = r2 / (r1 + r2) i loop is in ampere. r1= 200k w from figure 3 with ra = rb = 100 w for i loop = 20ma, r2 = 72.73 k w for i loop = 25ma, r2 = 100 k w for i loop = 30ma, r2 = 133.33 k w figure 3 - loop setting r2 ** k w v ref 6 MT91610 r1 +5v c2 0.47uf ** see figure 6 200k
preliminary information MT91610 5 for convenience, a graph which plots the value of r2 (k w ) versus the approximated loop current is shown in figure 6. this graph implies the slic is operating in constant current mode. as +5v is used as the reference voltage to generate the loop current, any noise on the +5v rail will deteriorate the psr (power supply rejection) parameter of the slic. it is therefore important to decouple +5v to gnd. a 0.1uf cap at vref pin (pin6) is recommended. the MT91610 operating current mode is recommended to be between 20ma and 30ma. the device will automatically switch to voltage fold over mode should an unexpected long loop situation occur for a given programmed loop current. the lowest operational current should be 16ma with vbat set at -48v. a typical operating current versus loop resistance with vbat at -48v is shown in figure 7. the actually loop current should settle to within +/- 2 ma of the targeted value. ud & line drivers overcurrent protection the line drivers control the external battery feed circuit which provide power to the line and allows bi- directional audio transmission. the loop supervision circuitry provides bias to the line drivers to feed a constant current. overcurrent protection is done by the following steps: (a) external bipolar transistors to limit the current of the npn drivers to 50ma (figure 5, q14, q15, r9, r19). (b) the local controller should monitor the unbalance detection output (ud) for any extended period of assertion (>5 seconds). in such case the controller should power down the device by asserting the pd pin, and poll the device every 5 seconds. the ud output can be used to support gnd start loop in a pabx operation. reference msan-180 for details. please note that this ud output should be disregarded and masked out if rc pin is active (ie set to +5v). powering up / down sequence agnd is always connected powering up: +5v, -5v, vbat pd to +5v for 100ms; pd to 0v powering down: vbat, -5v, +5v balanced ringing & automatic ring tripping balanced ringing is applied to the line by setting rc (pin 30) to +5v and connecting the ringing signal (20hz) to rv (pin 35) as shown in figure 4. a 1.2vrms input will give approximately 60vrms output across tip and ring, sufficient for short loop slic applications. the slic is capable of detecting an off hook condition during ringing by filtering out the large a.c. component. a 0.47uf cap should be connected to pin cp6 (pin 29) to form such filter. this filter allows a true off hook condition to be monitored at shk (pin 33). when an off hook condition is detected by the slic, it will remove the 20hz ac ringing voltage and revert to constant current mode. the local controller will, however, still need to deselect rc (set it to 0v). the MT91610 supports short burst of ringing cadence. a deglitching input (cp7) is provided to ensure that the shk pin is glitch free during the assertion and de-assertion of rc. a 33nf cap should be connected from this pin to gnd. a positive voltage source is required to be connected to the dcri pin (figure 5) for normal ringing operation. the slic can perform ringing even with the dcri input connected to 0v, however, it does require the vbat to be lower than -48v (ie at -53v or lower) and the 20hz ac input should be a 2vrms square wave. the MT91610 can also be used in applications requiring unbalanced ringing using an external relay. reference msan-180 for details of this and equations related to ringing. line reversal the MT91610 can deliver line reversal, which is required in operation such as ani, by simply setting lr (pin 7) to +5v. the device transmission parameters will cease during the reversal. the lr (pin 7) should be set to 0v for all normal loop operations.
MT91610 preliminary information 6 power down and wake up the MT91610 should normally be powered down to conserve energy by setting the pd pin to +5v. the shk pin will be asserted if the equipment side (2 wire) goes off hook. the local controller should then restore power to the slic for normal operations by setting the pd pin to 0v. please note that there will be a short break (about 80ms) in the assertion time of shk due to the time required for the loop to power up and loop current to flow. the local controller should be able to mask out this time. meter pulse injection the MT91610 provides a gain path input (esi) for meter pulse injection and an independent control logic input (ese) for turning the meter pulse signal on and off. gain (meter pulse) = 20 log [0.891 * (r10 / r11)] with configuration targeting z o = 220 w + (820 w // 115nf) component selection feed resistors the selection of feed resistors, ra and rb, can significantly affect the performance of the MT91610. the value of 100 w is used for both ra and rb. the resistors should have a tolerance of 1% (0.1% matched) and a power rating of 0.5 watt. calculating component values there are five parameters a designer should know before starting the component calculations. these five parameters are: 1) characteristic impedance of the line z o 2) network balance impedance z nb 3) value of the feed resistors (ra and rb) 4) 2w to 4w transmit gain 5) 4w to 2w receive gain the following example will outline a step by step procedure for calculating component values. given: z o = 600 w , z nb = 600 w , ra=rb= 100 w gain 2 - 4 = -6db, gain 4 - 2 = -1 db step 1: gain setting (r7, r8, r9, r10) gain 2 - 4 = 20 log [ r8 / r7] -6 db = 20 log [r8 / r7] \ choose r7 = 300k w , r8 = 150k w . gain 4 - 2 = 20 log [0.891 * [r10 / r9)] -1 db = 20 log [0.891 * [r10/ r9)] \ choose r9 = 200k w , r10 = 200k w . step 2: impedance matching (r4, r5) z o / ( ra+rb) = kz o / r4, where kz o = r5 z o / ( ra+rb) = kz o / r4 600/(100+100) = k*(600)/r4 let k=500 \ r4= 100k w kz o = r5 500*600=r5 \ r5= 300k w step 3: network balance impedance (r6) optimised case z o = z nb r6 = r7 * (r9 / r10) * 2.2446689 * ( z nb / z nb + z o ) r6 = 300k w * (1) * 1.1223344 \ r6= 336.7k w step 4: the loop current (r2) in order to remain in constant current mode during normal operation, it is necessary that the following equation holds: {| i * zt |} v < { | vbat | - 6*vref - 2} v where, i = desirable loop current zt = ra + rb + maximum dc loop resistance vbat = battery voltage vref= dc voltage at vref pin
preliminary information MT91610 7 given the parameters as follows: ra = rb = 100 w expected maximum loop impedance = 1.6k w ( including ra and rb) desirable loop current = 20ma 6*vref=8v then | vbat | (min) = 1600 * 0.020 +10 = 42v assume that the vbat of 42v is available, then read the value of r2 from figure 6, which is 72k w . step 5: calculation of non-clipping sinusoidal ringing voltage at tip ring (vtr) assume the peak ringing current is less than 50ma, the ringing voltage (20hz) at tip and ring is given as: vtr (rms) = 0.707 * {| vbat | + vdcri - (15.6 * vref)} vdcri= positive dc voltage at dcri pin vbat = negative battery voltage vref= positive dc voltage at vref pin ac voltage at the rv input pin is therefore rv (rms)~= vtr (rms) / 50
MT91610 preliminary information 8 figure 4 - typical application with a resistive 600 ohm line impedance rv 35 z1 20 cp5 21 z2 22 z3 23 gtx0 24 vx 25 esi 26 gtx1 27 +5v c10 r4 r5 c5 c4 **c6 2 td 3 tf 1 vdd vee 36 vr 28 ud 31 shk 33 vbat pd 17 lr 7 rc 30 rc 11 rd 34 cp7 18 dcri 15 cp4 14 cp3 5 tip ring 8 ring 9 rf 10 nc 6 vref c2 c11 c12 c13 c1 r2 dcri_in tip/ring driver r7 r6 r8 r11 **c8 r9 r10 r1 +5v 13 cp2 12 cp1 ese 16 = ground (earth) no connect 4 nc no connect c9 switch hook r13 shk c15 c14 unbalance detection ese power down pd line reverse ring control vr_in vx_out esi shk vbat_in tip ring voltage -5v c7 br pr1 ese **r3 d1** ** optional r12 19 agnd c3 cp6 29 vbat 32 1 vdd 2 pd 3 rf 4 ring 5 rci 6 vee 7 nc 8 vbat 9 rf_br 10 nc vbat 11 dcri 12 agnd 13 tf_br 14 vbat 15 rc 16 tf 17 tip 18 tci 19 +5v pd rf ring rd -5v vbat vbat dcri vbat rc tf tip td td tf tip ring rf rd dcri b r f1 f2
preliminary information MT91610 9 note: all resistors are 1/8 w, 1% unless otherwise indicated. *assumes z o = z nb = 600 w , gain 2 - 4 = -6db, gain 4 - 2 = -1db. d1 = 1n5819 schottky diode (optional) pr1 = this device must always be fitted to ensure damages does not occur from inductive loads. for simple applications pr1 can be replaced by a single tvs, such as 1.5ke220c, across tip and ring. for applications requiring lightning and mains cross protection further circuitry will be required and the following protection devices are suggested: p2353aa, p2353ab (teccor), thbt20011, thbt20012, thbt200s (sgs-thomson), tisp72290, tisp7360f3d (t.i.) br = raychem tr600-150 or equivalen t f1, f2 = teccor f1250t slow-blow fuse protection components figure 4 shows three possible combinations of protection. depending on the application, the user can select whether to use a resettable or non-resettable protection scheme. component list* for a typical application with a resistive 600 w line impendance - refer to figure 4 for component designation and recommended configuration resistor values r1 200k w r2 100k w (see figure 6) r3 200k w r4 100k w r5 300k w r6 336k7 w r7 300k w r8 150k w r9 200k w r10 200k w r11 200k w r12 10k w r13 51k w capacitor values c1 220nf, 5% c2 470nf, 5% c3 470nf, 5% c4 100nf, 5% c5 100nf, 5% c6 4.7uf, 5% c7 100nf, 5% c8 100nf, 5% c9 10nf, 5% c10 330nf, 5% c11 33nf, 5% c12 100nf, 5% c13 100nf, 5% c14 330nf, 5% c15 330nf, 5% method slow-blow fuse (f1, f2) varistor (pr1) breaker (br) 1 in place in place short out 2 short out in place in place 3 in place in place in place
MT91610 preliminary information 10 figure 5 - line driver stage rf ra dcri r10 r27 r29 r30 agnd agnd vdd pd r23 r24 q4 vee r21 r22 q3 r26 q13 d8 r13 r11 r17 r12 q9 r14 r15 r32 c2 q12 vee r16 r19 q11 vbat_in d9 tf rb r18 q16 q1 r25 d3 d4 tci vee vbat vbat d6 q10 r28 agnd r3 r1 r7 r2 q7 r4 r5 r31 c1 q8 r6 r9 q5 r8 d1 d2 vbat q6 rci vee d5 d7 vbat tip rc ring q15 q14 pin 13 pin 1 pin 2 pin 6 pin 19 pin 5 pin 12 pin 16 pin 3 pin 4 pin 17 pin 18 pin 8, 11, 15 rf_br tf_br pin 9 pin 14 r20 q2
preliminary information MT91610 11 note: all resistors are 1/8 w, 1% unless otherwise indicated. component list for the tip/ring line driver - refer to figure 5 for component designation and recommended configuration resistor values ra 100 w %1, 0.1% matched, 0.5w rb 100 w %1, 0.1% matched, 0.5w r1 2k5 w r2 3k6 w r3 2k5 w r4 470w r5 470w r6 2k 5w r7 300w r8 11w r9 11w r10 30k w r11 2k5 w r12 3k6 w r13 2k5 w r14 470w r15 470w r16 2k5 w r17 300w r18 11w r19 11w r20 25k w, 1/4 w r21 30k w r22 20 k w r23 20 k w r24 20 k w r25 3 k w r26 30 k w r27 30 k w r28 5 k 1w r29 20 k w r30 30 k w r31 1k w r32 1k w capacitor values c1 10nf, 5% c2 10nf, 5% diodes and transistors d1-d5 bas16 or equivalent d6-d9 baw101 or equivalent q1 mmbta92 or equivalent q2 mmbta92 or equivalent q3 mmbta92 or equivalent q4 mmbta42 or equivalent q5 pzta42 or equivalent q6 pzta92 or equivalent q7 mmbta42 or equivalent q8 mmbta92 or equivalent q9 mmbta42 or equivalent q10 pzta92 or equivalent q11 pzta42 or equivalent q12 mmbta92 or equivalent q13 mmbta92 or equivalent q14 mmbta42 or equivalent q15 mmbta42 or equivalent q16 mmbta42 or equivalent
MT91610 preliminary information 12 figure 6 - approximated r2 (kohm) versus programmed loop current (ma) for constant current mode applications. 145 140 135 130 125 120 115 110 105 100 95 90 85 80 75 70 65 60 55 50 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r2 (kohm) vs loop current (ma ) loop current (ma) r2 (kohm)
preliminary information MT91610 13 figure 7 - loop current (ma) versus loop resistance (ohm) for vbat = -48v loop current (ma) versus loop resistance (ohm) loop resistance (ohm) 31 30 29 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 0 200 400 600 800 1000 1200 1400 1600 27 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000
MT91610 preliminary information 14 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. note 1: refer to figure 3 & 6 for appropriate biasing values note 2: tip and ring drivers to be limited to about 50ma externally (figure 5). if the ud pin is asserted for longer than 5 seco nds, then pd should be asserted to power down the device. the device should then be checked (by de-asserting pd) every 5 seconds. ? typical figures are at 25c with nominal supply voltages and are for design aid only note 3: for a 1.2vrms 20hz input at rv terminal (figure 4) and with rc pin set to +5v. note 4: refer to figure 3 & 6 for biasing values absolute maximum ratings* parameter sym min max units comments 1 dc supply voltages v dd v ee v bat -0.3 +0.3 +0.3 +6.5 -6.5 -72 v v v 2 ringing voltage v ring 100 v rms differentially across tip & ring 3 voltage setting for loop current v ref 0 5 v note 1 4 overvoltage tip/gnd ring/gnd, tip/ring e e 200 v max 1ms (with power on) 5 ringing current i ring 35 ma 6 tip / ring ground over-current 50 ma note 2 7 storage temp t stg -65 +150 c 8 package power dissipation p diss 0.10 w +85c max, v bat = -48v 9 esd maximum rating 500 v recommended operating conditions parameter sym min typ ? max units test conditions 1 operating supply voltages v dd v ee v bat dcri 4.75 -5.25 -72 5 5.00 -5.00 -48 5.25 -4.75 -22 72 v v v v 50ma current capability 2 ringing voltage v ring 60 v rms note 3 3 ringing frequency f ring 16 20 80 hz 4 voltage setting for loop current v ref 1.67 v i loop = 25ma, vbat = -48v note 4 5 operating temperature t o -40 +25 +85 c
preliminary information MT91610 15 ? electrical characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c with nominal 5v and are for design aid only. dc electrical characteristics ? characteristics sym min typ ? max units test conditions 1 supply current i dd i ee i bat 8 6 28 ma ma ma pd= 0v v bat = -48v l bat ~ l loop + 3 ma 2 supply current i dd i ee i bat 300 300 1.8 ua ua ma pd = 5v v bat = -48v 3 constant current line feed i loop 25 ma v ref =1.67v 4 operating loop constant current mode (including the dc resistance of the telephone set) r loop 1600 400 w w i loop = 20ma v bat = -48v i loop = 20ma v bat = -22v 5 off hook detection threshold s hk 12 ma 6 rc, lr input low voltage input high voltage v il v ih 4.5 0.5 v v l il = -1 m a l ih = 1 m a 7 pd, ese input low voltage input high voltage v il v ih 4.5 0.5 v v l il = -1 m a l ih = 1 m a 8 shk output low voltage output high voltage v ol v oh 4.5 0.5 v v l ol = 7.5ma l oh = -1.5ma 9 unbalance detection threshold i ud 12 ma 10 ud output low voltage output high voltage v ol v oh 4.5 0.5 l ol = 0.25ma l oh = -0.25ma 11 dial pulse distortion 1 ms
MT91610 preliminary information 16 ? electrical characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c with nominal 5v and are for design aid only. note 5: refer to figure 4 & 5 for set up and component values. note 6: tlrr is measured from the time when the lr pin is set to 0v (de-selected), to the time when the loop current is within 1 0% of its programmed steady state value. ac electrical characteristics ? characteristics sym min typ ? max units test conditions 1 ring trip detect time tt 90 200 ms 3 return loss (2w) rl 20 30 db 300hz to 3400hz note 5 4 transhybrid loss thl 20 25 db 300hz to 3400hz note 5 5 output impedance at vx 10 w ac small signal 6 gain 4 to 2 wire @ 1khz -1.5 -1 -0.5 db note 5 7 gain relative to 1khz 0.15 db 300hz to 3400hz 8 gain 2w to vx @ 1khz -6.5 -6 -5.5 db note 5 9 gain relative to 1khz 0.15 db 300hz to 3400hz 10 longitudinal to metallic balance at 2w lcl 46 55 db input 2vrms, 1khz 11 total harmonic distortion @2w @vx thd 0.3 0.3 1.0 1.0 % % 1vrms, 1khz @ 2w 1vrms, 1khz @ vr 12 common mode rejection 2 wire to vx cmr 45 50 db input 2vrms, 1khz 13 idle channel noise @2w @vx nc 12 12 dbrnc dbrnc cmessage filter fig. 4 cmessage filter fig. 4 14 power supply rejection ratio at 2w and vx vdd vee psr 23 23 db db 0.1vp-p @ 1khz i loop = 30 ma 15 line reversal recovery timing tlrr 30 50 ms note 6
preliminary information MT91610 17 test circuits figures 8,9,10,11,12 are for illustrating the principles involved in making measurements and do not necessarily reflect the actual method used in production testing. figure 8 - loop current programming figure 9 - 2-4 wire gain figure 10 - 4-2 wire gain & transhybrid loss slic 6 i loop tip ring z o +5v r1 r 2 c2 slic 25 tip ring z o 2 __ z o 2 __ ~ v tr v s v x gain = 20*log(v x /v tr ) r 7 23 24 r 8 27 r9 slic 27 tip ring z o ~ v tr v s gain = 20*log(v tr /v s ) r9 r 1 0 28 24 v x 25 thl = 20*log(v x /v s ) r 6
MT91610 preliminary information 18 figure 11 - longitudinal balance & cmr figure 12 - return loss slic long. bal. = 20*log(v tr /v s ) v x 25 cmr = 20*log(v x /v s ) tip ring z o 2 __ z o 2 __ ~ v tr v s r9 27 slic tip ring r ~ v s gain = 20*log(2*v z /v s ) 27 r9 z o r v z r 5 r 4 23 22 20

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