1 industrial temperature range IDT5V925 programmable clock generator september 2002 2002 integrated device technology, inc. dsc-5943/1 c IDT5V925 industrial temperature range programmable clock generator functional block diagram features: ? 3v to 3.6v operating voltage ? 3.125 mhz to 160mhz output frequency range ? 4 programmable frequency outputs ? input from fundamental crystal oscillator or external source ? balanced drive outputs 12ma ? pll disable mode for low frequency testing ? select inputs (s [1:0] ) for divide selection (multiply ratio of 2, 3, 4, 5, 6, 7, and 8) ? 5v tolerant inputs ? low output skew/jitter ? external pll feedback, internal loop filter ? available in 16-pin qsop package description: the IDT5V925 is a high-performance, low skew, low jitter phase-locked loop (pll) clock driver. it provides precise phase and frequency alignment of its clock outputs to an externally applied clock input or internal crystal oscillator. the IDT5V925 has been specially designed to interface with gigabit ethernet and fast ethernet applications by providing a 125mhz clock from 25mhz input. it can also be programmed to provide output frequencies ranging from 3.125mhz to 160mhz with input frequencies ranging from 3.125mhz to 80mhz. the IDT5V925 includes an internal rc filter that provides excellent jitter characteristics and eliminates the need for external components. when using the optional crystal input, the chip accepts a 10-30mhz fundamental mode crystal with a maximum equivalent series resistance of 50 ?. the on- chip crystal oscillator includes the feedback resistor and crystal capacitors (nominal load capacitance is 15pf). applications: ? ethernet/fast ethernet ? router ? network switches ? san ? instrumentation the idt logo is a registered trademark of integrated device technology, inc. phase detector fb clkin x 1 x 2 optional crystal xtal osc loop filter vco q/n q 0 q 1 q 2 0 1 vco divide 1/n select mode s 0 s 1 oe
2 industrial temperature range IDT5V925 programmable clock generator pin configuration qsop top view pin names i/o description clkin i input clock x 1 (1) i crystal oscillator input. connected to gnd if oscillator not required. x 2 (1) o crystal oscillator output. leave unconnected for clock input. fb i pll feedback input which should be connected to q/n output pin only. pll locks onto positive edge of fb signal. s [1:0] i three level divider/mode select pins. float to mid. q [2:0] o output at n*clkin frequency q/n o programmable divide-by-n clock output oe i tri-state output enable. when asserted high, clock outputs are high impedance. v dd pwr power supply for output buffers gnd pwr ground supply for output buffers v ddq pwr power supply for pll gndq pwr ground supply for pll pin description note: 1. for best accuracy, use parallel resonant crystal specified for a load capacitance of 15pf. output used for allowable clkin range (mhz) (1,2) output frequency relationships feedback minimum maximum q/n q [2:0] q/n 25/n 160/n clkin clkin x n function table notes: 1. operation in the specified clkin frequency range guarantees that the vco will operate in the optimal range of 25mhz to 160mhz . operation with clkin outside specified frequency ranges may result in invalid or out-of-lock outputs. 2. q [2:0 ] is not allowed to be used as feedback. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 s 1 s 0 gndq v ddq x 1 x 2 clkin fb gnd q 2 q 1 q 0 q/n gnd oe v dd symbol description max unit v term supply voltage to ground ?0.5 to +7 v dc output voltage v out ?0.5 to v cc +0.5 v dc input voltage v in ?0.5 to +7 v t a = 85c maximum power dissipation .55 w t stg storage temperature ?65 to +150 c absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. crystal specification the crystal oscillators should be fundamental mode quartz crystals: overtone crystals are not suitable. crystal frequency should be specified for parallel resonance with 50 ? maximum equivalent series resonance.
3 industrial temperature range IDT5V925 programmable clock generator divide selection table (1) notes: 1. h = high m = medium l = low 2. factory test mode: operation not specified, 3. ethernet mode (use a 25mhz input frequency and q/n as feedback). 4. test mode for low frequency testing. in this mode, clkin bypasses the vco (vco powered down). frequency must be > 1mhz due to dynamic circuits in the frequency dividers. q [2:0] outputs are divided by 2 in test mode. s1 s0 divide-by-n value mode l l factory test (2) l m 2 pll l h 3 pll m l 4 pll mm5 (3) pll m h 6 pll h l 7 pll h m 8 pll h h 16 test (4) symbol description min. typ. max. unit v dd/ v ddq power supply voltage 3 3.3 3.6 v t a operating temperature ?40 +25 +85 c c l output load capacitance ? ? 15 pf c in input capacitance, clkin, fb, oe , f = 1mhz, v in = 0v, t a = 25c ? 5 7 pf operating conditions note: 1. these inputs are normally wired to v cc , gnd, or unconnected. if the inputs are switched in real time, the function and timing of the outputs may glitch, and the pll may require an additional lock time before all the datasheet limits are achieved. dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 3.3v 0.3v symbol parameter test conditions min. typ. (7) max unit v il input low voltage ? ? 0.8 v v ih input high voltage 2 ? ? v v ihh (1) input high voltage 3-level input only v dd - 0.6 ? ? v v imm (1) input mid voltage 3-level input only v dd /2 - 0.3 ? v dd /2 + 0.3 v v ill (1) input low voltage 3-level input only ? ? 0.6 v i in input leakage current v in = v dd or gnd, v dd = max - 5 ? +5 a (clkin, fb inputs only) v in = v dd high level ? ? +200 i 3 3-level input dc current, s [1:0] v in = v dd /2 mid level - 50 ? +50 a v in = gnd low level - 200 ? ? i ih input high current v in = v dd - 5 0.07 +5 a v ol output low voltage i ol = 12ma ? 0.15 0.55 v v oh output high voltage i oh = -12ma 2.4 2.8 ? v
4 industrial temperature range IDT5V925 programmable clock generator ac electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 3.3v 0.3v symbol parameter test conditions min. typ. max. unit t r, t f rise time, fall time (1) 0.8v to 2v ? 0.7 1.5 ns d t output/duty cycle (1) v t = v dd /2 45 ? 55 % t pd clkin to fb (1) v t = v dd /2 - 300 ? 300 ps t sk output to output skew (1) v t = v dd /2; q [2:0] ? ? 100 ps v t = v dd /2; q/n - q [2:0] ? ? 300 t j cycle - cycle jitter (1) ? ? 200 ps f out output frequency 25 ? 160 mhz power supply characteristics symbol parameter test conditions (1) min. typ. max unit i ddq quiescent supply current v dd = max. ? 0.7 2 ma clkin = fb = x 1 = gnd s [1:0] = hh oe = h all outputs unloaded ? i dd supply current per input v dd = max., v in = 3v ? 1 30 a i dd dynamic supply current v dd = 3.6v ? 77 130 ma s [1:0] =lm oe = gnd f out = 60mhz all outputs unloaded note: 1. for conditions shown as min. or max., use the appropriate values specified under dc electrical characteristics. note: 1. this parameter is guaranteed by design but not tested. input timing requirements symbol description min. max. unit t r, t f maximum input rise and fall time, 0.8v to 2v (1) ?2ns d h input duty cycle (1) 25 75 % f osc xtal oscillator frequency ? 30 mhz f in input frequency 25/n 160/n mhz note: 1. this parameter is guaranteed by design but not tested.
5 industrial temperature range IDT5V925 programmable clock generator test loads and waveforms how to use the 5v925 the 5v925 is a general-purpose phase-locked loop (pll) that can be used as a zero delay buffer or a clock multiplier. it generates three outputs at the vco frequency and one output at the vco frequency divided by n, where n is determined by the mode/frequency select input pins s 0 and s 1 . the pll will adjust the vco frequency (within the limits of the function table) to ensure that the input frequency equals the q/n frequency. the 5v925 can accept two types of input signal. the first is a reference clock generated by another device on the board which needs to be reproduced with a minimal delay between the incoming clock and output. the second is an external crystal. when used in the first mode, the crystal input (x 1 ) should be tied to ground and the crystal output (x 2 ) should be left unconnected. 15pf 150 ? output v cc 150 ? 2v v th = v cc /2 0v 1ns 3v 1ns 2v v th = v cc /2 0v t r t f v cc 0.8 0.8 ac test load input test waveform output waveform fb clkin x 2 x 1 s 0 s 1 q/n q 0 q 1 q 2 5v925 figure 1 by connecting q/n to fb (see figure 1), the 5v925 not only becomes a zero delay buffer, but also a clock multiplier. with proper selection of s 0 and s 1 , the q 0 ?q 2 outputs will generate two, three, up to eight times the input clock frequency. make sure that the input and output frequency specifica- tions are not violated (refer to function table). there are some applications where higher fan-out is required. these kinds of applications could be addressed by using the 5v925 in conjunction with a clock buffer such as the 49fct3805. figure 2 shows how higher fan-out with different clock rates can be generated. figure 2 5 copies of q/n 5 copies of q 49fct3805 fb clkin x 2 x 1 s 0 s 1 q [2:0] q/n ina inb 5v925
6 industrial temperature range IDT5V925 programmable clock generator by connecting one of the 49fct3505 outputs to the fb input of the 5v925 , the propagation delay from clkin to the output of the 49fct3505 will be nearly zero. to ensure pll stability, only one 49fct3505 should be included between q/n and fb. one of the questions often asked is what is the accuracy of our clock generators? in applications where clock synthesizers are used, the terms frequency accuracy and frequency error are used interchangeably. here, frequency accuracy (or error) is based on two factors. one is the input frequency and the other is the multiplication factor. clock multipliers (or synthesizers) are governed by the equation: output frequency = (m)* input frequency n where ?m? is the feedback divide and ?n? is the reference divide. if the ratio of m/n is not an integer, then the output frequency will not be an exact multiple of the input. on the other hand, if the ratio were a whole number, the output clock would be an exact multiple of the input. in the case of 5v925, since the reference divide (?n?) is ?1?, the equation is a strong function of the feedback divide (?m?). in addition, since the feedback is an integer, the output frequency error (or accuracy) is merely a function of how accurate the input is. for instance, 5v925 could accept two forms of input, one from a crystal oscillator (see figure 1) and the other from a crystal (see figure 3). by using a 20mhz clock with a multiplication factor of 5 (with an accuracy of 30 parts per million), one can easily have three copies of 100mhz of clock with 30ppm of accuracy. frequency accuracy is defined by the following equation: accuracy = (measured freq. ? nominal freq.) nominal frequency where measured frequency is the average frequency over certain number of cycles (typically 10,000) and the nominal frequency is the desired frequency. clkin x 2 x 1 s 0 s 1 q 0 q 1 q 2 q/n xtal osc 5v925 fb figure 3 the second way to drive the input of the 5v925 is via an external crystal. when connecting an external crystal to pins 5 and 6, the x 2 pin must be shorted to the clkin (pin 7) as shown in figure 3. for best accuracy, a parallel resonant crystal with a crystal load capacitance rating of 15pf should be used. to reduce the parasitic between the external crystal and the 5v925 , it is recommended to connect the crystal as close as possible to the x 1 and x 2 pins.
7 industrial temperature range IDT5V925 programmable clock generator ordering information idt xxxx x package device type quarter size outline package (150 mil.) q 5v925 programmable clock generator x process -40c to +85c (industrial) i corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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