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preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 1 features generates all clock frequencies for via kt266 chipset. support one pair of differential cpu clocks, one pair of differential push-pull cpu clocks, 3 agp and 10 pci. enhanced pci output drive selectable by i2c. one 48mhz clock and 24_48mhz clock via i2c. three 14.318mhz reference clocks. power management control to stop cpu, pci, ref, 24_48mhz, 48mhz and agp clocks. supports 2-wire i2c serial bus interface with readback. single byte micro-step linear frequency programming via i2c with glitch free smooth switching. built-in programmable watchdog timer up to 63 seconds with 1-second interval. it will generate a low reset output when timer expired. spread spectrum 0.25% center, 0.5% center, 0.75% center, and 0 to -0.5% downspread. 50% duty cycle with low jitter. available in 300 mil 48 pin ssop. block diagram pin configuration note: ^: pull up v: pull down #: active low * : bi-directional up latched at power-up power group vdd1: ref(0:1), ref_f, xin, xout vdd2: 48mhz or 24_48mhz vdd3: pci(0:8), pci9_e vdd4: agp(0:2) vddl1: cput0, cpuc0, cput_cs, cpuc_cs vddl2: pll core key specifications cpu cycle to cycle jitter: 250ps. pci cycle to cycle jitter: 500ps. pci to pci skew: 500ps. cpu to cpu skew: 175ps. agp to agp skew: 250ps. cpuc0 vddl1 cput_cs cpuc_cs gnd cpu_stop#^ pci_stop/ wdreset# pd# vddl2 gnd sdata vdd3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PLL205-14 ref0/fs0*^ ref1/fs1*^ ref_f ref_stop#^ agp_stop#^ gnd cput0 sclk gnd agp2 agp1 agp0 vdd4 sel24_48#^ pci4 vdd3 pci3 pci0 pci_f gnd 24_48mhz/fs4* v 48mhz/fs3*^ vdd2 xout xin gnd vdd1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 pci1 gnd pci2 pci8/fs2*^ pci7 gnd pci6 pci5 pci9_e/selpci9_e# 48mhz 24_48mhz pd xin xout fs (0:4)* xtal osc pll1 sst control logic vdd1 ref(0:1) vdd4 agp (0:2) pci (0:8) pci9_e vdd3 vdd2 pll2 ? 2 ref_f cput0 cpuc0 cput_cs cpuc_cs vddl1 sdata sclk i2c logic watch dog wdreset#
preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 2 pin descriptions name number type description vdd1 1 p power supply for ref(0:1), ref_f and crystal oscillator. vdd2 5 p power supply for 48mhz or 24_48mhz. vdd3 15,23 p power supply for pci(0:8), pci9_e. vdd4 25 p power supply for agp(0:2). vddl1 40 p power supply for cput0, cpuc0, cput_cs and cpuc_cs. vddl2 33 p power supply for pll core. gnd 2,8,12,19,29, 32,37,43 p ground. xin 3 i 14.318mhz crystal input to be connected to one end of the crystal. xout 4 o 14.318mhz crystal output. pd# 34 i pd is asynchronous active low input used to power down the device into a low power state. the internal clocks are disabled and the vco and the crystal are stopped. pci_stop/ wdreset# 35 b when input is low, it will stop pci(0:8) and pci9_e. the enable of the watchdog timer masks the pci_stop action. cpu_stop 36 i when input is low, it will disable cput_cs and cpuc_cs. agp_stop 44 i when input is low, it will stop agp(0:2). ref_stop 45 i when input is low, it will disable ref(0:1), 24_48mhz and 48mhz except ref_f output. pci(0:8) 10,11,13,14, 16,17,18,20,21 o pci clocks with frequencies defined by frequency table. these pins will be low when pci_stop is low. pci9_e/selpci9_e 22 b at power up, this pin is an input pin and will determine the operating frequency of pci9_e output. after input sampling, this pin will generate pci output clock. if selpci9_e=1, pci9_e will arrive 2 ns earlier than other pci clocks, if selpci9_e=0, pci9_e will be normal pci output like other pci clock outputs. pci_f 9 o free running pci clock. cput0 42 o ?true? clock of differential pair open drain cpu outputs. cpuc0 41 o ?complementary? clock of differential pair open drain cpu outputs. cput_cs, cpuc_cs 39,38 o differential cpu clock outputs for the chipset. they are push-pull outputs. these outputs will be disabled when cpu_stop is low. agp(0:2) 26,27,28 o agp clocks outputs defined as 2x pci. sdata 31 b sclk 30 i serial data input for serial interface port. ref0/fs0* ref1/fs1* pci8/fs2* 48mhz/fs3* 24_48mhz/fs4* 48,47,21,6,7 b at power up, these pins are input pins. after input sampling, these pins will generate output clocks. fs(0:3) have internal pull-up resistor while fs4 has internal pull-down resistor. sel24_48# 24 i this pin will select 24mhz (when high) or 48mhz (when low) for pin7. ref(0:1),ref_f 48,47,46 o 3.3v 14.318mhz clock output.
preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 3 power management cpu_stop pci_stop cput0 cpuc0 pci pci_f xtal,vco 1 1 running running running running running 0 1 stopped low stopped low running running running 1 0 running running stopped low running running frequency ( mhz) selection table fs4 fs3 fs2 fs1 fs0 cpu agp pci spread spectrum 0 0 0 0 0 90.00 60.00 30.00 0.25% 0 0 0 0 1 100.00 66.67 33.33 0.25% 0 0 0 1 0 101.00 67.33 33.67 0.25% 0 0 0 1 1 102.00 68.00 34.00 0.25% 0 0 1 0 0 103.00 68.67 34.33 0.25% 0 0 1 0 1 105.00 70.00 35.00 0.25% 0 0 1 1 0 107.00 71.33 35.67 0.25% 0 0 1 1 1 110.00 73.33 36.67 0.25% 0 1 0 0 0 113.00 75.33 37.67 0.25% 0 1 0 0 1 115.00 76.67 38.33 0.25% 0 1 0 1 0 117.00 78.00 39.00 0.25% 0 1 0 1 1 120.00 80.00 40.00 0.25% 0 1 1 0 0 120.00 60.00 30.00 0.25% 0 1 1 0 1 125.00 62.50 31.25 0.25% 0 1 1 1 0 133.33 66.67 33.33 0.25% 0 1 1 1 1 135.00 67.50 33.75 0.25% 1 0 0 0 0 100.00 66.67 33.33 0 to -0.5% 1 0 0 0 1 100.00 66.67 33.33 0.5% 1 0 0 1 0 100.00 66.67 33.33 0.75% 1 0 0 1 1 136.00 68.00 34.00 0.25% 1 0 1 0 0 138.00 69.00 34.50 0.25% 1 0 1 0 1 140.00 70.00 35.00 0.25% 1 0 1 1 0 142.00 71.00 35.50 0.25% 1 0 1 1 1 145.00 72.50 36.25 0.25% 1 1 0 0 0 150.00 75.00 37.50 0.25% 1 1 0 0 1 155.00 77.50 38.75 0.25% 1 1 0 1 0 166.00 66.40 33.20 0.25% 1 1 0 1 1 180.00 72.00 36.00 0.25% 1 1 1 0 0 200.00 80.00 40.00 0.25% 1 1 1 0 1 133.33 66.67 33.33 0 to -0.5% 1 1 1 1 0 133.33 66.67 33.33 0.5% 1 1 1 1 1 133.33 66.67 33.33 0.75%
preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 4 frequency ( mhz) selection table by group timing divider ratio (cpu:agp) fs4 fs3 fs2 fs1 fs0 cpu agp pci spread spectrum 0 0 0 0 0 90.00 60.00 30.00 0.25% 0 0 0 0 1 100.00 66.67 33.33 0.25% 1 0 0 0 0 100.00 66.67 33.33 0 to -0.5% 1 0 0 0 1 100.00 66.67 33.33 0.5% 1 0 0 1 0 100.00 66.67 33.33 0.75% 0 0 0 1 0 101.00 67.33 33.67 0.25% 0 0 0 1 1 102.00 68.00 34.00 0.25% 0 0 1 0 0 103.00 68.67 34.33 0.25% 0 0 1 0 1 105.00 70.00 35.00 0.25% 0 0 1 1 0 107.00 71.33 35.67 0.25% 0 0 1 1 1 110.00 73.33 36.67 0.25% 0 1 0 0 0 113.00 75.33 37.67 0.25% 0 1 0 0 1 115.00 76.67 38.33 0.25% 0 1 0 1 0 117.00 78.00 39.00 0.25% a ( 1.5 : 1 ) 0 1 0 1 1 120.00 80.00 40.00 0.25% 0 1 1 0 0 120.00 60.00 30.00 0.25% 0 1 1 0 1 125.00 62.50 31.25 0.25% 0 1 1 1 0 133.33 66.67 33.33 0.25% 1 1 1 0 1 133.33 66.67 33.33 0 to -0.5% 1 1 1 1 0 133.33 66.67 33.33 0.5% 1 1 1 1 1 133.33 66.67 33.33 0.75% 0 1 1 1 1 135.00 67.50 33.75 0.25% 1 0 0 1 1 136.00 68.00 34.00 0.25% 1 0 1 0 0 138.00 69.00 34.50 0.25% 1 0 1 0 1 140.00 70.00 35.00 0.25% 1 0 1 1 0 142.00 71.00 35.50 0.25% 1 0 1 1 1 145.00 72.50 36.25 0.25% 1 1 0 0 0 150.00 75.00 37.50 0.25% b ( 2 : 1 ) 1 1 0 0 1 155.00 77.50 38.75 0.25% 1 1 0 1 0 166.00 66.40 33.20 0.25% 1 1 0 1 1 180.00 72.00 36.00 0.25% c ( 2.5 : 1 ) 1 1 1 0 0 200.00 80.00 40.00 0.25%
preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 5 i2c bus configuration setting address assignment a6 a5 a4 a3 a2 a1 a0 r/w 1 1 0 1 0 0 1 _ slave receiver/transmitter provides both slave write and readback functionality data transfer rate standard mode at 100kbits/s serial bits reading the serial bits will be read or sent by the clock driver in the following order byte 0 ? bits 7, 6, 5, 4, 3, 2, 1, 0 byte 1 ? bits 7, 6, 5, 4, 3, 2, 1, 0 - byte n ? bits 7, 6, 5, 4, 3, 2, 1, 0 data protocol this serial protocol is designed to allow both blocks write and read from the controller. the bytes must be accessed in sequential order from lowest to highest byte. each byte transferred must be followed by 1 acknowledge bit. a byte transferred without acknowledged bit will terminate the transfer. the write or read block both begins with the master sending a slave address and a write condition (0xd2) or a read condition (0xd3). following the acknowledge of this address byte, in write mode: the command byte and byte count byte must be sent by the master but ignored by the slave, in read mode: the byte count byte will be read by the master then all other data byte . i2c control registers 1. byte 0: functional and frequency select clock register (1=enable, 0=disable) bit pin# default description bit 7 6 0 fs3 ( see frequency selection table ) bit 6 21 0 fs2 ( see frequency selection table ) bit 5 47 0 fs1 ( see frequency selection table ) bit 4 48 0 fs0 ( see frequency selection table ) bit 3 - 0 frequency selection control bit 1=via i2c, 0=via external jumper bit 2 7 0 fs4 ( see frequency selection table ) bit 1 - 1 0 = off, 1 = spread spectrum enable bit 0 - 0 0 = normal, 1 = tristate mode for all outputs
preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 6 2. byte 1: cpu clock register (1=enable, 0=disable) bit pin# default description bit 7 - x inverted power-up latched fs2 value (read only) bit 6 - x inverted power-up latched fs1 value (read only) bit 5 - 1 1 = normal, 0 = pci drive enhanced 25% bit 4 - x inverted power-up latched fs0 value (read only) bit 3 39,38 1 cput_cs, cpuc_cs ( active/inactive ) bit 2 42,41 1 cput0, cpuc0 ( active/inactive ) bit 1 22 1 pci9_e ( active/inactive ) bit 0 21 1 pci8 ( active/inactive ) 3. byte 2: pci clock register (1=enable, 0=disable) bit pin# default description bit 7 20 1 pci7 ( active/inactive ) bit 6 18 1 pci6 ( active/inactive ) bit 5 17 1 pci5 ( active/inactive ) bit 4 16 1 pci4 ( active/inactive ) bit 3 14 1 pci3 ( active/inactive ) bit 2 13 1 pci2 ( active/inactive ) bit 1 11 1 pci1 ( active/inactive ) bit 0 10 1 pci0 ( active/inactive ) 4. byte 3: agp clock register (1=enable, 0=disable) bit pin# default description bit 7 - x inverted power-up latched fs3 value (read only) bit 6 7 1 reserved bit 5 6 1 48mhz ( active/inactive ) bit 4 7 1 24_48mhz ( active/inactive ) bit 3 9 1 pci_f ( active/inactive ) bit 2 28 1 agp2 ( active/inactive ) bit 1 27 1 agp1 ( active/inactive ) bit 0 26 1 agp0 ( active/inactive )
preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 7 5. byte 4: linear programming register (1=enable, 0=disable) bit pin# default description bit 7 - 0 linear programming sign bit ( 0 is ? + ?, 1 is ? - ? ) bit 6 - 0 linear programming magnitude bit 6 (msb) bit 5 - 0 linear programming magnitude bit 5 bit 4 - 0 linear programming magnitude bit 4 bit 3 - 0 linear programming magnitude bit 3 bit 2 - 0 linear programming magnitude bit 2 bit 1 - 0 linear programming magnitude bit 1 bit 0 - 0 linear programming magnitude bit 0 (lsb) 6. byte 5: peripheral clock register (1=enable, 0=disable) bit pin# default description bit 7 - x inverted power-up latched fs4 value (read only) bit 6 - 1 reserved ( active/inactive ) bit 5 44 1 agp_stop ( active/inactive ) bit 4 45 1 ref_stop ( active/inactive ) bit 3 46 1 ref_f ( active/inactive ) bit 2 - 1 reserved bit 1 47 1 ref1 ( active/inactive ) bit 0 48 1 ref0 ( active/inactive ) 7. byte 6: reserved register (for external ddr buffer) bit pin# default description bit 7 - 1 reserved bit 6 - 1 reserved bit 5 - 1 reserved bit 4 - 1 reserved bit 3 - 1 reserved bit 2 - 1 reserved bit 1 - 1 reserved bit 0 - 1 reserved
preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 8 8. byte 7: reserved register (for external ddr buffer) bit pin# default description bit 7 - 1 reserved bit 6 - 1 reserved bit 5 - 1 reserved bit 4 - 1 reserved bit 3 - 1 reserved bit 2 - 1 reserved bit 1 - 1 reserved bit 0 - 1 reserved 9. byte 8: watchdog timer / revision id and vendor id register (1=enable, 0=disable) bit pin# default description bit 7 - 0 watchdog timer enable bit. 1=enable, 0=disable bit 6 - 0 revision id bit 2* bit 5 - 0 watchdog time interval bit 5 (msb) revision id bit 1* bit 4 - 0 watchdog time interval bit 4 revision id bit 0* bit 3 - 0 watchdog time interval bit 3 vendor id bit 3* bit 2 - 0 watchdog time interval bit 2 vendor id bit 2* bit 1 - 1 watchdog time interval bit 1 vendor id bit 1* bit 0 - 1 watchdog time interval bit 0 (lsb) vendor id bit 0* note: *: default value at power-up. don?t write into this register, writing into this register can cause malfunction.
preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 9 programming of cpu frequency to simplify traditional loop counter setting, the pll205-04 device incorporates smart-byte ? technology with a single byte programming via i2c to better optimize clock jitter and spread spectrum performance. detail of pll205-04's dual mode frequency programming method is described below: 1. rom-table frequency programming: the pre-defined 32 frequencies found in frequency table can be accessed either through 5 external jumpers or by setting internal i2c register in byte0. 2. fine-step linear frequency programming: cpu frequency can be programmed via i2c in fine and linear positive or negative stepping around current selected cpu frequency in frequency table. the highest step is either +127 or -127. other bus frequencies will be changed proportionally with the rate that cpu frequency change. the formula is as follow: f cpu = f cpu-rom-table a a (=0.30, 0.22 or 0.18) * m where : 1. m is magnitude factor defined in i2c byte4.bit (0:6) 2 . ( sign bit) of m is defined in i2c byte4.bit 7 3. a is a constant but related to cpu's three timing groups definition a = 0.30 (for group a), a = 0.22 (for group b) or a = 0.18 (for group c) frequency programming example: 1. procedures to program target cpu frequency to 122.0 mhz in group b timing: a. locate the closest cpu frequency from frequency from frequency-rom table: 120.0 b. a = 0.22 for group b c. solve m (linear magnitude factor) in integer: m = (f cpu - f cpu-romtable ) / a = (122 - 120) / 0.22 = 9 d. program i2c register: 7 6 5 4 3 2 1 0 1 1 0 0 1 0 0 0 fs3 fs2 fs1 fs0 ctr fs4 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 1 sign m6 m5 m4 m3 m2 m1 m0 f cpu = 120.0 + (0.22) * 9 = 121.98 ( % of frequency increased = 0.016% ) f agp = 60.0 * (1 + 0.016% ) = 60.01 f pci = 30.0 * (1 + 0.016%) = 30.00 setting of m = +9 in i2c.byte4 setting of i2c.byte0
preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 10 wdt operational flow chart success i2c register loading: fall-back, m, wd-timer , wd-enable i2c register loading: fsel wait for system response fail - after specified wd-timer expired disable wd- enable bit f cpu = target setting system restart @ fall-back frequency fail - after specified wd-timer expired success copy fall-back frequency setting to i2c frequency setting disable wd- enable bit f cpu = fall-back frequency setting system restart @ jumper-setting frequency end start end end
preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 11 electrical specifications 1. absolute maximum ratings parameters symbol min. max. units supply voltage v dd v ss - 0.5 7 v input voltage, dc v i v ss - 0.5 v dd + 0.5 v output voltage, dc v o v ss - 0.5 v dd + 0.5 v storage temperature t s -65 150 c ambient operating temperature t a 0 70 c junction temperature t j 115 c esd voltage 2 kv exposure of the device under conditions beyond the limits specified by maximum ratings for extended periods may cause permanent damage to the device and affect product reliability. these conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. dc/ac electrical specifications parameters symbol conditions min. typ. max. units input high voltage v ih all inputs except xin 2 v dd +0.3 v input low voltage v il all inputs except xin v ss -0.3 0.8 v input high current i ih v in = v dd 5 ua input low current i il1 v in =0 with no pull-up resistor -5 input low current i il2 v in =0 with pull-up resistor -200 ua i dd c l =0 pf@66mhz, 3.3v 5% i ddl c l =0 pf@133mhz, 3.3v 5% 180 i dd c l =0 pf@66mhz, 2.5v 5% 72 supply current i ddl c l =0 pf@133mhz, 2.5v 5% 100 ma transition time t trans to 1 st crossing of target freq. 3 ms pull-up resistor r pu pin 6,21,35,36,44,45,47,48 120 kohm pull-down resistor r dw pin 7 120 kohm input frequency f i v dd = 3.3v 12 14.318 16 mhz c in logic inputs 5 pf input capacitance c inx xin & xout pins 27 28 45 pf
preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 12 2. dc/ac electrical specifications (continued) unless otherwise stated, all power supplies = 3.3v 5%, and ambient temperature range t a = 0 c to 70 c parameters symbol outputs conditions min. typ. max. units cpu measured @ 0.4v ~ 2.0v, c l =10-20pf, 2.5v 5% 1.6 ref, 48mhz, 24mhz measured @ 0.4v ~ 2.4v, c l =10-20pf 4 output rise time t or pci_f, pci, agp, apic measured @ 0.4v ~ 2.4v, c l =10-30pf 2 ns cpu measured @ 2.0 ~ 0.4v, c l =10-20pf, 2.5v 5% 1.6 ref, 48mhz, 24mhz measured @ 2.4v ~ 0.4v, c l =10-20pf 4 output fall time t of pci_f, pci, agp, apic measured @ 2.4v ~ 0.4v, c l =10-30pf 2 ns cpu,apic,ref, 48mhz,24mhz measured @ 1.5v c l =20pf 45 50 55 duty cycle d t pci, agp measured @ 1.5v, c l =20~30pf 40 55 % cpu rising edge @ 1.25v, c l =20pf 175 pci rising edge @ 1.5v, c l =30pf 500 clock skew t skew agp rising edge @ 1.5v, c l =30pf 250 ps cpu measured @ 1.25v 250 jitter(cycle to cycle) j cyc-cyc pci, agp measured @ 1.5v 500 ps frequency stabilization time t fst cpu,pci_f,pci, apic,agp,ref, 48mhz,24mhz assumes full supply voltage reached within 1ms from power-up. short cycle exist prior to frequency stabilization. 3 ms cpu v dd =3.3v(2.5v) 5% 20 pci,agp v dd =3.3v 5% 30 ac output impedance z 0 ref,48mhz,24mhz v dd =3.3v 5% 40 ohm
preliminary PLL205-14 programmable clock generator for via kt-266 chipset 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 12/04/00 page 13 package information ordering information phaselink corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. the information furnished by phaselink is believed to be accurate and reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselink?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of phaselink corporation. for part ordering, please contact our sales department: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492-0990 fax: (510) 492-0991 part number the order number for this device is a combination of the following: device number, package type and operating temperature range PLL205-14 x c part number temperaturature c=commercial m=military i=industral package type x=ssop 0.008 - 0.016 (0.203 - 0.406) 0.620 - 0.630 (15.75 - 16.00) (0.254 - 0.406) 45 0 0.010 - 0.016 0.050 (1.27) min 3 0 -6 0 0.015 (0.381) 0.088 - 0.096 (2.235 - 2.438) 0.097 - 0.104 (2.464 - 2.642) 0.025 0.635 0.400 - 0.410 10.160 - 10.414 0.292 - 0.299 7.417 - 7.595 0.008 - 0.0135 0.203 - 0.343 48pin ssop

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