View AD7395AR_5228009.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7394/ad7395 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 +3 v, dual, serial input 12-/10-bit dacs functional block diagram dac b op amp b en dac a op amp a d pr cs clk sdi (data) lda ldb dgnd msb rs shdn v outa v outb v dd v ref agnd pr d 12 ad7394/ad7395 s h i f t r e g i s t e r d a c a r e g i s t e r d a c b r e g i s t e r features micropower: 100 m a/dac 0.1 m a typical power shutdown single-supply +2.7 v to +5.5 v operation compact 1.1 mm height tssop-14 package ad7394/12-bit resolution ad7395/10-bit resolution serial interface with schmitt trigger inputs applications automotive output span voltage portable communications digitally controlled calibration pc peripherals general description the ad7394/ad7395 family of dual, 12-/10-bit, voltage output digital-to-analog converters is designed to operate from a single +3 v supply. built using a cbcmos process, this monolithic dac offers the user low cost and ease of use in single-supply +3 v systems. operation is guaranteed over the supply voltage range of +2.7 v to +5.5 v making this device ideal for battery operated applications. the full-scale output voltage is determined by the applied exter- nal reference input voltage, vref. the rail-to-rail vref input to v out outputs allows for a full-scale voltage set equal to the positive supply v dd or any value in between. a doubled-buffered serial data interface offers high speed, microcontroller compatible inputs using serial-data-in (sdi), clock (clk) and load strobe ( lda + ldb ) pins. a chip-select ( cs ) pin simplifies connection of multiple dac packages by enabling the clock input when active low. additionally, an rs input sets the output to zero scale or to 1/2 scale based on the logic level applied to the msb pin. the power shutdown pin, shdn , reduces power dissipation to nanoamp current levels. all digital inputs contain schmitt-triggered logic levels to mini- mize power dissipation and prevent false triggering on the clock input. both parts are offered in the same pinout to allow users to select the amount of resolution appropriate for their application with- out circuit card redesign. the ad7394/ad7395 is specified over the extended industrial (C40 c to +85 c) temperature range. packages available in- clude plastic dip and low profile 1.75 mm height so-14 surface mount packages. the AD7395ARu is available for ultr acompact applications in a thin 1.1 mm tssop-14 package. for automotive applications the AD7395AR is specified for operation over the (C40 c to +125 c) temperature range. v dd = 3v v ref = 2.5v code C decimal 1 0.8 C1 0 1000 500 dnl C lsb C0.2 C0.4 C0.6 C0.8 0.2 0 0.4 0.6 1500 2500 2000 3000 4000 3500 t a = C55 8 c, +25 8 c, +85 8 c superimposed figure 1. differential nonlinearity error vs. code
C2C rev. 0 ad7394/ad7395Cspecifications ad7394 12-bit rail-to-rail voltage out dac electrical characteristics parameter symbol conditions 3 v 6 10% 5 v 6 10% units static performance resolution 1 n 12 12 bits relative accuracy 2 inl t a = +25 c 1.5 1.5 lsb max relative accuracy 2 inl t a = C40 c, +85 c 2.0 2.0 lsb max differential nonlinearity 2 dnl t a = +25 c, monotonic 0.9 0.9 lsb max differential nonlinearity 2 dnl monotonic 1 1 lsb max zero-scale error v zse data = 000 h 4.0 4.0 mv max full-scale voltage error v fse t a = +25 c, +85 c, data = fff h 8 8 mv max full-scale voltage error v fse t a = C40 c, data = fff h 20 20 mv max full-scale tempco 3 tcv fs C30 C30 ppm/ c typ reference input v ref in range v ref 0/v dd 0/v dd v min/max input resistance r ref 2.5 2.5 m w typ 4 input capacitance 3 c ref 5 5 pf typ analog output output current (source) i out data = 800 h , d v out = 5 lsb 1 1 ma typ output current (sink) i out data = 800 h , d v out = 5 lsb 3 3 ma typ capacitive load 3 c l no oscillation 100 100 pf typ logic inputs logic input low voltage v il 0.5 0.8 v max logic input high voltage v ih v dd C0.6 4.0 v min input leakage current i il 10 10 m a max input capacitance 3 c il 10 10 pf max interface timing 3, 5 clock width high t ch 50 30 ns min clock width low t cl 50 30 ns min load pulsewidth t ldw 30 20 ns min data setup t ds 10 10 ns min data hold t dh 30 15 ns min clear pulsewidth t clrw 15 15 ns min load setup t ld1 30 15 ns min load hold t ld2 40 20 ns min ac characteristics output slew rate sr data = 000 h to fff h to 000 h 0.05 0.05 v/ m s typ settling time 6 t s to 0.1% of full scale 70 60 m s typ dac glitch q code 7ff h to 800 h to 7ff h 65 65 nv/s typ digital feedthrough q 15 15 nv/s typ feedthrough v out /v ref v ref = 1.5 v dc +1 v p-p , data = 000 h , f = 100 khz C63 C63 db typ supply characteristics power supply range v dd range dnl < 1 lsb 2.7/5.5 2.7/5.5 v min/max shutdown supply current i dd_sd shdn = 0, v il = 0 v, no load 0.1/1.5 0.1/1.5 m a typ/max positive supply current i dd v il = 0 v, no load 125/200 125/200 m a typ/max power dissipation p diss v il = 0 v, no load 600 1000 m w max power supply sensitivity pss d v dd = 5% 0.006 0.006 %/% max notes 1 one lsb = v ref /4096 v for the 12-bit ad7394. 2 the first two codes (000 h , 001 h ) are excluded from the linearity error measurement. 3 these parameters are guaranteed by design and not subject to production testing. 4 typicals represent average readings measured at +25 c. 5 all input control signals are specified with t r = t f = 2 ns (10% to 90% of +3 v) and timed from a voltage level of 1.6 v. 6 the settling time specification does not apply for negative going transitions within the last three lsbs of ground. specifications subject to change without notice. (@ v ref in = 2.5 v, C40 8 c < t a < +85 8 c, unless otherwise noted)
C3C rev. 0 ad7394/ad7395 ad7395 10-bit rail-to-rail voltage out dac electrical characteristics parameter symbol conditions 3 v 6 10% 5 v 6 10% units static performance resolution 1 n 10 10 bits relative accuracy 2 inl t a = +25 c 1.5 1.5 lsb max relative accuracy 2 inl t a = C40 c, +85 c, +125 c 2.0 2.0 lsb max differential nonlinearity 2 dnl monotonic 1 1 lsb max zero-scale error v zse data = 000 h 9.0 9.0 mv max full-scale voltage error v fse t a = +25 c, +85 c, +125 c data = fff h 42 42 mv max full-scale voltage error v fse t a = C40 c, data = fff h 48 48 mv max full-scale tempco 3 tcv fs C35 C35 ppm/ c typ reference input v ref in range v ref 0/v dd 0/v dd v min/max input resistance r ref 2.5 2.5 m w typ 4 input capacitance 3 c ref 5 5 pf typ analog output output current (source) i out data = 200 h , d v out = 5 lsb 1 1 ma typ output current (sink) i out data = 200 h , d v out = 5 lsb 3 3 ma typ capacitive load 3 c l no oscillation 100 100 pf typ logic inputs logic input low voltage v il 0.5 0.8 v max logic input high voltage v ih v dd C0.6 4.0 v min input leakage current i il 10 10 m a max input capacitance 3 c il 10 10 pf max interface timing 3, 5 clock width high t ch 50 30 ns min clock width low t cl 50 30 ns min load pulsewidth t ldw 30 20 ns min data setup t ds 10 10 ns min data hold t dh 30 15 ns min clear pulsewidth t clrw 15 15 ns min load setup t ld1 30 15 ns min load hold t ld2 40 20 ns min ac characteristics output slew rate sr data = 000 h to 3ff h to 000 h 0.05 0.05 v/ m s typ settling time 6 t s to 0.1% of full scale 70 60 m s typ dac glitch q code 7ff h to 800 h to 7ff h 65 65 nv/s typ digital feedthrough q 15 15 nv/s typ feedthrough v out /v ref v ref = 1.5 v dc +1 v p-p , data = 000 h , f = 100 khz C63 C63 db typ supply characteristics power supply range v dd range dnl < 1 lsb 2.7/5.5 2.7/5.5 v min/max shutdown supply current i dd_sd shdn = 0, v il = 0 v, no load 0.1/1.5 0.1/1.5 m a typ/max positive supply current i dd v il = 0 v, no load 125/200 125/200 m a typ/max power dissipation p diss v il = 0 v, no load 600 1000 m w max power supply sensitivity pss d v dd = 5% 0.006 0.006 %/% max notes 1 one lsb = v ref /4096 v for the 10-bit ad7395. 2 the first two codes (000 h , 001 h ) are excluded from the linearity error measurement. 3 these parameters are guaranteed by design and not subject to production testing. 4 typicals represent average readings measured at +25 c. 5 all input control signals are specified with t r = t f = 2 ns (10% to 90% of +3 v) and timed from a voltage level of 1.6 v. 6 the settling time specification does not apply for negative going transitions within the last three lsbs of ground. specifications subject to change without notice. (@ v ref in = 2.5 v, C40 8 c < t a < +85 8 c/+125 8 c, unless otherwise noted)
ad7394/ad7395 C4C rev. 0 table i. control logic truth table cs clk rs msb shdn lda / b serial shift register function dac register function h x h x h h no effect latched l l h x h h no effect latched l h h x h h no effect latched l - + h x h h shift-register-data advanced one bit latched l - + h x h l shift-register-data advanced one bit transparent l h h x h l no effect transparent - + l h x h h no effect latched hx h x h C no effect updated with current shift register contents h x h x h l no effect transparent x x l h h x no effect loaded with 800 h xx - + h h h no effect latched with 800 h x x l l h x no effect loaded with all zeros xx - + l h h no effect latched all zeros x x x x l x no effect no affect notes 1. - + positive logic transition; C negative logic transition; x dont care 2. do not clock in serial data while level sensitive inputs lda or ldb are logic low. t ld1 t csh 6 1 lsb error band t clrw t s t s t ldw t ch t cl t css t ld2 t ds t dh d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 sdi clk cs lda,b sdi clk fs v out zs lda,b rs figure 2. timing diagram t sdr i dd shdn figure 3. timing diagram
ad7394/ad7395 C5C rev. 0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7394/ad7395 features proprietary esd protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings* v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +7 v v ref to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd logic inputs to gnd . . . . . . . . . . . . . . . . . . . . . C0.3 v, +8 v v out to gnd . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v i out short circuit to gnd . . . . . . . . . . . . . . . . . . . . . 50 ma package power dissipation . . . . . . . . . . . . . (t j max C t a )/ q ja thermal resistance q ja 14-lead plastic dip package (n-14) . . . . . . . . . . 103 c/w 14-lead soic package (r-14) . . . . . . . . . . . . . . . 158 c/w 14-lead thin shrink surface mount (ru-14) . . . 180 c/w maximum junction temperature (t j max) . . . . . . . . . . 150 c ordering guide res temperature package package model (lsb) range description options ad7394an 12 C40 c to +85 c 14-lead p-dip n-14 ad7394ar 12 C40 c to +85 c 14-lead soic r-14 ad7395an 10 C40 c to +125 c 14-lead p-dip n-14 AD7395AR 10 C40 c to +125 c 14-lead soic r-14 AD7395ARu 10 C40 c to +85 c 14-lead thin shrink small outline package (tssop) ru-14 the ad7394/ad7395 contains 709 transistors. the die size measures 70 mil 99 mil. operating temperature range . . . . . . . . . . . C40 c to +85 c AD7395AR and ad7395an only . . . . . . C40 c to +125 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature n-14 (soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . . +300 c r-14 (vapor phase, 60 sec) . . . . . . . . . . . . . . . . . . . . +215 c ru-14 (infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . . . +224 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table ii. ad7394 serial input register data format, data is loaded in msb-first format msb lsb b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ad7394 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table iii. ad7395 serial input register data format, data is loaded in msb-first format msb lsb b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ad7395 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
ad7394/ad7395 C6C rev. 0 pin function descriptions pin no. name function 1 agnd analog ground. 2v outa dac a voltage output. 3v ref dac reference voltage input terminal. establishes dac full-scale output voltage. pin can be tied to v dd pin. 4 dgnd digital ground. should be tied to analog gnd. 5 cs chip sel ect, active low input. di sables shift regis ter loading when hi gh. does not effect lda or ldb operation. 6 clk clock input, positive edge clocks data into shift register, msb data bit first. 7 sdi serial data input, input data loads directly into the shift register. 8 lda load dac register strobe, level sensitive active low. transfers shift register data to dac a register. asyn- chronous active low input. see control logic truth table for operation. 9 rs resets dac register to zero condition or half-scale, depending on msb pin logic level. asynchronous active low input. 10 ldb load dac register strobe, level-sensitive active low. transfers shift register data to dac b register. asyn- chronous active low input. see control logic truth table for operation. 11 msb digital input: logic high presets dac registers to half-scale 800 h (sets msb bit to one) when the rs pin is strobed; logic low clears all dac registers to zero (000 h ) when the rs pin is strobed. 12 shdn active low shutdown control input. does not affect register contents as long as power is present on v dd . new data can be loaded into the shift register and dac register during shutdown. when device is powered up the most recent data loaded into the dac register will control the dac output. 13 v dd positive power supply input. specified range of operation +2.7 v to +5.5 v 14 v outb dac b voltage output. pin configurations top view (not to scale) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 agnd v outa v ref dgnd cs clk sdi v outb v dd shdn msb ldb rs lda ad7394 ad7395
ad7394/ad7395 C7C rev. 0 code C decimal 1.5 C1.5 0 1000 500 inl C lsb 0 C0.5 0.5 1 C1 1500 2500 2000 3000 4000 3500 t a = +25 8 c, +85 8 c v dd = 3v v ref = 2.5v t a = C55 8 c figure 4. ad7394 integral nonlinear- ity error vs. code tempco C ppm/ 8 c frequency 35 0 40 30 20 15 10 5 25 26 38 28 30 32 34 36 ss = 200, v dd = 2.7v v ref = 2.5v t a = +85 8 c to C40 8 c ad7395 figure 7. full-scale output tempco histogram frequency C hz output noise density C m v/ hz 10 8 0 1 10 100k v dd = 5v v ref = 2.5v t a = +25 8 c 100 1k 10k 6 4 2 figure 10. ad7394 output noise density vs. frequency typical performance characteristicsC total unadjusted error C lsb 25 20 0 frequency 15 10 5 2 3 2 2 2 1 01 ss = 200 units t a = +25 8 c v dd = 2.7v v ref = 2.5v ad7394 figure 5. total unadjusted error histogram v ref C volts inl C lsb 0.6 0.3 0 0 0.5 5 1 1.5 2 2.5 3 3.5 4 4.5 0.5 0.4 0.2 0.1 v dd = 5.0v t a = +25 8 c code = 768 h ad7394 figure 8. integral nonlinearity error vs. v ref v in C volts i dd C m a 140 100 135 120 115 110 105 130 125 0 0.5 3 1 1.5 2 2.5 v dd = 3v v in 3v to 0v v in 0v to 3v ad7394 figure 11. supply current vs. logic input voltage total unajusted error C lsb freqeuency 50 40 0 C5 0 51015 30 20 10 ss = 200 units t a = +25 8 c v dd = 2.7v v ref = 2.5v ad7395 figure 6. total unadjusted error histogram v ref C volts 0 0.5 5 1 1.5 2 2.5 3 3.5 4 4.5 fse C lsb 30 25 2 15 5 0 2 5 2 10 20 10 15 t a = +25 8 c total unadjusted full scale error full scale error ad7394 figure 9. full-scale error vs. v ref v dd C volts logic threshold C v 5 4.5 1 23 7 456 3 2.5 2 1.5 4 3.5 v logic from low to high v logic from high to low ad7394 figure 12. logic threshold vs. sup- ply voltage
ad7394/ad7395 C8C rev. 0 clock frequency C hz i dd C m a 1800 1600 0 1k 10k 10m 100k 1m 800 600 400 200 1400 1200 1000 a: i dd = 2.7v, code = 555 h b: i dd = 2.7v, code = 3ff h c: v dd = 5.5v, code = 155 h d: v dd = 5.5v, code = 3ff h a d c b ad7394 figure 13. supply current vs. clock frequency d v out C lsb current sourcing C ma 10 3 0 2 10 2 9 0 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 9 4 2 1 6 5 8 7 v dd = 5v v dd = 3v v ref = 2.5v code = 800 h figure 16. ad7394 i out source cur- rent vs. d v out hours of operation C 150 8 c nominal change in v out C mv 1.4 0 0 100 600 200 300 400 500 1.2 1 0.8 0.4 0.2 0.6 code = 000 h code = fff h ad7394 figure 19. long-term drift acceler- ated by burn-in frequency C hz psrr C db 80 70 0 1 10 10k 100 1k 40 30 20 10 60 50 v dd = 5.0v, 6 5% v dd = 3.0v, 6 5% t a = +25 8 c figure 14. ad7394 power supply rejection vs. frequency time C 2 m s/div v out C volts 1.262 1.257 1.237 1.252 1.247 1.242 v dd = +5v v ref = 2.5v t a = +25 8 c code = 800 h to 7ff h 5mv/div figure 17. midscale transition performance d v out C lsb current sinking C ma 20 6 0 01 10 23 4 56 7 89 18 8 4 2 12 10 16 14 v dd = 3v v dd = 5v v ref = 2.5v code = 800 h figure 15. ad7394 i out sink current vs. d v out gain C db 0 2 5 2 50 100 1k v dd = 5v code = fff h 10k 100k 2 30 2 35 2 40 2 45 2 10 2 15 2 20 2 25 frequency C hz figure 18. ad7395 reference multi- plying bandwidth
ad7394/ad7395 C9C rev. 0 operation the ad7394 and ad7395 are a set of pin compatible, dual, 12-bit/10-bit digital-to-analog converters. these single-supply operation devices consume less than 200 microamps of current while operating from power supplies in the +2.7 v to +5.5 v range, making them ideal for battery operated applications. they contain a voltage-switched, 12-bit/10-bit, laser trimmed digital-to-analog converter, rail-to-rail output op amps, two dac registers and a serial input shift register. the external reference input has constant input resistance independent of the digital code setting of the dac. in addition, the reference input can be tied to the same supply voltage as v dd , resulting in a maximum output voltage span of 0 to v dd . the serial interface consists of a serial data input (sdi), clock (clk) and chip select pin ( cs ) and two load dac register pins ( lda and ldb ). a reset ( rs ) pin is available to reset the dac register to zero scale or midscale, depending on the digital level applied to the msb pin. this function is useful for power-on reset or system failure recovery to a known state. additional power savings are accomplished by activating the shdn pin resulting in a 1.5 m a maximum consumption sleep mode. d/a converter section the voltage switched r-2r dac generates an output voltage dependent on the external reference voltage connected to the ref pin according to the following equation: v out = v ref d 2 n (1) where d is the decimal data word loaded into the dac register and n is the number of bits of dac resolution. in the case of the 10-bit ad7395 using a 2.5 v reference, equation 1 simpli- fies to: v out = 2.5 d 1024 (2) using equation 2 the nominal midscale voltage at v out is 1.25 v for d = 512; full-scale voltage is 2.497 v. the lsb step size is = 2.5 1/1024 = 0.0024 v. for the 12-bit ad7394 operating from a 5.0 v reference equa- tion 1 becomes: v out = 5. 0 d 4096 (3) using equation 3 the ad7394 provides a nominal midscale voltage of 2.50 v for d = 2048, and a full-scale output of 4.998 v. the lsb step size is = 5.0 1/4096 = 0.0012 v. amplifier section the internal dacs output is buffered by a low power con- sumption precision amplifier. the op amp has a 60 m s typical settling time to 0.1% of full scale. there are slight differences in settling time for negative slewing signals versus positive. also, negative transition settling time to within the last 6 lsbs of zero volts has an extended settling time. the rail-to-rail output stage of this amplifier has been designed to provide precision perfor- mance while operating near either power supply. figure 20 shows an equivalent output schematic of the rail-to-rail-ampli- fier with its n-channel pull-down fets that will pull an output load directly to gnd. the output sourcing current is provided by a p-channel pull-up device that can source current to gnd terminated loads. n-ch v dd v out agnd p-ch figure 20. equivalent analog output circuit the rail-to-rail output stage provides more than 1 ma of out- put current. the n-channel output pull-down mosfet shown in figure 20 has a 35 w on resistance, which sets the sink cur- rent capability near ground. in addition to resistive load driving capability, the amplifier has also been carefully designed and characterized for up to 100 pf capacitive load driving capability. reference input the reference input terminal has a constant input resistance independent of digital code which results in reduced glitches on the external reference voltage source. the high 2.5 m w input resistance minimizes power dissipation within the ad7394/ ad7395 d/a converters. the v ref input accepts input voltages ranging from ground to the positive supply voltage v dd . one of the simplest applications, which saves an external reference voltage source, is connection of the v ref terminal to the positive v dd supply. this connection results in a rail-to-rail voltage output span maximizing the programmed range. the reference input will accept ac signals as long as they are kept within the supply voltage range, 0 < v ref < v dd . the reference bandwidth and integral nonlinearity error performance are plotted in the typical performance characteristics section (see figures 8 and 18). the ratiometric reference feature makes the ad7394/ad7395 an ideal companion to ratiometric analog-to-digital converters such as the ad7896.
ad7394/ad7395 C10C rev. 0 power supply the very low power consumption of the ad7394/ad7395 is a direct result of a circuit design optimizing the use of a cbcmos process. by using the low power characteristics of cmos for the logic, and the low noise, tight matching of the complemen- tary bipolar transistors, excellent analog accuracy is achieved. one advantage of the rail-to-rail output amplifiers used in the ad7394/ad7395 is the wide range of usable supply voltage. the part is fully specified and tested for operation from +2.7 v to +5.5 v. power supply bypassing and grounding local supply bypassing consisting of a 10 m f tantalum electro- lytic in parallel with a 0.1 m f ceramic capacitor is recommended in all applications (figure 21). c * 0.1 m f 10 m f ad7394 or ad7395 cs clk lda , b rs sdi dgnd v outb v outa *optional external reference bypass ref v dd agnd +2.7v to +5.5v figure 21. recommended supply bypassing for the ad7394/ad7395 input logic levels all digital inputs are protected with a zener-type esd protec- tion structure (figure 22) that allows logic input voltages to exceed the v dd supply voltage. this feature can be useful if the user is driving one or more of the digital inputs with a 5 v cmos logic input-voltage level while operating the ad7394/ad7395 on a +3 v power supply. if this mode of interface is used, make sure that the v ol of the 5 v cmos meets the v il input re- quirement of the ad7394/ad7395 operating at 3 v. see figure 12 for a graph of digital logic input threshold versus operating v dd supply voltage. v dd logic in gnd figure 22. equivalent digital input esd protection in order to minimize power dissipation from input logic levels that are near the v ih and v il logic input voltage specifications, a schmitt trigger design was used that minimizes the input- buffer current consumption compared to traditional cmos input stages. figure 11 is a plot of incremental input voltage versus supply current showing that negligible current consump- tion takes place when logic levels are in their quiescent state. the normal crossover current still occurs during logic transi- tions. a secondary advantage of this schmitt trigger is the pre- vention of false triggers that would occur with slow moving logic transitions when a standard cmos logic interface or opto isolators are used. the logic inputs sdi, clk, cs , lda , ldb , rs , shdn all contain the schmitt trigger circuits. dac b register dpr cs clk shift register q dac a register dpr lda ldb rs msb sdi en figure 23. equivalent digital interface logic digital interface the ad7394/ad7395 has a serial data input. a functional block diagram of the digital section is shown in figure 23, while table i contains the truth table for the logic control inputs. three pins control the serial data input register loading. two additional pins determine which dac will receive the data loaded into the input shift register. data at the sdi is clocked into the shift register on the rising edge of the clk. data is entered in the msb-first format. the active low chip select ( cs ) pin enables loading of data into the shift register from the sdi pin. twelve clock pulses are required to load the 12-bit ad7390 dac shift register. if additional bits are clocked into the shift register, for example, when a microcontroller sends two 8-bit bytes, the msbs are ignored (table iv). the lowest resolution ad7395 is also loaded msb-first with 10 bits of data. again, if additional bits are clocked into the shift register only the last 10 bits clocked in are used. when cs returns to logic high, shift- register loading is disabled. the load pins lda and ldb con- trol the flow of data from the shift register to the dac register. after a new value is clocked into the serial-input register, it will be transferred to the dac register associated with its lda or ldb logic control line. note, if the user wants to load both dac registers with the current contents of the shift register, both control lines lda and ldb should be strobed together. the lda and ldb pins are level-sensitive and should be re- turned to logic high prior to any new data being sent to the input shift register to avoid changing the dac register values. see truth table for complete set of conditions. reset ( rs ) pin forcing the asynchronous rs pin low will set the dac register to all zeros, or midscale, depending on the logic level applied to the msb pin. when the msb pin is set to logic high, both dac registers will be reset to midscale (i.e., the dac registers msb bit will be set to logic 1 followed by all zeros). the reset func- tion is useful for setting the dac outputs to zero at power-up or after a power supply interruption. test s ystems and motor controllers are two of many applications that benefit from powering up to a known state. the external reset pulse can be
ad7394/ad7395 C11C rev. 0 generated by the microprocessors power-on reset signal, by an output from the microprocessor, or by an external resistor and capacitor. reset has a schmitt trigger input which results in a clean reset function when using external resistor/capacitor generated pulses. see the control-logic truth table i. power shutdown ( shdn ) maximum power savings can be achieved by using the power shutdown control function. this hardware activated feature is controlled by the active low input shdn pin. this pin has a schmitt trigger input which helps to desensitize it to slowly changing inputs. by placing a logic low on this pin the internal consumption of the device is reduced to nano amp levels, guar- anteed to 1.5 m a maximum over the operating temperature range. when the ad7394/ad7395 has been programmed into the power shutdown state, the present dac register data is maintained as long as v dd remains greater than 2.7 v. once a wake-up command shdn = 1 is given, the dac voltage out- puts will return to their previous values. it typically takes 80 microseconds for the output voltage to fully stabilize. in the shutdown state the dac output amplifier exhibits an open- circuit with a nominal output resistance of 500 k w to ground. if the power shutdown feature is not needed, then the user should tie the shdn pin to the v dd voltage thereby disabling this function. unipolar output operation this is the basic mode of operation for the ad7394. as shown in figure 24, the ad7394 has been designed to drive loads as low as 5 k w in parallel with 100 pf. the code table for this operation is shown in table v. 5 v dd digital interface circuitry omitted for clarity. digital v ref dgnd agnd dac a dac b ext ref +2.7v to +5.5v r m c 0.01 m f 0.1 m f10 m f 75k v 100pf 75k v 100pf v outa v outb figure 24. ad7394 unipolar output operation table iv. typical microcontroller interface formats msb byte 1 lsb msb byte 0 lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 x x x x d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxd9d8d7d6d5d4d3d2d1d0 d11Cd0: 12-bit ad7394 dac data; d9Cd0: 10-bit ad7395 dac data; x = dont care; the msb of byte 1 is the first bit that is loade d into the sdi input. table v. unipolar code table hexadecimal decimal output number number voltage (v) in dac register in dac register [v ref = 2.5 v] fff 4095 2.4994 801 2049 1.2506 800 2048 1.2500 7ff 2047 1.2494 000 0 0 the circuit can be configured with an external reference plus power supply, or powered from a single dedicated regulator or reference depending on the application performance requirements. bipolar output operation although the ad7395 has been designed for single-supply op- eration, the output can easily be configured for bipolar opera- tion. a typical circuit is shown in figure 25. this circuit uses a clean regulated +5 v supply for power, which also provides the circuits reference voltage. since the ad7395 output span s wings from ground to very near +5 v, it is necessary to choose an external amplifier with a common-mode input voltage range that extends to its positive supply rail. the micropower consumption op196 has been designed just for this purpose and results in only 50 microamps of maximum current consumption. connec- tion of the equally valued 470 k w resistors results in a differen- tial amplifier mode of operation with a voltage gain of two, which produces a circuit output span of ten volts, that is, C5 v to +5 v. as the dac is programmed from zero code 000 h to mid- scale 200 h to full-scale 3ff h , the circuit output voltage v o is set at C5 v, 0 v and +5 v (C1 lsb). the output voltage v o is coded in offset binary according to equation 4. v out = d 512 ? ? ? ? 1 ? ? 5 (4) where d is the decimal code loaded in the ad7395 dac regis- ter. note that the lsb step size is 10/1024 = 10 mv. this cir- cuit has been optimized for micropower consumption including the 470 k w gain setting resistors, which should have low tem- perature coefficients to maintain accuracy and matching (prefer- ably the same resistor material, such as metal film). if better stability is required, the power supply could be substituted with a precision reference voltage such as the low dropout ref195, which can easily supply the circuits 262 microamps of current, and still provide additional power for the load connected to v out . the micropower ref195 is guaranteed to source 10 ma
ad7394/ad7395 C12C rev. 0 c3323C8C4/98 printed in u.s.a. table vi. bipolar code table hexadecimal number decimal number analog output in dac register in dac register voltage (v) 3ff 1023 4.9902 201 513 0.0097 200 512 0.0000 1ff 511 C0.0097 000 0 C5.0000 outline dimensions dimensions shown in inches and (mm). plastic dip package (n-14) 14 17 8 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) pin 1 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) soic package (r-14) 14 8 7 1 0.3444 (8.75) 0.3367 (8.55) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc

▲Up To Search▲

Price & Availability of AD7395AR

	To Download AD7395AR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .