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ds04-21365-1e fujitsu semiconductor data sheet assp dual s erial input pll frequency synthesizer mb15f73sp n description the fujitsu mb15f73sp is a serial input phase locked loop (pll) frequency synthesizer with a 2000 mhz pres- caler and a 600 mhz prescaler. a 64/65 or a 128/129 for the 2000 mhz prescaler, and a 8/9 or a 16/17 for the 600 mhz prescaler can be selected for the prescaler that enables pulse swallow operation. mb15f73sp has the same configuration with mb15f03 or mb15f03l. the bicmos process is used , as a result a supply current is typically 3.5 ma at 2.7 v. the supply voltage range is from 2.4 v to 3.6 v. a refined charge pump supplies well-balanced output current with 1.5 ma and 6 ma selectable by serial data. the new package (bcc20) decreases an area of mb15f73sp more than 30 % comparing with the former bcc16 (for dual pll). mb15f73sp is ideally suited for wireless mobile communications, such as pdc. n features ? high frequency operation : rf synthesizer : 2000 mhz max : if synthesizer : 600 mhz max ? low power supply voltage : v cc = 2.4 to 3.6 v ? ultra low power supply current : i cc = 3.5 ma typ. (v cc = vp = 2.7 v, ta = +25 c, sw if = sw rf = 0 in if/rf locking state) (continued) n packages 20-pin plastic tssop 20-pad plastic bcc (fpt-20p-m06) (lcc-20p-m04)
mb15f73sp 2 (continued) ? direct power saving function: power supply current in power saving mode typ. 0.1 m a (v cc = vp = 2.7 v, ta = +25 c) max. 10 m a (v cc = vp = 2.7 v) ? software selectable charge pump current: 1.5 ma/6.0 ma typ. ? dual modulus prescaler: 2000 mhz prescaler (64/65 or128/129 )/600 mhz prescaler (8/9 or 16/17) ? 23 bit shift register ? serial input binary 14-bit programmable reference divider: r = 3 to 16,383 ? serial input programmable divider consisting of: - binary 7-bit swallow counter: 0 to 127 - binary 11-bit programmable counter: 3 to 2,047 ? built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit ? onCchip phase control for phase comparator ? built-in digital locking detector circuit to detect pll locking and unlocking ? operating temperature: ta = C40 to +85 c ? sireal data format compatible with mb15f02sl n pin assignments (tssop-20) top view (fpt-20p-m06) (bcc-20) top view (lcc-20p-m04) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clock data le fin rf xfin rf gnd rf v ccrf ps rf vp rf do rf osc in gnd fin if xfin if gnd if v ccif ps if vp if do if ld/fout fin if xfin if gnd if v ccif ps if vp if 1 2 3 4 5 6 16 15 14 13 12 11 le fin rf xfin rf gnd rf v ccrf ps rf 78910 20 19 18 17 do if do rf ld/fout vp rf gnd osc in data clock
mb15f73sp 3 n pin description pin no. pin name i/o descriptions tssop bcc 119osc in i the programmable reference divider input. tcxo should be connected with a ac coupling capacitor. 220gnd ? ground for osc input buffer and the shift register circuit. 31fin if i prescaler input pin for the if-pll. connection to an external vco should be ac coupling. 42xfin if i prescaler complimentary input for the if-pll section. this pin should be grounded via a capacitor. 53gnd if ? ground for the if-pll section. 64v ccif ? power supply voltage input pin for the if-pll section (except for the charge pump circuit), the shift register and the oscillator input buffer. 75ps if i power saving mode control for the if-pll section. this pin must be set at "l" power-on. (open is prohibited.) ps if = "h" ; normal mode / ps if = "l" ; power saving mode 86vp if ? power supply voltage input pin for the if-pll charge pump. 97do if o charge pump output for the if-pll section. 10 8 ld/fout o look detect signal output (ld)/ phase comparator monitoring output (fout). the output signal is selected by a lds bit in a serial data. lds bit = "h" ; outputs fout signal / lds bit = "l" ; outputs ld signal 11 9 do rf o charge pump output for the rf-pll section. 12 10 vp rf ? power supply voltage input pin for the rf-pll charge pump. 13 11 ps rf i power saving mode control for the rf-pll section. this pin must be set at "l" power-on. (open is prohibited. ) ps rf = "h" ; normal mode / ps rf = "l" ; power saving mode 14 12 v ccrf ? power supply voltage input pin for the rf-pll section (except for the charge pump circuit). 15 13 gnd rf ? ground for the rf-pll section. 16 14 xfin rf i prescaler complimentary input for the rf-pll section. this pin should be grounded via a capacitor. 17 15 fin rf i prescaler input pin for the rf-pll. connection to an external vco should be ac coupling. 18 16 le i load enable signal input (with the schmitt trigger circuit.) when le is set "h", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. 19 17 data i serial data input (with the schmitt trigger circuit.) a data is transferred to the corresponding latch (if-ref. counter, if-prog. counter, rf-ref. counter, rf-prog. counter) according to the control bit in a serial data. 20 18 clock i clock input for the 23-bit shift register (with the schmitt trigger circuit.) one bit data is shifted into the shift register on a rising edge of the clock.
mb15f73sp 4 n block diagram ( ) clock data le ps rf xfin rf fin rf osc in fin if ps if fc if sw if lds v ccif gnd if fp if do if ld if t1 t2 t1 t2 fc rf sw rf lds do rf or ld / fout ld fr if fr rf fp if fp rf fr if fr rf fp rf c n 1 c n 2 and v ccrf gnd rf gnd ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 6 4 vp if ( ) 86 53 9 7 10 8 11 9 15 13 14 12 vp rf ( ) 12 10 20 18 19 17 ( ) 18 16 13 11 16 14 17 15 1 19 3 1 xfin if ( ) 4 2 7 5 ( ) 2 20 intermittent mode control (if-pll) prescaler (if-pll) (8/9, 16/17) schmitt circuit 3 bit latch 7 bit latch 11 bit latch binary 7-bit swallow counter (if-pll) binary 11-bit programable counter (if-pll) phase comp. (if-pll) charge pump (if-pll) current switch lock det. (if-pll) 2 bit latch 14 bit latch 1 bit latch binary 14-bit pro- grammable ref. counter(if-pll) c/p setting counter selector latch selector 23-bit shift register prescaler (rf-pll) (64/65, 128/129) intermittent mode control (rf-pll) phase comp. (rf-pll) charge pump (rf-pll) current switch lock det. (rf-pll) 3 bit latch 7 bit latch 11 bit latch 2 bit latch 14 bit latch 1 bit latch schmitt circuit schmitt circuit binary 14-bit pro- grammable ref. counter(rf-pll) c/p setting counter binary 7-bit swallow counter (rf-pll) binary 11-bit programmable counter(rf-pll) o -- tssop ( ) -- bcc
mb15f73sp 5 n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. power supply voltage v cc - 0.5 4.0 v vp v cc 4.0 v input voltage v i - 0.5 v cc + 0.5 v output voltage ld/fout v o gnd v cc v do v do gnd vp v storage temperature tstg - 55 + 125 c parameter symbol value unit min. typ. max. power supply voltage v cc 2.4 2.7 3.6 v vp v cc 2.7 3.6 v input voltage v i gnd ? v cc v operating temperature ta - 40 ?+ 85 c
mb15f73sp 6 * n electrical characteristics (v cc = 2.4 v to 3.6 v, ta = - 40 c to + 85 c) (continued) parameter symbol condition value unit min. typ. max. power supply current i ccif *1 if pll ? 1.3 ? ma i ccrf *2 rf pll ? 2.2 ? ma power saving current i psif ps if = ps rf = l ? 0.1 *8 10 m a i psrf ps if = ps rf = l ? 0.1 *8 10 m a operating frequency fin if *3 fin if if pll 50 ? 600 mhz fin rf *3 fin rf rf pll 100 ? 2000 mhz osc in f osc ? 3 ? 40 mhz input sensitivity fin if pfin if if pll, 50 w system - 15 ?+ 2dbm fin rf pfin rf rf pll, 50 w system - 15 ?+ 2dbm input available voltage osc in v osc ? 0.5 ? v cc v p - p h level input voltage data le clock v ih schmitt triger input 0.7 v cc + 0.4 ?? v l level input voltage v il schmitt triger input ?? 0.3 v cc - 0.4 v h level input voltage ps if ps rf v ih ? 0.7 v cc ?? v l level input voltage v il ??? 0.3 v cc v h level input current data le clock ps i ih *4 ?- 1.0 ?+ 1.0 m a l level input current i il *4 ?- 1.0 ?+ 1.0 m a h level input current osc in i ih ? 0 ?+ 100 m a l level input current i il *4 ? - 100 ? 0 m a h level output voltage ld/ fout v oh v cc = vp = 2.7 v, i oh = - 1 ma v cc - 0.4 ?? v l level output voltage v ol v cc = vp = 2.7 v, i ol = 1 ma ?? 0.4 v h level output voltage do if do rf v doh v cc = vp = 2.7 v, i doh = - 0.5 ma vp - 0.4 ?? v l level output voltage v dol v cc = vp = 2.7 v, i dol = 0.5 ma ?? 0.4 v high impedance cutoff current do if do rf i off v cc = vp = 2.7 v v off = 0.5 v to vp - 0.5 v ?? 2.5 na h level output current ld/ fout i oh *4 v cc = vp = 2.7 v ??- 1.0 ma l level output current i ol v cc = vp = 2.7 v 1.0 ?? ma
mb15f73sp 7 (continued) (v cc = 2.4 v to 3.6 v, ta = - 40 c to + 85 c) * 1 : fin if = 480 mhz, fosc = 12.8 mhz, v ccif = vp if = 2.7 v, sw if = 0, ta = + 25 c, in locking state. *2 : fin rf = 2000 mhz, fosc = 12.8 mhz, v ccrf = vp rf = 2.7 v, sw rf = 0, ta = + 25 c, in locking state. *3 :ac coupling. 1000 pf capacitor is connected under the condition of minimum operating frequency. *4 : the symbol C (minus) means direction of current flow. *5 : v cc = vp = 2.7 v, ta = + 25 c (||i 3 | C |i 4 ||) / [ (|i 3 | + |i 4 |) / 2 ] 100 (%) *6 : v cc = vp = 2.7 v, ta = + 25 c (applied to each i dol , i doh ) [ (||i 2 | C |i 1 ||) / 2 ] / [ (|i 1 | + |i 2 |) / 2 ] 100 (%) *7 : v cc = vp = 2.7 v, ta = + 25 c (applied to each i dol , i doh ) [ ||i do (85 c) | C |i do (C40 c) || / 2 ] / [ |i do (85 c) | + |i do (C40 c) | / 2 ] 100 (%) *8 : fosc = 12.8 mhz, v ccrf = vp rf = v ccif = vp if = 2.7 v, ta = + 25 c parameter symbol condition value unit min. typ. max. h level output current do if do rf i doh *4 v cc = vp = 2.7 v, v doh = vp / 2, ta = + 25 c cs bit = h ?- 6.0 ? ma cs bit = l ?- 1.5 ? ma l level output current do if do rf i dol v cc = vp = 2.7 v, v dol = vp / 2, ta = + 25 c cs bit = h ? 6.0 ? ma cs bit = l ? 1.5 ? ma charge pump current rate i dol /i doh i domt *5 v do = vp / 2 ? 3 ?% vs v do i dovd *6 0.5 v v do vp - 0.5 v ? 10 ?% vs ta i dota *7 - 40 c ta 85 c, v do = vp / 2 ? 10 ?% i dol i 1 i 3 i 2 i 1 i 4 i 2 0.5 vp/2 vp - 0.5 vp i doh charge pump output voltage (v)
mb15f73sp 8 n functional description 1. pulse swallow function f vco = [(p n) + a] f osc ? r f vco : output frequency of external voltage controlled oscillator (vco) p : preset divide ratio of dual modulus prescaler (8 or 16 for if-pll, 64or 128 for rf-pll) n : preset divide ratio of binary 11-bit programmable counter (3 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127, a < n) f osc : reference oscillation frequency (osc in input frequency) r : preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) 2. serial data input serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of if/rf-pll sec- tions, programmable reference dividers of if/rf-pll sections are controlled individually. serial data of binary data is entered through data pin. on rising edge of clock, one bit of serial data is transferred into the shift register. on a rising edge of load enable signal, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. (1) shift register configuration the programmable reference counter for the if-pll the programmable reference counter for the rf-pll the programmable counter and the swallow counter for the if-pll the programmable counter and the swallow counter for the rf-pll cn1 0 1 0 1 cn2 0 0 1 1 ? programmable reference counter cs : charge pump current select bit r1 to r14 : divide ratio setting bits for the programmable reference counter (3 to 16,383) t1, 2 : test purpose bit cn1, 2 : control bit x : dummy bits (set 0 or 1) note : data input with msb first. (lsb) (msb) 1 2 3 4 5 6 7 8 9 10111213 14 15 16 17 18 19 20212223 cn1cn2t1t2r1r2r3r4r5r6r7r8r9r10r11r12r13r14csxxxx data flow
mb15f73sp 9 (2) data setting ? binary 14-bit programmable reference counter data setting note : divide ratio less than 3 is prohibited. ? binary 11-bit programmable counter data setting note : divide ratio less than 3 is prohibited ? binary 7-bit swallow counter data setting divide ratio r14r13r12r11r10r9r8r7r6r5r4r3r2r1 3 00000000000011 4 16383 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 divide ration11n10n9n8n7n6n5n4n3n2n1 3 00000000011 4 2047 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 divide ratio a7 a6 a5 a4 a3 a2 a1 0 0000000 1 127 0 1 0 1 0 1 0 1 0 1 0 1 1 1 ? programmable counter a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) n1 to n11 : divide ratio setting bits for the programmable counter (3 to 2,047) lds : ld/fout signal select bit sw if/rf : divide ratio setting bit for the prescaler (8/9 or 16/17 for the sw if , 64/65 or 128/129 for the sw rf ) fc if/rf : phase control bit for the phase detector (if: fc if , rf: fc rf ) cn1, 2 : control bit note : data input with msb first. (lsb) (msb) data flow 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cn1 cn2 lds sw if/rf fc if/rf a1 a2 a3 a4 a5 a6 a7 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11
mb15f73sp 10 ? prescaler data setting ? test purpose bit setting ? phase comparator phase switching data setting z : high-impedance depending upon the vco and lpf polarity, fc bit should be set. divide ratio sw = h sw = l prescaler divide ratio if-pll 8 / 916 / 17 prescaler divide ratio rf-pll 64/65 128 / 129 ? charge pump current setting ? ld/fout output select data setting current value cs ld/fout output signal lds 6.0 ma 1 fout signals 1 1.5 ma 0 ld signal 0 ld/fout pin state t1 t2 outputs fr if .0 0 outputs fr rf .1 0 outputs fp if .0 1 outputs fp rf .1 1 phase comparator input fc if , rf = h fc if , rf = l do if , rf do if , rf fr > fp h l fr < fp l h fr = fp z z (1) (2) (1) vco polarity fc = h (2) vco polarity fc = l note : give attention to the polarity for using active type lpf. vco output frequency high lpf output voltage max.
mb15f73sp 11 3. power saving mode (intermittent mode control circuit) the intermittent mode control circuit reduces the pll power consumption. by setting the ps pin low, the device enters into the power saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do, becomes high impedance. for the single pll, the lock detector, ld, remains high, indicating a locked condition. for the dual pll, the lock detector, ld, is as shown in the ld output logic table. setting the ps pin high, releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is be- cause of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparaor output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error sig- nal from the phase detector when it returns to normal operation. note : when power (vcc) is first applied, the device must be in standby mode, ps = low, for at least 1 m s. note : ps pin must be set "l" for power-on. status ps pin normal mode h power saving mode l (1) ps = l (power saving mode) at power-on (2) set serial data 1 m s later after power supply remains stable (v cc > 2.2 v). (3) release power saving mode (ps : l ? h) 100 ns later after setting serial data. on off v cc clock data le ps (1) (2) (3) t ps 3 100 ns t v 3 1 m s
mb15f73sp 12 4. serial data input timing frequency multiplier setting is performed through a serial interface using the data pin, clock pin, and le pin. setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of the le signal. the following diagram shows the data input timing. lsb msb clock data le t 7 t 1 t 2 t 5 t 3 t 6 t 4 1st data 2nd data control bit invalid data note : le should be l when the data is transferred into the shift register. parameter min. typ. max. unit parameter min. typ. max. unit t 1 20 ?? ns t 5 30 ?? ns t 2 20 ?? ns t 6 100 ?? ns t 3 30 ?? ns t 7 100 ?? ns t 4 20 ?? ns
mb15f73sp 13 n phase comparator output waveform ? ld output logic notes : phase error detection range = C2 p to +2 p pulses on do if/rf signals during locking state are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on osc in input frequency as follows. t wu > 2/fosc: e.g. t wu > 156.3 ns when fosc = 12.8 mhz t wu < 4/fosc: e.g. t wl < 312.5 ns when fosc = 12.8 mhz if-pll section rf-pll section ld output locking state/power saving state locking state/power saving state h locking state/power saving state unlocking state l unlocking state locking state/power saving state l unlocking state unlocking state l fr if / rf fp if / rf ld d o if / rf t wu t wl d o if / rf h l l h z z (fc bit = high) ( fc bit = low )
mb15f73sp 14 n test circuit (for measuring input sensitivity fin/osc in ) note : the terminal number shows that of tssop-20. 10987654321 11 12 13 14 15 16 17 18 19 20 ld/fout do if vp if vp if v ccif 1000 pf 1000 pf 1000 pf 1000 pf 1000 pf 0.1 m f 0.1 m f fout ps if v ccif gnd if xfin if fin if gnd osc in do rf vp rf vp rf v ccrf ps rf v ccrf gnd rf xfin rf fin rf le data clock 0.1 m f 0.1 m f 50 w 50 w 50 w s.g. s.g. s.g. oscilloscope controller (divide ratio setting)
mb15f73sp 15 n typical characteristics 1. fin input sensitivity v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v 10.0 0.0 - 10.0 - 20.0 - 30.0 - 40.0 - 50.0 0 500 1000 1500 2000 2500 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v 0 100 200 300 400 500 600 700 10.0 0.0 - 10.0 - 20.0 - 30.0 - 40.0 - 50.0 rf-pll input sensitivity - input frequency input frequency fin rf (mhz) input sensitivity pfin rf (dbm) if-pll input sensitivity - input frequency input frequency fin if (mhz) input sensitivity pfin if (dbm) spec spec
mb15f73sp 16 2. osc in input sensitivity input sensitivity - input frequency input frequency f osc (mhz) input sensitivity vco (dbm) 10 0 - 30 - 10 - 20 - 40 - 50 - 60 0 20 40 100 80 60 200 180 160 140 120 220 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = + 25 c spec
mb15f73sp 17 3. rf-pll do output current ? 1.5 ma mode ? 6.0 ma mode i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) 10.0 - 10.0 1.0 0.0 ta = + 25 c v cc = vp = 2.7 v i dol i doh 0.0 2.0 2.7 10.0 - 10.0 0.0 ta = + 25 c v cc = vp = 2.7 v i dol i doh 0.0 1.0 2.0 2.7 i do - v do charge pump output current i do (ma) charge pump output voltage v do (v)
mb15f73sp 18 4. if-pll do output current ? 1.5 ma mode ? 6.0 ma mode i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) 10.0 - 10.0 0.0 ta = + 25 c v cc = vp = 2.7 v i dol i doh 0.0 1.0 2.0 2.7 10.0 - 10.0 1.0 ta = + 25 c v cc = vp = 2.7 v 0.0 i dol i doh 0.0 2.0 2.7 i do - v do charge pump output current i do (ma) charge pump output voltage v do (v)
mb15f73sp 19 5. fin input impedance fin if input impedance fin rf input impedance 669.97 w - 1.0088 k w 50 mhz 72.875 w - 351.75 w 200 mhz 27.047 w - 178.02 w 400 mhz 1 : 2 : 3 : start 50.000 000 mhz stop 600.000 000 mhz - 115.55 w 2.2956 pf 600.000 000 mhz 4 : 17.262 w 1 2 3 4 289.69 w - 647.06 w 100 mhz 12.887 w - 65.199 w 1 ghz 11.751 w - 30.16 w 1.5 ghz 1 : 2 : 3 : start 100.000 000 mhz stop 2 000.000 000 mhz - 5.6699 w 14.035 pf 2 000.000 000 mhz 4 : 13.596 w 1 2 3 4
mb15f73sp 20 6. osc in input impedance osc in input impedance 12.425 k w - 10.812 k w 3 mhz 524 w - 3.3809 k w 20 mhz 128.94 w - 1.7113 k w 40 mhz 1 : 2 : 3 : start 3.000 000 mhz stop 100.000 000 mhz - 679.69 w 2.3416 pf 100.000 000 mhz 4 : 31.813 w 1 2 3 4
mb15f73sp 21 n reference information (for lock-up time, phase noise and reference leakage) (continued) test circuit s.g. osc in fin do lpf vco spectrum analyzer 10 k w 4.1 k w 0.047 m f 3900 pf 3300 pf v cc = 3.0 v v vco = 3.0 v ta = + 25 c cp : 6 ma mode f vco = 1624 mhz k v = 22 mhz/v fr = 10 khz f osc = 19.68 mhz lpf ? pll reference leakage ? pll phase noise atten 10 db rl 0 dbm d mkr - 70.00 db 10.0 khz vavg 25 10 db/ center 1.6240000 ghz * rbw 300 hz span 100.0 khz swp 2.80 sec vbw 300 hz d mkr 10.0 khz - 70.00 db d s atten 10 db rl 0 dbm d mkr - 43.00 db 1.18 khz vavg 20 10 db/ center 1.62400000 ghz rbw 100 hz span 10.00 khz swp 802 ms vbw 100 hz d mkr 1.18 khz - 43.00 db d s
mb15f73sp 22 (continued) pll lock up time 953 mhz ? 981 mhz within 1 khz l ch ? h ch 4.822 ms pll lock up time 981 mhz ? 953 mhz within 1 khz h ch ? l ch 4.956 ms 1.646004500 ghz 1.646000500 ghz 1.645996500 ghz - 2.178 ms 2.822 ms 7.822 ms 1.000 ms/div t 1 489 m st 2 5.311 ms d 4.822 ms 1.624004750 ghz 1.624000750 ghz 1.623996750 ghz - 2.178 ms 2.822 ms 7.822 ms 1.000 ms/div t 1 489 m st 2 5.444 ms d 4.956 ms
mb15f73sp 23 n application example note clock, data, le : schmitt trigger circuit is provided(insert a pull-down or pull-up registor to prevent oscillation when open-circuite in the input). the terminal number shows that of tssop-20. clock data le fin rf xfin rf gnd rf v ccrf ps rf vp rf do rf 20 19 18 17 16 15 14 13 12 11 1 tcxo 2345678910 osc in gnd fin if xfin if gnd if v ccif ps if vp if do if ld/fout mb 15f73sp vco lpf 2.7 v 0.1 m f 2.7 v 2.7 v 2.7 v 0.1 m f 1000 pf 1000 pf 1000 pf 1000 pf 1000 pf vco lpf 0.1 m f output 0.1 m f output lock det. from controller
mb15f73sp 24 n usage precautions (1) v ccrf , vp rf , v ccif and vp if must equal equal voltage. even if either rf-pll or if-pll is not used, power must be supplied to both v ccrf , vp rf , v ccif and vp if to keep them equal. it is recommended that the non-use pll is controlled by power saving function. (2) to protect against damage by electrostatic discharge, note the following handling precautions: -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting or removing this device into or from a socket. -protect leads with conductive sheet, when transporting a board mounted device n ordering information part number package remarks mb15f73sppft 20-pin plastic tssop (fpt-20p-m06) MB15F73SPPV 20-pad plastic bcc (lcc-20p-m04)
mb15f73sp 25 n package dimensions (continued) 20-pin plastic ssop (fpt-20p-m06) c 1998 fujitsu limited f20026s-1c-1 1 10 11 20 6.50?.10(.256?004) 6.42/6.78(.253/.267) 4.40?.10 (.173?004) 4.80(.189) max 6.40?.10 (.252?004) index 0.65(.026) typ .009 ?003 +.006 ?.07 +0.03 0.22 0.415(.016) 0.98?.02 (.039?001) 0.10(.004) 5.40?.18 (.213?007) "a" 0.50(.020) 0.07?.03 (.003?001) ? +3 5 1.05?.05 (.041?002) details of "a" part dimensions in mm (inches)
mb15f73sp 26 (continued) c 1999 fujitsu limited c20055s-1c-1 3.60?.10(.142?004) 11 16 16 11 16 1 6 3.40?.10 (.134?004) index area 0.05(.002) 0.80(.031)max (mounting height) 0.085?.04 (.003?002) (stand off) 0.25?.10 (.010?004) typ 0.50(.020) 3.00(.118)typ 2.80(.110)ref typ 0.50(.020) (.010?004) 0.25?.10 2.70(.106) typ "d" "b" "a" "c" 0.60?.10 (.024?004) 0.50?.10 (.020?004) details of "a" part (.020?004) 0.50?.10 0.30?.10 (.012?004) details of "b" part details of "c" part (.020?004) 0.50?.10 (.024?004) 0.60?.10 c0.20(.008) details of "d" part 0.40?.10 (.016?004) 0.30?.10 (.012?004) dimensions in mm (inches) 20-pad plastic bcc (lcc-20p-m04)
mb15f73sp fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9911 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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