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thine electronics, inc. 1/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. THV3543 2 channel buck/boost 2 channel charge pump controll er description THV3543 is a controller ic for multichannel power supply system which includes 2 channel dc/dc converter with builtin power mosfets and 2 channel charge pump circuits. THV3543 has internal soft start, under voltage protection, over voltage protection and over curren t protection. ch1 is a boost dc/dc converter which can provide two optional modes of output voltage: the adjustabl e mode with external resistor or the fixed 15.6v mode requires no external resistors. ch2 is a buck dc/dc converter. its output voltage is fixed at 3.3v. positive charge pump (vgh) and negative charge pump (vgl) can provide two optional modes of output voltage: the adjustable mode with external resistor or the fixed mode (vgh at 35.6v, vgl at 6v) requires no external resistors. THV3543 has ldo and operational amplifier which can be used for half avdd or vcom. thus THV3543 can produce various necessary voltages for lcd panels and ideal for constructing tftlcd bias power supply system. applications ? lcd tv bias power supply ? lcd monitor bias power supply features ? qfn40 package ? input voltage range : 4.2 15v ? boost converter with builtin power mosfet ? buck converter with builtin power mosfet 500khz switching frequency under voltage protection over voltage protection over current protection ? positive/negative charge pumps ? ldo ? operational amplifier pin assignment pvcc lx1 lx1 ll2 lx1 vcc ll2 bst2 lsw_out1 vo1_in sysuvlo nc nc inv_ldo sgnd v_amp inv_amp panel_en non_amp v_ldo connect the exposed pad to gnd for enhanced thermal performance.
thine electronics, inc. 2/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. output channel descriptions output channel description ch1 pwm boost dc/dc converter ch2 pwm buck dc/dc converter vgh positive voltage charge pump vgl negative voltage charge pump amp operational amplifier ldo ldo lsw_out1 output for the external load switch 1 lsw_out2 output for the external load switch 2
thine electronics, inc. 3/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. block diagram THV3543 tft multi channel controller vcc vin=12v vo1 vreg5 lx1 max duty + vreg5 + comp lsw_out1 avdd uvlo 5v reg vo2=3.3v bst2 ll2 + comp stop vreg5 stop max duty test sysuvlo tsd + ss_ok1 ovp1 + inv1 vo1 + ss fb1 vref op + uvp1 sgnd vref ovp2 + vo2_in vo2 + vref gm uvp2 + pc2 lx1 pg_vgl lsw pvcc vref vref + out_ldo cur_ limit ss_ok2 ss uvlo vo2_ok uvp2 p_good vo2=3.3v pg_logic vcc3.3v vin=12v lsw_out2 out_vgh + + pg_ vgh vref v_ vgh vgh ss_ok_lsw vgh_ok pg_vgh avdd vgh_fb stop p_good out_vgl + vgl + pg_ vgl ss_ok1 stop v_ vgl vo1 vin v_amp out_amp inv_amp + op osc osc osc osc vo1_in mode select mode select vgh mode select vgl_fb vgl error detection stop uvp1, uvp2 timer latch uvlo ovp2 pg_vgl, pg_vgh osc pgnd sel sel sel lx1 ll2 panel_en ss_ok2 vcc non_amp inv_ldo v_ldo v_vgh
thine electronics, inc. 4/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. pin descriptions pin # symbol function description 1 pc2 output for ch2 error amplifier output pin for ch2 error amplifier. connect a capa citor between pc2 and gnd for phase compensation. 2 fb1 output for ch1 error amplifier output pin for ch1 error amplifier. connect a resi stor and a capacitor between fb1 pin and inv1 pin for phase co mpensation. 3 vreg5 output for 5v regulator output pin for 5v regulator of the control circuit. connect an external capacitor (10f). 4 vo2_in input for ch2 feedback voltage feedback voltage input pin for ch2. ch2 is controlled so that vo2_in pin becomes 3.3v. 5 inv1 inverting input for ch1 error amplifier inverting input for ch1 error amplifier. in fixed output voltage mode, connect a resistor and a capacitor for phase compensation. in adjustable output voltage mode, connect resistor s between the output and inv1 pin, and between inv1 pin and gnd, so that this pin become 1.2v. 6 vgh_ok vgh power good output after positive charge pump started properly, this p in switches from low level to high level. connect an external p ullup resistor. 7 pg_logic input for load switch control input pin for controlling lsw_out2. 8 vo2_ok output for ch2 power good after ch2 started properly, this pin switches from low level to high level. connect an external pullup resistor. 9 vref reference voltage 1.2v reference voltage for feedback of negative vol tage charge pump. connect an external capacitor (0.01f) for the stab ility. 10 test test pin used for the production test befor e shipment. connect to gnd. 11 sysuvlo input for system uvlo sysuvlo pin shuts down the operation of ic, when th e power supply voltage drops below regulated value. resisto rs are internally connected between vcc pin and sysuvlo pi n, and between sysuvlo pin and gnd. it is possible to set the detection voltage at any value by connecting extern al resister divider to sysuvlo pin. 12 panel_en input for panel power supply enable when low level voltage is applied to panel_en pin, negative voltage charge pump, load switch 1 and positive vol tage charge pump stop their operations. if not in use, connect to vreg5 pin. 13 14 nc nc no connection. leave open. 15 inv_ldo ldo amplifier inverting input ldo inverting input. the voltage on this pin is 1.2 v in the normal operation. 16 sgnd ground for signal ground pin for the contro l circuit block. 17 v_ldo power supply for ldo power supply pin for ldo amplifier.
thine electronics, inc. 5/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. pin # symbol function description 18 non_amp noninverting input for operational amplifier noninverting input pin for operational amplifier. 19 inv_amp inverting input for operational amplifier inverting input pin for operational amplifier. 20 v_amp power supply for operational amplifier power supply pin for operational amplifier. 21 out_amp output for operational amplifier output pin for operational amplifier. 22 out_ldo output for ldo output pin for ldo. 23 out_vgl output for vgl driver output pin for the negative voltage charge pump driver. 24 v_vgl power supply for vgl power supply pin for negative voltage charge pump driver circuit. 25 v_vgh power supply for vgh power supply pin for positive voltage charge pump driver circuit. 26 out_vgh output for vgh driver output pin for the positive voltage charge pump driver. 27 pgnd power ground power ground pin. 28 vgl_fb input for vgl feedback feedback voltage input for negative voltage charge pump. in fixed output voltage mode, connect this pin to the output of negative voltage charge pump. in adjustable output voltage mode, connect resistors between the output and vgl_fb pin , and between vgl_fb pin and vref pin, so that this pin b ecome 0v. 29 vgh_fb input for vgh feedback feedback voltage input for positive voltage charge pump. in fixed output voltage mode, connect to the output of posit ive voltage charge pump. in adjustable output voltage mode, con nect resistors between the output and vgh_fb pin, and between vgh_ fb pin and gnd, so that this pin become 1.2v. 30 lsw_out2 output 2 for load switch control gate control pin for load switch 2. 31 lsw_out1 output 1 for load switch control gate control pin for load switch 1, with builtin s oft start function. 32 33 ll2 output for ch2 switching output pin for ch2. 34 bst2 power supply for ch2 high side driver power supply pin for ch2 high side driver. connect a capacitor between bst2 pin and ll2 pin. 35 pvcc power supply for ch2 power supply pin for ch2. 36 vcc power supply for control circuit power supply pin for the control circuit block. 37 38 39 lx1 output for ch1 switching output pin for ch1. 40 vo1_in feedback voltage input for ch1 feedback voltage input pin for ch1 in fixed output voltage mode. connect to output for ch1. in adjustable out put voltage mode, connect to ground.
thine electronics, inc. 6/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. absolute maximum ratings parameter symbol rating units vcc, pvcc vcc 18 v inv1, fb1, vo2_in, pg_logic, test, sysuvlo, panel_en, inv_ldo, vgl_fb vl_in 6.5 v vreg5, pc2, vgh_ok, vo2_ok, vref, bst2ll2 vl_out 6 .5 v non_amp, inv_amp, vo1_in vh_in1 20 v vgh_fb vh_in2 40 v vgl_fb vh_in3 8 v out_amp, out_ldo, out_vgl, out_vgh, lsw_out2, lsw_out1 vh_out1 20 v ll2 vh_out2 18 v bst2 vh_out3 24.5 v lx1 vh_out4 25 v v_ldo, v_amp, v_vgl, v_vgh vh_cc 20 v power dissipation pd 4295 (ta<25 c) mw junction temperature tj 150 c operating temperature range ta 40 ~ +85 c storage temperature range tstg 55 ~ +150 c power dissipation 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 -40 -20 0 20 40 60 80 100 120 140 160 ambient temperature ta () power dissipation pd (mw)
thine electronics, inc. 7/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. recommended operating conditions parameter min typ max units vcc, pvcc 4.2 15 v vgh_ok, pg_logic, vo2_ok, sysuvlo, panel_en 0.1 5.5 v v_ldo 3.0 17 v v_amp, v_vgl, v_vgh 4.2 17 v non_amp, lsw_out2, lsw_out1 0.1 17 v external capacitor for vref 0.01 f external capacitor for vreg5 10 f
thine electronics, inc. 8/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. electrical characteristics at vcc=12v, ta=25 , unless otherwise noted. parameter symbol conditions min typ max units whole of circuit average current consumption icc vcc pin ? 5.0 ? ma reference voltage vref cvref=0.01f 1.188 1.200 1.2 12 v load regulation (reference voltage) vref(load) iref=100a ~ 1ma ? 2 5 mv line regulation (reference voltage) vref(line) iref=100a vcc=4.2 ~ 15v ? 2 8 mv output voltage (5v regulator) vreg5(range) io=1ma ? 5.0 ? v load regulation (5v regulator) vreg5(load) io=0.1m a ~ 5ma ? ? 100 mv line regulation (5v regulator) vreg5(line) io=1ma vcc=5.5 ~ 15v ? ? 50 mv oscillation frequency fosc 430 500 570 khz uvlo release voltage vuvlo vcc pin 5.0 5.46 6.00 v uvlo hysteresis voltage vuvlo(hys) vcc pin 1.4 1.96 2.5 v system uvlo release voltage vsysuvlo sysuvlo pin 1. 44 1.56 1.68 v system uvlo hysteresis voltage vsysuvlo(hys) sysuvlo pin 0.41 0.56 0.71 v ch-1 boost converter block feedback voltage (in fixed mode) vo1(fix) 15.2 15.6 16.0 v feedback voltage (in adjustable mode) vo1(adj) vref C 10m vref vref + 10m v vo1_in voltage level (in fixed mode) vo1_in(fix)_th 4.6 ? ? v vo1_in voltage level (in adjustable mode) vo1_in(adj)_th ? ? 2.7 v output onresistance ron(ch1) ? 100 170 m output off leakage current ileak(ch1) ? ? 10 a maximum duty cycle dmax(ch1) lx1 pin pulse ? 5 ? % short circuit detection threshold voltage vuvp(ch1 vo1 output voltage ? 85 ? % delay time for short circuit detection latch tuvp(ch1) ? 12.2 ? ms over voltage detection threshold voltage vovp(ch1 vo1 output voltage ? 125 ? % over current detection threshold voltage ics1 vcc=12v, vo1=15.6v, vo1 output current 4.0 ? ? a ch-2 buck converter block feedback voltage vo2 3.23 3.30 3.37 v output onresistance ron(ch2) ? 170 290 m
thine electronics, inc. 9/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. parameter symbol conditions min typ max units output off leakage current ileak(ch2) ? ? 10 a maximum duty cycle dmax(ch2) ll2 pin pulse ? 88 ? % short circuit detection threshold voltage vuvp(ch2 vo2 output voltage ? 85 ? % delay time for short circuit detection latch tuvp(ch2) ? 12.2 ? ms over voltage detection threshold voltage vovp(ch2 vo2 output voltage ? 125 ? % delay time for over voltage detection latch tovp(ch2) ? 2.44 ? ms over current detection threshold voltage ics(ch2) vcc=12v, vo2 output current 3.5 ? ? a power good threshold voltage vpg(ch2) ? 85 ? % output onresistance of power good ipg(ch2) vo2_ok pin ? 0.8 1.6 k output leakage current of power good ipgleak(ch2) vo2_ok=5v ? ? 2 a vgh positive charge pump block feedback voltage (in fixed mode) vgh(fix) 34.5 35.6 36.7 v feedback voltage (in variable mode) vgh(adj) vref C 20m vref vref + 20m v high side output onresistance ronh(vgh) v_vgh=15v ioh=50ma ? 3.5 ? low side output onresistance ronl(vgh) v_vgh=15v ioh=50ma ? 3.5 ? duty cycle duty(vgh) ? 50 ? % short circuit detection threshold voltage vuvp(vgh vgh output voltage ? 85 ? % power good threshold voltage vpg(vgh) vgh output vo ltage ? 85 ? % output onresistance of power good ipg(vgh) vgh_ok pin ? 0.8 1.6 k output leakage current of power good ipgleak(vgh) vgh_ok=5v ? ? 2 a vgl negative charge pump block feedback voltage (in fixed mode) vgl(fix) 6.19 6.00 5.81 v feedback voltage (in variable mode) vgl(adj) 20 0 20 mv high side output onresistance ronh(vgl) v_vgl=15v ioh=50ma ? 11 ? low side output onresistance ronl(vgl) v_vgl=15v ioh=50ma ? 5 ?
thine electronics, inc. 10/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. parameter symbol conditions min typ max units duty cycle duty(vgl) ? 80 ? % short circuit detection threshold voltage vuvp(vgl vgl output voltage ? 82 ? % vgl startup control input threshold voltage panel_en (th) panel_en voltege 0.88 1.0 1.12 v ldo block feedback voltage vldo vref C 20m vref vref + 20m v load regulation vldo(load) v_ldo=15.6v, out_ldo=15.2v ildo=0.1m ~ 20ma ? ? 45 mv max output current ildo(max) v_ldo=15.6v, out_ldo=15.2v 250 ? ? ma dropout voltage vdrop(ldo) v_ldo=15.6v, out_ldo=15.2v ildo=10ma ? ? 0.15 v operational amplifier block input offset voltage vamp(off) 13 10 34 mv load regulation vamp(load) iamp=0 ~ +/5ma 50 ? 50 mv line regulation vamp(line) v_amp=9v ~ 17v out_amp=6v ? ? 50 mv common mode input voltage range vamp(range) 3 ? v_amp C 0.1 v output source maximum current ivcomh(max) v_amp=12v, out_amp=6v output drop : 0.5v 100 180 ? ma output sink maximum current ivcoml(max) v_amp=12v, out_amp=6v output rise : 0.5v ? 180 100 ma input bias current iib(vcom) ? ? 200 na switching control block 1 soft start time tss(lsw_out1) ? 10 ? ms output resistance ro(1sw_out1) io=1ma ? 1.2 ? k output off leakage current ileak ? ? 1 a switching control block 2 input threshold voltage v(pg_logic) 0.6 ? 1.1 v output resistance ro(1sw_out2) io=1ma ? 1.2 ? k output off leakage current ileak ? ? 1 a
thine electronics, inc. 11/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. functional description system uvlo THV3543 has builtin uvlo (under voltage lockout) c ircuit to prevent lowvoltage input malfunction. th e internal specified threshold voltage is 3.5v, the release vo ltage is 5.46v. when input power supply voltage (vi n) reaches the uvlo release voltage (5.46v), the device starts the soft start operation and output voltage (vo) gradu ally rises up to the regular voltage. when the input power supply vo ltage (vin) drops below 3.5v, uvlo stops switching operation immediately and starts discharging soft start. acco rdingly, the output voltage (vo) drops (see figure 1). vin vo switching operating stop operating stop 5.46 v 3.50 v figure 1. uvlo operation example the uvlo threshold voltage also can be set optional ly by applying divided vin by an external resistanc e to sysuvlo pin (see figure 2). please use external res istance of enough lower value than the internal res istance. the system uvlo threshold voltage is given by the follo wing formulas. r2 r2 r1 1.56 voltage release uvlo system + = r2 r2 r1 1.0 operation) of voltage limit wer voltage(lo detection uvlo system + = uvlo comp vcc sysuvlo vin r1 r2 500k 200k figure 2. system uvlo setting circuit
thine electronics, inc. 12/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. voltage reference circuit voltage reference circuit generates temperaturecom pensated voltage (1.2v) which is used as the intern al reference voltage. also an external load current (up to 1ma, maximum) can be obtained from vref pin. please conn ect a capacitor (0.01f) between vref pin and sgnd for st ability. vreg5 vreg5 is builtin 5v local regulator. please connec t an external capacitor (10f) between vreg5 pin an d sgnd. oscillator circuit oscillation frequency is internally fixed at 500khz . thermal shut down (tsd) thermal shut down circuit is built in to prevent da mages caused by excessive heat. when the junction t emperature reaches 175 c, tsd circuit stops switching operation and the re gulator vreg5 operation. the release temperature is 160 c. dc/dc converter ch-1, ch-2 ch1 and ch2 are pwm controllers. ch1 is for boos t, ch2 is fixed at 3.3v for buck. power mosfet and over current detection circuit are built in. maximum dut y cycle ratio of ch1 lx1 pin is 8.3%, ch2 ll2 pin is 88%. charge pump circuit vgh, vgl vgh is positive charge pump, and vgl is negative. v gh and vgl also can operate in pfm mode. the duty c ycle ratio of vgh is fixed at 50%, vgl is fixed at 80%. vo2_ok, vgh_ok vo2_ok and vgh_ok are open drain output of the pull down transistor. when the power supply is turned o n, the transistor is turned on pulling vo2_ok pin and vgh_ ok pin to ground level. when each voltage on ch2 a nd vgh reaches 85% of normal output voltage, vo2_ok and vg h_ok are turned off respectively. load switch control lsw_out1 pin controls the external pch mosfet load switch after normal startup of vgl. soft start fu nction is built in. lsw_out2 pin is open drain output. when pg_logic pi n is turned high level, pulldown transistor is tur ned off. lsw_out2 pin can be used as the external nch mosfe t load switch controller or level shifter. operational amplifier operational amplifier is used for vcom or half avdd . use an external bipolar transistor when large out put current is required. ldo ldo have builtin recovery type current limiting pr otection. the load current capacity is within 250ma . the output voltage is set by external resistance (see output voltage setting (ldo)).
thine electronics, inc. 13/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. soft start circuit soft start function raises the output voltage gradu ally to prevent overshoot and inrush current at sta rtup. ch1, ch2 and load switch 1 circuit have internal soft start function. the output voltage of these internal soft start circuits rise according to each internal startup sequences. acco rdingly, the output of dc/dc converter and the outp ut after load switch rise. soft start operation is completed when these outputs have reached each regular voltage. s oft start time of ch1, ch2 and load switch 1 are set to 10msec (see figure 3). start-up sequence figure 3 shows the waveform of startup sequence. t he device starts switching after normal startup of ch1 and ch2. vgl starts after normal startup of ch1 outp ut (vo1) and also when panel_en pin is turned high level. vgh starts with 5msec delay after startup of load switch 1. open drain pins, vo2_ok and vgh_ok, start after normal startup of ch2 and vgh respectively. vgh vo2 3.3v 5msec 10msec 10msec vo1 avdd 10msec vgl (panel_en=high) ldo (v_ldo=v_vgh) vgh_ok vo2_ok figure 3. startup sequence waveforms panel_en during the startup operation of ic, vgl starts aft er normal startup of ch1 output (vo1) and also wh en panel_en pin is turned high level. if low level vol tage is applied to panel_en pin, vgl/load switch 1/ vgh stop operating. high level voltage is applied to vg l_on pin again, operations after vgl are restarted. if not in use, please connect to vreg5 pin.
thine electronics, inc. 14/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. under voltage protection (uvp) uvp is protective function which shuts down the pow er supply, when under voltage condition of dc/dc, v gh and vgl caused by short circuit continues for more than a definite period of time. the internal comparator monitors the output voltage. if the output voltage drops below a definite value, timer latch circuit starts operati ng (see figure 4). when abnormal output continues for more than 12.2ms ec, the device stops switching operation and goes i nto latch state. if uvlo operates before the device goes into the latch state, the timer will be reset. as to vgh and vgl, uvp detection does not operate f or 3msec immediately after startup sequence. pleas e set the startup time of charge pumps within 15msec to prev ent startup failure. + amp or comp vref + vth uvp comp output voltage detection timer latch figure 4. under voltage detection circuit over voltage protection (ovp) ovp is protective function which shuts down the pow er supply when output voltage on ch1 and ch2 exce ed a defined voltage. ch1 stops switching operation, wh en the voltage on inv1 pin exceeds 1.5v. ch2 stops switching operation, when the voltage on vo2_in pin exceeds 4 .13v (see figure 5) . as to ch2, if abnormal output is detected, timer l atch circuit operates. when abnormal output continu es for 2.44msec, the device stops switching operation and goes into latch state. + amp vref + vth ovp comp ss output voltage dtection pwm comp out figure 5. over voltage detection circuit over current protection (ocp) ch1 and ch2 have builtin over current protection circuit. when load current exceeds a definite curr ent, ocp stops switching operation of the device. ocp operates at more than 4.0a on ch1, 3.5a on ch2. if over current is detected continuously, low duty switching pulse is generated and that causes output voltage drop. when output voltage drops below a definite voltage for more than 12.2msec, uvp operates and the device goes into latch state.
thine electronics, inc. 15/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. switching channel output voltage mode output voltage mode of switching channel can be cho sen the adjustable mode or the fixed mode, accordin g to the setting of vo1_in pin. when ch1 output is connected directly to vo1_in pi n, the output voltage is turned into the fixed mode . ch1 is fixed at 15.6v, vgh at 35.6v and vgl at 6v. whe n vo1_in pin is connected to ground, the output vol tage is turned into the adjustable mode. output voltage of ch1, vgh and vgl can be set by an external resi stance. ch2 is fixed at 3.3v in both modes. output voltage setting (adjustable mode) in ch1, the voltage on inv1 pin will be equal to t he voltage on vref by the action of feedback (see f igure 6). the voltage on inv1 pin is divided vout1 by r1 and r2. therefore, vref r2 r1 r2 vout1 = + thus, ?? ? ?? ? + = ?? ? ?? ? + = r2 r1 1 2.1 r2 r1 1 vref vout1 in vgh, the voltage on vgh_fb pin is controlled to be equal to the voltage on vref (see figure 7). the voltage on inv_vgh pin is divided voltage on vgh by r4 and r5. therefore, ?? ? ?? ? + = ?? ? ?? ? + = r5 r4 1 2.1 r5 r4 1 vref vgh c1 fb1 inv1 vout1 r2 r3 r1 + error amp1 vref =1.2v pwm comp. c2 figure 6. ch1 output voltage setting vgh_fb vgh r5 r4 + comp vref =1.2v output circuit figure 7. vgh output voltage setting
thine electronics, inc. 16/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. in vgl, the voltage on vgl_fb pin is controlled to be equal to zero (see figure 8). the current throug h vgl_fb pin can be ignored. thus, ( ) r7 r6 2.1 r7 r6 vref vgl ? = ? = vgl_fb vgl r7 r6 + - comp vref =1.2v output circuit r6 vref =1.2v r7 vgl 0v figure 8. vgl output voltage setting output voltage setting (fixed mode) when the output of ch1 is connected directly to vo 1in pin, the output voltage is in the fixed mode. connect the output of vgh and vgl directly to vgh_fb pin and vg l_fb pin respectively. ch1, vgh and vhl are fixed at 15.6v, 35.6v and 6v respectively. in ch1, connect a capacitor for phase compensation between vo1_in pin and inv1 pin, and also a resist ance and a capacitor between inv1 pin and fb1 pin (see figure 9). fb1 inv1 vout1 + error amp1 vref =1.2v pwm comp. vo1_in figure 9. ch1 circuit in fixed output voltage mode
thine electronics, inc. 17/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. output voltage setting (ldo) in ldo, the voltage on inv_ldo pin will be equal to the voltage on vref by the action of feedback (see figure 10). the voltage on inv_ldo pin is divided out_ldo by r8 and r9. thus, ?? ? ?? ? + = r9 r8 1 1.2 out_ldo figure 10. ldo circuit
thine electronics, inc. 18/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. package dimensions qfn40 pin connect the exposed pad to gnd for enhanced thermal performance.
thine electronics, inc. 19/19 THV3543_rev.1.00_e copyright? 2011 thine electronics, inc. notices and requests 1. the product specifications described in this mat erial are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not alway s apply to the customers design. we are not responsible for possi ble errors and omissions in this material. please n ote if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copy right, knowhow or other proprietary. copying or disclosing to thir d parties the contents of this material without our prior permiss ion is prohibited. 4. note that if infringement of any third party's i ndustrial ownership should occur by using this prod uct, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. this product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly c oncerning people's life, aerospace equipment, or nu clear control equipment). also, when using this product for the e quipment concerned with the control and safety of t he transportation means, the traffic signal equipment, or various types of safety equipment, please do it after applying appropriate measures to the product. 6. despite our utmost efforts to improve the qualit y and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semiconducto r product. therefore, you are encouraged to have su fficiently redundant or error preventive design applied to the use of the product so as not to have our product c ause any social or public damage. 7. please note that this product is not designed to be radiationproof. 8. customers are asked, if required, to judge by th emselves if this product falls under the category o f strategic goods under the foreign exchange and foreign trade contro l law. 9. the product or peripheral parts may be damaged b y a surge in voltage over the absolute maximum rati ngs or malfunction, if pins of the product are shorted by such as foreign substance. the damage may cause a smoking and ignition. therefore, you are encouraged to impl ement safety measures by adding protection devices, such as fuses. thine electronics, inc. email: sales@thine.co.jp

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