1 ? fn4874.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2000, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners. hs-201hsrh radiation hardened high speed, quad spst, cmos analog switch the hs-201hsrh is a monolithic cmos analog switch featuring power-off high input impedance, very fast switching speeds and low on resistance. fabrication on our di rsg process assures sel immunity and only very slight sensitivity to low dose rate (eldrs). these class v/q devices are tested and guaranteed for 300krad (si) total dose performance. power-off high input impedance enables the use of this device in redundant circuits without causing data bus signal degradation. esd protection, ov ervoltage protection, fast switching times, low on resistance, and guaranteed radiation hardness, make the hs-201hsrh ideal for any space application where improv ed switching performance is required. specifications for rad hard qm l devices are controlled by the defense supply center (dscc). the smd numbers listed here must be used when ordering flight units. detailed electrical specifications for this device are contained in smd 5962-99618. a ?hot-link? is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp pinout hs1-201hsrh, sbdip (cdip2-t16) hs9-201hsrh, flatpack (cdfp4-f16) top view features ? electrically screened to dscc smd 5962-99618 ? qml qualified per mil-prf-38535 ? radiation performance - guaranteed total dose performance . . . . . 300krad (si) - sel immune. . . . . . . . . . . . . . . . . . . . .di rsg process ? overvoltage protection (power on, switch off) . . . . . . 30v ? power off high impedance . . . . . . . . . . . . . . . . . . . 17v ? fast switching times -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110ns (max) -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80ns (max) ? low ?on? resistance . . . . . . . . . . . . . . . . . . . 50 ? (max) ? pin compatible with industry standard 201 types ? operating supply range . . . . . . . . . . . . . . . . . 10v to 15v ? wide analog voltage range ( 15v supplies) . . . . . . . 15v ? ttl compatible applications ? high speed multiplexing ? sample and hold circuits ? digital filters ? operational amplifier gain switching networks ? integrator reset circuits 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 a1 out1 in1 v- gnd in4 a4 out4 a2 in2 v+ nc in3 out3 a3 out2 data sheet march 24, 2006
2 fn4874.1 march 24, 2006 die characteristics die dimensions 2790 m x 4950 m (110 mils x 195 mils) thickness: 483 m 25.4 m (19 mils 1 mil) interface materials glassivation type: phosphorus silicon glass (psg) thickness: 8.0k ? +/-1.0k ? metallization type: ti/alcu thickness: 16.0k ? +/- 2k ? substrate rad hard silicon gate, dielectric isolation backside finish silicon assembly related information substrate potential unbiased (di) additional information worst case current density <2.0 x 10 5 a/cm 2 transistor count 328 metallization mask layout hs-201hsrh ordering information ordering number internal mkt. number part marking temp. range (c) package pkg. dwg. # 5962f9961801vec hs1-201hsrh-q q 5962f9961801vec -55 to 125 16 ld sbdip d16.3 5962f9961801qec hs1-201hsrh-8 q 5962f9961801qec -55 to 125 16 ld sbdip d16.3 5962f9961801vxc hs9-201hsrh-q q 5962f9961801vxc -55 to 125 16 ld flatpack k16.a 5962f9961801qxc hs9-201hsrh-8 q 5962f9961801qxc -55 to 125 16 ld flatpack k16.a 5962f9961801v9a hs0-201hsrh-q - -55 to 125 - - hs1-201hsrh/proto hs1-201hsrh/proto hs1-201hsrh/proto -55 to 125 16 ld sbdip d16.3 hs9-201hsrh/proto hs9-201hsrh/proto hs9-201hsrh/proto -55 to 125 16 ld flatpack k16.a out4 in4 gnd v- in1 a4 a3 a1 a2 out3 in3 v+ in2 out2 out1 hs-201hsrh
3 fn4874.1 march 24, 2006 hs-201hsrh ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off- center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the finished lead surfac es, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from t he body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k16.a mil-std-1835 cdfp4-f16 (f-5a, configuration b) 16 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d- 0.440 - 11.18 3 e 0.245 0.285 6.22 7.24 - e1 - 0.315 - 8.00 3 e2 0.130 - 3.30 -- e3 0.030 - 0.76 -7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 -6 m- 0.0015 - 0.04 - n16 16- rev. 1 2-20-95
4 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn4874.1 march 24, 2006 hs-201hsrh ceramic dual-in-line me tal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this c onfiguration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d16.3 mil-std-1835 cdip2-t16 (d-2, configuration c) 16 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a- 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d- 0.840 - 21.34 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 -6 s2 0.005 - 0.13 -7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m- 0.0015 - 0.038 2 n16 168 rev. 0 4/94
|
