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d a t a sh eet preliminary speci?cation supersedes data of 2002 may 23 2002 nov 21 integrated circuits UDA1338H multichannel audio coder-decoder
2002 nov 21 2 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H contents 1 features 1.1 general 1.2 multiple format data interface 1.3 digital sound processing 1.4 advanced audio configuration 2 applications 3 general description 4 ordering information 5 quick reference data 6 block diagram 7 pinning 8 functional description 8.1 system clock 8.2 audio analog-to-digital converter (audio adc) 8.3 voice analog-to-digital converter (voice adc) 8.4 decimation filter of audio adc 8.5 decimation filter of voice adc 8.6 interpolation filter of dac 8.7 noise shaper of dac 8.8 digital mixer 8.9 audio digital-to-analog converters 8.10 power-on reset 8.11 audio digital interface 8.12 voice digital interface 8.13 dsd mode 8.14 microcontroller interface mode 9 l3-bus interface 9.1 general 9.2 device addressing 9.3 register addressing 9.4 data write mode 9.5 data read mode 10 i 2 c-bus interface 10.1 general 10.2 characteristics of the i 2 c-bus 10.3 bit transfer 10.4 byte transfer 10.5 data transfer 10.6 start and stop conditions 10.7 acknowledgment 10.8 device address 10.9 register address 10.10 write and read data 10.11 write cycle 10.12 read cycle 11 register mapping 11.1 address mapping 11.2 register mapping 11.3 system settings 11.4 audio adc and dac subsystem settings 11.5 voice adc system settings 11.6 status output register (read only) 11.7 dac channel selection 11.8 dac features settings 11.9 dac channel 1 to 6 settings 11.10 dac mixing channel settings 11.11 audio adc 1 and adc 2 input amplifier gain settings 11.12 voice adc gain settings 11.13 supplemental settings 1 11.14 supplemental settings 2 12 limiting values 13 handling 14 quality specification 15 thermal characteristics 16 dc characteristics 17 ac characteristics 18 timing 19 package outline 20 soldering 20.1 introduction to soldering surface mount packages 20.2 reflow soldering 20.3 wave soldering 20.4 manual soldering 20.5 suitability of surface mount ic packages for wave and reflow soldering methods 21 data sheet status 22 definitions 23 disclaimers 24 purchase of philips i 2 c components
2002 nov 21 3 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 1 features 1.1 general 2.7 to 3.6 v power supply 5 v tolerant digital inputs 24-bit data path selectable control: via l3-bus or i 2 c-bus microcontroller interface supports sample frequency ranges for: C audio adc: f s = 16 to 100 khz C voice adc: f s =7to50khz C audio dac: f s = 16 to 200 khz. separate power control for adc and dac adc plus integrated high-pass filter to cancel dc offset integrated digital filter plus dac slave mode only applications easy application. 1.2 multiple format data interface audio interface supports standard i 2 s-bus, msb-justified, lsb-justified and two multichannel formats voice interface supports i 2 s-bus and mono channel formats. 1.3 digital sound processing control via l3-bus or i 2 c-bus: C channel independent digital logarithmic volume C digital de-emphasis for f s = 32, 44.1, 48 or 96 khz C soft or quick mute C output signal polarity control. 1.4 advanced audio con?guration inputs: C 4 single-ended audio inputs (2 stereo) with programmable gain amplifiers C 1 single-ended voice input outputs: C 6 differential audio outputs (3 stereo) dsd mode to support stereo dsd playback high linearity, wide dynamic range and low distortion dac digital filter with selectable sharp or soft roll-off. 2 applications excellently suitable for multichannel home audio-video application. 3 general description the UDA1338H is a single-chip consisting of 4 plus 1 analog-to-digital converters and 6 digital-to-analog converters with signal processing features employing bitstream conversion techniques. the multichannel configuration makes the device eminently suitable for use in digital audio equipment which incorporates surround feature. the UDA1338H supports conventional 2 channels per line data transfer conformable to the i 2 s-bus format with word lengths of up to 24 bits, the msb-justified format with word lengths of up to 24 bits and the lsb-justified format with word lengths of 16, 20 and 24 bits, as well as 4 to 6 channels per line transfer mode. the device also supports a combination of the msb-justified output format and the lsb-justified input format. the UDA1338H has special sound processing features in the direct stream digital (dsd) playback mode, de-emphasis, volume and mute which can be controlled via the l3-bus or i 2 c-bus interface. 4 ordering information type number package name description version UDA1338H qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2
2002 nov 21 4 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 5 quick reference data v ddd =v dda(ad) =v dda(da) = 3.3 v; t amb =25 c; r l =22k w ; all voltages referenced to ground (pins v ss ); unless otherwise speci?ed. notes 1. the input voltage can be up to 2 v (rms) when the current through the adc input pin is limited to approximately 1 ma by using a series resistor. 2. the input voltage to the adc scales proportionally with the power supply voltage. symbol parameter conditions min. typ. max. unit supplies v dda(ad) adc analog supply voltage 2.7 3.3 3.6 v v dda(da) dac analog supply voltage 2.7 3.3 3.6 v v ddd digital supply voltage 2.7 3.3 3.6 v i dda(ad) adc analog supply current f adc =48khz - 30 - ma i dda(da) dac analog supply current f dac =48khz - 20 - ma i ddd digital supply current f adc =f dac = 48 khz; f voice = 48 khz - 31 - ma i ddd(pd) digital supply current in power-down mode audio and voice adcs power-down - tbf - ma dac power-down - tbf - ma t amb ambient temperature - 20 - +85 c audio analog-to-digital converter d 0 digital output level at 0 db setting; 900 mv (rms) input; notes 1 and 2 - 2.5 - 1.2 - 0.7 db (thd+n)/s total harmonic distortion-plus-noise to signal ratio at - 1 dbfs -- 90 - 83 db at - 60 dbfs; a-weighted -- 40 - 34 db s/n signal-to-noise ratio code = 0; a-weighted 94 100 - db a cs channel separation - 100 - db digital-to-analog converter d ifferential mode v o(rms) output voltage (rms value) at 0 dbfs digital input 1.9 2.0 2.1 v (thd+n)/s total harmonic distortion-plus-noise to signal ratio at 0 dbfs -- 100 - 93 db at - 60 dbfs; a-weighted -- 50 - 45 db s/n signal-to-noise ratio code = 0; a-weighted 107 114 - db a cs channel separation - 117 - db s ingle - ended mode v o(rms) output voltage (rms value) at 0 dbfs digital input - 1.0 - v (thd+n)/s total harmonic distortion-plus-noise to signal ratio at 0 dbfs -- 90 - db at - 60 dbfs; a-weighted -- 45 - db s/n signal-to-noise ratio code = 0; a-weighted - 110 - db a cs channel separation - 114 - db
2002 nov 21 5 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 6 block diagram handbook, full pagewidth mgu581 pga adc 2l pll pll i 2 s-bus interface 3 hp filter decimation filter 6 21 20 22 30 37 40 24 23 vinl2 mcclk mcmode mcdata i2c_l3 bckda wsda 53 decimation filter dc-cancellation filter i 2 s-bus interface 2 l3-bus or i 2 c-bus control interface v dda(da) v ssa(da) interpolation filter volume, mute, de-emphasis noise shaper i 2 s-bus interface 1 v dda(ad) 9 v adcp 7 v adcn 1 v ref v ssa(ad) UDA1338H lna 10 vvoice pga adc 1l pga adc 2r pga adc 1r 2 vinl1 vout2n vout2p vout4n vout4p vout6n vout6p vout1n vout1p vout3n vout3p vout5n vout5p dac 2 34 - + 33 39 38 44 43 32 31 36 35 42 41 dac 4 - + dac 6 dac 1 dac 3 dac 5 - + - + adc clock test - + - + 25 datada1 26 datada2 27 datada3 13 dataad1 12 dataad2 14 bckad 11 test 4 vinr1 8 vinr2 19 sysclk 15 wsad 17 bckv 16 datav 18 wsv 28 29 v ddd v ssd fig.1 block diagram.
2002 nov 21 6 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 7 pinning note 1. see table 1. table 1 pin types symbol pin type (1) description v ref 1 aio adc reference voltage vinl1 2 aio adc 1 input left v ssa(ad) 3 agnd adc analog ground vinr1 4 aio adc 1 input right v dda(ad) 5 as adc analog supply voltage vinl2 6 aio adc 2 input left v adcn 7 aio adc reference voltage n vinr2 8 aio adc 2 input right v adcp 9 aio adc reference voltage p vvoice 10 aio voice adc input test 11 did test input; must be connected to digital ground (v ssd ) in application dataad2 12 do adc 2 data output dataad1 13 do adc 1 data output bckad 14 dis adc bit clock input wsad 15 di adc word select input datav 16 do voice data output bckv 17 dis voice bit clock input wsv 18 dio voice word select input or output sysclk 19 dis system clock input: 256f s , 384f s , 512f s or 768f s mcmode 20 di l3-bus l3mode input or i 2 c-bus dac mute control input mcclk 21 dis l3-bus l3clock input or i 2 c-bus scl input mcdata 22 iic l3-bus l3data input and output or i 2 c-bus sda input and output wsda 23 di dac word select input bckda 24 dis dac bit clock input datada1 25 di dac channel 1 and channel 2 data input datada2 26 di dac channel 3 and channel 4 data input datada3 27 di dac channel 5 and channel 6 data input v ssd 28 dgnd digital ground v ddd 29 ds digital supply voltage i2c_l3 30 di selection input for l3-bus or i 2 c-bus control vout1p 31 aio dac 1 positive output vout1n 32 aio dac 1 negative output vout2p 33 aio dac 2 positive output vout2n 34 aio dac 2 negative output vout3p 35 aio dac 3 positive output vout3n 36 aio dac 3 negative output v dda(da) 37 as dac analog supply voltage vout4p 38 aio dac 4 positive output vout4n 39 aio dac 4 negative output v ssa(da) 40 agnd dac analog ground vout5p 41 aio dac 5 positive output vout5n 42 aio dac 5 negative output vout6p 43 aio dac 6 positive output vout6n 44 aio dac 6 negative output type description agnd analog ground aio analog input and output as analog supply dgnd digital ground di digital input did digital input with internal pull-down resistor dio digital input and output dis digital schmitt-triggered input do digital output ds digital supply iic input and open-drain output for i 2 c-bus symbol pin type (1) description
2002 nov 21 7 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H handbook, full pagewidth UDA1338H mgu583 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 vout6n vout6p vout5n vout5p v ssa(da) vout4n vout4p v dda(da) vout3n vout3p vout2n dataad2 dataad1 bckad wsad datav bckv wsv sysclk mcmode mcclk mcdata v ref vinl1 v ssa(ad) vinr1 v dda(ad) vinl2 v adcn vinr2 v adcp vvoice test vout2p vout1n vout1p i2c_l3 v ddd v ssd datada3 datada2 datada1 bckda wsda fig.2 pin configuration.
2002 nov 21 8 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 8 functional description 8.1 system clock the UDA1338H operates in slave mode only; this means that in all applications the system must provide either the system clock (the bit clock for the voice adc) or the word clock. the audio adc part, the voice adc part and the dac part can operate at different sampling frequencies (dac-ws and adc-ws modes) as well as a common frequency (sysclk, wsda and dsd modes). the voice adc part supports a sampling frequency up to 50 khz and the audio adc supports a sampling frequency up to 100 khz. the dac sampling frequency range is extended up to 200 khz with the range above 100 khz being supported through 192 khz sampling mode, which halves the oversampling ratio of sysclk and internal clocks. the mode of operation of the audio and voice channels can be set via the l3-bus or i 2 c-bus microcontroller interface and are summarized in tables 2 and 3. when applied, the system clock must be locked in frequency to the corresponding digital interface clocks. the voice adc part can either receive or generate the wsv signal as shown in table 3. table 2 audio adc and dac operating clock mode table 3 voice adc operating clock mode mode audio adc audio dac clock frequency clock frequency sysclk sysclk 256f s , 384f s , 512f s or 768f s sysclk 256f s , 384f s , 512f s or 768f s sysclk 128f s , 192f s , 256f s or 384f s ; 192 khz sampling mode dac-ws sysclk 256f s , 384f s , 512f s or 768f s wsda 1f s adc-ws wsad 1f s sysclk 256f s , 384f s , 512f s or 768f s sysclk 128f s , 192f s , 256f s or 384f s ; 192 khz sampling mode wsda wsda 1f s wsda 1f s dsd sysclk 44.1 khz 512 sysclk 44.1 khz 512 mode voice adc bit clock frequency (bckv) word select (wsv) wsv-in input: 32f s , 64f s , 128f s or 256f s input wsv-out input: 32f s , 64f s , 128f s or 256f s output
2002 nov 21 9 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 8.2 audio analog-to-digital converter (audio adc) the audio analog-to-digital front-end of the UDA1338H consists of 4-channel single-ended adds with programmable gain stage (from 0 to 24 db with 3 db steps), controlled via the microcontroller interface. using the pga feature, it is possible to accept an input signal of 900 mv (rms) or 1.8 v (rms) if an external resistor of 10 k w is used in series. the schematic of audio adc front-end is shown in fig.3. 8.3 voice analog-to-digital converter (voice adc) the voice analog-to-digital front-end of the UDA1338H consists of a single-channel single-ended adc with a fixed gain (26 db) low noise amplifier (lna). together with the digital variable gain amplification stage, the voice adc provides optimal processing and reproduction of the microphone signal. the supported sampling frequency range is from 7 to 50 khz. power-down of the lna and the adc can be controlled separately. 8.4 decimation ?lter of audio adc the decimation from 64f s is performed in two stages. the first stage realizes characteristics with a decimation factor of 8. the second stage consists of three half-band filters, each decimating by a factor of 2. the filter characteristics are shown in table 4. table 4 decimation ?lter characteristics (audio adc) 8.5 decimation ?lter of voice adc the voice adc decimation filter is realized with the combination of a finite impulse response (fir) filter and infinite impulse response (iir) filter for shorter group delay. the filter characteristics are shown in table 5. during the power-on sequence, the output of the adc is hard muted for a certain period. this hard-mute time can be chosen between 1024 and 2048 samples. table 5 decimation ?lter characteristics (voice adc) 8.6 interpolation ?lter of dac the digital interpolation filter interpolates from 1f s to 128f s (or to 64f s in the 192 khz sampling mode) by cascading fir filters, and has two sets of filter coefficients for sharp and slow roll-off as given in tables 6 and 7. table 6 interpolation ?lter characteristics (sharp roll-off) table 7 interpolation ?lter characteristics (slow roll-off) 8.7 noise shaper of dac the 3rd-order noise shaper operates at either 128f s or 64f s (in the 192 khz sampling mode), and converts the 24-bit input signal into a 5-bit signal stream. the noise shaper shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. item condition value (db) pass-band ripple 0 to 0.45f s 0.01 pass-band droop 0.45f s - 0.2 stop band >0.55f s - 70 dynamic range 0 to 0.45f s >135 handbook, halfpage mgu582 v ref adc v dda = 3.3 v vinl, vinr 10 k w (0 db setting) 10 k w 10 k w input signal 2 v (rms) fig.3 schematic of audio adc front-end. x sin x ----------- ? ?? 4 item condition value (db) pass-band ripple 0 to 0.45f s 0.05 pass-band droop 0.45f s - 0.2 stop band >0.55f s - 65 dynamic range 0 to 0.45f s >110 item condition value (db) pass-band ripple 0 to 0.45f s 0.002 stop band >0.55f s - 75 dynamic range 0 to 0.45f s >135 item condition value (db) pass-band ripple 0 to 0.22f s 0.002 pass-band droop 0.45f s - 3.1 stop band >0.78f s - 94 dynamic range 0 to 0.22f s >135
2002 nov 21 10 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 8.8 digital mixer the UDA1338H has 6 digital mixers inside the interpolator (see fig.4). the adc signals can be mixed with the i 2 s-bus input signals. the mixing of the adc signals can be selected by the bits mix[1:0]. handbook, full pagewidth mgw786 mix [ 1:0 ] dis [ 1:0 ] ics [ 1:0 ] from adc mixer volume mixer mute dac1 1f s volume de-emphasis mute dac2 same as above dac3 same as above dac4 same as above dac5 same as above dac6 same as above interpolation filter ch1 mixer input ch2 ch3 ch4 from i 2 s-bus datada1 datada2 datada3 + fig.4 block diagram of dac mixer. 8.9 audio digital-to-analog converters the audio digital-to-analog front-end of the UDA1338H consists of 6-channel differential sdacs: an sdac is a multi-bit dac based upon switched resistors. to minimize data dependent modulation effects, a dynamic element matching (dem) algorithm scrambler circuit and dc current compensation circuit are implemented with the sdac. 8.10 power-on reset the UDA1338H has an internal power-on reset circuit which initializes the device (see fig.5). all the digital sound processing features and the system controlling features are set to their default values in the l3-bus and the i 2 c-bus modes. the reset time (see fig.6) is determined by an external capacitor which is connected between pin v ref and ground. the reset time should be at least 250 m s for v ref < 1.25 v. when v dda(ad) is switched off, the device will be reset again for v ref < 0.75 v. during the reset time, the system clock should be running.
2002 nov 21 11 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 8.11 audio digital interface the following audio formats can be selected via the microcontroller interface: i 2 s-bus format with data word length of up to 24 bits msb-justified format with data word length of up to 24 bits lsb-justified format with data word length of 16, 20 or 24 bits multichannel formats with data word length of 20 or 24 bits. the used data lines are dataad1 and datada1 and the sampling frequency must be below 50 khz. the formats are illustrated in figs 7 and 8. 8.12 voice digital interface the following voice formats can be selected via the microcontroller interface: i 2 s-bus format with data word length of up to 20 bits. the left and the right channels contain the same data. mono channel format with data word length of up to 20 bits. the formats are illustrated in fig.9. handbook, halfpage v dda(ad) v ref mgu585 c1 > 10 m f reset circuit 9 k w 9 k w fig.5 power-on reset circuit. handbook, halfpage 3.3 v ddd (v) 0 t 3.3 v dda(ad) (v) 0 t v ref (v) 1.65 1.25 0.75 t rst 0 t mgu586 > 250 m s fig.6 power-on reset timing.
2002 nov 21 12 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 2002 nov 21 12 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... a ndbook, full pagewidth 16 msb b2 b3 b4 b5 b6 left lsb-justified format 20 bits ws bck data right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb msb msb b2 2 1 > = 8 12 3 left i 2 s-bus format ws bck data right 3 > = 8 msb b2 mgt020 16 b5 b6 b7 b8 b9 b10 left lsb-justified format 24 bits ws bck data right 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 msb b2 left lsb-justified format 16 bits ws bck data right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb msb-justified format ws left right 3 2 1 3 2 1 msb b2 msb lsb lsb msb b2 b2 > = 8 > = 8 bck data fig.7 formats of input and output data (single-channel).
2002 nov 21 13 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 2002 nov 21 13 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... k , full pagewidth mgu588 multichannel format 20 bits ws bck data 2 122 21 ch1 42 41 61 msb lsb msb msb lsb ch3 lsb ch5 2 122 21 ch2 42 41 61 msb lsb msb multichannel format 24 bits (1) bck ws ws data 2 126 25 ch1 50 49 73 msb lsb msb msb lsb ch3 lsb ch5 2 126 25 ch2 50 49 73 msb lsb msb msb lsb ch4 lsb ch6 multichannel format 24 bits (2) bck data 126 25 ch1 50 49 74 msb lsb msb 73 97 ch3 msb lsb ch5 lsb 126 25 ch2 50 49 74 msb lsb msb 73 97 ch4 msb lsb ch6 lsb msb lsb ch4 lsb ch6 fig.8 formats of input and output data (multichannel). (1) format 1. (2) format 2.
2002 nov 21 14 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H handbook, full pagewidth mgu587 msb msb b2 2 1 3 8 12 3 left i 2 s-bus format ws bck data right 3 3 8 msb b2 msb b2 2 1 3 8 123 mono channel format ws bck data msb b2 fig.9 voice digital interface formats. 8.13 dsd mode the UDA1338H can receive 2.8224 mhz dsd signals and generate 88.2 khz multibit pcm signals as well as analog signal outputs. the configuration of the UDA1338H in the dsd mode is shown in fig.10. mgu584 left channel 2.8224 mhz dsd right channel 5.6448 mhz 88.2 khz bckad datada3 datada2 wsad wsda 88.2 khz 22.5792 mhz 5.6448 mhz i 2 s-bus (left and right) 88.2 khz pcm data datada1 dataad1 bckda sysclk dac + - interpolation noise shaping i 2 s-bus interface 2 decimation filter i 2 s-bus interface 1 v out1n v out1p left channel dac + - v out2n v out2p right channel analog output fig.10 dsd mode
2002 nov 21 15 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 8.14 microcontroller interface mode the microcontroller interface mode can be selected as shown in table 8: l3-bus mode when pin i2c_l3 = low i 2 c-bus mode when pin i2c_l3 = high. table 8 pin function in the l3-bus or i 2 c-bus mode table 9 qmute all the features are accessible with the i 2 c-bus interface protocol as with the l3-bus interface protocol. the detailed description of the device operation in the l3-bus mode and i 2 c-bus mode is given in chapters 9 and 10, respectively. 9 l3-bus interface 9.1 general the UDA1338H has an l3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. the exchange of data and control information between the microcontroller and the UDA1338H is lsb first and is accomplished through a serial hardware l3-bus interface comprising the following pins: mcclk: clock line with signal l3clock mcdata: data line with signal l3data mcmode: mode line with signal l3mode. the l3-bus format has two modes of operation: address mode data transfer mode. the address mode is used to select a device for a subsequent data transfer. the address mode is characterized by signal l3mode = low and a burst of 8 pulses for signal l3clock, accompanied by 8 bits (see fig.11). the data transfer mode is characterized by signal l3mode = high and is used to transfer one or more bytes representing a register address, instruction or data. basically, two types of data transfers can be defined: write action: data transfer to the device read action: data transfer from the device. 9.2 device addressing the device address consists of one byte with: data operating mode (dom) bits 0 and 1 representing the type of data transfer (see table 8) address bits 2 to 7 representing a 6-bit device address. the address of the UDA1338H is 01 0100 (bits 2 to 7). table 10 selection of data transfer 9.3 register addressing after sending the device address (including dom bits), indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. basically, there are 3 methods for register addressing: 1. addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see fig.11) 2. addressing for prepare read: bit is logic 1, indicating that data will be read from the register (see fig.12) 3. addressing for data read action. here, the device returns a register address prior to sending data from that register. when bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid (see fig.12). pin level on pin i2c_l3 low high l3-bus mode signal i 2 c-bus mode signal mcclk l3clock scl mcdata l3data sda mcmode l3mode qmute signal qmute function low no muting high muting dom transfer bit 0 bit 1 0 0 not used 1 0 not used 0 1 write data or prepare read 1 1 read data
2002 nov 21 16 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 2002 nov 21 16 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... mbl567 l3clock l3mode l3data 0 write device address dom bits register address data byte 1 data byte 2 10 fig.11 data write mode. mbl565 l3clock l3mode l3data 0 read valid/invalid device address prepare read send by the device dom bits register address device address register address data byte 1 data byte 2 111 0/1 1 fig.12 data read mode.
2002 nov 21 17 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 9.4 data write mode the data write mode is explained in the signal diagram of fig.11. for writing data to a device, 4 bytes must be sent (see table 11): 1. byte 1 starting with 01 for signalling the write action to the device, followed by the device address 01 0100. 2. byte 2 starting with a 0 for signalling the write action, followed by 7 bits indicating the destination address in binary format with bit a6 being the msb and bit a0 being the lsb. 3. byte 3 with bit d15 being the msb. 4. byte 4 with bit d0 being the lsb. it should be noted that each time a new destination register address needs to be written, the device address must be sent again. 9.5 data read mode to read data from the device, a prepare read must first be done and then data read. the data read mode is explained in the signal diagram of fig.12. for reading data from a device, the following 6 bytes are involved (see table 12): 1. byte 1 with the device address, including 01 for signalling the write action to the device. 2. byte 2 is sent with the register address from which data needs to be read. this byte starts with a 1, which indicates that there will be a read action from the register, followed by 7 bits for the destination address in binary format, with bit a6 being the msb and bit a0 being the lsb. 3. byte 3 with the device address, including 11 is sent to the device. the 11 indicates that the device must write data to the microcontroller. 4. byte 4 sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1). 5. byte 5 sent by the device to the bus, with the data information in binary format, with bit d15 being the msb. 6. byte 6 sent by the device to the bus, with the data information in binary format, with bit d0 being the lsb. table 11 l3-bus write data table 12 l3-bus read data byte l3-bus mode action first in time latest in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 address device address 01010100 2 data transfer register address 0 a6 a5 a4 a3 a2 a1 a0 3 data transfer data byte 1 d15 d14 d13 d12 d11 d10 d9 d8 4 data transfer data byte 2 d7 d6 d5 d4 d3 d2 d1 d0 byte l3-bus mode action first in time latest in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 address device address 01010100 2 data transfer register address 1 a6 a5 a4 a3 a2 a1 a0 3 address device address 11010100 4 data transfer register address 0 or 1 a6 a5 a4 a3 a2 a1 a0 5 data transfer data byte 1 d15 d14 d13 d12 d11 d10 d9 d8 6 data transfer data byte 2 d7 d6 d5 d4 d3 d2 d1 d0
2002 nov 21 18 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 10 i 2 c-bus interface 10.1 general the UDA1338H has an i 2 c-bus microcontroller interface. all the features are accessible with the i 2 c-bus interface protocol. in the i 2 c-bus mode, the dac mute function is accessible via pin mcmode with signal qmute. the exchange of data and control information between the microcontroller and the UDA1338H is accomplished through a serial hardware interface comprising the following pins as shown in table 8: mcclk: clock line with signal scl mcdata: data line with signal sda. 10.2 characteristics of the i 2 c-bus the bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to the supply voltage v dd via a pull-up resistor when connected to the output stages of a microcontroller. for a 400 khz ic, the recommendation for this type of bus from philips semiconductors must be followed (e.g. up to loads of 200 pf on the bus a pull-up resistor can be used, between 200 and 400 pf a current source or switched resistor must be used). data transfer can only be initiated when the bus is not busy. 10.3 bit transfer one data bit is transferred during each clock pulse (see fig.13). the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals. the maximum clock frequency is 400 khz. to be able to run on this high frequency, all the inputs and outputs connected to this bus must be designed for this high-speed i 2 c-bus according to the philips specification. 10.4 byte transfer each byte (8 bits) is transferred with the msb first (see table 13). table 13 byte transfer 10.5 data transfer a device generating a message is a transmitter; a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. msb bit number lsb 76543210 handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl fig.13 bit transfer on the i 2 c-bus.
2002 nov 21 19 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 10.6 start and stop conditions both data and clock line will remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high, is defined as a start condition (s); see fig.14. a low-to-high transition of the data line while the clock is high is defined as a stop condition (p). 10.7 acknowledgment the number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit (see fig.15). at the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed, must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so the sda line is stable low during the high period of the acknowledge related clock pulse. set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.14 start and stop conditions on the i 2 c-bus. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master fig.15 acknowledge on the i 2 c-bus.
2002 nov 21 20 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 10.8 device address before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always done with byte 1 transmitted after the start procedure. the UDA1338H acts as a slave receiver or a slave transmitter. therefore, the clock signal scl is only an input signal. the data signal sda is a bidirectional line. the UDA1338H device address is shown in table 14. table 14 i 2 c-bus device address of UDA1338H 10.9 register address the register addresses in the i 2 c-bus mode are the same as in the l3-bus mode. the register addresses are defined in chapter 11. 10.10 write and read data the i 2 c-bus configurations for a write and read cycle are shown in tables 15 and 16, respectively. the write cycle is used to write groups of two bytes to the internal registers for the settings. it is also possible to read the registers for the device status information. device address r/ w a6 a5 a4 a3 a2 a1 a0 - 00110000/1
2002 nov 21 21 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 2002 nov 21 21 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 10.11 write cycle the i 2 c-bus configuration for a write cycle is shown in table 15. the write cycle is used to write the data to the internal registers. the device and register addresses are one byte each, the setting data is always a pair of two bytes. the format of the write cycle is as follows: 1. the microcontroller starts with a start condition (s). 2. the first byte (8 bits) contains the device address 0011 000 and a logic 0 (write) for the r/ w bit. 3. this is followed by an acknowledge (a) from the UDA1338H. 4. after this the microcontroller writes the 8-bit register address (addr) where the writing of the register content of the uda1 338h must start. 5. the UDA1338H acknowledges this register address (a). 6. the microcontroller sends 2 bytes data with the most significant (ms) byte first and then the least significant (ls) byte. aft er each byte an acknowledge is followed from the UDA1338H. 7. if repeated groups of 2 bytes data are transmitted, then the register address is auto incremented. after each byte an acknowledge is followed from the UDA1338H. 8. finally, the UDA1338H frees the i 2 c-bus and the microcontroller can generate a stop condition (p). table 15 master transmitter writes to UDA1338H registers in the i 2 c-bus mode note 1. auto increment of register address. device address r/ w register address data 1 data 2 (1) data n (1) s 0011 000 0 a addr a ms1 a ls1 a ms2 a ls2 a msn a lsn a p acknowledge from UDA1338H
2002 nov 21 22 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 2002 nov 21 22 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 10.12 read cycle the read cycle is used to read the data values from the internal registers. the i 2 c-bus configuration for a read cycle is shown in table 16. the format of the read cycle is as follows: 1. the microcontroller starts with a start condition (s). 2. the first byte (8 bits) contains the device address 0011 000 and a logic 0 (write) for the r/ w bit. 3. this is followed by an acknowledge (a) from the UDA1338H. 4. after this the microcontroller writes the 8-bit register address (addr) where the reading of the register content of the uda1 338h must start. 5. the UDA1338H acknowledges this register address. 6. then the microcontroller generates a repeated start (sr). 7. then the microcontroller generates the device address 0011 000 again, but this time followed by a logic 1 (read) of the r/ w bit. an acknowledge is followed from the UDA1338H. 8. the UDA1338H sends 2 bytes data with the most significant (ms) byte first and then the least significant (ls) byte. after each byte an acknowledge is followed from the microcontroller (master). 9. if repeated groups of 2 bytes are transmitted, then the register address is auto incremented. after each byte an acknowledge is followed from the microcontroller. 10. the microcontroller stops this cycle by generating a negative acknowledge (na). 11. finally, the UDA1338H frees the i 2 c-bus and the microcontroller can generate a stop condition (p). table 16 master transmitter reads from the UDA1338H registers in the i 2 c-bus mode note 1. auto increment of register address. device address r/ w register address device address r/ w data 1 data 2 (1) data n (1) s 0011 000 0 a addr a sr 0011 000 1 a ms1 a ls1 a ms2 a ls2 a msn a lsn na p acknowledge from UDA1338H acknowledge from master
2002 nov 21 23 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 11 register mapping in this chapter the register addressing and mapping of the microcontroller interface of the UDA1338H is given. in table 17 an overview of the register mapping is given. in table 18 the actual register mapping is given and the register definitions are explained in sections 11.3 to 11.14. 11.1 address mapping table 17 overview of register mapping address function system settings 00h system 01h audio adc and dac subsystem 02h voice adc system status (read out registers) 0fh status outputs interpolator settings 10h dac channel and feature selection 11h dac feature control 12h dac channel 1 13h dac channel 2 14h dac channel 3 15h dac channel 4 16h dac channel 5 17h dac channel 6 18h dac mixing channel 1 19h dac mixing channel 2 1ah dac mixing channel 3 1bh dac mixing channel 4 1ch dac mixing channel 5 1dh dac mixing channel 6 adc input ampli?er gain settings 20h audio adc input ampli?er gain 21h voice adc input ampli?er gain supplemental settings 30h supplemental settings 1 31h supplemental settings 2
2002 nov 21 24 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 2002 nov 21 24 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 11.2 register mapping table 18 UDA1338H register mapping; note 1 add function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 system settings 00h system rst (2) vfs1 vfs0 vce vap dsd sc1 sc0 op1 op0 fs1 fs0 ace adp dce dap - 00100000 0 0 1 10 1 0 01h audio adc and dac subsystem dc pab paa mtb mta aif2 aif1 aif0 dag fil dvd dis1 dis0 dif2 dif1 dif0 1 00000000 0 0 0 00 0 0 02h voice adc system - ------- bck1 bck0 wsm vh1 vh0 pva mtv vif 0 00000000 1 1 0 10 0 0 status (read out only) 0fh status outputs - -------- - vs as1 as0 ds2 ds1 ds0 interpolator settings 10h dac channel and feature selection mix1 mix0 mc5 mc4 mc3 mc2 mc1 mc0 sel1 sel0 cs5 cs4 cs3 cs2 cs1 cs0 0 00000000 0 0 0 00 0 0 11h dac feature control ics1 ics0 de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0 12h dac channel 1 ics1 ics0 de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0 13h dac channel 2 -- de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0 14h dac channel 3 ics1 ics0 de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0 15h dac channel 4 -- de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0 16h dac channel 5 ics1 ics0 de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0 17h dac channel 6 -- de2 de1 de0 pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0
2002 nov 21 25 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 2002 nov 21 25 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... note 1. when writing new settings via the l3-bus interface, the default values should always be set to warrant correct operation. read access to the dac features register 11h will not return valid data. 2. when bit rst is set to logic 1, the default values are set to all the registers as shown in table 18. when start-up, all the registers in 00h are initialized as the default values and the mute control bits mta, mtb, mtv, mt and qm are set to logic 1. all other registers have non fixed values. 18h dac mixing channel 1 ics1 ics0 --- pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0 19h dac mixing channel 2 - ---- pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0 1ah dac mixing channel 3 ics1 ics0 --- pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0 1bh dac mixing channel 4 - ---- pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0 1ch dac mixing channel 5 ics1 ics0 --- pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0 1dh dac mixing channel 6 - ---- pd mt qm vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 0 00000000 0 0 0 00 0 0 adc input ampli?er gain settings 20h adc 1 and adc 2 input ampli?er gain - --- ib3 ib2 ib1 ib0 ---- ia3 ia2 ia1 ia0 0 00000000 0 0 0 00 0 0 21h voice adc input ampli?er gain - -------- - - iv4 iv3 iv2 iv1 iv0 - ------- 00000000 supplemental settings 30h supplemental settings 1 - ------- pdt ------- 0 00000000 0 0 0 00 0 0 31h supplemental settings 2 - -------- dith2 dith1 dith0 -- vmtp pdln a 0 00000000 0 0 0 00 0 0 add function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
2002 nov 21 26 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 11.3 system settings table 19 system register (address 00h) table 20 description of system register bits bit 15 14 13 12 11 10 9 8 symbol rst vfs1 vfs0 vce vap dsd sc1 sc0 reset default - 0010000 bit76543210 symbol op1 op0 fs1 fs0 ace adp dce dap reset default 00011010 bit symbol description 15 rst reset. a 1-bit value to initialize the l3-bus registers with the default settings by writing bit rst = 1. if bit rst = 0, there is no reset. 14 to 13 vfs[1:0] voice adc sampling frequency. a 2-bit value to select the voice adc sampling frequency. default 00. see table 21. 12 vce voice adc clock enable. a 1-bit value to enable the voice adc clock. if bit vce = 1 (default), then the clock is enabled; if bit vce = 0, then the clock is disabled. 11 vap voice adc power control . a 1-bit value to reduce the power consumption of the voice adc. if bit vap = 1, then the state is power-on; if bit vap = 0 (default), then the state is power-off. 10 dsd dsd mode selection. a 1-bit value to select the dsd mode. if bit dsd = 1, then the dsd mode; if bit dsd = 0 (default), then the normal mode. 9 to 8 sc[1:0] system clock frequency. a 2-bit value to select the used external clock frequency. 128f s system clock for the dac can be used by setting bit dvd = 1. default 00. see table 22. 7 to 6 op[1:0] operating mode selection. a 2-bit value to select the operation mode of the audio adc and dac. default 00. see table 23. 5 to 4 fs[1:0] sampling frequency. a 2-bit value to select the sampling frequency of the audio adc and dac in the ws mode. default 01. see table 24. 3ace adc clock enable. a 1-bit value to enable the audio adc clock. if bit ace = 1 (default), then the clock is enabled; if bit ace = 0, then the clock is disabled. 2 adp adc power control . a 1-bit value to reduce the power consumption of the audio adc. if bit adp = 1, then the state is power-on; if bit adp = 0 (default), then the state is power-off. 1 dce dac clock enable. a 1-bit value to enable the dac clock. if bit dce = 1 (default), then the clock is enabled; if bit dce = 0, then the clock is disabled. 0dap dac power control . a 1-bit value to reduce the power consumption of the dac. if bit dap = 1, then the state is power-on; if bit dap = 0 (default), then the state is power-off.
2002 nov 21 27 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H table 21 voice adc sampling frequency bits table 22 system clock frequency bits table 23 operating mode bits table 24 audio adc and dac sampling frequency bits 11.4 audio adc and dac subsystem settings table 25 audio adc and dac subsystem register (address 01h) vfs1 vfs0 function 0 0 6.25 to 12.5 khz (default) 0 1 12.5 to 25 khz 1 0 25 to 50 khz 1 1 reserved sc1 sc0 adc dac remark bit dvd = 0 bit dvd = 1 0 0 256f s 256f s 128f s default 0 1 384f s 384f s 192f s 1 0 512f s 512f s 256f s 1 1 768f s 768f s 384f s op1 op0 adc mode dac mode remark 0 0 sysclk (256f s , 384f s , 512f s or 768f s ) sysclk (128f s , 256f s , 384f s , 512f s or 768f s ) default 0 1 sysclk (256f s , 384f s , 512f s or 768f s ) wsda (1f s ) 1 0 wsad (1f s ) sysclk (128f s , 256f s , 384f s , 512f s or 768f s ) 1 1 wsda (1f s ) wsda (1f s ) fs1 fs0 function 0 0 12.5 to 25 khz 0 1 25 to 50 khz (default) 1 0 50 to 100 khz 1 1 100 to 200 khz bit 15 14 13 12 11 10 9 8 symbol dc pab paa mtb mta aif2 aif1 aif0 reset default 10000000 bit76543210 symbol dag fil dvd dis1 dis0 dif2 dif1 dif0 reset default 00000000
2002 nov 21 28 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H table 26 description of the audio adc and dac subsystem register bits table 27 data interface format bits bit symbol description 15 dc adc dc-?lter. a 1-bit value to enable the digital dc-?lter of the adc. if bit dc = 1 (default), then the dc-?ltering is active; if bit dc = 0, then there is no dc-?ltering. 14 pab polarity adc 2 control. a 1-bit value to control the adc 2 polarity. if bit pab = 1, then the polarity is inverted; if bit pab = 0 (default), then the polarity is non-inverted. 13 paa polarity adc 1 control. a 1-bit value to control the adc 1 polarity. if bit paa = 1, then the polarity is inverted; if bit paa = 0 (default), then the polarity is non-inverted. 12 mtb mute adc 2. a 1-bit value to enable the digital mute of adc 2. if bit mtb = 1, then adc 2 is soft muted; if bit mtb = 0 (default), then adc 2 is not muted. 11 mta mute adc 1. a 1-bit value to enable the digital mute of adc 1. if bit mta = 1, then adc 1 is soft muted; if bit mta = 0 (default), then adc 1 is not muted. 10 to 8 aif[2:0] adc output data interface format. a 3-bit value to select the used data format to the i 2 s-bus adc output interface. default 000. see table 27. 7dag dac gain switch. a 1-bit value to select the dac gain. if bit dag = 1, then the gain is 6 db; if bit dag = 0 (default), then the gain is 0 db. 6 fil filter selection. a 1-bit value to select the interpolation ?lter characteristics. if bit fil = 1, then slow roll-off; if bit fil = 0 (default), then sharp roll-off. 5dvd 192 khz sampling mode selection. a 1-bit value to select the oversampling rate of the noise shaper. the 64f s rate is used for 192 and 176.4 khz sampling frequencies. if 7bit dvd = 1, then 64f s rate is selected (192 khz sampling mode); if bit dvd = 0 (default), then 128f s rate is selected. 4 to 3 dis[1:0] data interface selection. a 2-bit value to select the data interface connection. default 00. see table 28. 2 to 0 dif[2:0] dac input data interface format. a 3-bit value to select the used data format to the i 2 s-bus dac input interface. default 000. see table 27. aif2 aif1 aif0 function dif2 dif1 dif0 000i 2 s-bus format (default) 0 0 1 lsb-justi?ed format, 16 bits 0 1 0 lsb-justi?ed format, 20 bits 0 1 1 lsb-justi?ed format, 24 bits 1 0 0 msb-justi?ed format 1 0 1 multichannel format, 20 bits 1 1 0 multichannel format, 24 bits (format 1) 1 1 1 multichannel format, 24 bits (format 2)
2002 nov 21 29 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H table 28 data interface selection bits 11.5 voice adc system settings table 29 voice adc system register (address 02h) table 30 description of the voice adc system register bits table 31 bck frequency of voice adc bits dis1 dis0 input to dac 0 0 datada1 to dac channel 1 and 2, datada2 to dac channel 3 and 4, and datada3 to dac channel 5 and 6 (default) 0 1 datada1 to dac channels 1 to 6 1 0 datada2 to dac channels 1 to 6 1 1 datada3 to dac channels 1 to 6 bit 15 14 13 12 11 10 9 8 symbol -------- reset default 00000000 bit76543210 symbol bck1 bck0 wsm vh1 vh0 pva mtv vif reset default 01101000 bit symbol description 15 to 8 - default 0000 0000 7 to 6 bck[1:0] bck frequency of voice adc. a 2-bit value to select the bck frequency of the voice adc in the wsv-out mode. default 01. see table 31. 5 wsm wsv mode selection. a 1-bit value to select the wsv mode of the voice adc. if bit wsm = 1 (default), then wsv-in mode; if bit wsm = 0, then wsv-out mode. 4 to 3 vh[1:0] voice adc high-pass ?lter setting. a 2-bit value to enable the high-pass ?lter of the voice adc. default 01. see table 32. 2pva polarity voice adc control. a 1-bit value to control the voice adc polarity. if bit pva = 1, then the polarity is inverted; if bit pva = 0 (default), then the polarity is non-inverted. 1 mtv mute voice adc. a 1-bit value to enable the digital mute of the voice adc. if bit mtv = 1, then the voice adc is soft muted; if bit mtv = 0 (default), then the voice adc is not muted. 0 vif voice adc interface format. a 1-bit value to select the data interface format of the voice adc. if bit vif = 1, then mono-channel format; if bit vif = 0 (default), then i 2 s-bus format. bck1 bck0 function 0 0 32f s 0 1 64f s (default) 1 0 128f s 1 1 256f s
2002 nov 21 30 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H table 32 voice adc high-pass ?lter setting bits 11.6 status output register (read only) table 33 status output register (address 0fh) table 34 description of status output register bits. vh1 vh0 function 0 0 high-pass ?lter off 01f c = 0.00008f s (default) 10f c = 0.0125f s 11f c = 0.025f s bit 15 14 13 12 11 10 9 8 symbol -------- bit76543210 symbol -- vs as1 as0 ds2 ds1 ds0 bit symbol description 15 to 6 - not used 5vs voice adc status. a 1-bit value to indicate the hard mute status of the voice adc. if bit vs = 1, then power-down is ready and the clock may be disabled; if bit vs = 0, then power-down is not ready and the clock should not be disabled. 4 as1 adc 2 status. a 1-bit value to indicate the hard mute status of adc 2. if bit as1 = 1, then power-down is ready and the clock may be disabled; if bit as1 = 0, then power-down is not ready and the clock should not be disabled. 3 as0 adc 1 status. a 1-bit value to indicate the hard mute status of adc 1. if bit as0 = 1, then power-down is ready and the clock may be disabled; if bit as0 = 0, then power-down is not ready and the clock should not be disabled. 2 ds2 dac channel 5 and 6 status. a 1-bit value to indicate the hard mute status of dac channel 5 and 6. if bit ds2 = 1, then power-down is ready and the clock may be disabled; if bit ds2 = 0, then power-down is not ready and the clock should not be disabled. 1 ds1 dac channel 3 and 4 status. a 1-bit value to indicate the hard mute status of dac channel 3 and 4. if bit ds1= 1, then power-down is ready and the clock may be disabled; if bit ds1 = 0, then power-down is not ready and the clock should not be disabled. 0 ds0 dac channel 1 and 2 status. a 1-bit value to indicate the hard mute status of dac channel 1 and 2. if bit ds0 = 1, then power-down is ready and the clock may be disabled; if bit ds0 = 0, then power-down is not ready and the clock should not be disabled.
2002 nov 21 31 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 11.7 dac channel selection table 35 dac channel select register (address 10h) table 36 description of dac channel select register bits table 37 dac mixer setting bits table 38 dac channel and mixing channel selection bits bit 15 14 13 12 11 10 9 8 symbol mix1 mix0 mc5 mc4 mc3 mc2 mc1 mc0 reset default 00000000 bit76543210 symbol sel1 sel0 cs5 cs4 cs3 cs2 cs1 cs0 reset default 00000000 bit symbol description 15 to 14 mix[1:0] dac mixer setting. a 2-bit value to enable the dac mixer. default 00. see table 37. 13 to 8 mc[5:0] dac mixing channel selection. a group of 6 enable bits to make dac mixing channels ready for receiving feature settings through register address 11h. only selected registers accept new settings. default 00 0000 (no channel ready). see table 38. 7 and 6 sel[1:0] feature selection. a 2-bit value to select the features to be set through register address 11h. when the feature settings are written, only selected feature settings are changed and non selected features are kept unchanged. default 00. see table 39. 5 to 0 cs[5:0] dac channel selection. a group of 6 enable bits to make dac channel ready for receiving feature settings through register address 11h. default 00 0000 (no channel ready). see table 38. mix1 mix0 function 0 0 no mixing (default) 0 1 no mixing 1 0 mixing adc 1 1 1 mixing adc 2 mc5 mc4 mc3 mc2 mc1 mc0 function cs5 cs4 cs3 cs2 cs1 cs0 000001 channel 1 selected :::::: 001010 channel 2 and channel 4 selected :::::: 111111 all channels selected
2002 nov 21 32 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H table 39 feature selection bits 11.8 dac features settings table 40 dac features register (addresses 11h) table 41 description of dac features register bits table 42 input channel selection bits sel1 sel0 function 0 0 all features (default) 0 1 volume 1 0 mute and quick mute 1 1 de-emphasis, polarity and input channel selection bit 15 14 13 12 11 10 9 8 symbol ics1 ics0 de2 de1 de0 pd mt qm reset default 00000000 bit76543210 symbol vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 reset default 00000000 bit symbol description 15 to 14 ics[1:0] input channel selection. a 2-bit value to select the input channels. as the controlled channels are paired off, this 2-bit value must be written to each odd channel register. default 00. see table 42. 13 to 11 de[2:0] de-emphasis setting. a 3-bit value to enable the digital de-emphasis ?lter. default 000. see table 43. 10 pd polarity dac control. a 1-bit value to control the dac polarity. if bit pd = 1, then the polarity is inverted; if bit pd = 0 (default), then the polarity is non-inverted. 9mt muting. a 1-bit value to enable the digital mute. all the dac outputs are muted at start-up. it is necessary to explicitly switch off for the audio output by means of bit mt. if bit mt = 1 (start-up), then muting; if bit mt = 0 (default), then no muting. 8qm quick mute. a 1-bit value to set the quick mute mode. if bit qm = 1 (start-up), then quick mute mode; if bit qm = 0 (default), then soft mute mode. 7 to 0 vc[7:0] interpolator volume control. an 8-bit value to program the volume attenuation of each channel. the range is from 0 to - 53 db in steps of 0.25 db, from - 53 to - 80 db in steps of 3 db and - db. default 0000 0000. see table 44. ics1 ics0 input to dac output 0 0 left channel input data to odd channel output; right channel input data to even channel output 0 1 left channel input data to odd and even channel outputs 1 0 right channel input data to odd and even channel outputs 1 1 left channel input data to even channel output; right channel input data to odd channel output
2002 nov 21 33 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H table 43 de-emphasis bits table 44 interpolator volume control bits de2 de1 de0 function 0 0 0 no de-emphasis (default) 0 0 1 de-emphasis of 32 khz 0 1 0 de-emphasis of 44.1 khz 0 1 1 de-emphasis of 48 khz 1 0 0 de-emphasis of 96 khz 1 0 1 not used 1 1 0 not used 1 1 1 not used vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 volume (db) 00000000 0 (default) 00000001 - 0.25 00000010 - 0.50 00000011 - 0.75 00000100 - 1.00 00000101 - 1.25 :::::::: : 11010100 - 53 11011000 - 56 11011100 - 59 11100000 - 62 11100100 - 65 11101000 - 68 11101100 - 71 11110000 - 74 11110100 - 77 11111000 - 80 11111100 - :::::::: : 11111111 -
2002 nov 21 34 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 11.9 dac channel 1 to 6 settings all the dac features which are written in register 11h are copied into the odd channel registers. table 45 dac channel 1, 3 and 5 registers (addresses 12h, 14h and 16h) all the dac features which are written in register 11h are copied into the even channel registers, except the bits ics[1:0]. table 46 dac channel 2, 4 and 6 registers (addresses 13h, 15h and 17h) 11.10 dac mixing channel settings all the dac features which are written in register 11h are copied into the odd mixing channel registers, except the bits de[2:0]. table 47 dac mixing channel 1, 3 and 5 registers (addresses 18h, 1ah and 1ch) all the dac features which are written in register 11h are copied into the even channel registers, except the bits ics[1:0] and de[2:0]. bit 15 14 13 12 11 10 9 8 symbol ics1 ics0 de2 de1 de0 pd mt qm reset default 00000000 bit76543210 symbol vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 reset default 00000000 bit 15 14 13 12 11 10 9 8 symbol -- de2 de1 de0 pd mt qm reset default 00000000 bit76543210 symbol vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 reset default 00000000 bit 15 14 13 12 11 10 9 8 symbol ics1 ics0 --- pd mt qm reset default 00000000 bit76543210 symbol vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 reset default 00000000
2002 nov 21 35 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H table 48 dac mixing channel 2, 4 and 6 registers (addresses 19h, 1bh and 1dh) 11.11 audio adc 1 and adc 2 input ampli?er gain settings table 49 audio adc input ampli?er gain register (address 20h) table 50 description of audio adc input ampli?er gain register bits table 51 audio adc input ampli?er gain bits bit 15 14 13 12 11 10 9 8 symbol ----- pd mt qm reset default 00000000 bit76543210 symbol vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 reset default 00000000 bit 15 14 13 12 11 10 9 8 symbol ---- ib3 ib2 ib1 ib0 reset default 00000000 bit76543210 symbol ---- ia3 ia2 ia1 ia0 reset default 00000000 bit symbol description 15 to 12 - default 0000 11 to 8 ib[3:0] audio adc 2 input ampli?er gain. a 4-bit value to program the input ampli?er gain in steps of 3 db (9 settings). default 0000. see table 51. 7to4 - default 0000 3 to 0 ia[3:0] audio adc 1 input ampli?er gain. a 4-bit value to program the input ampli?er gain in steps of 3 db (9 settings). default 0000. see table 51. ia3 ia2 ia1 ia0 gain (db) ib3 ib2 ib1 ib0 0000 0 (default) 0001 +3 0010 +6 0011 +9 0100 +12 0101 +15 0110 +18 0111 +21 1000 +24
2002 nov 21 36 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 11.12 voice adc gain settings table 52 voice adc input ampli?er gain register (address 21h) table 53 description of voice adc input ampli?er gain register bits table 54 voice adc input ampli?er gain bits 11.13 supplemental settings 1 table 55 supplemental settings 1 register (address 30h) bit 15 14 13 12 11 10 9 8 symbol -------- reset default -------- bit76543210 symbol --- iv4 iv3 iv2 iv1 iv0 reset default 00000000 bit symbol description 15 to 8 - not used 7to5 - default 000 4 to 0 iv[4:0] voice adc input ampli?er gain. a 5-bit value to program the voice ampli?er gain in steps of 1.5 db (21 settings). default 0 0000. see table 54. iv4 iv3 iv2 iv1 iv0 gain (db) 0 0 0 0 0 0 (default) 0 0 0 0 1 +1.5 00010 +3 0 0 0 1 1 +4.5 00100 +6 0 0 1 0 1 +7.5 ::::: : 1 0 0 1 1 +28.5 10100 +30 : : : : : not used 1 1 1 1 1 not used bit 15 14 13 12 11 10 9 8 symbol -------- reset default 00000000 bit76543210 symbol pdt ------- reset default 00000000
2002 nov 21 37 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H table 56 description of supplemental settings 1 register bits 11.14 supplemental settings 2 table 57 supplemental settings 2 register (address 31h) table 58 description of supplemental settings 2 register bits table 59 dac dither control bits bit symbol description 15 to 8 - default 0000 0000 7 pdt power down time. a 1-bit value to select the time of the sdac power-down sequence. if bit pdt = 1, then 1024/f s seconds; if bit pdt = 0 (default), then 512/f s seconds. 6to0 - default 000 0000 bit 15 14 13 12 11 10 9 8 symbol -------- reset default 00000000 bit76543210 symbol - dith2 dith1 dith0 -- vmtp pdlna reset default 00000000 bit symbol description 15 to 7 - default 0000 0000 0 6 to 4 dith[2:0] dac dither control. a 3-bit value to control the dithering of the sdac. default 000. see table 59. 3to2 - default 00 1 vmtp voice mute period control. a 1-bit value to select the voice adc mute period at power-up. if bit vmtp = 1, then mute for 1024 samples (1024/f s ); if bit vmtp = 0 (default), then mute for 2048 samples (2048/f s ). 0 pdlna power-down voice lna. a 1-bit value to power-down the voice adc lna. it should be noted that disabling the lna requires a recovery time defined by the external rc circuit. if bit pdnla = 1, then power-down; if bit pdnla = 0 (default), then power-on. dith2 dith1 dith0 function 0 0 0 dc dither (mid level); default 0 0 1 reserved 0 1 0 reserved 0 1 1 reserved 1 0 0 dc dither (low level) 1 0 1 dc plus ac dither (low level) 1 1 0 dc dither (high level) 1 1 1 dc plus ac dither (high level)
2002 nov 21 38 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 12 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. all supply connections must be made to the same power supply. 2. equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor. 3. equivalent to discharging a 200 pf capacitor via a 0.75 m h series inductor. 13 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. 14 quality specification in accordance with the general specification for integrated circuits (snw-fq-611d) . 15 thermal characteristics symbol parameter conditions min. max. unit v dd supply voltage note 1 - 4.0 v t xtal(max) maximum crystal temperature - 150 c t stg storage temperature - 65 +125 c t amb operating ambient temperature - 20 +85 c v esd electrostatic discharge voltage note 2 - 2000 +2000 v note 3 - 200 +200 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 85 k/w
2002 nov 21 39 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 16 dc characteristics v ddd =v dda(ad) =v dda(da) = 3.3 v; t amb =25 c; r l =22k w ; all voltages referenced to ground (pins v ss ); unless otherwise speci?ed. note 1. all supply connections must be made to the same power supply unit. symbol parameter conditions min. typ. max. unit supplies v dda(ad) adc analog supply voltage note 1 2.7 3.3 3.6 v v dda(da) dac analog supply voltage note 1 2.7 3.3 3.6 v v ddd digital supply voltage note 1 2.7 3.3 3.6 v i dda(ad) adc analog supply current f adc =48khz - 30 - ma f adc =96khz - 31 - ma i dda(da) dac analog supply current f dac =48khz - 20 - ma f dac =96khz - 32 - ma i ddd digital supply current f adc =f dac = 48 khz; f voice = 48 khz - 31 - ma f adc =f dac = 96 khz; f voice = 48 khz - 55 - ma i ddd(pd) digital supply current in power down-mode audio and voice adcs power-down - tbf - ma dac power-down - tbf - ma digital input pins (5 v tolerant ttl compatible) v ih high-level input voltage 2.0 -- v v il low-level input voltage -- 0.8 v ? i li ? input leakage current -- 1 m a c i input capacitance -- 10 pf digital output pins v oh high-level output voltage i oh = - 2 ma 0.85v ddd -- v v ol low-level output voltage i ol =2ma -- 0.4 v analog-to-digital converter v ref reference voltage on pin v ref with respect to v ssa(ad) 0.45v dda(ad) 0.5v dda(ad) 0.55v dda(ad) v v adcp positive reference voltage of adc - v dda(ad) - v v adcn negative reference voltage of adc 0.0 0.0 0.0 v r o output resistance on pin v ref - 5 - k w r i(adc) input resistance of audio adc - 10 - k w r i(vadc) input resistance of voice adc - 5 - k w digital-to-analog converter r l load resistance 4 -- k w r o output resistance - 1 - k w
2002 nov 21 40 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 17 ac characteristics v ddd =v dda(ad) =v dda(da) = 3.3 v; f i = 1 khz; t amb =25 c; r l =22k w ; sampling frequency f s = 48 khz; all voltages referenced to ground (pins v ss ); unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit audio analog-to-digital converter d 0 digital output level at 0 db setting; 900 mv input; notes 1 and 2 - 2.5 - 1.2 - 0.7 db at 3 db setting; 637 mv input; note 2 -- 1.2 - db at 6 db setting; 451 mv input; note 2 -- 1.2 - db at 9 db setting; 319 mv input; note 2 -- 1.2 - db at 12 db setting; 226 mv input; note 2 -- 1.2 - db at 15 db setting; 160 mv input; note 2 -- 1.2 - db at 18 db setting; 113 mv input; note 2 -- 1.2 - db at 21 db setting; 80 mv input; note 2 -- 1.2 - db at 24 db setting; 57 mv input; note 2 -- 1.2 - db d v i input voltage unbalance between channels - 0.1 - db
2002 nov 21 41 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H (thd + n)/s total harmonic distortion-plus-noise to signal ratio normal mode; at - 1 dbfs at 0 db setting -- 90 - 83 db at 3 db setting -- 90 - db at 6 db setting -- 90 - db at 9 db setting -- 90 - db at 12 db setting -- 90 - db at 15 db setting -- 89 - db at 18 db setting -- 87 - db at 21 db setting -- 85 - db at 24 db setting -- 83 - db normal mode; at - 20 dbfs at 0 db setting -- 75 - db at 3 db setting - tbf - db at 6 db setting - tbf - db at 9 db setting - tbf - db at 12 db setting - tbf - db at 15 db setting - tbf - db at 18 db setting - tbf - db at 21 db setting - tbf - db at 24 db setting - tbf - db normal mode; at - 60 dbfs; a-weighted at 0 db setting -- 40 - 34 db at 3 db setting -- 40 - db at 6 db setting -- 40 - db at 9 db setting -- 39 - db at 12 db setting -- 38 - db at 15 db setting -- 37 - db at 18 db setting -- 35 - db at 21 db setting -- 32 - db at 24 db setting -- 30 - db s/n signal-to-noise ratio code = 0; a-weighted 94 100 - db a cs channel separation - 100 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple = 30 mv (p-p) - tbf - db symbol parameter conditions min. typ. max. unit
2002 nov 21 42 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H notes 1. the input voltage can be up to 2 v (rms) when the current through the adc input pin is limited to approximately 1 ma by using a series resistor. 2. the input voltage to the adc scales proportionally with the power supply voltage. voice analog-to-digital converter v i(rms) input voltage (rms value) at 0 dbfs digital output; 2.2 k w source impedance - 50.0 - mv (thd + n)/s total harmonic distortion-plus-noise to signal ratio at - 1 dbfs -- 78 - db at - 20 dbfs -- 65 - db at - 40 dbfs; a-weighted -- 47 - db s/n signal-to-noise ratio code = 0; a-weighted - 87 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple = 30 mv (p-p) - tbf - db digital-to-analog converter d ifferential mode v o(rms) output voltage (rms value) at 0 dbfs digital input 1.9 2.0 2.1 v d v o output voltage unbalance between channels - <0.1 - db (thd + n)/s total harmonic distortion-plus-noise to signal ratio at 0 dbfs -- 100 - 93 db at - 20 dbfs -- 90 - db at - 60 dbfs; a-weighted -- 50 - 45 db s/n signal-to-noise ratio code = 0; a-weighted 107 114 - db a cs channel separation - 117 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple = 30 mv (p-p) - tbf - db s ingle - ended mode v o(rms) output voltage (rms value) at 0 dbfs digital input - 1.0 - v d v o output voltage unbalance between channels - <0.1 - db (thd + n)/s total harmonic distortion-plus-noise to signal ratio at 0 dbfs -- 90 - db at - 20 dbfs -- 85 - db at - 60 dbfs; a-weighted -- 45 - db s/n signal-to-noise ratio code = 0; a-weighted - 110 - db a cs channel separation - 114 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple = 30 mv (p-p) - tbf - db symbol parameter conditions min. typ. max. unit
2002 nov 21 43 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 18 timing v ddd =v dda(ad) =v dda(ad) = 2.7 to 3.6 v; t amb = - 20 to +85 c; typical timing speci?ed at sampling frequency f s = 48 khz; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit system clock (see fig.16) t sys system clock cycle time note 1 f sys = 256f s 35 81 780 ns f sys = 384f s 23 54 520 ns f sys = 512f s 17 41 390 ns f sys = 768f s 17 27 260 ns t cwl system clock low time f sys < 19.2 mhz 0.3t sys - 0.7t sys ns f sys 3 19.2 mhz 0.4t sys - 0.6t sys ns t cwh system clock high time f sys < 19.2 mhz 0.3t sys - 0.7t sys ns f sys 3 19.2 mhz 0.4t sys - 0.6t sys ns i 2 s-bus interface s erial data of audio adc and dac (see fig.17) f bck audio bit clock frequency note 2 -- 12.8 mhz t cy(bck) bck cycle time -- 78 ns t bckh bit clock high time 30 -- ns t bckl bit clock low time 30 -- ns t r rise time -- 20 ns t f fall time -- 20 ns t su(ws) word select set-up time 10 -- ns t h(ws) word select hold time 10 -- ns t su(datai) data input set-up time 10 -- ns t h(datai) data input hold time 10 -- ns t h(datao) data output hold time 0 -- ns t d(datao-bck) data output to bit clock delay -- 30 ns t d(datao-ws) data output to word select delay -- 30 ns s erial data of voice adc f bckv voice bit clock frequency note 2 -- 6.4 mhz t cy(bckv) bckv cycle time -- 156 ns t bckvh bit clock high time 50 -- ns t bckvl bit clock low time 50 -- ns t r rise time -- 20 ns t f fall time -- 20 ns t su(wsv) word select set-up time 10 -- ns t h(wsv) word select hold time 10 -- ns t h(datav) data output hold time 0 -- ns t d(datav-bckv) data output to bit clock delay -- 30 ns t d(datav-wsv) data output to word select delay -- 30 ns
2002 nov 21 44 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H t d(wsv-bckv) word select to bit clock delay wsv-out mode - 30 - +30 ns l3-bus interface (see figs 18 and 19) l3clock timing f cy(clk)l3 l3clk frequency -- 2000 khz t cy(clk)l3 l3clock cycle time 500 -- ns t clk(l3)h l3clock high time 250 -- ns t clk(l3)l l3clock low time 250 -- ns l3mode timing t su(l3)a l3mode set-up time in address mode 190 -- ns t h(l3)a l3mode hold time in address mode 190 -- ns t su(l3)d l3mode set-up time in data transfer mode 190 -- ns t h(l3)d l3mode hold time in data transfer mode 190 -- ns t stp(l3) l3mode stop time in data transfer mode 190 -- ns l3data timing t su(l3)da l3data set-up time in data transfer and address mode 190 -- ns t h(l3)da l3data hold time in data transfer and address mode 30 -- ns t d(l3)r l3data delay time for read data 0 - 50 ns t dis(l3)r l3data disable time for read data 0 - 50 ns i 2 c-bus interface timing (see fig.20) scl timing f scl scl clock frequency 0 - 400 khz t low scl low time 1.3 --m s t high scl high time 0.6 --m s t r rise time sda and scl note 3 20 + 0.1c b - 300 ns t f fall time sda and scl note 3 20 + 0.1c b - 300 ns sda timing t buf bus free time between stop and start condition 1.3 --m s t su;sta set-up time repeated start 0.6 --m s t hd;sta hold time start condition 0.6 --m s t su;dat data set-up time 100 -- ns t hd;dat data hold time 0 --m s t su;sto set-up time stop condition 0.6 --m s t sp pulse width of spikes note 4 0 - 50 ns c b capacitive load for each bus line -- 400 pf symbol parameter conditions min. typ. max. unit
2002 nov 21 45 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H notes 1. the system clock should not exceed 58 mhz in any mode. 2. the bit clock frequency should not exceed 256 times the corresponding sampling frequency. 3. c b is the total capacitance for each bus line. 4. to be suppressed by the input filter. handbook, full pagewidth mgr984 t sys t cwh t cwl fig.16 system clock timing. handbook, full pagewidth mgs756 ws bck datao datai t f t r t h(ws) t su(ws) t bckh t bckl t cy(bck) t h(datao) t su(datai) t h(datai) t d(datao-bck) t d(datao-ws) fig.17 i 2 s-bus serial interface timing.
2002 nov 21 46 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H handbook, full pagewidth t h(l3)a t h(l3)da t su(l3)da t cy(clk)(l3) bit 0 l3mode l3clock l3data bit 7 mgl723 t clk(l3)h t clk(l3)l t su(l3)a t su(l3)a t h(l3)a fig.18 l3-bus address mode timing. handbook, full pagewidth t stp(l3) t su(l3)d t h(l3)da t su(l3)da t h(l3)d t cy(clk)l3 bit 0 l3mode l3clock l3data read l3data write bit 7 mgu015 t clk(l3)h t clk(l3)l t d(l3)r t dis(l3)r fig.19 l3-bus data transfer (write and read) mode timing.
2002 nov 21 47 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H handbook, full pagewidth msc610 s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta fig.20 i 2 c-bus timing
2002 nov 21 48 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 19 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 95-02-04 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
2002 nov 21 49 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 20 soldering 20.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 20.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 20.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 20.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2002 nov 21 50 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 20.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2002 nov 21 51 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 21 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 22 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 23 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 nov 21 52 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H 24 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2002 nov 21 53 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H notes
2002 nov 21 54 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H notes
2002 nov 21 55 philips semiconductors preliminary speci?cation multichannel audio coder-decoder UDA1338H notes
? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753503/2/pp 56 date of release: 2002 nov 21 document order number: 9397 750 10089

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