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10-/12-/14-bit, 1200 msps dacs ad9734/ad9735/ad9736 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features pin-compatible family excellent dynamic performance ad9736: sfdr = 82 dbc at f out = 30 mhz ad9736: sfdr = 69 dbc at f out = 130 mhz ad9736: imd = 87 dbc at f out = 30 mhz ad9736: imd = 82 dbc at f out = 130 mhz lvds data interface with on-chip 100 terminations built-in self test lvds sampling integrity lvds-to-dac data transfer integrity low power: 380 mw (i fs = 20 ma; f out = 330 mhz) 1.8/3.3 v dual-supply operation adjustable analog output 8.66 ma to 31.66 ma (r l = 25 to 50 ) on-chip 1.2 v reference 160-lead chip scale ball grid array (csp_bga) package applications broadband communications systems cellular infrastructure (digital predistortion) point-to-point wireless cmts/vod instrumentation, automatic test equipment radar, avionics general description the ad9736, ad9735, and ad9734 are high performance, high frequency dacs that provide sample rates of up to 1200 msps, permitting multicarrier generation up to their nyquist frequency. the ad9736 is the 14-bit member of the family, while the ad9735 and the ad9734 are the 12-bit and 10-bit members, respectively. they include a serial peripheral interface (spi) port that provides for programming of many internal parameters and enables readback of status registers. a reduced-specification lvds interface is utilized to achieve the high sample rate. the output current can be programmed over a range of 8.66 ma to 31.66 ma. the ad973x family is manufactured on a 0.18 m cmos process and operates from 1.8 v and 3.3 v supplies for a total power consumption of 380 mw in bypass mode. it is supplied in a 160-lead chip scale ball grid array for reduced package parasitics. functional block diagram lvds receiver synchronizer band gap dataclk_in+ dataclk_in? db[13:0]? db[13:0]+ spi 14-, 12-, 10-bit dac core iouta ioutb sdo sdio sclk csb lvds driver controller reference current dacclk? irq dacclk+ i120 vref reset dataclk_out+ dataclk_out? s1 s2 s3 c1 c2 c3 c2 c1s1 s3 s2 c3 04862-001 2 clock distribution figure 1. product highlights 1. low noise and intermodulation distortion (imd) features enable high quality synthesis of wideband signals at inter- mediate frequencies up to 600 mhz. 2. double data rate (ddr) lvds data receivers support the maximum conversion rate of 1200 msps. 3. direct pin programmability of basic functions or spi port access offers complete control of all ad973x family functions. 4. manufactured on a cmos process, the ad973x family uses a proprietary switching technique that enhances dynamic performance. 5. the current output(s) of the ad9736 family are easily con- figured for single-ended or differential circuit topologies.
ad9734/ad9735/ad9736 rev. a | page 2 of 72 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 3 specifications..................................................................................... 4 dc specifications ......................................................................... 4 digital specifications ................................................................... 6 ac specifications.......................................................................... 8 absolute maximum ratings............................................................ 9 thermal resistance ...................................................................... 9 esd caution.................................................................................. 9 pin configurations and function descriptions ......................... 10 location of supply and control pins....................................... 16 terminology .................................................................................... 17 typical performance characteristics ........................................... 18 ad9736 static linearity, 10 ma full scale ............................. 18 ad9736 static linearity, 20 ma full scale ............................. 19 ad9736 static linearity, 30 ma full scale ............................. 20 ad9735 static linearity, 10 ma, 20 ma, 30 ma full scale...................................................................................... 21 ad9734 static linearity, 10 ma, 20 ma, 30 ma full scale...................................................................................... 22 ad9736 power consumption, 20 ma full scale ....................... 23 ad9736 dynamic performance, 20 ma full scale................ 24 ad9735, ad9734 dynamic performance, 20 ma full scale...................................................................................... 27 ad973x wcdma aclr, 20 ma full scale .......................... 28 spi register map............................................................................. 29 spi register details ........................................................................ 30 mode register (reg. 0) .............................................................. 30 interrupt request register (irq) (reg. 1) .............................. 30 full scale current (fsc) registers (reg. 2, reg. 3)............... 31 lvds controller (lvds_cnt) registers (reg. 4, reg. 5, reg. 6) ............................................................... 31 sync controller (sync_cnt) registers (reg. 7, reg. 8)............................................................................ 32 cross controller (cros_cnt) registers (reg. 10, reg. 11)........................................................................ 32 analog control (ana_cnt) registers (reg. 14, reg. 15)........................................................................ 33 built-in self test control (bist_cnt) registers (reg. 17, reg. 18, reg. 19, reg. 20, reg. 21)........................... 33 controller clock predivider (cclk_div) reading register (reg. 22) ....................................................................... 34 theory of operation ...................................................................... 35 serial peripheral interface ............................................................. 36 general operation of the serial interface............................... 36 short instruction mode (8-bit instruction) ........................... 36 long instruction mode (16-bit instruction).......................... 36 serial interface port pin descriptions ..................................... 36 sclkserial clock............................................................... 36 csbchip select................................................................... 37 sdioserial data i/o.......................................................... 37 sdoserial data out .......................................................... 37 msb/lsb transfers .................................................................... 37 notes on serial port operation ................................................ 37 pin mode operation .................................................................. 38 reset operation....................................................................... 38 programming sequence ............................................................ 38 interpolation filter..................................................................... 39 data interface controllers......................................................... 39 lvds sample logic.................................................................... 40 lvds sample logic calibration............................................... 40 operating the lvds controller in manual mode via the spi port ........................................................................................ 41
ad9734/ad9735/ad9736 rev. a | page 3 of 72 operating the lvds controller in surveillance and auto mode ................................................................................... 41 sync logic and controller........................................................... 42 sync logic and controller operation.................................... 42 operation in manual mode....................................................... 42 operation in surveillance and auto modes ............................ 42 fifo bypass................................................................................. 42 digital built-in self test (bist) .................................................... 44 overview ...................................................................................... 44 ad973x bist procedure............................................................ 45 ad973x expected bist signatures .......................................... 45 generating expected signatures ............................................... 46 cross controller registers ............................................................. 47 analog control registers ............................................................... 48 band gap temperature characteristic trim bits ................... 48 mirror roll-off frequency control ......................................... 48 headroom bits............................................................................. 48 voltage reference........................................................................ 48 applications information............................................................... 50 driving the dacclk input ...................................................... 50 dac output distortion sources................................................... 51 dc-coupled dac output............................................................. 52 dac data sources .......................................................................... 53 input data timing .......................................................................... 54 synchronization timing................................................................. 55 power supply sequencing .............................................................. 56 ad973 x evaluation board schematics ........................................ 57 ad973 x evaluation board pcb layout....................................... 62 outline dimensions........................................................................ 69 ordering guide ........................................................................... 69 revision history 9/06rev. 0 to rev. a updated format.................................................................. universal changes to table 1 ............................................................................5 changes to table 2 ............................................................................6 changes to table 3 ............................................................................8 inserted table 5..................................................................................9 replaced pin configuration and function descriptions section ..............................................................................................10 changes to figure 27 to figure 38 ................................................21 changes to figure 40 ......................................................................23 changes to table 9 ..........................................................................29 changes to figure 103 ....................................................................56 changes to figure 105 ....................................................................58 changes to figure 107 ....................................................................60 changes to figure 108 ....................................................................61 changes to figure 115 ....................................................................68 updated outline dimensions........................................................69 changes to ordering guide...........................................................69 4/05revision 0: initial version
ad9734/ad9735/ad9736 rev. a | page 4 of 72 specifications dc specifications avdd33 = dvdd33 = 3.3 v, cvdd18 = dvdd18 = 1.8 v, maximum sample rate, i fs = 20 ma, 1 mode, 25 , 1% balanced load, unless otherwise noted. table 1. ad9736 ad9735 ad9734 parameter min typ max min typ max min typ max unit resolution 14 12 10 bits accuracy integral nonlinearity (inl) ?5.6 1.0 +5.6 ?1.5 0.50 +1.5 ?0.5 0.12 +0.5 lsb differential nonlinearity (dnl) ?2.1 0.6 +2.1 ?0.5 0.25 +0.5 ?0.1 0.06 +0.1 lsb analog outputs offset error ?0.01 0.005 +0.01 ?0.01 0.005 +0.01 ?0.01 0.005 +0.01 % fsr gain error (with internal reference) 1.0 1.0 1.0 % fsr gain error (without internal reference) 1.0 1.0 1.0 % fsr full-scale output current 8.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 ma output compliance range ?1.0 +1.0 ?1.0 1.0 ?1.0 +1.0 v output resistance 10 10 10 m output capacitance 1 1 1 pf temperature drift offset 0 0 0 ppm/c gain 80 80 80 ppm/c reference voltage 1 40 40 40 ppm/c reference internal reference voltage 1 1.14 1.2 1.26 1.14 1.2 1.26 1.14 1.2 1.26 v output resistance 2 5 5 5 k analog supply voltages avdd33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 v cvdd18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 v digital supply voltages dvdd33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 v dvdd18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 v supply currents 1 mode, 1.2 gsps i avdd33 25 25 25 ma i cvdd18 47 47 47 ma i dvdd33 10 10 10 ma i dvdd18 122 122 122 ma fir bypass (1) mode 380 380 380 mw 2 mode, 1.2 gsps i avdd33 25 25 25 ma i cvdd18 47 47 47 ma i dvdd33 10 10 10 ma i dvdd18 234 234 234 ma fir 2 interpolation filter enabled 550 550 550 mw
ad9734/ad9735/ad9736 rev. a | page 5 of 72 ad9736 ad9735 ad9734 parameter min typ max min typ max min typ max unit static, no clock i avdd33 25 25 25 ma i cvdd18 8 8 8 ma i dvdd33 10 10 10 ma i dvdd18 2 2 2 ma fir bypass (1) mode 133 133 133 mw sleep mode, no clock i avdd33 2.5 3.15 2.5 3.15 2.5 3.15 ma fir bypass (1) mode 59 65 59 65 59 65 mw power-down mode 3 i avdd33 0.01 0.13 0.01 0.13 0.01 0.13 ma i cvdd18 0.02 0.12 0.02 0.12 0.02 0.12 ma i dvdd33 0.01 0.12 0.01 0.12 0.01 0.12 ma i dvdd18 0.01 0.11 0.01 0.11 0.01 0.11 ma fir bypass (1) mode 0.12 1.24 0.12 1.24 0.12 1.24 mw 1 default band gap adjustment (reg. 0x0e <2:0> = 0x0). 2 use an external amplifier to drive any external load. 3 typical wake-up time is 8 s with recommended 1 nf capacitor on vref pin.
ad9734/ad9735/ad9736 rev. a | page 6 of 72 digital specifications avdd33 = dvdd33 = 3.3 v, cvdd18 = dvdd18 = 1.8 v, maximum sample rate, i fs = 20 ma, 1 mode, 25 , 1% balanced load, unless otherwise noted. lvds drivers and receivers are compli ant to the ieee-1596 reduced range link, unless otherwise noted. table 2. parameter min typ max unit lvds data input (db[13:0]+, db[13:0]?) db+ = v ia , db? = v ib input voltage range, v ia or v ib 825 1575 mv input differential threshold, v idth ?100 +100 mv input differential hysteresis, v idthh ? v idthl 20 mv receiver differential input impedance, r in 80 120 lvds input rate 1200 msps lvds minimum data valid period (t mde ) 344 ps lvds clock input (dataclk_in+, dataclk_in?) dataclk_in+ = v ia , dataclk_in? = v ib input voltage range, v ia or v ib 825 1575 mv input differential threshold, 1 v idth ?100 +100 mv input differential hysteresis, v idthh ? v idthl 20 mv receiver differential input impedance, r in 80 120 maximum clock rate 600 mhz lvds clock output (dataclk_out+, dataclk_ out?) dataclk_out+ = v oa , dataclk_out? = v ob 100 termination output voltage high, v oa or v ob 1375 mv output voltage low, v oa or v ob 1025 mv output differential voltage, |v od | 150 200 250 mv output offset voltage, v os 1150 1250 mv output impedance, single-ended, r o 80 100 120 r o mismatch between a and b, r o 10 % change in |v od | between 0 and 1, | v od | 25 mv change in v os between 0 and 1, v os 25 mv output currentdriver shorted to ground, i sa , i sb 20 ma output currentdrivers shorted together, i sab 4 ma power-off output leakage, |i xa |, |i xb | 10 ma maximum clock rate 600 mhz dac clock input (clk+, clk?) input voltage range, clk? or clk+ 0 800 differential peak-to-peak voltage 400 800 1600 mv common-mode voltage 300 400 500 mv maximum clock rate 1200 mhz serial peripheral interface maximum clock rate (f sclk , 1/t sclk ) 20 mhz minimum pulse width high, t pwh 20 ns minimum pulse width low, t pwl 20 ns minimum sdio and csb to sclk setup, t ds 10 ns minimum sclk to sdio hold, t dh 5 ns maximum sclk to valid sdio and sdo, t dv 20 ns minimum sclk to invalid sdio and sdo, t dnv 5 ns
ad9734/ad9735/ad9736 rev. a | page 7 of 72 parameter min typ max unit input (sdi, sdio, sclk, csb) voltage in high, v ih 2.0 3.3 v voltage in low, v il 0 0.8 v current in high, i ih ?10 +10 a current in low, i il ?10 +10 a sdio output voltage out high, v oh 2.4 3.6 v voltage out low, v ol 0 0.4 v current out high, i oh 4 ma current out low, i ol 4 ma 1 refer to the input data timing section for recommended lvds differential drive levels.
ad9734/ad9735/ad9736 rev. a | page 8 of 72 ac specifications avdd33 = dvdd33 = 3.3 v, cvdd18 = dvdd18 = 1.8 v, maximum sample rate, i fs = 20 ma, 1 mode, 25 , 1% balanced load, unless otherwise noted. table 3. ad9736 ad9735 ad9734 parameter min typ max min typ max min typ max unit dynamic performance maximum update rate 1200 1200 1200 msps spurious-free dynamic range (sfdr) f dac = 800 msps f out = 20 mhz 75 75 75 dbc f dac = 1200 msps f out = 50 mhz 80 76 76 dbc f out = 100 mhz 77 74 71 dbc f out = 316 mhz 63 63 60 dbc f out = 550 mhz 55 54 53 dbc two-tone intermodulation distortion (imd) f dac = 1200 msps f out2 = f out + 1.25 mhz f out = 40 mhz 88 84 83 dbc f out = 50 mhz 85 84 83 dbc f out = 100 mhz 84 81 79 dbc f out = 316 mhz 70.5 67 66 dbc f out = 550 mhz 65 60 60 dbc noise spectral density (nsd) single tone f dac = 1200 msps f out = 50 mhz ?165 ? 162 ?154 dbm/hz f out = 100 mhz ?164 ?161 ?154 dbm/hz f out = 241mhz ?158.5 ?160.5 ?159.5 ?155 dbm/hz f out = 316 mhz ?158 ?157 ?152 dbm/hz f out = 550 mhz ?155 ?155 ?149 dbm/hz eight-tone f dac = 1200 msps, 500 khz tone spacing f out = 50 mhz ?166.5 ?163 ?154 dbm/hz f out = 100 mhz ?166 ?163 ?152 dbm/hz f out = 241mhz ?163.3 ?165 ?161.5 ?150.5 dbm/hz f out = 316 mhz ?164 ?162 ?151 dbm/hz f out = 550 mhz ?162 ?160 ?150 dbm/hz
ad9734/ad9735/ad9736 rev. a | page 9 of 72 absolute maximum ratings table 4. parameter with respect to min max avdd33 avss ?0.3 v +3.6 v dvdd33 dvss ?0.3 v +3.6 v dvdd18 dvss ?0.3 v +1.98 v cvdd18 cvss ?0.3 v +1.98 v avss dvss ?0.3 v +0.3 v avss cvss ?0.3 v +0.3 v dvss cvss ?0.3 v +0.3 v clk+, clk? cvss ?0.3 v cvdd18 + 0.18 v pin_mode dvss ?0.3 v dvdd33 + 0.3 v dataclk_in, dataclk_out dvss ?0.3 v dvdd33 + 0.3 v lvds data inputs dvss ?0.3 v dvdd33 + 0.3 v iouta, ioutb avss ?1.0 v avdd33 + 0.3 v i120, vref, iptat avss ?0.3 v avdd33 + 0.3 v irq, csb, sclk, sdo, sdio, reset dvss ?0.3 v dvdd33 + 0.3 v junction temperature 150c storage temperature ?65c +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 5. thermal resistance package type ja 1 unit 160-lead ball, csp_bga 31.2 c/w 1 ja measurement in still air. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. note that this device in its current form does not meet analog devices standard requirements for esd as measured against the c harged device model (cdm). as such, special care should be used when handling this product, especially in a manufacturing environment. analog devices will provide a more esd-hardy product in the near future at which time this warning will be removed from this data shee t.
ad9734/ad9735/ad9736 rev. a | page 10 of 72 pin configurations a nd function descriptions a b c d e f dacclk? dacclk+ g h j k l m db0 (lsb) n p 14 13 12 11 10 8 7 6 3 2 19 5 4 04862-005 db1 db10 db11 db12 db13 (msb) db9 db8 db7 db6 dataclk_in dataclk_out db5 db4 db3 db2 figure 2. ad9736 digital lvds input, clock i/o (top view) table 6. ad9736 pin function descriptions pin no. mnemonic description a1, a2, a3, b1, b2, b3, c1, c2, c3, d2, d3 cvdd18 1.8 v clock supply. a4, a5, a6, a9, a10, a11, b4, b5, b6, b9, b10, b11, c4, c5, c6, c9, c10, c11, d4, d5, d6, d9, d10, d11 avss analog supply ground. a7, b7, c7, d7 ioutb dac negative output. 10 ma to 30 ma full-scale output current. a8, b8, c8, d8 iouta dac positive output. 10 ma to 30 ma full-scale output current. a12, a13, b12, b13, c12, c13, d12, d13 avdd33 3.3 v analog supply. a14 dnc do not connect. b14 i120 nominal 1.2 v reference. tie to analog ground via 10 k resistor to generate a 120 a reference current. c14 vref band gap voltage reference i/o. tie to analog ground via 1 nf capacitor; output impedance is approximately 5 k. d1, e2, e3, e4, f2, f3, f4, g1, g2, g3, g4 cvss clock supply ground. d14 iptat factory test pin. output current, proportional to absolute temperature, is approximately 10 a at 25c with a slope of approximately 20 na/c. e1, f1 dacclk?/dacclk+ negative/positive dac clock input (dacclk). e11, e12, f11, f12, g11, g12 avss analog supply ground shield. tie to avss at the dac. e13 irq/unsigned if pin_mode = 0, irq: active low open-drain interrupt request output, pull up to dvdd33 with 10 k resistor. if pin_mode = 1, unsigned: digital input pin where 0 = twos complement input data format, 1 = unsigned. e14 reset/pd if pin_mode = 0, reset: 1 resets the ad9736. if pin_mode = 1, pd: 1 puts the ad9736 in the power-down state. f13 csb/2 see the serial peripheral interface section and the pin mode operation section for pin description. f14 sdio/fifo see the pin mode operation section for pin description. g13 sclk/fsc0 see the pin mode operation section for pin description. g14 sdo/fsc1 see the pin mode operation section for pin description. h1, h2, h3, h4, h11, h12, h13, h14, j1, j2, j3, j4, j11, j12, j13, j14 dvdd18 1.8 v digital supply.
ad9734/ad9735/ad9736 rev. a | page 11 of 72 pin no. mnemonic description k1, k2, k3, k4, k11, k12, l2, l3, l4, l5, l6, l9, l10, l11, l12, m3, m4, m5, m6, m9, m10, m11, m12 dvss digital supply ground. k13, k14 db<13>?/db<13>+ negative/positive data input bit 13 (msb). conforms to ieee-1596 reduced range link. l1 pin_mode 0 = spi mode. spi is enabled. 1 = pin mode. spi is disabled; direct pin control. l7, l8, m7, m8, n7, n8, p7, p8 dvdd33 3.3 v digital supply. l13, l14 db<12>?/db<12>+ negative/positive data input bit 12. conforms to ieee-1596 reduced range link. m2, m1 db<0>?/db<0>+ negative/positive data input bit 0 (lsb). conforms to ieee-1596 reduced range link. m13, m14 db<11>?/db<11>+ negative/positive data input bit 11. conforms to ieee-1596 reduced range link. n1, p1 db<1>?/db<1>+ negative/positive data input bit 1. conforms to ieee-1596 reduced range link. n2, p2 db<2>?/db<2>+ negative/positive data input bit 2. conforms to ieee-1596 reduced range link. n3, p3 db<3>?/db<3>+ negative/positive data input bit 3. conforms to ieee-1596 reduced range link. n4, p4 db<4>?/db<4>+ negative/positive data input bit 4. conforms to ieee-1596 reduced range link. n5, p5 db<5>?/db<5>+ negative/positive data input bit 5. conforms to ieee-1596 reduced range link. n6, p6 dataclk_out?/ dataclk_out+ negative/positive data output clock. conforms to ieee-1596 reduced range link. n9, p9 dataclk_in?/ dataclk_in+ negative/positive data input clock. conforms to ieee-1596 reduced range link. n10, p10 db<6>?/db<6>+ negative/positive data input bit 6. conforms to ieee-1596 reduced range link. n11, p11 db<7>?/db<7>+ negative/positive data input bit 7. conforms to ieee-1596 reduced range link. n12, p12 db<8>?/db<8>+ negative/positive data input bit 8. conforms to ieee-1596 reduced range link. n13, p13 db<9>?/db<9>+ negative/positive data input bit 9. conforms to ieee-1596 reduced range link. n14, p14 db<10>?/db<10>+ negative/positive data input bit 10. conforms to ieee-1596 reduced range link.
ad9734/ad9735/ad9736 rev. a | page 12 of 72 04862-115 a b c d e f dacclk? dacclk+ g h j k l m nc n p 14 13 12 11 10 8 7 6 3 2 19 5 4 nc db8 db9 db10 db11 (msb) db7 db6 db5 db4 dataclk_in db3 dataclk_out db2 db1 db0 (lsb) figure 3. ad9735 digital lvds input, clock i/o (top view) table 7. ad9735 pin function descriptions pin no. mnemonic description a1, a2, a3, b1, b2, b3, c1, c2, c3, d2, d3 cvdd18 1.8 v clock supply. a4, a5, a6, a9, a10, a11, b4, b5, b6, b9, b10, b11, c4, c5, c6, c9, c10, c11, d4, d5, d6, d9, d10, d11 avss analog supply ground. a7, b7, c7, d7 ioutb dac negative output. 10 ma to 30 ma full-scale output current. a8, b8, c8, d8 iouta dac positive output. 10 ma to 30 ma full-scale output current. a12, a13, b12, b13, c12, c13, d12, d13 avdd33 3.3 v analog supply. a14 dnc do not connect. b14 i120 nominal 1.2 v reference. tie to analog ground via 10 k resistor to generate a 120 a reference current. c14 vref band gap voltage reference i/o. tie to analog ground via 1 nf capacitor; output impedance approximately 5 k. d1, e2, e3, e4, f2, f3, f4, g1, g2, g3, g4 cvss clock supply ground. d14 iptat factory test pin; output current, proportional to absolute temperature, is approximately 10 a at 25c with a slope of approximately 20 na/c. e1, f1 dacclk?/dacclk+ negative/positive dac clock input (dacclk). e11, e12, f11, f12, g11, g12 avss analog supply ground shield. tie to avss at the dac. e13 irq/unsigned if pin_mode = 0, irq: active low open-drain interrupt request output, pull up to dvdd33 with 10 k resistor. if pin_mode = 1, unsigned: digital input pin where 0 = twos complement input data format, 1 = unsigned. e14 reset/pd if pin_mode = 0, reset: 1 resets the ad9735. if pin_mode = 1, pd: 1 puts the ad9735 in the power-down state. f13 csb/2 see the serial peripheral interface section and the pin mode operation section for pin description. f14 sdio/fifo see the pin mode operation section for pin description. g13 sclk/fsc0 see the pin mode operation section for pin description. g14 sdo/fsc1 see the pin mode operation section for pin description. h1, h2, h3, h4, h11, h12, h13, h14, j1, j2, j3, j4, j11, j12, j13, j14 dvdd18 1.8 v digital supply. k1, k2, k3, k4, k11, k12, l2, l3, l4, l5, l6, l9, l10, l11, l12, m3, m4, m5, m6, m9, m10, m11, m12 dvss digital supply ground.
ad9734/ad9735/ad9736 rev. a | page 13 of 72 pin no. mnemonic description k13, k14 db<11>?/db<11>+ negative/positive data input bit 11 (msb). conforms to ieee-1596 reduced range link. l1 pin_mode 0 = spi mode. spi is enabled. 1 = pin mode. spi disabled; direct pin control. l7, l8, m7, m8, n7, n8, p7, p8 dvdd33 3.3 v digital supply. l13, l14 db<10>?/db<10>+ negative/positive data input bit 10. conforms to ieee-1596 reduced range link. m1, m2 nc no connect. m13, m14 db<9>?/db<9>+ negative/positive data input bit 9. conforms to ieee-1596 reduced range link. n1, p1 nc no connect. n2, p2 db<0>?/db<0>+ negative/positive data input bit 0 (lsb). conforms to ieee-1596 reduced range link. n3, p3 db<1>?/db<1>+ negative/positive data input bit 1. conforms to ieee-1596 reduced range link. n4, p4 db<2>?/db<2>+ negative/positive data input bit 2. conforms to ieee-1596 reduced range link. n5, p5 db<3>?/db<3>+ negative/positive data input bit 3. conforms to ieee-1596 reduced range link. n6, p6 dataclk_out?/ dataclk_out+ negative/positive data output clock. conforms to ieee-1596 reduced range link. n9, p9 dataclk_in?/ dataclk_in+ negative/positive data input clock. conforms to ieee-1596 reduced range link. n10, p10 db<4>?/db<4>+ negative/positive data input bit 4. conforms to ieee-1596 reduced range link. n11, p11 db<5>?/db<5>+ negative/positive data input bit 5. conforms to ieee-1596 reduced range link. n12, p12 db<6>?/db<6>+ negative/positive data input bit 6. conforms to ieee-1596 reduced range link. n13, p13 db<7>?/db<7>+ negative/positive data input bit 7. conforms to ieee-1596 reduced range link. n14, p14 db<8>?/db<8>+ negative/positive data input bit 8. conforms to ieee-1596 reduced range link.
ad9734/ad9735/ad9736 rev. a | page 14 of 72 04862-114 a b c d e f dacclk? dacclk + g h j k l m nc n p 14 13 12 11 10 8 7 6 3 2 19 5 4 nc db6 db7 db8 db9 (msb) db5 db4 db3 db2 db1 dataclk_out dataclk_in db0 (lsb) nc nc figure 4. ad9734 digital lvds input, clock i/o (top view) table 8. ad9734 pin function descriptions pin no. mnemonic description a1, a2, a3, b1, b2, b3, c1, c2, c3, d2, d3 cvdd18 1.8 v clock supply. a4, a5, a6, a9, a10, a11, b4, b5, b6, b9, b10, b11, c4, c5, c6, c9, c10, c11, d4, d5, d6, d9, d10, d11 avss analog supply ground. a7, b7, c7, d7 ioutb dac negative output. 10 ma to 30 ma full-scale output current. a8, b8, c8, d8 iouta dac positive output. 10 ma to 30 ma full-scale output current. a12, a13, b12, b13, c12, c13, d12, d13 avdd33 3.3 v analog supply. a14 dnc do not connect. b14 i120 nominal 1.2 v reference. tie to analog ground via 10 k resistor to generate a 120 a reference current. c14 vref band gap voltage reference i/o. tie to analog ground via 1 nf capacitor; output impedance approximately 5 k. d1, e2, e3, e4, f2, f3, f4, g1, g2, g3, g4 cvss clock supply ground. d14 iptat factory test pin. output current, proportional to absolute temperature, is approximately 10 a at 25c with a slope of approximately 20 na/c. e1, f1 dacclk?/dacclk+ negative/positive dac clock input (dacclk). e11, e12, f11, f12, g11, g12 avss analog supply ground shield. tie to avss at the dac. e13 irq/unsigned if pin_mode = 0, irq: active low open-drain interrupt request output, pull up to dvdd33 with 10 k resistor. if pin_mode = 1, unsigned: digital input pin where 0 = twos complement input data format, 1 = unsigned. e14 reset/pd if pin_mode = 0, reset: 1 resets the ad9734. if pin_mode = 1, pd: 1 puts the ad9734 in the power-down state. f13 csb/2 see the serial peripheral interface section and the pin mode operation section for pin description. f14 sdio/fifo see the pin mode operation section for pin description. g13 sclk/fsc0 see the pin mode operation section for pin description. g14 sdo/fsc1 see the pin mode operation section for pin description. h1, h2, h3, h4, h11, h12, h13, h14, j1, j2, j3, j4, j11, j12, j13, j14 dvdd18 1.8 v digital supply. k1, k2, k3, k4, k11, k12, l2, l3, l4, l5, l6, l9, l10, l11, l12, m3, m4, m5, m6, m9, m10, m11, m12 dvss digital supply ground.
ad9734/ad9735/ad9736 rev. a | page 15 of 72 pin no. mnemonic description k13, k14 db<9>?/db<9>+ negative/positive data input bit 9 (msb). conforms to ieee-1596 reduced range link. l1 pin_mode 0 = spi mode. spi is enabled. 1 = pin mode. spi is disabled; direct pin control. l7, l8, m7, m8, n7, n8, p7, p8 dvdd33 3.3 v digital supply. l13, l14 db<8>?/db<8>+ negative/positive data input bit 8. conforms to ieee-1596 reduced range link. m1, m2 nc no connect. m13, m14 db<7>?/db<7>+ negative/positive data input bit 7. conforms to ieee-1596 reduced range link. n1, p1 nc no connect. n2, p2 nc no connect. n3, p3 nc no connect. n4, p4 db<0>?/db<0>+ negative/positive data input bit 0 (lsb). conforms to ieee-1596 reduced range link. n5, p5 db<1>?/db<1>+ negative/positive data input bit 1. conforms to ieee-1596 reduced range link. n6, p6 dataclk_out?/ dataclk_out+ negative/positive data output clock. conforms to ieee-1596 reduced range link. n9, p9 dataclk_in?/ dataclk_in+ negative/positive data input clock. conforms to ieee-1596 reduced range link. n10, p10 db<2>?/db<2>+ negative/positive data input bit 2. conforms to ieee-1596 reduced range link. n11, p11 db<3>?/db<3>+ negative/positive data input bit 3. conforms to ieee-1596 reduced range link. n12, p12 db<4>?/db<4>+ negative/positive data input bit 4. conforms to ieee-1596 reduced range link. n13, p13 db<5>?/db<5>+ negative/positive data input bit 5. conforms to ieee-1596 reduced range link. n14, p14 db<6>?/db<6>+ negative/positive data input bit 6. conforms to ieee-1596 reduced range link.
ad9734/ad9735/ad9736 rev. a | page 16 of 72 location of supply and control pins 04862-002 a b c d e f g h j k l m n p 14 13 12 11 10 8 7 6 3 2 19 5 4 avss, analog supply ground avss, analog supply ground shield avdd33, 3.3v, analog supply figure 5. analog supply pins (top view) a b c d e f g h j k l m n p 14 13 12 11 10 8 7 6 3 2 19 5 4 cvdd18, 1.8v clock supply cvss, clock supply ground 04862-003 figure 6. clock supply pins (top view) a b c d e f g h j k l m n p 14 13 12 11 10 8 7 6 3 2 19 5 4 04862-004 dvdd33, 3.3v digital supply dvss digital supply ground dvdd18, 1.8v digital supply figure 7. digital supply pins (top view) a b c d e f g h j k l m n p 14 13 12 11 10 8 7 6 3 2 19 5 4 04862-006 i120 vref iptat pin_mode = 0, spi enabled pin_mode = 1, spi disabled pin_mode unsigned 2 fsc0 pd fifo fsc1 irq csb sclk reset sdio sdo ioutb iouta figure 8. analog i/o and spi control pins (top view)
ad9734/ad9735/ad9736 rev. a | page 17 of 72 terminology linearity error (integral nonlinearity or inl) the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (dnl) the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero. for iouta, 0 ma output is expected when the inputs are all 0s. for ioutb, 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. temp er atu re d r i f t specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. power supply rejection the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion (thd) the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. it is expressed as a percentage or in decibels (db). multitone power ratio the spurious-free dynamic range containing multiple carrier tones of equal amplitude. it is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone.
ad9734/ad9735/ad9736 rev. a | page 18 of 72 typical performance characteristics ad9736 static linearity, 10 ma full scale 04862-008 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 1.00 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 ?1.25 ?1.50 ?1.75 ?2.00 figure 9. ad9736 inl, ?40c, 10 ma fs 04862-008 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 1.00 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 ?1.25 ?1.50 ?1.75 ?2.00 figure 10. ad9736 inl, 25c, 10 ma fs 04862-009 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 1.00 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 ?1.25 ?1.50 ?1.75 ?2.00 figure 11. ad9736 inl, 85c, 10 ma fs 04862-010 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 figure 12. ad9736 dnl, ?40c, 10 ma fs 04862-011 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 figure 13. ad9736 dnl, 25c, 10 ma fs 04862-012 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 figure 14. ad9736 dnl, 85c, 10 ma fs
ad9734/ad9735/ad9736 rev. a | page 19 of 72 ad9736 static linearity, 20 ma full scale 04862-013 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 ?1.4 figure 15. ad9736 in l, ?40c, 20 ma fs 04862-014 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 ?1.4 figure 16. ad9736 inl, 25c, 20 ma fs 04862-015 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 ?1.4 figure 17. ad9736 inl, 85c, 20 ma fs 04862-016 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 figure 18. ad9736 dnl, ?40c, 20 ma fs 04862-017 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 figure 19. ad9736 dnl, 25c, 20 ma fs 04862-018 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 figure 20. ad9736 dnl, 85c, 20 ma fs
ad9734/ad9735/ad9736 rev. a | page 20 of 72 ad9736 static linearity, 30 ma full scale 04862-019 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 figure 21. ad9736 in l, ?40c, 30 ma fs 04862-020 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 figure 22. ad9736 inl, 25c, 30 ma fs 04862-021 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 2.0 1.5 1.0 0.5 0 0 0 0 ?0.5 ?0.5 ?1.0 ?1.0 ?1.5 ?1.5 ?2.0 figure 23. ad9736 inl, 85c, 30 ma fs 04862-022 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 0.6 0.3 0.4 0.5 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 figure 24. ad9736 dnl, ?40c, 30 ma fs 04862-023 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 0.6 0.3 0.4 0.5 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 figure 25. ad9736 dnl, 25c, 30 ma fs 04862-024 code 16384 0 2048 4096 6144 8192 10240 12288 14336 error (lsb) 1.0 0 0.5 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 figure 26. ad9736 dnl, 85c, 30 ma fs
ad9734/ad9735/ad9736 rev. a | page 21 of 72 ad9735 static linearity, 10 ma, 20 ma, 30 ma full scale 04862-025 0.4 0.2 0.3 0.1 ?0.1 0 ?0.2 4096 3584 3072 2560 2048 1536 1024 0 512 code error (lsb) figure 27. ad9735 inl, 25c, 10 ma fs 04862-026 0.15 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 4096 3584 3072 2560 2048 1536 1024 0 512 code error (lsb) figure 28. ad9735 inl, 25c, 20 ma fs 04862-027 0.2 0 0.1 ?0.2 ?0.1 ?0.4 ?0.5 ?0.3 ?0.6 4096 3584 3072 2560 2048 1536 1024 0 512 code error (lsb) figure 29. ad9735 inl, 25c, 30 ma fs 04862-028 4096 3584 3072 2560 2048 1536 1024 0 512 0.100 0.050 0 ?0.050 ?0.100 ?0.150 ?0.200 ?0.250 code error (lsb) figure 30. ad9735 dnl, 25c, 10 ma fs 04862-029 0.100 0.075 0.025 0.050 0 ?0.025 ?0.075 ?0.050 ?0.100 ?0.125 4096 3584 3072 2560 2048 1536 1024 0 512 code error (lsb) figure 31. ad9735 dnl, 25c, 20 ma fs 04862-030 4096 3584 3072 2560 2048 1536 1024 0 512 code error (lsb) 0.050 0 ?1.000 ?0.050 ?1.150 ?0.200 ?0.300 ?0.250 ?0.350 ?0.400 figure 32. ad9735 dnl, 25c, 30 ma fs
ad9734/ad9735/ad9736 rev. a | page 22 of 72 ad9734 static linearity, 10 ma, 20 ma, 30 ma full scale 04862-031 0.06 0.04 0.02 0 ?0.02 ?0.04 ?0.06 1024 896 768 640 512 384 256 0 128 code error (lsb) figure 33. ad9734 inl, 25c, 10 ma fs 04862-032 error (lsb) 0.03 0.02 0.01 0 ?0.01 ?0.03 ?0.02 ?0.04 ?0.05 ?0.06 1024 896 768 640 512 384 256 0 128 code figure 34. ad9734 inl, 25c, 20 ma fs 04862-033 error (lsb) 1024 896 768 640 512 384 256 0 128 code 0.06 0.04 0.02 0 ?0.02 ?0.06 ?0.04 ?0.08 ?0.10 ?0.12 figure 35. ad9734 inl, 25c, 30 ma fs 04862-034 error (lsb) 1024 896 768 640 512 384 256 0 128 code 0.04 0.03 0.02 0.01 0 ?0.01 ?0.02 figure 36. ad9734 dnl, 25c, 10 ma fs 04862-035 error (lsb) 1024 896 768 640 512 384 256 0 128 code 0.03 0.02 0.01 0 ?0.01 ?0.02 ?0.03 figure 37. ad9734 dnl, 25c, 20 ma fs 04862-036 error (lsb) 1024 896 768 640 512 384 256 0 128 code 0.01 0 ?0.01 ?0.02 ?0.03 ?0.04 ?0.05 ?0.06 figure 38. ad9734 dnl, 25c, 30 ma fs
ad9734/ad9735/ad9736 rev. a | page 23 of 72 ad9736 power consumption, 20 ma full scale 04862-037 dvdd18 dvdd33 cvdd18 avdd33 total f dac (mhz) 1500 0 250 500 750 1000 1250 power (w) 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 figure 39. ad9736 1 mode power vs. f dac at 25c 04862-038 f dac (mhz) 1500 0 250 500 750 1000 1250 power (w) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 dvdd18 dvdd33 cvdd18 avdd33 total figure 40. ad9736, 2 interpolation mode power vs. f dac at 25c
ad9734/ad9735/ad9736 rev. a | page 24 of 72 ad9736 dynamic performance, 20 ma full scale 04862-039 800msps 1gsps 1.2gsps f out (mhz) 600 0 50 100 150 200 250 300 350 400 450 500 550 sfdr (dbc) 80 75 70 65 60 55 50 figure 41. ad9736 sfdr vs. f out over f dac at 25c 04862-040 f out (mhz) 600 0 50 100 150 200 250 300 350 400 450 500 550 sfdr (dbc) 80 75 70 65 60 55 50 +85c +25c ?40c figure 42. ad9736 sfdr vs. f out over temperature 04862-041 550 0 50 100 150 200 250 300 350 400 450 500 76 78 72 74 70 68 66 64 62 60 56 54 58 52 f out (mhz) sfdr (dbc) figure 43. ad9736 sfdr vs. f out over 50 parts, 25c, 1.2 gsps 04862-042 550 0 50 100 150 200 250 300 350 400 450 500 92 86 88 90 82 80 84 78 76 74 70 72 66 68 62 60 64 58 f out (mhz) imd (dbc) figure 44. ad9736 imd vs. f out over 50 parts, 25c,1.2 gsps 04862-043 f out (mhz) 600 0 100 200 300 400 500 imd (dbc) 90 85 80 75 70 65 60 55 50 800msps 1gsps 1.2gsps figure 45. ad9736 imd vs. f out over f dac at 25c 04862-044 f out (mhz) 600 0 100 200 300 400 500 imd (dbc) 90 85 80 75 70 65 60 55 50 +85c +25c ?40c figure 46. ad9736 imd vs. f out over temperature, 1.2 gsps
ad9734/ad9735/ad9736 rev. a | page 25 of 72 04862-045 f out (mhz) 100 010 imd and sfdr (dbc) 95 90 85 80 75 70 65 60 55 imd sfdr figure 47. ad9736 low frequency imd and sfdr vs. f out , 25c, 1.2 gsps 04862-046 f out (mhz) 350 0 50 100 150 200 250 300 sfdr, imid (dbc) 90 85 80 75 70 65 60 55 50 third-order imd sfdr figure 48. ad9736 imd and sfdr vs. f out , 25c, 1.2 gsps, 2 interpolation 04862-047 f out (mhz) 600 0 100 200 300 400 500 sfdr (dbc) 80 75 70 65 60 55 50 45 40 0dbfs ?6dbfs ?12dbfs figure 49. ad9736 sfdr vs. f out over a out , 25c, 1.2 gsps 04862-048 f out (mhz) 600 0 100 200 300 400 500 imd (dbc) 90 85 80 75 70 65 60 55 50 0dbfs ?6dbfs ?12dbfs figure 50. ad9736 imd vs. f out over a out , 25c, 1.2 gsps 04862-049 f out (mhz) 350 0 50 100 150 200 250 300 sfdr, imd (dbc) 90 85 80 75 70 65 60 55 50 sfdr_1 sfdr_2 figure 51. ad9736 sfdr vs. f out , 25c, 1.2 gsps, 1 and 2 interpolation 04862-050 f out (mhz) 350 0 50 100 150 200 250 300 sfdr, imd (dbc) 90 85 80 75 70 65 60 55 50 third-order imd_1 third-order imd_2 figure 52. ad9736 imd vs. f out , 25c, 1.2 gsps, 1 and 2 interpolation
ad9734/ad9735/ad9736 rev. a | page 26 of 72 04862-051 f out (mhz) 600 0 100 200 300 400 500 nsd (dbm/hz) ?150 ?154 ?156 ?152 ?158 ?160 ?162 ?164 ?166 ?168 ?170 1gsps 1.2gsps figure 53. ad9736 1-tone nsd vs. f out over f dac , 25c 04862-052 f out (mhz) 600 0 100 200 300 400 500 nsd (dbm/hz) ?150 ?154 ?156 ?152 ?158 ?160 ?162 ?164 ?166 ?168 ?170 +85c +25c ?40c figure 54. ad9736 1-tone nsd vs. f out over temperature, 1.2 gsps 04862-053 f out (mhz) 600 0 100 200 300 400 500 nsd (dbm/hz) ?150 ?154 ?156 ?152 ?158 ?160 ?162 ?164 ?166 ?168 ?170 1gsps 1.2gsps figure 55. ad9736 8-tone nsd vs. f out over f dac , 25c 04862-054 f out (mhz) 600 0 100 200 300 400 500 nsd (dbm/hz) ?150 ?154 ?156 ?152 ?158 ?160 ?162 ?164 ?166 ?168 ?170 +85c +25c ?40c figure 56. ad9736 8-tone nsd vs. f out over temperature, 1.2 gsps 04862-055 550 0 50 100 150 200 250 300 350 400 450 500 ?159 ?158 ?160 ?157 ?161 ?162 ?163 ?164 ?165 ?166 f out (mhz) nsd (dbm/hz) figure 57. ad9736 1-tone nsd vs. f out over 50 parts, 1.2 gsps, 25c 04862-056 550 0 50 100 150 200 250 300 350 400 450 500 ?162 ?163 ?161 ?164 ?165 ?166 ?167 f out (mhz) nsd (dbm/hz) figure 58. ad9736 8-tone nsd vs. f out over 50 parts, 1.2 gsps, 25c
ad9734/ad9735/ad9736 rev. a | page 27 of 72 ad9735, ad9734 dynamic performance, 20 ma full scale 04862-060 f out (mhz) 600 0 50 100 150 200 250 300 350 400 450 500 550 sfdr (dbc) 80 75 70 65 60 55 50 800msps 1gsps 1.2gsps figure 59. ad9735 sfdr vs. f out over f dac , 1.2 gsps 04862-061 f out (mhz) 600 0 50 100 150 200 250 300 350 400 450 500 550 sfdr (dbc) 80 75 70 65 60 55 50 800msps 1gsps 1.2gsps figure 60. ad9734 sfdr vs. f out over f dac , 1.2 gsps 04862-062 f out (mhz) 600 0 50 100 150 200 250 300 350 400 450 500 550 imd (dbc) 90 85 80 75 70 65 60 55 50 800msps 1gsps 1.2gsps figure 61. ad9735 imd vs. f out over f dac , 1.2 gsps 04862-063 f out (mhz) 600 0 50 100 150 200 250 300 350 400 450 500 550 imd (dbc) 90 85 80 75 70 65 60 55 50 800msps 1gsps 1.2gsps figure 62. ad9734 imd vs. f out over f dac , 1.2 gsps 04862-064 f out (mhz) 600 0 50 100 150 200 250 300 350 400 450 500 550 nsd (dbc/hz) ?150 ?152 ?154 ?156 ?158 ?160 ?162 ?164 ?166 ?168 ?170 1 tone 8 tones figure 63. ad9735 nsd vs. f out , 1.2 gsps 04862-065 f out (mhz) 600 0 50 100 150 200 250 300 350 400 450 500 550 nsd (dbc/hz) ?149 ?147 ?145 ?151 ?153 ?155 ?157 ?159 ?161 ?163 ?165 1 tone 8 tones figure 64. ad9734 nsd vs. f out , 1.2 gsps
ad9734/ad9735/ad9736 rev. a | page 28 of 72 ad973x wcdma aclr, 20 ma full scale 04862-057 #atten 6db pavg 10 w1 s2 center 134.83mhz #res bw 30khz vbw 300khz span 33.88mhz sweep 109.9ms (601pts) ref ?22.75dbm #avg log 10db/ rms results offset freq ref bw dbc dbm dbc dbm carrier power 5.00mhz 3.840mhz ?81.65 ?92.37 ?81.39 ?92.11 ?10.72dbm/ 10.0mhz 3.840mhz ?82.06 ?92.78 ?82.43 ?93.16 3.84000mhz 15.0mhz 3.884mhz ?82.11 ?92.83 ?82.39 ?93.11 lower upper figure 65. ad9736 wcdma carrier at 134.83 mhz, f dac = 491.52 msps 04862-058 rms results offset freq ref bw dbc dbm dbc dbm carrier power 5.00mhz 3.840mhz ?80.32 ?91.10 ?80.60 ?91.38 ?10.72dbm/ 10.0mhz 3.840mhz ?81.13 ?91.91 ?80.75 ?91.53 3.84000mhz 15.0mhz 3.884mhz ?80.43 ?91.21 ?81.36 ?92.13 lower upper pavg 10 s2 center 134.83mhz #res bw 30khz vbw 300khz #atten 6db span 33.88mhz sweep 109.9ms (601pts) ref ?22.75dbm #avg log 10db/ figure 66. ad9735 wcdma carrier at 134.83 mhz, f dac = 491.52 msps 04862-059 rms results offset freq ref bw dbc dbm dbc dbm carrier power 5.00mhz 3.840mhz ?71.07 ?81.83 ?71.23 ?81.99 ?10.76dbm/ 10.0mhz 3.840mhz ?70.55 ?81.31 ?71.42 ?82.19 3.84000mhz 15.0mhz 3.884mhz ?70.79 ?81.56 ?71.25 ?82.01 lower upper pavg 10 s2 center 134.83mhz #res bw 30khz vbw 300khz #atten 6db span 33.88mhz sweep 109.9ms (601pts) ref ?22.75dbm #avg log 10db/ figure 67. ad9734 wcdma carrier at 134.83 mhz, f dac = 491.52 msps
ad9734/ad9735/ad9736 rev. a | page 29 of 72 spi register map write 0 to unspecified or reserved bit locations. reading these bits returns unknown values. table 9. spi register map reg. addr. default pin mode dec. hex. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (hex) (hex) 0 00 mode sdio_dir lsbfirst reset long_ins 2x mode fifo mode datafrmt pd 00 00 1 01 irq lvds sync cross reserved ie _lvds ie_sync ie_cross reserved 00 00 2 02 fsc_1 sleep fsc<9> fsc<8> 02 02 3 03 fsc_2 fsc<7> fsc<6> fsc<5> fsc<4> fsc<3> fsc<2> fsc<1> fsc<0> 00 00 4 04 lvds_cnt1 msd<3> msd<2> msd<1> msd< 0> mhd<3> mhd<2> mhd<1> mhd<0> 00 00 5 05 lvds_cnt2 sd<3> sd<2> sd<1> sd<0> lchange err_hi err_lo check 00 00 6 06 lvds_cnt3 lsurv lauto lflt<3> lflt<2> lflt<1> lflt<0> ltrh<1> ltrh<0> 00 00 7 07 sync_cnt1 fifostat3 fifostat2 fifostat1 fi fostat0 valid schange phof<1> phof<0> 00 00 8 08 sync_cnt2 ssurv sauto sflt<3> sflt<2 > sflt<1> sflt<0> reserved strh<0> 00 00 9 09 reserved 10 0a cros_cnt1 updel<5> updel<4> upde l<3> updel<2> updel<1> updel<0> 00 00 11 0b cros_cnt2 dndel<5> dndel<4> dnde l<3> dndel<2> dndel<1> dndel<0> 00 00 12 0c reserved 13 0d reserved 14 0e ana_cnt1 msel<1> msel<0> trmbg<2> trmbg<1> trmbg<0> c0 c0 15 0f ana_cnt2 hdrm<7> hdrm<6> hdrm<5> hdrm<4> hdrm<3> hdrm<2> hdrm<1> hdrm<0> ca ca 16 10 reserved 17 11 bist_cnt sel<1> sel<0> sig_re ad lvds_en sync_en clear 00 00 18 12 bist<7:0> 19 13 bist<15:8> 20 14 bist<23:16> 21 15 bist<31:24> 22 16 cclk_div reserved reserved reserved reserved ccd<3> ccd<2> ccd<1> ccd<0> 00 00
ad9734/ad9735/ad9736 rev. a | page 30 of 72 spi register details reading these registers returns previously written values for all defined register bits, unless otherwise noted. reset value fo r write registers in bold text. mode register (reg. 0) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 mode sdio_dir lsb/msb reset long_i ns 2 mode fifo mode datafrmt pd table 10. mode register bit descriptions bit name read/write description sdio_dir write 0 , input only per spi standard. 1, bidirectional per spi standard. lsb/msb write 0 , msb first per spi standard. 1, lsb first per spi standard. note: only change lsb/msb order in single-byte instructions to avoid erratic behavior due to bit order errors. reset write 0 , execute software reset of spi and controllers, reload default register values except registers 0x00 and 0x04. 1, set software reset, write 0 on the next (or any following) cycle to release the reset. long_ins write 0 , short (single-byte) instruction word. 1, long (two-byte) instruction word, not necess ary since the maximum internal address is reg31 (0x1f). 2_mode write 0 , disable 2 interpolation filter. 1, enable 2 interpolation filter. fifo_mode write 0 , disable fifo synchronization. 1, enable fifo synchronization. datafrmt write 0 , signed input data with midscale = 0x0000. 1, unsigned input data with midscale = 0x2000. pd write 0 , enable lvds receiver, dac, and clock circuitry. 1, power down lvds receiver, dac, and clock circuitry. interrupt request register (irq) (reg. 1) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x01 irq lvds sync cross reserved ie_lvds ie_sync ie_cross reserved table 11. interrupt register bit descriptions bit name read/write description lvds write dont care. read 0, no active lvds receiver interrupt. 1, interrupt in lvds receiver occurred. sync write dont care. read 0, no active sync logic interrupt. 1, interrupt in sync logic occurred. cross write dont care. read 0, no active cross logic interrupt. 1, interrupt in cross logic occurred. ie_lvds write 0 , reset lvds receiver interrupt and di sable future lvds receiver interrupts. 1, enable lvds receiver interrupt to activate irq pin. ie_sync write 0 , reset sync logic interrupt and disable future sync logic interrupts. 1, enable sync logic interrupt to activate irq pin. ie_cross write 0 , reset cross logic interrupt and di sable future cross logic interrupts. 1, enable cross logic interrupt to activate irq pin.
ad9734/ad9735/ad9736 rev. a | page 31 of 72 full scale current (fsc) registers (reg. 2, reg. 3) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02 fsc_1 sleep C C C C C fsc<9> fsc<8> 0x03 fsc_2 fsc<7> fsc<6> fsc<5> fsc< 4> fsc<3> fsc<2> fsc<1> fsc<0> table 12. full scale current outp ut register bit descriptions bit name read/write description sleep write 0 , enable dac output. 1, set dac output current to 0 ma. fsc<9:0> write 0x000, 10 ma full-scale output current. 0x200 , 20 ma full-scale output current. 0x3ff, 30 ma full-scale output current. lvds controller (lvds_cnt) registers (reg. 4, reg. 5, reg. 6) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x04 lvds_cnt1 msd<3> msd<2> msd<1> msd<0> mhd<3> mhd<2> mhd<1> mhd<0> 0x05 lvds_cnt2 sd<3> sd<2> sd<1> sd<0> lchange err_hi err_lo check 0x06 lvds_cnt3 lsurv lauto lflt<3> lflt<2> lflt<1> lflt<0> ltrh<1> ltrh<0> table 13. lvds controller register bit descriptions bit name read/write description msd<3:0> write 0x0 , set setup delay for the measurement system. read if ( lauto = 1), the latest measured value for the setup delay. if ( lauto = 0), readback of the last spi write to this bit. mhd<3:0> write 0x0 , set hold delay for the measurement system. read if ( lauto = 1), the latest measured value for the hold delay. if ( lauto = 0), readback of the last spi write to this bit. sd<3:0> write 0x0 , set sample delay. read if ( lauto = 1), the result of a measurement cycle is stored in this register. if ( lauto = 0), readback of the last spi write to this bit. lchange read 0, no change from previous measurement. 1, change in value from the previous measurement. note: the average filter and the threshold detection are not applied to this bit. err_hi read one of the 15 lvds inputs is above the in put voltage limits of the ieee reduced link specification. err_lo read one of the 15 lvds inputs is below the in put voltage limits of the ieee reduced link specification. check read 0, phase measurementsampling in the previous or following data cycle. 1, phase measurementsampling in the correct data cycle. lsurv write 0 , the controller stops after completion of the current measurement cycle. 1, continuous measurements are taken and an interrupt is issued if the clock alignment drifts beyond the threshold value. lauto write 0 , sample delay is not automatically updated. 1, continuously starts measuremen t cycles and updates the sample de lay according to the measurement. note: lsurv (reg. 6, bit 7) must be set to 1 and the lvds irq (reg. 1, bit 3) must be set to 0 for auto mode. lflt<3:0> write 0x0 , average filter length, delay = delay + delta delay/2^ lflt <3:0>, values greater than 12 (0x0c) are clipped to 12. ltrh<2:0> write 000 , set auto update threshold values.
ad9734/ad9735/ad9736 rev. a | page 32 of 72 sync controller (sync_cnt) re gisters (reg. 7, reg. 8) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x07 sync_cnt1 fifostat3 fifostat2 fifostat1 fifostat0 valid schange phof<1> phof<0> 0x08 sync_cnt2 ssurv sauto sflt<3> sflt<2> sflt<1> sflt<0> reserved strh<0> table 14. sync controller register bit descriptions bit name read/write description fifostat<2:0> read position of fifo read counter ranges from 0 to 7. fifostat<3> read 0, sync logic ok. 1, error in sync logic. valid read 0, fifostat<3:0> is not valid yet. 1, fifostat<3:0> is valid after a reset. schange read 0, no change in fifostat<3:0>. 1, fifostat<3:0> has changed since the previous measurement cycle when ssurv = 1 (surveillance mode active). phof<1:0> write 00 , change the readout counter. read current setting of the readout counte r (phof<1:0>) in surveillance mode (ssurv = 1) after an interrupt. current calculated optimal readout counter value in auto mode (sauto = 1). ssurv write 0 , the controller stops after completion of the current measurement cycle. 1, continuous measurements are taken and an interrupt is issued if the readout counter drifts beyond the threshold value. sauto write 0 , readout counter (phof<3:0>) is not automatically updated. 1, continuously starts measurement cycles an d updates the readout counter according to the measurement. note: ssurv (reg. 8, bit 7) must be set to 1 and the sync irq (reg. 1, bit 2) must be set to 0 for auto mode. sflt<3:0> write 0x0 , average filter length, fifostat = fifostat + delta fifostat/2 ^ sflt<3:0>; values greater than 12 (0x0c) are clipped to 12. strh<0> write 0 , if fifostat<2:0> = 0 or 7, a sync interrupt is generated. 1, if fifostat<2:0> = 0, 1, 6 or 7, a sync interrupt is generated. cross controller (cros_cnt) re gisters (reg. 10, reg. 11) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0a cros_cnt1 C C updel<5> updel<4> up del<3> updel<2> up del<1> updel<0> 0x0b cros_cnt2 C C dndel<5> dndel<4> dn del<3> dndel<2> dn del<1> dndel<0> table 15. cross controller register description bit name read/write description updel<5:0> write 0x00 , move the differential output stage switching point up, set to 0 if dndel is non-zero. dndel<5:0> write 0x00 , move the differential output stage switching point down, set to 0 if updel is non-zero.
ad9734/ad9735/ad9736 rev. a | page 33 of 72 analog control (ana_cnt) registers (reg. 14, reg. 15) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0e ana_cnt1 msel<1> msel<0> C C C trmbg<2> tr mbg<1> trmbg<0> 0x0f ana_cnt2 hdrm<7> hdrm<6> hdrm<5> hdrm<4> hdrm<3> hdrm<2> hdrm<1> hdrm<0> table 16. analog control register bit descriptions bit name read/write description msel<1:0> write 00, mirror roll off frequency control = bypass. 01, mirror roll off frequency control = narrowest bandwidth. 10, mirror roll off frequency control = medium bandwidth. 11 , mirror roll off frequency control = widest bandwidth. note: see the plot in the analog control registers section. trmbg<2:0> write 000 , band gap temperature characteristic trim. note: see the plot in the analog control registers section. hdrm<7:0> write 0xca , output stack headroom control. hdrm<7:4> set reference offset from avdd33 (vcas centering). hdrm<3:0> set overdrive (current de nsity) trim (temperature tracking). note: set to 0xca for optimum performance. built-in self test control (bist_cnt) registers (reg. 17, reg. 18, reg. 19, reg. 20, reg. 21) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x11 bist_cnt sel<1> sel<0> sig_read C C lvds_en sync_en clear 0x12 bist<7:0> bist<7> bist<6> bist<5> bi st<4> bist<3> bist<2> bist<1> bist<0> 0x13 bist<15:8> bist<15> bist< 14> bist<13> bist<12> bist< 11> bist<10> bist<9> bist<8> 0x14 bist<23:16> bist<23> bist< 22> bist<21> bist<20> bist<19> bist<18> bist<17> bist<16> 0x15 bist<31:24> bist<31> bist< 30> bist<29> bist<28> bist<27> bist<26> bist<25> bist<24> table 17. bist control register bit descriptions bit name read/write description sel<1:0> write 00 , write result of the lvds phase 1 bist to bist<31:0>. 01, write result of the lvds phase 2 bist to bist<31:0>. 10, write result of the sync phase 1 bist to bist<31:0>. 11, write result of the sync phase 2 bist to bist<31:0>. sig_read write 0 , no action. 1, enable bist signature readback. lvds_en write 0 , no action. 1, enable lvds bist. sync_en write 0 , no action. 1, enable sync bist. clear write 0 , no action. 1, clear all bist registers. bist<31:0> read results of the built-in self test.
ad9734/ad9735/ad9736 rev. a | page 34 of 72 controller clock predivider (cclk_ div) reading register (reg. 22) adr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x16 cclk_div reserved reserved reserved reserved ccd<3> ccd<2> ccd<1> ccd<0> table 18. controller clock predivid er register bit descriptions bit name read/write description ccd<3:0> write 0x0 , controller clock = dacclk/16. 0x1, controller clock = dacclk/32. 0x2, controller clock = dacclk/64 0xf, controller clock = dacclk/524288. note: the 100 mhz to 1.2 ghz dacclk must be divided to less than 10 mhz for correct operation. ccd<3:0> must be programmed to divide the dacclk so that th is relationship is not violated. controller clock = dacclk/(2 ^ ( ccd<3:0> + 4 )).
ad9734/ad9735/ad9736 rev. a | page 35 of 72 theory of operation the ad9736, ad9735, and ad9734 are 14-bit, 12-bit, and 10-bit dacs that run at an update rate up to 1.2 gsps. input data can be accepted up to the full 1.2 gsps rate, or a 2 interpolation filter can be enabled (2 mode) allowing full speed operation with a 600 msps input data rate. the data and dataclk_in inputs are parallel lvds, meeting the ieee reduced swing lvds specifications with the exception of input hysteresis. the dataclk_in input runs at one-half the input data rate in a double data rate (ddr) format. each edge of dataclk_in transfers data into the ad9736, as shown in figure 79. the dacclk?/dacclk+ inputs (pin e1 and pin f1) directly drive the dac core to minimize clock jitter. the dacclk signal is also divided by 2 (1 and 2 mode), then output as the dataclk_out. the dataclk_out signal clocks the data source. the dac expects ddr lvds data (db<13:0>) aligned with the ddr input clock (dataclk_in) from a circuit simi- lar to the one shown in figure 96. table 19 shows the clock relationships. table 19. ad973x clock relationship mode dacclk dataclk_out dataclk_in data 1 1.2 ghz 600 mhz 600 mhz 1.2 gsps 2 1.2 ghz 600 mhz 300 mhz 600 msps maintaining correct alignment of data and clock is a common challenge with high speed dacs, complicated by changes in temperature and other operating conditions. using the dataclk_out signal to generate the data allows most of the internal process, temperature, and voltage delay variation to be cancelled. the ad973x further simplifies this high speed data capture problem with two adaptive closed-loop timing controllers. one timing controller manages the lvds data and data clock alignment (lvds controller), and the other manages the lvds data and dacclk alignment (sync controller). the lvds controller locates the data transitions and delays the dataclk_in so that its transition is in the center of the valid data window. the sync controller manages the fifo that moves data from the lvds dataclk_in domain to the dacclk domain. both controllers can operate in manual mode under external processor control, in surveillance mode where error conditions generate external interrupts, or in automatic mode where errors are automatically corrected. the lvds and sync controllers include moving average filtering for noise immunity and variable thresholds to control activity. normally, the controllers are set to run in automatic mode, making any necessary adjustments without dropping or dupli- cating samples sent to the dac. both controllers require initial calibration prior to entering automatic update mode. the ad973x analog output changes 35 dacclk cycles after the input data changes in 1 mode with the fifo disabled. the fifo adds up to eight additional cycles of delay. this delay is read from the spi port. internal clock delay variation is less than a single dacclk cycle at 1.2 ghz (833 ps). stopping the ad973x dataclk_in while the dacclk is still running can lead to unpredictable output signals. this occurs because the internal digital signal path is interleaved. the last two samples clocked into the dac continue to be clocked out by dacclk even after dataclk_in has stopped. the result- ing output signal is at a frequency of one-half f dac, and the amplitude depends on the difference between the last two samples. control of the ad973x functions is via the serially programmed registers listed in table 9. optionally, a limited number of func- tions can be directly set by external pins in pin mode.
ad9734/ad9735/ad9736 rev. a | page 36 of 72 serial peripheral interface the ad973x serial port is a flexible, synchronous serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola spi? and intel? ssr protocols. the interface allows read/write access to all registers that configure the ad973x. single- or multiple-byte transfers are supported, as well as most significant bit first (msb-first) or least significant bit first (lsb-first) transfer formats. the ad973x serial interface port can be configured as a single pin i/o (sdio) or two unidirectional pins for in/out (sdio/sdo). sdo (pin g14) sdio (pin f14) s clk (pin g13) csb (pin f13) ad973x spi port 04862-066 figure 68. ad973x spi port the ad973x can optionally be configured via external pins rather than the serial interface. when the pin_mode input (pin l1) is high, the serial interface is disabled and its pins are reassigned for direct control of the dac. specific functionality is described in the pin mode operation section. general operation of the serial interface there are two phases to a communication cycle with the ad973x. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad973x, coincident with the first eight sclk rising edges. the instruction byte provides the ad973x serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad973x. the remaining sclk edges are for phase 2 of the communica- tion cycle. phase 2 is the actual data transfer between the ad973x and the system controller. phase 2 of the communica- tion cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. using one multibyte transfer is the preferred method. single-byte data transfers are useful to reduce cpu overhead when register access requires one byte only. registers change immediately upon writing to the last bit of each transfer byte. csb (chip select) can be raised after each sequence of 8 bits (except the last byte) to stall the bus. the serial transfer resumes when csb is lowered. stalling on nonbyte boundaries resets the spi. short instruction mode (8-bit instruction) the short instruction byte is shown in the following table: msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/w n1 n0 a4 a3 a2 a1 a0 r/w, bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. logic high indicates read operation. logic 0 indicates a write operation. n1, n0, bit 6, and bit 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in table 20. a4, a3, a2, a1, a0, bit 4, bit 3, bit 2, bit 1, and bit 0 of the instruction byte, determine which register is accessed during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the ad973x, based on the lsbfirst bit (reg. 0, bit 6). table 20. byte transfer count n1 n2 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes long instruction mode (16-bit instruction) the long instruction bytes are shown in the following table: msb lsb i15 i14 i13 i12 i11 i10 i9 i8 r/w n1 n0 a12 a11 a10 a9 a8 i7 i6 i5 i4 i3 i2 i1 i0 a7 a6 a5 a4 a3 a2 a1 a0 if long_ins = 1 (reg. 0, bit 4), the instruction byte is extended to 2 bytes where the second byte provides an additional 8 bits of address information. address 0x00 to address 0x1f are equivalent in short and long instruction modes. the ad973x does not use any addresses greater than 31 (0x1f), so always set long_ins = 0. serial interface port pin descriptions sclkserial clock the serial clock pin is used to synchronize data to and from the ad973x and to run the internal state machines. the maximum frequency of sclk is 20 mhz. all data input to the ad973x is registered on the rising edge of sclk. all data is driven out of the ad973x on the rising edge of sclk.
ad9734/ad9735/ad9736 rev. a | page 37 of 72 csbchip select active low input starts and gates a communication cycle. it allows more than one device to be used on the same serial communications lines. the sdo and sdio pins go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle. sdioserial data i/o data is always written into the ad973x on this pin. however, this pin can be used as a bidirectional data line. the configu- ration of this pin is controlled by sdio_dir at reg. 0, bit 7. the default is logic 0, which configures the sdio pin as unidirectional. sdoserial data out data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad973x operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. msb/lsb transfers the ad973x serial port can support both msb-first or lsb-first data formats. this functionality is controlled by lsbfirst at reg. 0, bit 6. the default is msb first (lsbfirst = 0). when lsbfirst = 0 (msb first), the instruction and data bytes must be written from the most significant bit to the least significant bit. multibyte data transfers in msb-first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes should follow in order from high address to low address. in msb-first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. when lsbfirst = 1 (lsb first), the instruction and data bytes must be written from least significant bit to most significant bit. multibyte data transfers in lsb-first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. the serial port internal byte address generator increments for each byte of the multibyte communication cycle. the ad973x serial port controller data address decrements from the data address written toward 0x00 for multibyte i/o operations if the msb-first mode is active. the serial port controller address increments from the data address written toward 0x1f for multibyte i/o operations if the lsb-first mode is active. notes on serial port operation the ad973x serial port configuration is controlled by reg. 0, bit 4, bit 5, bit 6, and bit 7. note that the configuration changes immediately upon writing to the last bit of the register. for multibyte transfers, writing to this register can occur during the middle of the communication cycle. care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. the same considerations apply to setting the software reset, reset (reg. 0, bit 5). all registers are set to their default values except reg. 0 and reg. 4, which remain unchanged. use of only single-byte transfers when changing serial port configurations or initiating a software reset is highly recommended. in the event of unexpected programming sequences, the ad973x spi can become inaccessible. for example, if user code inadvertently changes the long_ins bit or the lsbfirst bit, the following bits experience unexpected results. the spi can be returned to a known state by writing an incomplete byte (1 to 7 bits) of all 0s followed by 3 bytes of 0x00. this returns to msb-first short instructions (reg. 0 = 0x00), so the device can be reinitialized. r/w n1 n0 a4 a3 a2 a1 a0 d7 n d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle csb sclk sdio 04862-067 figure 69. serial register interface timing, msb-first write r/w n1 n0 a4 a3 a2 a1 a0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle csb sclk sdio sdo 04862-068 d7 figure 70. serial register interface timing, msb-first read a0 a1 a2 a3 a4 n0 n1 r/w d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle csb sclk sdio 04862-069 figure 71. serial register interface timing, lsb-first write instruction cycle data transfer cycle csb sclk sdio sdo a0 a1 a2 a3 a4 n0 n1 r/w d1 0 d2 0 d7 n d6 n d5 n d4 n d1 0 d2 0 d7 n d6 n d5 n d4 n 04862-070 d0 d0 figure 72. serial register interface timing, lsb-first read
ad9734/ad9735/ad9736 rev. a | page 38 of 72 instruction bit 6 instruction bit 7 csb sclk sdio t ds t ds t dh t pwh t pwl t sclk 04862-071 figure 73. timing diagram for spi register write i1 i0 d7 d6 d5 t dv t dnv csb s clk s dio 04862-072 figure 74. timing diagram for spi register read after the last instruction bit is written to the sdio pin, the driving signal must be set to a high impedance in time for the bus to turn around. the serial output data from the ad973x is enabled by the falling edge of sclk. this causes the first output data bit to be shorter than the remaining data bits, as shown in figure 74. to assure proper reading of data, read the sdio or sdo pin prior to changing the sclk from low to high. due to the more complex multibyte protocol, multiple ad973x devices cannot be daisy-chained on the spi bus. multiple dacs should be controlled by independent csb signals. pin mode operation when the pin_mode input (pin l1) is set high, the spi port is disabled. the spi port pins are remapped, as shown in table 21. the function of these pins is described in table 22. the remain- ing pin_mode register settings are shown in table 9. table 21. spi_mode vs. pin_mode inputs pin number pin_mode = 0 pin_mode = 1 e13 irq unsigned f13 csb 2 g13 sclk fsc0 e14 reset pd f14 sdio fifo g14 sdo fsc1 table 22. pin_mode input functions mnemonic function unsigned 0, twos complement input data format 1, unsigned input data format 2 0, interpolation disabled 1, interpolation = 2 enabled fsc1, fsc0 00, sleep mode 01, 10 ma full-scale output current 10, 20 ma full-scale output current 11, 30 ma full-scale output current pd 0, chip enabled 1, chip in power-down state fifo 0, input fifo disabled 1, input fifo enabled care must be taken when using pin_mode because only the control bits shown in table 22 can be changed. if the remaining register default values are not suitable for the desired operation, pin_mode cannot be used. if the fifo is enabled, the controller clock must be less than 10 mhz. this limits the dac clock to 160 mhz. reset operation the reset pin forces all spi register contents to their default values (see table 9), which places the dac in a known state. the software reset bit forces all spi register contents, except reg. 0 and reg. 4, to their default values. the internal reset signal is derived from a logical or operation on the reset pin state and from the software reset state. this internal reset signal drives all spi registers to their default values, except reg. 0 and reg. 4, which are unaffected. the data registers are not affected by either reset. the software reset is asserted by writing 1 to reg. 0, bit 5. it may be cleared on the next spi write cycle or a later write cycle. programming sequence the ad973x registers should be programmed in this order: 1. reset hardware. 2. make changes to spi port configuration, if necessary. 3. input format, if unsigned. 4. interpolation, if in 2 mode. 5. calibrate and set the lvds controller. 6. enable the fifo. 7. calibrate and set the sync controller. step 1 through step 4 are required, while step 5 through step 7 are optional. the lvds controller can help assure proper data reception in the dac with changes in temperature and voltage. the sync controller manages the fifo to assure proper transfer of the received data to the dac core with changes in temperature and voltage. the dac is intended to operate with both controllers active unless data and clock alignment is managed externally.
ad9734/ad9735/ad9736 rev. a | page 39 of 72 interpolation filter in 2 mode, the input data is interpolated by a factor of 2 so that it aligns with the dac update rate. the interpolation filter is a hard-coded, 55-tap, symmetric fir with a 0.001 db pass- band flatness and a stop-band attenuation of about 90 db. the transition band runs from 20% of f dac to 30% of f dac . the fir response is shown in figure 75 where the frequency axis is normalized to f dac . figure 76 shows the pass-band flatness and table 23 shows the 16-bit filter coefficients. table 23. fir interpolation filter coefficients coefficient number coefficient number tap weight 1 55 ?7 2 54 0 3 53 +24 4 52 0 5 51 ?62 6 50 0 7 49 +135 8 48 0 9 47 ?263 10 46 0 11 45 +471 12 44 0 13 43 ?793 14 42 0 15 41 +1273 16 40 0 17 39 ?1976 18 38 0 19 37 +3012 20 36 0 21 35 ?4603 22 34 0 23 33 +7321 24 32 0 25 31 ?13270 26 30 0 27 29 +41505 28 +65535 04862-073 frequency normalized to f dac 0.50 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 magnitude (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 figure 75. interpolation filter response 04862-074 frequency normalized to f dac 0.25 0 0.10 0.05 0.15 0.20 magnitude (db) 0.10 0.06 0.08 0.02 ?0.02 ?0.06 0.04 0 ?0.04 ?0.08 ?0.10 figure 76. interpolation filter pass-band flatness data interface controllers two internal controllers are utilized in the operation of the ad973x. the first controller helps maintain optimum lvds data sampling; the second controller helps maintain optimum synchronization between the dacclk and the incoming data. the lvds controller is responsible for optimizing the sampling of the data from the lvds bus (db13:0), while the sync controller resolves timing problems between the dac_clk (clk+, clk?) and the dataclk. a block diagram of these controllers is shown in figure 77. dataclk_out dataclk dataclk_in fifo dac lvds sample logic clk control lvds controller db<13:0> data source i.e., fpga sync logic sync controller 04862-075 figure 77. data controllers the controllers are clocked with a divided-down version of the dac_clk. the divide ratio is set utilizing the controller clock predivider bits (ccd<3:0>) located at reg. 22, bits 3:0 to generate the controller clock as follows: controller clock = dac_clk /(2( ccd <3:0> + 4)) note that the controller clock cannot exceed 10 mhz for correct operation. until ccd<3:0> is properly programmed to meet this requirement, the dac output may not be stable. this means the fifo cannot be enabled in pin_mode unless the dacclk is less than 160 mhz.
ad9734/ad9735/ad9736 rev. a | page 40 of 72 the lvds and sync controllers are independently operated in three modes via spi port reg. 6 and reg. 8: ? manual mode ? surveillance mode ? auto mode in manual mode, all of the timing measurements and updates are externally controlled via the spi. in surveillance mode, each controller takes measurements and calculates a new optimal value continuously. the result of the measurement is passed through an averaging filter before evaluating the results for increased noise immunity. the filtered result is compared to a threshold value set via reg. 6 and reg. 8 of the spi port. if the error is greater than the threshold, an interrupt is triggered and the controller stops. reg. 1 of the spi port controls the interrupts with bit 3 and bit 2 enabling the respective interrupts and bit 7 and bit 6 indicating the respective controller interrupt. if an interrupt is enabled, it also activates the ad973x irq pin. to clear an interrupt, the interrupt enable bit of the respective controller must be set to 0 for at least 1 controller clock cycle (controller clock <10 mhz). auto mode is almost identical to surveillance mode. instead of triggering an interrupt and stopping the controller, the controller automatically updates its settings to the newly calculated optimal value and continues to run. lvds sample logic a simplified diagram of the ad973x lvds data sampling engine is shown in figure 78 and the timing diagram is shown in figure 79. the incoming lvds data is latched by the data sampling signal (dss), which is derived from dataclk_in. the lvds controller delays dataclk_in to create the data sampling signal (dss), which is adjusted to sample the lvds data in the center of the valid data window. the skew between the dataclk_in and the lvds data bits (db<13:0>) must be minimal for proper operation. therefore, it is recommended that the dataclk_in be generated in the same manner as the lvds data bits (db<13:0>) with the same driver and data lines (that is, it should just be another lvds data bit running a constant 01010101 sequence, as shown in figure 96). if the dataclk_in signal is stopped, the dacclk continues to generate an output signal based on the last two values clocked into the registers that drive d1 and d2, as shown in figure 78. if these two registers are not equal, a large output at a frequency of one-half f dac can be generated at the dac output. db<13:0> dataclk_in lvds rx delayed clock signal clock sampling signal check d1 d2 data sampling signal lvds rx msd<3:0> delay msd<3:0> delay ff sd<3:0> sample delay ff ff dbl dbu 04862-076 figure 78. internal lvds data sampling logic sample delay prop delay to latch prop delay to latch clk to db skew db13:0 d1 d2 dataclk_in data sampling signal (dss) 04862-077 figure 79. internal lvds data sampling logic timing lvds sample logic calibration the internal dss delay must be calibrated to optimize the data sample timing. once calibrated, the ad973x generates an irq or automatically corrects its timing if temperature or voltage variations change the timing too much. this calibration is done using the delayed clock sampling signal (css) to sample the delayed clock signal (dcs). the lvds sampling logic finds the edges of the dataclk_in signal and, from this measurement, the center of the valid data window is located. the internal delay line that derives the delayed dss from dataclk_in is controlled by sd3:0 (reg. 5, bits 7:4), while the dcs is controlled by msd3:0 (reg. 4, bits 7:4), and the css is controlled by mhd3:0 (reg. 4, bits 3:0). dataclk_in transitions must be time aligned with the lvds data (db<13:0>) transitions. this allows the css, derived from the dataclk_in, to find the valid data window of db<13:0> by locating the dataclk_in edges. the latching (rising) edge of css is initially placed using bits sd<3:0> and can then be shifted to the left using msd<3:0> and to the right using mhd<3:0>. when css samples the dcs and the result is 1 (which can be read back via the check bit at reg. 5, bit 0), the sampling occurs in the correct data cycle.
ad9734/ad9735/ad9736 rev. a | page 41 of 72 to find the leading edge of the data cycle, increment the measured setup delay until the check bit goes low. to find the trailing edge, increment the measured hold delay (mhd) until check goes low. always set mhd = 0 when incrementing msd and vice versa. the incremental units of sd, msd, and mhd are in units of real time, not fractions of a clock cycle. the nominal step size is 80 ps. operating the lvds controller in manual mode via the spi port the manual operation of the lvds controller allows the user to step through both the setup and hold delays to calculate the optimal sampling delay (that is, the center of the data eye). with sd<3:0> and mhd<3:0> set to 0, increment the setup time delay (msd<3:0>, reg. 4, bits 7:4) until the check bit (reg. 5, bit 0) goes low and record this value. this locates the leading dataclk_in (and data) transition, as shown in figure 80. with sd<3:0> and msd<3:0> set to 0, increment the hold time delay (mhd<3:0>, reg. 4, bits 3:0) until the check bit (reg. 5, bit 0) goes low and record this value. this locates the trailing dataclk_in (and db<13:0>) transition, as shown in figure 81. once both dataclk_in edges are located, the sample delay (sd<3:0>, reg. 5, bits 7:4) must be updated by sample delay = ( mhd ? msd )/2 after updating sd<3:0>, verify that the sampling signal is in the middle of the valid data window by adjusting both mhd and msd with the new sample delay until the check bit goes low. the new mhd and msd values should be equal to or within one unit delay if sd<3:0> was set correctly. mhd and msd may not be equal to or within one unit delay if the external clock jitter and noise exceeds the internal delay resolution. differences of 2, 3, or more are possible and can require more filtering to provide stable operation. the sample delay calibration should be performed prior to enabling surveillance mode or auto mode. setup time ( t s ) sample delay msd<3:0> = 0 1 2 3 4 5 css sample dcs check = 1 sd<3:0> db<13:0> dataclk_in css with mhd<3:0> = 0 dsc delayed by msd<3:0> 04862-078 figure 80. setup delay measurement setup time ( t s ) hold time ( t h ) sample delay css sample dcs check = 1 1 1 1 1 0 check = 1 sd<3:0> 0 4862-079 msd<3:0> = 0 1 2 3 4 5 db<13:0> dataclk_in css with mhd<3:0> = 0 dsc delayed by msd<3:0> = 0 figure 81. hold delay measurement operating the lvds controller in surveillance and auto mode in surveillance mode, the controller searches for the edges of the data eye in the same manner as in the manual mode of operation and triggers an interrupt if the clock sampling signal (css) has moved more than the threshold value set by ltrh<1:0> (reg. 6, bits 1:0). there is an internal filter that averages the setup and hold time measurements to filter out noise and glitches on the clock lines. average value = (mhd C msd )/2 new average = average value + ( average/ 2 ^ lflt <3:0>) if an accumulating error in the average value causes it to exceed the threshold value (lthr<1:0>), an interrupt is issued. the maximum allowable value for lflt<3:0> is 12. if lflt<3:0> is too small, clock jitter and noise can cause erratic behavior. in most cases, lflt can be set to the maximum value. in surveillance mode, the ideal sampling point should first be found using manual mode and then applied to the sample delay registers. set the threshold and filter values depending on how far the css signal is allowed to drift before an interrupt occurs. then, set the surveillance bit high (reg. 6, bit 7) and monitor the interrupt signal either via the spi port (reg. 1, bit 7) or the irq pin. in auto mode, follow the same steps to set up the sample delay, threshold, and filter length. to run the controller in auto mode, both the lauto (reg. 6, bit 6) and lsurv (reg. 6, bit 7) bits need to be set to 1. in auto mode, the lvds interrupt should be set low (reg. 1, bit 3) to allow the sample delay to be automati- cally updated if the threshold value is exceeded.
ad9734/ad9735/ad9736 rev. a | page 42 of 72 sync logic and controller a fifo structure is utilized to synchronize the data transfer between the dacclk and the dataclk_in clock domains. the sync controller writes data from db<13:0> into an 8-word memory register based on a cyclic write counter clocked by the dss, which is a delayed version of dacclk_in. the data is read out of the memory based on a second cyclic read counter clocked by dacclk. the 8-word fifo shown in figure 82 provides sufficient margin to maintain proper timing under most conditions. the sync logic is designed to prevent the read and write pointers from crossing. if the timing drifts far enough to require an update of the phase offset (phof<1:0>), two samples are duplicated or dropped. figure 83 shows the timing diagram for the sync logic. 8 word memory read counter phof<1:0> dacclk fifostat<2:0> dss m0 m7 zd dac<13:0> adder write counter ff dac<13:0> 04862-080 figure 82. sync logic block diagram sync logic and cont roller operation the relationship between the readout pointer and the write pointer initially is unknown because the startup relationship between dacclk and dataclk_in is unknown. the sync logic measures the relative phase between the two counters with the zero detect block and the flip-flop in figure 82. the relative phase is returned in fifostat<2:0> (reg. 7, bits 6:4), and sync logic errors are indicated by fifostat<3> (reg. 7, bit 7). if fifostat<2:0> returns a value of 0 or 7, the memory is sampling in a critical state (read and write pointers are close to crossing). if the fifostat<2:0> returns a value of 3 or 4, the memory is sampling at the optimal state (read and write pointers are farthest apart). if fifostat<2:0> returns a critical value, the pointer can be adjusted with the phase offset phof<1:0> (reg. 7, bits 1:0). due to the architecture of the fifo, the phase offset can only adjust the read pointer in steps of 2. operation in manual mode to start operating the dac in manual mode, allow dacclk and dataclk_in to stabilize, then enable fifo mode (reg. 0, bit 2). read fifostat<2:0> (reg. 7, bits 6:4) to determine if adjustment is needed. for example, if fifostat<2:0> = 6, the timing is not yet critical, but it is not optimal. to return to an optimal state (fifostat<2:0> = 4), the phof<1:0> (reg. 7, bits 1:0) needs to be set to 1. setting phof<1:0> = 1 effectively increments the read pointer by 2. this causes the write pointer value to be captured two clocks later, decreasing fifostat<2:0> from 6 to 4. operation in surveillance and auto modes once fifostat<2:0> is manually placed in an optimal state, the ad973x sync logic can run in surveillance or auto mode. to start, turn on surveillance mode by setting ssurv = 1 (reg. 8, bit 7), then enable the sync interrupt (reg. 1, bit 2). if strh<0> = 0 (reg. 8, bit 0), an interrupt occurs if fifostat<2:0> = 0 or 7. if strh<0> = 1 (reg. 8, bit 0), an interrupt occurs if fifostat<2:0> = 0, 1, 6, or 7. the interrupt is read at reg. 1, bit 6 at the ad973x irq pin. to enter auto mode, complete the preceding steps then set sauto = 1 (reg. 8, bit 6). next, set the sync interrupt = 0 (reg. 1, bit 2), to allow the phase offset (phof<1:0>) to be automatically updated if fifostat<2:0> violates the threshold value. the fifostat signal is filtered to improve noise immunity and reduce unnecessary phase offset updates. the filter operates with the following algorithm: fifostat = fifostat + fifostat/2 ^ sflt <3:0> where: 0 sflt <3:0> 12 values greater than 12 are set to 12. if sflt<3:0> is too small, clock jitter and noise can cause erratic behavior. normally, sflt can be set to the maximum value. fifo bypass when the fifo_mode bit (reg. 1, bit 2) is set to 0, the fifo is bypassed with a mux. when the fifo is enabled, the pipeline delay through the ad973x increa ses by the delta between the fifo read pointer and write pointer plus 4 more clock periods.
ad9734/ad9735/ad9736 rev. a | page 43 of 72 d internal delay dacclk dataclk_ou t dataclk_in data_in a a b b 01 2 3456701 234 5 670 45670 12 34 1 234 5670 c c d d e e f f g g h h i i j j k k l l m a b c d e f g h ijkl m m n n i a o o q p p qr dss1 dss2 d2 write_ptr1 safe zone data 'a' can be safely read from the fifo in the safe zone. in the error zone, the pointers may briefly overlap due to clock jitter or noise. fifostat is set equal to the write pointer each time the read pointer changes from 7 to 0. error zone m0 m1 b c e f g 4 4 4 h j m2 m3 m4 m5 m6 m7 read_ptr1 fifostat dac_data d1 external delay sample_hold sample_setup sample_delay 04862-081 figure 83. sync logic timing diagram
ad9734/ad9735/ad9736 rev. a | page 44 of 72 digital built-in self test (bist) overview the ad973x includes an internal signature generator that processes incoming data to create unique signatures. these signatures are read back from the spi port, allowing verification of correct data transfer into the ad973x. bist vectors provided on the ad973x-eb evaluation board cd check the full width data input or individual bits for pcb debug, utilizing the procedure in the ad973x bist procedure section. alterna- tively, any vector can be used provided the expected signature is calculated in advance. the matlab? routine, in the generating expected signatures section, calculates the expected signature. bist verifies correct data transfer because not all errors are always evident on a spectrum analyzer. there are four bist signature generators that can be read back using reg. 18 to reg. 21, based on the setting of the bist selection bits (reg. 17, bits 7:6), as shown in table 24. the bist signature returned from the ad973x depends on the digital input during the test. because the filters in the dac have memory, it is important to put the correct idle value on the data input to flush the memory prior to reading the bist signature. placing the idle value on the data input also allows the bist to be set up while the dac clock is running. the idle value should be all 0s in unsigned mode (0x0000) and all 0s except for the msb in twos complement mode (0x2000). the bist consists of two stages; the first stage is after the lvds receiver and the second stage is after the fifo. the first bist stage verifies correct sampling of the data from the lvds bus while the second bist stage verifies correct synchronization between the dac_clk domain and the dataclk_in domain. the bist vector is generated using 32-bit lfsr signature logic. because the internal architecture is a 2-bus parallel system, there are two 32-bit lfsr signature logic blocks on both the lvds and sync blocks. figure 84 shows where the lvds and sync phases are located. table 24. bist selection bits bit sel<1> sel<0> lvds phase 1 0 0 lvds phase 2 0 1 sync phase 1 1 0 sync phase 2 1 1 lvds rx db<13:0> dataclk_in sync logic fifo 2x d1 d 2 dac lvds bist ph1 (rise) lvds bist ph2 (fall) sync bist ph1 (rise) sync bist ph2 (fall) spi port 04862-082 figure 84. block diagram showing lvds and sync phase 1 and sync phase 2
ad9734/ad9735/ad9736 rev. a | page 45 of 72 ad973x bist procedure 1. set reset pin = 1. 2. set input data = 0x0000 for signed (0x2000 for unsigned). 3. enable dataclk_in if it is not already running. 4. run for at least 16 dataclk_in cycles. 5. set reset pin = 0. 6. run for at least 16 dataclk_in cycles. 7. set reset pin = 1. 8. run for at least 16 dataclk_in cycles. 9. set reset pin = 0. 10. set desired operating mode (1 mode and signed data are default values and expected for the supplied bist vectors). 11. set clear (reg. 17, bit 0), sync_en (reg. 17, bit 1), and lvds_en (reg. 17, bit 2) high. 12. wait 50 dataclk_in cycles to allow 0s to propagate through and clear sync signatures. 13. set clear low. 14. read all signature registers (r eg. 21, reg. 20, reg. 19, and reg. 18) for each of the four sel (reg. 17, bits 7:6) values and verify they are all 0x00. lvds phase 1 a. reg. 17 set to 0x26 (sel1 = 0, sel0 = 0, sig_read = 1, lvds_en = 1, sync_en = 1). b. read reg. 20, reg. 19, reg. 18, and reg. 17. lvds phase 2 a. reg. 17 set to 0x66 (sel1= 0, sel0 = 1, sig_read = 1, lvds_en = 1, sync_en = 1). b. read reg. 20, reg. 19, reg. 18, and reg. 17. sync phase 1 a. reg. 17 set to 0xa6 (sel1= 1, sel0 = 0, sig_read = 1, lvds_en = 1, sync_en = 1). b. read reg. 20, reg. 19, reg. 18, and reg. 17. sync phase 2 a. reg. 17 set to 0xe6 (sel1= 1, sel0 = 1, sig_read = 1, lvds_en = 1, sync_en = 1). b. read reg. 20, reg. 19, reg. 18, and reg. 17. 15. clock the bist vector into the ad973x. 16. after the bist vector is clocked into the part, hold data = 0x0000 for signed (0x2000 for unsigned); otherwise, the additional nonzero data changes the signature. 17. read all signature registers (r eg. 21, reg. 20, reg. 19, and reg. 18, as described in step 14 ) for each of the four sel (reg. 17, bits 7:6) values, and verify that they match the expected signatures shown in table 25. 18. flush the bist circuitry. this must be done once before valid data can be read. loop back to step 11 and rerun the test to obtain the correct result. each time bist mode is entered, this flush needs to be performed once. multiple bist runs can be performed without reflushing, as long as the device remains in bist mode. ad973x expected bist signatures the bist vectors provided on the ad973x-eb cd are in signed mode, so no programming is necessary for the part to pass the bist. the bist vector is for 1, no fifo, and signed data. for testing all 14 input bits, use the vector all_bits_unsnew.txt and verify against the signatures in table 25. table 25. expected bist da ta readback for all bits lvds phase 1 lvds phase 2 sync phase 1 sync phase 2 cf71487c 66df5250 cf71487c 66df5250 for individual bit tests, use the vectors named bit n .txt (where n is the desired bit number being tested) and compare them against the values in table 26. table 26. expected bist data readback for individual bits vector bit number lvds rise expected lvds fall expected bit0.txt 0 aabf0a00 2a400500 bit1.txt 1 2bbf0a00 6b400500 bit2.txt 2 29be0a00 e9400500 bit3.txt 3 2dbc0a00 ed410500 bit4.txt 4 25b80a00 e5430500 bit5.txt 5 35b00a00 f5470500 bit6.txt 6 15a00a00 d54f0500 bit7.txt 7 55800a00 955f0500 bit8.txt 8 d5c00a00 157f0500 bit9.txt 9 d5410a00 153e0500 bit10.txt 10 d5430b00 15bc0500 bit11.txt 11 d5470900 15b80400 bit12.txt 12 d54f0d00 15b00600 bit13.txt 13 d55f0500 15a00200 note the following for table 26: ? the term rise refers to phase 1 and fall refers to phase 2. ? byte order is decimal register address 21, address 20, address 19, and address 18. ? sync phase should always equal lvds phase in 1 mode.
ad9734/ad9735/ad9736 rev. a | page 46 of 72 generating expected signatures the following matlab code duplicates the internal logic of the ad973x. to use it, save this code in a file called bist.m. --- begin bist.m --- function [ ret1 , ret2] = bist(vec) ret1 = bist1(vec(1:2:length(vec)-1)); ret2 = bist1(vec(2:2:length(vec))); function ret = bist1(v) sum = zeros(1,32); for i = 1 :length(v) if v(i) ~= 0 su(1) = ~xor(sum(32) ,bitget(v(i),1)); su(2) = ~xor(sum(1) ,bitget(v(i),2)); su(3) = ~xor(sum(2) ,bitget(v(i),3)); su(4) = ~xor(sum(3) ,bitget(v(i),4)); su(5) = ~xor(sum(4) ,bitget(v(i),5)); su(6) = ~xor(sum(5) ,bitget(v(i),6)); su(7) = ~xor(sum(6) ,bitget(v(i),7)); su(8) = ~xor(sum(7) ,bitget(v(i),8)); su(9) = ~xor(sum(8) ,bitget(v(i),9)); su(10) = ~xor(sum(9) ,bitget(v(i),10)); su(11) = ~xor(sum(10) ,bitget(v(i),11)); su(12) = ~xor(sum(11) ,bitget(v(i),12)); su(13) = ~xor(sum(12) ,bitget(v(i),13)); su(14) = ~xor(sum(13) ,bitget(v(i),14)); su(15) = sum(14); su(16) = sum(15); su(17) = sum(16); su(18) = sum(17); su(19) = sum(18); su(20) = sum(19); su(21) = sum(20); su(22) = sum(21); su(23) = sum(22); su(24) = sum(23); su(25) = sum(24); su(26) = sum(25); su(27) = sum(26); su(28) = sum(27); su(29) = sum(28); su(30) = sum(29); su(31) = sum(30); su(32) = sum(31); sum = su; end end % for ret = dec2hex( 2.^[0:31] sum',8); --- end bist.m --- to generate the expected bist signatures, follow this procedure: 1. start matlab and type the following at the command prompt: t = round(randn(1,100) 2 13 /8+2 13 ) ; [ b1 b2 ] = bist(t) the first statement creates a random vector of 14-bit words, with a length of 100. 2. set t equal to any desired vector, or take this random vector and input it to the ad973x. 3. alter the command randn(1,100) to change the vector length as desired. 4. type b1 at the command line to see the calculated signature for the lvds bist, phase 1. 5. type b2 to see the value for lvds bist, phase 2. the values returned for b1 and b2 each are 32-bit hex values. they correspond to reg. 18, reg. 19, reg. 20, and reg. 21, where b1 is the value read for sel<1:0> = 0, 0 (see table 17) and b2 is the value read for sel<1:0> = 0, 1. when the dac is in 1 mode, the signature at sync bist, phase 1 should equal the signature at lvds bist, phase 1. the same is true for phase 2.
ad9734/ad9735/ad9736 rev. a | page 47 of 72 cross controller registers the ad973x differential output stage is adjustable to equalize the charge injection into the positive and negative outputs. this adjustment impacts certain performance characteristics, such as harmonic distortion or imd. system performance can be en- hanced by adjusting the cross controller. if the system is calibrated after manufacture, adjust the cross controller offsets to provide optimum performance. to start, increment dndel<5:0> (reg. 11, bits 5:0) while observing hd2 (second harmonic distortion) and/or imd to find the desired optimum. if dndel does not influence the perform- ance, set it to 0 and increment updel<5:0> (reg. 10, bits 5:0). based on system characterization, set one of these controls to the maximum value to yield the best performance. figure 85 shows the effect of updel and dndel. 04862-083 increment dndel to move the crossing toward the ideal value ideal differential output crossing alignment increment updel to move the crossing toward the ideal value figure 85. effect of updel and dndel
ad9734/ad9735/ad9736 rev. a | page 48 of 72 analog control registers the ad973x includes some registers for optimizing its analog performance. these registers include temperature trim for the band gap, noise reduction in the output current mirror, and output current mirror headroom adjustments. band gap temperature characteristic trim bits using trmbg<2:0> (reg. 14, bits 2:0), the temperature characteristic of the internal band gap can be trimmed to minimize the drift over temperature, as shown in figure 86. ?50 ?40 ?30 ?20 ? 1 0 010203040506070 8090 temperature ( c) vref (v) 1.23 1.22 1.21 1.2 1.19 1.18 04862-084 000 010 001 011 101 110 111 100 figure 86. band gap temperature characteristic for various trmbg values the temperature changes are sensitive to process variations, and figure 86 may not be representative of all fabrication lots. optimum adjustment requires measurement of the device operation at two temperatures and development of a trim algorithm to program the correct trmbg<2:0> values in external nonvolatile memory. mirror roll-off frequency control with msel <1:0> (reg. 14, bits 7:6), the user can adjust the noise contribution of the internal current mirror to optimize the 1/f noise. figure 87 shows msel vs. the 1/f noise with 20 ma full-scale current into a 50 resistor. f (khz) noise (idbm/hz) ? 110 ?115 ?120 ?125 ?130 ?140 ?135 1 10 100 04862-0-085 m s e l 0 m s e l 2 m s e l 1 m s e l 3 figure 87. 1/f noise with respect to msel bits headroom bits hdrm<7:0> (reg. 15, bits 7:0) are for internal evaluation. changing the default reset values is not recommended. voltage reference the ad973x output current is set by a combination of digital control bits and the i120 reference current, as shown in figure 88. current scaling fsc<9:0> ad973x dac ifull-scale 10k 1nf v ref i120 avss i120 v bg 1.2v + ? 04862-086 figure 88. voltage reference circuit the reference current is obtained by forcing the band gap voltage across an external 10 k resistor from i120 (pin b14) to ground. the 1.2 v nominal band gap voltage (v ref ) generates a 120 a reference current in the 10 k resistor. this current is adjusted digitally by fsc<9:0> (reg. 2, reg. 3) to set the output full-scale current i fs : ? ? ? ? ? ? ? ? ? ? ? ? > < + = 0 . 9 1024 192 72 fsc r v i ref fs
ad9734/ad9735/ad9736 rev. a | page 49 of 72 the full-scale output current range is approximately 10 ma to 30 ma for register values from 0x000 to 0x3ff. the default value of 0x200 generates 20 ma full scale. the typical range is shown in figure 89. 35 30 25 20 i fs (ma) 15 10 5 0 0 200 400 600 800 dac gain code 1000 04862-087 figure 89. i fs vs. dac gain code always connect a 10 k resistor from the i120 pin to ground and use the digital controls to vary the full-scale current. the ad973x is not a multiplying dac. applying an analog signal to i120 is not supported. vref (pin c14) must be bypassed to ground with a 1 nf capacitor. the band gap voltage is present on this pin and can be buffered for use in external circuitry. the typical output impedance is near 5 k. if desired, an external reference can be used to overdrive the internal reference by connecting it to the vref pin. iptat (pin d14) is used for factory testing. leave this pin floating.
ad9734/ad9735/ad9736 rev. a | page 50 of 72 applications information driving the dacclk input the dacclk input requires a low jitter differential drive signal. it is a pmos input differential pair powered from the 1.8 v supply, so it is important to maintain the specified 400 mv input common-mode voltage. each input pin can safely swing from 200 mv p-p to 800 mv p-p about the 400 mv common- mode voltage. while these input levels are not directly lvds compatible, dacclk can be driven by an offset ac-coupled lvds signal, as shown in figure 90. 04862-088 lvds_p_in clk+ 50 50 0.1 f 0.1 f lvds_n_in clk? v cm = 400mv figure 90. lvds dacclk drive circuit if a clean sine clock is available, it can be transformer-coupled to dacclk, as shown in figure 107. use of a cmos or ttl clock can also be acceptable for lower sample rates. it is routed through a cmos to lvds translator, then ac-coupled, as described previously. alternatively, it can be transformer- coupled and clamped, as shown in figure 91. 04862-089 50 50 ttl or cmos clk input clk+ clk? v cm = 400mv bav99zxct high speed dual diode 0.1 f figure 91. ttl or cmos dacclk drive circuit a simple bias network for generating v cm is shown in figure 92. it is important to use cvdd18 and cvss for the clock bias circuit. any noise or other signal that is coupled onto the clock is multiplied by the dac digital input signal and may degrade the dac performance. 0 4862-090 0.1f 1nf 1nf v cm = 400m v cvdd 1.8v cvss 1k ? 2 87 ? figure 92. dacclk v cm generator circuit
ad9734/ad9735/ad9736 rev. a | page 51 of 72 dac output distortion sources the second harmonic is mostly due to an imbalance in the output load. the dc transfer characteristic of the dac is capable of second harmonic distortion of at least ?75 dbc. output load imbalance or digital data noise coupling onto dacclk causes additional second harmonic distortion. the dac architecture inherently generates third harmonics, the levels of which depend on the output frequency and amplitude generated. if any output signal is rectified and coupled back onto the dac clock, it can generate additional third-harmonic energy. the distortion components should be identical in amplitude and phase at both ad973x outputs. even though each single- ended output includes a large amount of second-harmonic energy, a careful differential-to-single-ended conversion can remove most of it. optimum performance at high intermediate frequency (if) output is obtained with the output circuit shown in figure 93. this is the configuration implemented on the evaluation board ( figure 107). the 20 series resistors allow the dac to drive a less reactive load, which improves distortion. further improvement is realized by adding the balun t3 to help provide an equal load to both dac outputs. 04862-091 iouta ioutb j2, 50 output avss r17 20 156 5 1 3443 r19 20 t3 t1 avss r8 50 r6 50 figure 93. if signal output circuit because t1 has a differential input, but a single-ended output, pin 4 of t1 has a higher capacitance to ground due to parasitics to pin 3. t1 pin 6 has lower parasitic capacitance to ground because it drives 50 at pin 1. this presents an unbalanced load to the dac output, so t3 is added to improve the load balancing. refer to figure 107 for the transformer part numbers.
ad9734/ad9735/ad9736 rev. a | page 52 of 72 dc-coupled dac output in some cases, it may be desirable to dc-couple the ad973x output. the best method for doing this is shown in figure 94. this circuit can be used with voltage or current feedback amplifiers. because the dac output current is driving a virtual ground, this circuit may offer enhanced settling times. the settling time is limited by the op amp rather than by the dac. this circuit is intended for use where the amplifiers can be powered by a bipolar supply. 04862-092 iouta dac output 20ma full scale ioutb 100 100 100 500 500 100 500 500 avss avss output 2v p-p +1v to ?1v 2v p-p 0v to ?2v figure 94. op amp i to v conversion output circuit an alternate circuit is shown in figure 95. it suffers from dc offset at the output unless the dac load resistors are small, relative to the amplifier gain and feedback resistors. 04862-093 iouta output avss ioutb 25 25 2k avss 2k 1k 1k dac output 20ma full scale 2v p-p 0v to ?2v 0.5v p-p 0v to ?0.5v figure 95. differential op amp output circuit
ad9734/ad9735/ad9736 rev. a | page 53 of 72 dac data sources the circuit shown in figure 96 allows optimum data alignment when running the ad973x at full speed. this circuit can be easily implemented in the fpga or asic used to drive the digital input. it is important to use the dataclk_out signal because it helps to cancel some of the timing errors. in this configuration, dataclk_out generates the ddr lvds dataclk_in to drive the ad973x. the circuit aligns the dataclk_in and the digital input data (db<13:0>) as required by the ad973x. the lvds controller in the ad973x uses dataclk_in to generate the internal dss to capture the incoming data in the center of the valid data window. 04862-094 mux mux d1 dataclk_out from ad9736 (ddr) dataclk_in to ad9736 (ddr) db(13:0) to ad9736 data source logic 0 logic 1 data2 data1 d2 figure 96. recommended fpga/asic configuration for driving ad9736 digital inputs, 1 mode 04862-095 data1 data2 ac ac e b abc d b d d1 d2 db dataclk_out+ dataclk_in+ figure 97. fpga/asic timing for driving ad973x digital inputs, 1 mode to operate in 2 mode, the circuit in figure 96 must be modified to include a divide-by-2 block in the path of dataclk_out. without this additional divider, the data and dataclk_in runs 2 too fast. dataclk_out is always dacclk/2. contact fpga vendors directly regarding the maximum output data rates supported by their products. 04862-096 mux mux d1 dataclk_out from ad9736 (ddr) dataclk_in to ad9736 (ddr) db(13:0) to ad9736 data source logic 1 logic 0 data2 data1 d2 2 figure 98. recommended fpga/asic configuration for driving ad9736 digital inputs, 2 mode 04862-097 clk_out+/2 data2 data1 ac ac e b abc d b d d1 d2 db dataclk_out+ dataclk_in+ figure 99. fpga/asic timing for driving ad973x digital inputs, 2 mode
ad9734/ad9735/ad9736 rev. a | page 54 of 72 input data timing the ad973x is intended to operate with the lvds and sync controllers running to compensate for timing drift due to voltage and temperature variations. in this mode, the key to correct data capture is to present valid data for a minimum amount of time. the ad973x minimum valid data time is measured by increasing the input data rate to the point of failure. the nominal supply voltages are used and the temperature is set to the worst case of 85c. the input data is verified via the bist signature registers, because the dac output does not run as fast as the input data logic. the following example explains how the minimum data valid period is calculated for the typical performance case. these factors must be considered in determining the minimum valid data window at the receiver input: ? data rise and fall times: 100 ps (rise + fall) ? internal clock jitter: 10 ps (dataclk_out + dataclk_in) ? bit-to-bit skew: 50 ps ? bit-to-dataclk_in skew: 50 ps ? internal data sampling signal resolution: 80 ps for nominal silicon, the bist typically indicates failure at 2.15 gsps or a dacclk period of 465 ps. the valid data window is calculated by subtracting all the other variables from the total data period: minimum data valid time = dacclk period ? data rise ? data fall ? jitter ? bit-to-bit skew ? bit-to-dataclk_in skew ? data sampling signal resolution for the 400 mv p-p lvds signal case: minimum data valid = 465 ps ? 100 ps ? 10 ps ? 50 ps ? 80 ps = 465 ps ? 240 ps = 225 ps for correct data capture, the input data must be valid for 225 ps. slower edges, more jitter, or more skew require an increase in the clock period to maintain the minimum data valid period. table 27 shows the typical minimum data valid period (t mde ) for 400 mv p-p differential and 250 mv p-p differential lvds swings. the ability of the ad973x to capture incoming data is dependent on the speed of the silicon, which varies from lot to lot. the typical (or average) silicon speed operates with data that is valid for 225 ps at 85c. statistically, the worst extreme for slow silicon may require up to a 344 ps valid data period, as specified in table 2. table 27. typical mini mum data valid times differential input voltage bist max f cl min clock period typ min data valid at receiver 400 mv 2.15 ghz 465 ps 225 ps 250 mv 2.00 ghz 500 ps 260 ps at 1.2 ghz, the typical 400 mv p-p minimum data valid period of 225 ps leaves 608 ps for external factors. under the same conditions, the worst expected minimum data valid period of 344 ps leaves 489 ps for external data uncertainty. the 100 mv lvds v od threshold test is a dc test to verify that the input logic state changes. it does not indicate the operating speed. the ability of the receiver to recover the data depends on the input signal overdrive. with a 250 mv input, there is a 150 mv overdrive, and with a 400 mv signal, there is a 300 mv overdrive. the relationship between overdrive level and timing is very nonlinear. higher levels of overdrive result in smaller minimum valid data windows. for typical silicon, decreasing the lvds swing from 400 mv p-p to 250 mv p-p requires the minimum data valid period to increase by 15%. this is illustrated in figure 100. 225ps 400mv 260ps 250mv 04862-098 figure 100. typical minimum valid data time (t mde ) vs. lvds swing the minimum valid data window changes with temperature, voltage, and process. the maximum value presented in the specification table was determined from a 6 distribution in the worst-case conditions.
ad9734/ad9735/ad9736 rev. a | page 55 of 72 synchronization timing when more than one ad973x must be synchronized or when a constant group delay must be maintained, the internal controllers cannot be used. if the fifo is enabled, the delay between multiple ad973x devices is unknown. if the dataclk_out from multiple devices is used, there is an uncertainty of two dacclk periods because the initial phase of dataclk_out with respect to dacclk cannot be controlled. this means one dac must be used to provide dataclk_out for all synchronized dacs and all timing must be externally managed. the following timing information allows system timing to be calculated so that multiple ad973xs can be synchronized. dataclk_out changes relative to the rising edge of dacclk+ and is delayed, as shown in figure 101. because dacclk is divided by 2 to create dataclk_out, the phase of dataclk_out can be 0 or 180. there is no way to predict or control this relationship. it can be different after each power cycle and is not affected by hardware or software resets. t ddco dacclk dataclk_out 04862-099 figure 101. dacclk to dataclk_out delay the incoming data is de-interleaved internally as shown in figure 78. in figure 78, dbu (upper) and dbl (lower) represent the de-interleaved data paths. each edge of dataclk_in latches an incoming sample in two alternating registers. the dataclk_in to data setup and hold definitions are illustrated in figure 102. all the data input must be valid during the setup- and-hold period. external skew effectively increases the setup and hold times that the data source must meet. 04862-100 dataclk_in or dataclk_out data_in t dh t dsu figure 102. standard definitions for dataclk_in or dataclk_out to data setup and hold, sd = 0 while correct data_in vs. dataclk_in timing is critical, the transition of the incoming data to the dacclk domain is equally critical. by referencing the incoming data and dataclk_in timing to the dataclk_out signal, some timing uncertainty can be removed. the dataclk_out timing very closely tracks the timing of the dacclk- controlled registers. any variation in the path delay affects both paths in almost the same way. if dataclk_out is not used, the full dacclk to dataclk_out path variation reduces the external timing margin. figure 101 shows a simplified view of the internal clocking scheme with the relevant delay paths. the internal architecture is interleaved such that each phase has twice as long to make the transition across the clock domains. this results in an extremely narrow window where the incoming data must be held stable. table 28 shows the timing parameters for figure 101 and figure 102. these parameters were measured for a sample of five devices from five silicon lots. worst-case fast and slow skew lots were included in addition to the nominal (or average) lot. the typical ?40c to typical +85c spread illustrates the variability with temperature for a single lot. adding in lot-to-lot variation with the fast and slow lots indicates the worst-case spread in timing. the timing varies such that all of the parameters move in the same direction. for example, if the dataclk_in to data setup time is fast, the hold time is similarly fast. the dacclk to dataclk_out delay and the dataclk_out to data setup and hold is also at the fast end of the range. note that the polarities of setup-and-hold values in table 28 conform to the standard convention of setup time occurring prior to the latching edge and hold time occurring after the latching edge, as shown in figure 102. table 28. ad973x clock and data timing parameters symbol and definition fast 40c typ 40c all 25c typ 85c slow 85c nit t ddco ? dacclk to dataclk_out delay +1650 +1800 +1890 +2050 +2350 ps t dcisu ? dataclk_in to data setup ?100 ?120 ?150 ?170 ?220 ps t dcih ? dataclk_in to data hold +210 +220 +240 +280 +360 ps t disu ? dataclk_out to data setup + 1310 +1440 +1611 +1710 +1970 ps t dih ? dataclk_out to data hold ?1250 ?1360 ?1548 ?1640 ?1890 ps
ad9734/ad9735/ad9736 rev. a | page 56 of 72 power supply sequencing the 1.8 v supplies should be enabled prior to enabling the 3.3 v supplies. do not enable the 3.3 v supplies when the 1.8 v supplies are off. 04862-101 lvds rx dataclk_in dataclk_in domain dacclk domain db<13:0> path a path b dataclk_out d1a dac_data dac_output d1 d2 d2a sd<3:0> sample delay dacclk ff ff 2 clk rx ff ff sd<3:0> sample delay data sampling signal dac sampling signal common system clock delays through path a and b will track, thus reducing timing uncertainty in the system lvds rx lvds tx dac core figure 103. simplified internal clock routing
ad9734/ad9735/ad9736 rev. a | page 57 of 72 ad973 x evaluation board schematics l1, l3, l4, l5, l6, and l7 ferrite bead core: panasonic exc?cl3225u1 digikey pn: p9811ct?nd vss tp5 blk 33dig vss tb1 1 tb1 2 l6 ferrite tp4 red vdd33 lc1210 c14 10 f 6.3v acase + vssa tp3 blk 33ana vssa tb2 1 tb2 2 l1 ferrite tp1 red vdda33 lc1210 c1 10 f 6.3v acase + vssa tp11 blk 18ana vssa tb2 3 tb2 4 l3 ferrite tp9 red vddc lc1210 c10 10 f 6.3v l4 ferrite lc1210 acase + vss tp13 blk tp6 red tp14 blk vdd18a vdd18b vss tp7 red c22 10 f 6.3v l7 ferrite lc1210 l5 ferrite lc1210 18dig tb1 3 vss tb1 4 acase + c18 10 f 6.3v acase + power input filters vssa vss under dut jp1 04862?102 figure 104. power supply input for ad973x evaluation board, rev. f
ad9734/ad9735/ad9736 rev. a | page 58 of 72 04862-103 in1 in2 in3 in4 ip1 a8 b8 c8 d8 a9 c19 4.7 f 6.3v vssa vdd18b vss c23 4.7 f 6.3v c24 0.1 f c25 1nf h1 vdd1 vdd2 vdd3 vdd5 vdd4 vdd6 vdd7 vdd8 vss1 vss2 vss3 vss4 vss5 vss6 vss7 vss8 vss9 vss10 vss21 nck1 vss22 vdd16 vdd15 vdd14 vdd12 vdd13 vdd11 vdd10 vdd9 vss20 vss19 vss18 vss17 vss16 vss15 vss14 vss13 vss12 v s s 1 1 lvds13n lvds13p lvds12n lvds12p lvds11n lvds11p lvds10n lvds10p lvds9n lvds9p lvds8n lvds8p lvds7n lvds7p lvds6n lvds6p vdd338 vdd337 vdd336 vdd335 spi_mode lvds0n lvds0p lvds1n lvds1p lvds2n lvds2p lvds3n lvds3p lvds4n lvds4p lvds5n lvds5p lvdsclkoutn lvdsclkoutp lvdsclkinn lvdsclkinp vdd331 vdd332 vdd333 vdd334 bottom h2 h3 h4 j1 j2 j3 j4 k3 k4 l3 l4 l5 l6 m3 m4 m5 m6 k2 k1 l2 l1 m2 m1 n1 p1 n2 n3 p2 p3 n4 p4 n5 p5 n6 p 6 l7 m7 n7 p7 h14 h13 h12 h11 j14 j13 j12 j11 k11 k12 l9 l10 l11 l12 m9 m10 m11 m12 k13 k14 l13 l14 m13 m14 n14 p14 n13 n12 p13 p12 n11 p11 n10 p10 n9 p 9 l8 m8 n8 p8 vss c34 dnp c20 0.1 f c21 1nf vdd18a c7 dnp vss vdd33 jp15 jp8 a 2 3 b c6 dnp irq iptat spare c9 1nf r16 10k tp2 wht tp12 wht wht tp8 wht tp10 tp16 wht jp4 irq reset_a reset spcsb spsdi jp3 4 3 sw1 vdd33 vss;5 vss spclk spsdo vref i120 vdd33 c15 4.7 f 6.3v c16 0.1 f c17 1nf cc060 a10 a11 b9 b10 b11 c9 c10 c11 d9 d10 d11 a12 a13 b12 b13 c12 c13 d12 d13 a14 ip2 ip3 ip4 top 3 3 d d v a5 a4 vssa331 vssa332 vssa333 vssa334 vssa335 vssa336 vssa337 vssa338 vssa339 vssa3310 vssa3311 vssa3312 vddc1 vddc2 vddc3 vddc4 vddc5 vddc6 vddc7 vddc8 vddc9 vddc11 vddc10 vssc1 clkn clkp vssc2 vssc3 vssc4 vssc5 vssc6 vssc7 vssc8 vssc9 vssc10 vssc11 vdda331 vdda332 vdda333 vdda334 vdda335 vdda336 vdda337 vdda338 spare i 1 2 0 vref iptat signed_irq pd_reset 2x_csb fifo_sdio fsc0_sclk fsc1_sdo shield1 shield2 shield3 shield4 shield5 shield6 hydrogen u1 u1 hydrogen vssa r5 10k rc1206 vssa3314 vssa3313 vssa3315 vssa3316 vssa3317 vssa3318 vssa3319 vssa3320 vssa3321 vssa3322 vssa3323 vssa3324 b4 d6 d5 d4 c6 c5 c4 d1 e1 f1 e2 e3 e4 f2 f3 f4 g1 g2 g3 g4 d3 c2 c1 b2 b1 a3 a2 d2 d14 e13 e14 f13 f14 g13 g14 e11 e12 f11 f12 g11 g12 c14 b14 a6 b5 a1 c5 cc063 dnp c3 b6 b3 s s v 1 2 db0n c8 dnp db0p db1n db1p db2n db2p db3n db3p db4n db4p db5n db5p db6n db6p db7n db7p dclknin dclkpin in ip ad9736 ad9736 a7 b7 c7 d7 clkn clkp vddc c11 6.3v vssa 4.7 f c12 0.1 f c13 1nf acase cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 vssa vssa db13n db13p db12n db12p db11n db11p db10n db10p db9n db9p db8n db8p dclknout dclkpout r1 0.1% 10k cc0603 rc0603 cc0603 cc0603 cc0603 cc0603 a 2 1 1 3 b acase acase acase acase note: ad9736 msb ?lsb bit order is reversed from the connector bit order. c4 1nf c3 0.1 f c2 4.7 f 6.3v vdda33 figure 105. circuitry local to ad973x, evaluation board, rev. f
ad9734/ad9735/ad9736 rev. a | page 59 of 72 db13n db12n db13p db12p vss db11p db10p db8p db7p db7n db6n db0n db1n db2n db3n db4n db5n db0p db1p db2p db3p db4p db5p g2 s2 g3 g4 s3 s4 g5 g6 s5 s6 g7 g8 s7 s8 g9 g10 s9 s10 g11 g12 s11 s12 g13 g14 s13 s14 g15 g16 s15 s16 g17 g18 s17 s18 g19 g20 s19 s20 g21 g22 s21 s22 g23 g24 s23 s24 g25 g26 s25 s26 g27 g28 s27 s28 g29 g30 s29 s30 g31 g32 s31 s32 g33 g34 s33 s34 g35 g36 s35 s36 g37 g38 s37 s38 g39 g40 s39 s40 g41 g42 s41 s42 g43 g44 s43 s44 g45 g46 s45 s46 g47 g48 s47 s48 g49 g50 g1 s1 j3 dclknin dclknout db8n db9n db10n db11n db6p dclkpin dclkpout db9p testoutn extclk testoutp note: ad9736 msb-lsb bit order is reversed from the connector bit order. connector db13 db0 ad9736 db0 db13 tp15 wht jack jack fcn?268 f024?g/0 d 04862?104 figure 106. high speed digital i/o connector, ad973x evaluation board, rev. f
ad9734/ad9735/ad9736 rev. a | page 60 of 72 s p sp vssa 6 5 3 4 2 1 1 4 3 6 j2 r4 300 3 1 5 4 415mv common mode voltage 400mv p?p note: t1, t3, and t3b are installed, r6 and r8 = 50 , r7 = dnp r17 and r19 = 20 , r161 and r162 = 0 , jumper added from t1 pin 3 to t1 pin 2 on the rev. c eval board. j1 vssa;3,4,5 sma200up vssa t3a t3b t3 adtl1?12xx etc1?1?13 s p nc=2 etc1?1?13 etc1?1?13 t2 adt2?1t?1p 4 5 1 3 p s nc=2 c35 c36 0.1 f 0.1 f cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 cc0603 r20 r21 r3 1k r6 50 c26 dnp c27 dnp c38 1nf c29 1nf c28 0.1 f clkp clkn vddc vssa 25 25 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 r7 dnp r17 20 r161 0 r162 0 r18 dnp r19 20 rc0603 r8 50 rc0603 rc0603 an lvds signal may be used to drive c35 and c36 if r20 and r21 are increased to 50 each. r17 and r19 can be removed and t1 replaced with a 1:1 transformer for higher output amplitude if more h2 is acceptable (typically at lower f out ). r17 and r19 present a more real load to the dac which improves h2 performance. t2 and t4b are not populated t1:mini-circuits ?3db: 8-600mhz ?1db: 13-300mhz this configuration provides optimum ac performance for if signal generation. typical signal levels shown for 50 load. vssa vssa vssa vssa in ip t3:m/a-com ?1db: 4.5-1000mhz sp 6 5 3 4 2 1 t4b t1 adt2?1t?1p 4 5 3 1 p s nc=2 vssa;3,4,5 sma200up 04862?105 t3a is not populated figure 107. clock input and analog output, ad973x evaluation board, rev. f
ad9734/ad9735/ad9736 rev. a | page 61 of 72 irq reset_a 2 rc0603 rc0603 2 b 3 1 2 l9 6 1 2 4 5 3 p1 vss l8 rc0805 9k r11 rc0805 9k r10 rc0805 9k r12 3 3 d d v vss vss vss vss vss vss use these jumpers to set pin_mode control signals or connect spi port signals in spi_mode. vdd33 vdd33 vdd33 vdd33 vdd33 vdd33 spcsb spclk spsdi spsdo jp13 jp6 jp7 jp2 jp5 jp14 jp9 jp10 jp12 jp11 a b 3 1 2 a b 3 1 2 a b 3 1 2 a b 3 1 2 a b 3 1 2 a r13 10k r14 10k lc1210 lc1210 ferrite ferrite ferrite bead core: panasonic exc-cl3225u1 digikey pn: p9811ct-nd 74ac14 1 2 u5 vss;7 vdd33;14 74ac14 3 4 u5 vss;7 vdd33;14 74ac14 5 6 u5 vss;7 vdd33;14 74ac14 4 3 u6 vss;7 vdd33;14 74ac14 6 5 u6 vss;7 vdd33;14 74ac14 12 13 u6 vss;7 vdd33;14 74ac14 2 1 u6 vss;7 vdd33;14 74ac14 13 12 u5 vss;7 vdd33;14 74ac14 11 10 u5 vss;7 vdd33;14 74ac14 9 8 u5 vss;7 vdd33;14 vss 74ac14 10 11 u6 vss;7 vdd33;14 74ac14 8 9 u6 vss;7 vdd33;14 acase cc0805 + c30 4.7 f 6.3v c31 0.1 f acase cc0805 + c32 4.7 f 6.3v c33 0.1 f spi port 04862?106 figure 108. spi port interface, ad973x evaluation board, rev. f
ad9734/ad9735/ad9736 rev. a | page 62 of 72 ad973 x evaluation board pcb layout 04862-107 silkscreen error: spi and pin are reversed. note: the ad9736 is soldered directly to the pcb. the socket is not installed. figure 109. cb layout top placement, ad973x evaluation board, rev. f
ad9734/ad9735/ad9736 rev. a | page 63 of 72 04860-108 figure 110. pcb layout layer 1, ad973x evaluation board, rev. f
ad9734/ad9735/ad9736 rev. a | page 64 of 72 04861-109 figure 111. pcb layout layer 2, ad973x evaluation board, rev. f
ad9734/ad9735/ad9736 rev. a | page 65 of 72 04862-110 figure 112. pcb layout layer 3, ad973x evaluation board, rev. f
ad9734/ad9735/ad9736 rev. a | page 66 of 72 014862-111 figure 113. pcb layout layer 4, ad973x evaluation board, rev. f
ad9734/ad9735/ad9736 rev. a | page 67 of 72 04862-112 figure 114. pcb layout bottom placemen t, ad973x evaluation board, rev. f
ad9734/ad9735/ad9736 rev. a | page 68 of 72 04862-113 notes 1. material: four layer, fr4 glass?epoxy laminate .062 +/- .007 thick 1/4 oz. copper clad ? external layers plated to 1 ounce 2 oz. copper clad ? internal layers 2. plated thru holes and the conductive pattern electroplated with .001 inch min. thick copper. terminal areas and exposed plated thru holes to b e coated with solder and hot air leveled. 3. processing tolerances: a. conductive pattern fron to back registration +/? .002 inch total b. minimum annular ring surrounding holes .002 inch. c. finished conductive pattern +/? .0005 inch of aperture size. 4. warp and twist +/? .005 inch per inch. 5. dimentions: are for the finished part 6. solder mask: liquid photo imagable solder mask color green, both sides using the pattern(s) provided. no mask is permitted on the exposed areas. solder mask to etch registration +/? .002 inch total 7. screening: screen component outlines and nomenclature using opaque white ink on the primary and secondary sides (as required). nomenclature shall be legible. screen to etch registration +/? .005 inch total. 8. surfaces: punched or machined surfaces 125 micro inches rms max. 9. break all sharp edges .015 r max. 10. fabrication vendor to add ul vendor id number in this area on the secondary side 11. do not drill. for gold plated socketed version only. figure 115. pcb fabrication detail, ad973x evaluation board, rev. f
ad9734/ad9735/ad9736 rev. a | page 69 of 72 outline dimensions 12.10 12.00 sq 11.90 seating plane 0.43 max 0.25 min detail a 0.55 0.50 0.45 0.12 max coplanarity 1.00 max 0.85 min ball diameter 0.80 bsc 0.80 ref 10.40 bsc sq a b c d e f g h j k l m n p 14 13 12 11 10 8 7 6 3 2 1 95 4 a 1 corne r index area top view ball a1 indicator detail a bottom view 1.40 max compliant to jedec standards mo-205-ae. figure 116. 160-lead chip scale package ball grid array [csp_bga] (bc-160-1) dimensions shown in millimeters ordering guide model temperature range package description package option ad9734bbc ?40c to +85c 160-lead chip scale package ball grid array (csp_bga) bc-160-1 ad9734bbcrl ?40c to +85c 160-lead chip scale package ball grid array (csp_bga) bc-160-1 ad9734bbcz 1 ?40c to +85c 160-lead chip scale package ball grid array (csp_bga) bc-160-1 ad9734bbczrl 1 ?40c to +85c 160-lead chip scale package ball grid array (csp_bga) bc-160-1 ad9735bbc ?40c to +85c 160-lead chip scale package ball grid array (csp_bga) bc-160-1 ad9735bbcz 1 ?40c to +85c 160-lead chip scale package ball grid array (csp_bga) bc-160-1 AD9735BBCRL ?40c to +85c 160-lead chip scale package ball grid array (csp_bga) bc-160-1 ad9735bbczrl 1 ?40c to +85c 160-lead chip scale package ball grid array (csp_bga) bc-160-1 ad9736bbc ?40c to +85c 160-lead chip scale package ball grid array (csp_bga) bc-160-1 ad9736bbcrl ?40c to +85c 160-lead chip scale package ball grid array (csp_bga) bc-160-1 ad9736bbcz 1 ?40c to +85c 160-lead chip scale package ball grid array (csp_bga) bc-160-1 ad9736bbczrl 1 ?40c to +85c 160-lead chip scale package ball grid array (csp_bga) bc-160-1 ad9734-eb evaluation board ad9735-eb evaluation board ad9736-eb evaluation board 1 z = pb-free part.
ad9734/ad9735/ad9736 rev. a | page 70 of 72 notes
ad9734/ad9735/ad9736 rev. a | page 71 of 72 notes
ad9734/ad9735/ad9736 rev. a | page 72 of 72 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04862-0-9/06(a)

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