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| 6-bit programmable 2-/3-/4-phase synchronous buck controller adp3188 features selectable 2-, 3 - or 4-phase op eration at up t o 1 mhz per phase 9.5 m v worst-case differ e nti a l sensing erro r over temperature logic-level pw m outputs for i n terface to ext e rnal high power drivers active current balancing between all outp ut phases built-in power good/cr owbar bl anking supports on-the-fly vid co de chan ges 6-bit digital l y p r ogrammable 0.8375 v to 1. 6 v output programmable short-circu i t protection with programmable latch-off de lay applic ati o ns desktop pc power supplies fo r next-generatio n intel? processors vrm mo dules general description the ad p3188 is a hig h l y ef f i cien t, m u l t i p has e , syn c hr on o u s b u ck s w itch ing reg u l a tor c o n t rol l er op t i mi ze d for c o n v er t i ng a 1 2 v main su p p ly in to t h e c o re su p p ly vol t age re qu ire d b y hi g h p e r f o r ma n c e i n t e l p r o c ess o rs. the p a r t us es a n i n t e r n al 6- b i t d a c t o r e ad a vol t a g e iden t i f i ca tio n (vid) co de dir e c t l y f r o m t h e p r o c e s s o r , w h ich is us e d t o s e t t h e o u t p u t v o l t a g e b e tw e e n 0.8375 v a nd 1. 6 v . i t us es a m u l t im o d e pwm a r c h i t ec t u r e t o dr i v e t h e log i c-l e v e l o u t p u t s a t a p r og ra mma b l e swi t chi n g f r e q uen c y t h a t c a n b e o p t i mi ze d fo r vr size an d ef f i cien c y . the phas e re l a t i o n s h i p o f t h e ou t p ut sig n als can b e p r o- g r a m m e d to p r o v i d e 2-, 3 - , o r 4-phas e o p er a t i o n, a l lo wing th e co n s tr ucti o n o f u p t o f o ur co m p le m e n t a r y b u c k swi t c h in g s t a g es . the ad p3188 a l s o in c l u d es p r og ra mma b l e n o -l o a d o f fs et a nd s l o p e f u n c t i o n s t o ad j u s t t h e ou t p u t v o l t a g e as a f u n c t i on o f t h e l o ad cu rr en t, so i t i s al wa ys o p ti mall y posi ti o n e d f o r a s y s t em tra n sien t. th e ad p3188 als o p r o v ides acc u ra te a nd r e l i ab le sh o r t - c i rc u i t p r ot e c t i on, a d j u st able c u r r e n t li m i t i ng, and a d e l a y e d po w e r g o od o u t p u t t h a t a c c o m m od a t e s o n - t h e - f l y o u t p u t v o l t a g e cha n g e s r e q u es t e d b y t h e cpu . the ad p3188 is s p ecif ie d o v er th e co mm er cial t e m p era - tu re ran g e o f 0c t o 8 5 c and is a v ai lab l e in 2 8 -l ead , t ssop and q s op p a ck a g es. func tio n a l block di agram 04835-001 vcc gnd adp3188 en delay ilimit pwrgd rt rampadj pwm2 fb pwm3 pwm4 sw1 cssum cscomp sw2 sw3 sw4 csref pwm1 vid4 vid3 vid2 vid1 vid5 vid0 fbrtn comp dac+150mv dac-250mv csref en crowbar current limit reset reset reset reset 2-/3-/4-phase driver logic en set current balancing circuit oscillator delay uvlo shutdown and bias current limit circuit soft start precision reference vid dac cmp cmp cmp cmp 28 13 14 26 8 25 24 23 17 18 22 21 20 16 27 1 2 3 4 6 5 7 19 11 12 15 10 9 fi g u r e 1 . rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . specifications subjec t to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 461. 31 13 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed .
adp3188 rev. a | page 2 of 28 table of contents specifications ..................................................................................... 3 test circ u its ....................................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................ 7 typical performance characteristics ............................................. 8 theory of operation ........................................................................ 9 start-up sequence ........................................................................ 9 master clock frequency .............................................................. 9 output voltage differential sensing .......................................... 9 output current sensing .............................................................. 9 active impedance control mode ............................................. 10 current-control mode and thermal balance ........................ 10 volt age c ont rol mo de ................................................................ 10 soft start ...................................................................................... 10 current-limit, short-circuit, and latch-off protection ...... 11 dynamic vid .............................................................................. 11 power good monitoring ........................................................... 12 output crowbar ......................................................................... 13 output enable and uvlo ........................................................ 13 application information ................................................................ 15 setting the clock frequency ..................................................... 15 soft start and current-limit latch-off delay times ........... 15 inductor selection ...................................................................... 15 designing an inductor ............................................................... 16 selecting a standard inductor .............................................. 16 output droop resistance .......................................................... 16 inductor dcr temperature correction ................................. 17 output offset .............................................................................. 17 c out selection ............................................................................. 18 power mosfets ......................................................................... 18 ramp resistor selection ............................................................ 20 comp pin ramp ....................................................................... 20 current-limit setpoint .............................................................. 20 feedback loop compensation design .................................... 20 c in selection and input current di/dt reduction .................. 22 tuning the adp3188 ................................................................. 23 dc loadline setting .............................................................. 23 ac loadline setting ............................................................... 24 layout and component placement .............................................. 26 general recommendations ....................................................... 26 power circuitry recommendations ........................................ 26 signal circuitry recommendations ......................................... 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 4/05rev. 0 to rev. a changes to figure 10.........................................................................14 changes to ordering guide .............................................................27 4/04revision 0: initial version adp3188 rev. a | page 3 of 28 specifications vcc = 12 v, fbrtn = gnd, t a = 0c to 85c, unless otherwise noted. 1 table 1. parameter symbol conditions min typ max unit error amplifier output voltage range 2 v comp 0.7 3.1 v accuracy v fb relative to nominal dac output, referenced to fbrtn, cssum = cscomp, figure 2 ?9.5 +9.5 mv line regulation ? v fb vcc = 10 v to 14 v 0.05 % input bias current i fb 14 15.5 17 a fbrtn current i fbrtn 100 140 a output current i o(err) fb forced to v out C 3% 500 a gain bandwidth product gbw (err) comp = fb 20 mhz slew rate c comp = 10 pf 25 v/ s vid inputs input low voltage v il(vid) 0.4 v input high voltage v ih(vid) 0.8 v input current, input voltage low i il(vid) vid(x) = 0 v ?25 ?35 a input current, input voltage high i ih(vid) vid(x) = 1.25 v 5 15 a pull-up resistance r vid 35 60 85 k ? internal pull-up voltage 0.9 1.1 v vid transition delay time 2 vid code change to fb change 400 ns no cpu detection turn-off delay time 2 vid code change to 11111 to pwm going low 400 ns oscillator frequency range 2 f osc 0.25 4 mhz frequency variation f phase t a = 25c, r t = 250 k ? , 4-phase 155 200 245 khz t a = 25c, r t = 115 k ? , 4-phase 400 khz t a = 25c, r t = 75 k ? , 4-phase 600 khz output voltage v rt r t = 100 k ? to gnd 1.9 2.0 2.1 v rampadj output voltage v rampadj rampadj C fb ?50 +50 mv rampadj input current range i rampadj 0 100 a current-sense amplifier offset voltage v os(csa) cssum C csref, figure 3 ?1.75 +1.75 mv t a = 25c to 85c, cssum C csref, figure 3 ?1.5 +1.5 mv input bias current i bias(cssum) ?50 +50 na gain bandwidth product gbw (csa) 10 mhz slew rate c cscomp = 10 pf 10 v/ s input common-mode range cssum and csref 0 2.7 v positioning accuracy ? v fb figure 4 ?77 ?80 ?83 mv output voltage range 0.05 2.7 v output current i cscomp 500 a current-balance circuit common-mode range v sw(x)cm ?600 +200 mv input resistance r sw(x) sw(x) = 0 v 20 30 40 k ? input current i sw(x) sw(x) = 0 v 4 7 10 a input current matching ? i sw(x) sw(x) = 0 v ?5 +5 % adp3188 rev. a | page 4 of 28 parameter symbol conditions min typ max unit current-limit comparator output voltage normal mode v ilimit(nm) en > 0.8 v, r ilimit = 250 k ? 2.9 3 3.1 v shutdown mode v ilimit(sd) en < 0.4 v, i ilimit = ?100 a 400 mv output current, normal mode i ilimit(nm) en > 0.8 v, r ilimit = 250 k ? 12 a maximum output current 2 60 a current-limit threshold voltage v cl v csref C v cscomp , r ilimit = 250 k ? 105 125 145 mv current-limit setting ratio v cl /i ilimit 10.4 mv/ a delay normal mode voltage v delay(nm) r delay = 250 k ? 2.9 3 3.1 v delay overcurrent threshold v delay(oc) r delay = 250 k ? 1.7 1.8 1.9 v latch-off delay time t delay r delay = 250 k ? , c delay = 12 nf 1.5 ms soft start output current, soft-start mode i delay(ss) during startup, delay < 2.4 v 15 20 25 a soft-start delay time t delay(ss) r delay = 250 k ? , c delay = 12 nf, vid code= 011111 1 ms enable input input low voltage v il(en) 0.4 v input high voltage v ih(en) 0.8 v input current, input voltage low i il(en) en = 0 v ?1 +1 a input current, input voltage high i ih(en) en = 1.25 v 10 25 a power good comparator undervoltage threshold v pwrgd(uv) relative to nominal dac output ?180 ?250 ?300 mv overvoltage threshold v pwrgd(ov) relative to nominal dac output 90 150 200 mv output low voltage v ol(pwrgd) i pwrgd(sink) = 4 ma 225 400 mv power good delay time during soft start 2 r delay = 250 k ? , c delay = 12 nf, vid code = 011111 1 ms vid code changing 100 250 s vid code static 200 ns crowbar trip point v crowbar relative to nominal dac output 90 150 200 mv crowbar reset point rela tive to fbrtn 450 550 650 mv crowbar delay time t crowbar overvoltage to pwm going low vid code changing 100 250 s vid code static 400 ns pwm outputs output low voltage v ol(pwm) i pwm(sink) = ?400 a 160 500 mv output high voltage v oh(pwm) i pwm(source) = 400 a 4.0 5 v supply dc supply current 5 10 ma uvlo threshold voltage v uvlo vcc rising 6.5 6.9 7.3 v uvlo hysteresis 0.7 0.9 1.1 v 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc). 2 guaranteed by design or bench characterization, not tested in production. adp3188 r e v. a | pa ge 5 o f 2 8 test circuits 250k ? 12v 1.25v 1 f 1 00n f 100nf adp3188 vid4 vid3 vid2 vid1 vid0 vid5 fbrtn fb comp pwrgd en delay rt rampadj vcc pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 gnd cscomp cssum csref ilimit 1 2 3 28 27 26 4 8 10 12 14 5 6 7 21 24 23 22 9 11 17 18 19 13 15 16 20 25 6-bit code 250k ? 20k ? 1k ? 12nf 04835-002 + f i gure 2. closed-l oop o u tput v o ltage a c cur a c y cssum 18 cscomp 17 28 vcc csref 16 gnd 19 39k ? 100nf 1k ? 1.0v adp3188 12v v os = cscomp ? 1v 40 04835-003 f i gure 3. cu rrent-s ens e a m p lif ier v os ? v fb = fb ? v = 80mv ? fb ? v = 0mv cssum 18 cscomp 17 28 vcc csref 16 gnd 19 200k ? 100nf ? v 1.0v adp3188 12v 04835-004 200k ? comp 8 fb 9 10k ? f i gure 4 . p o si tio n in g v o l t a g e adp3188 r e v. a | pa ge 6 o f 2 8 absolute maximum ra tings table 2. p a r a m e t e r r a t i n g vcc ?0.3 v to +15 v fbrtn ?0.3 v to +0.3 v vid0 to vi d5, e n , delay, i l imi t , cscomp, rt, pw m1 to p w m4, comp ?0.3 v to +5.5 v sw1 C sw4 ?5 v to +25 v all other inputs and outputs ? 0 . 3 v t o v c c + 0 . 3 v storage temperature ?65c to +150c operating ambient temperature range 0c to 85c operating junct i on temperature 125c thermal imped a nce ( ja ) 100c/w lead temperature soldering (10 sec) 300c infrared (15 sec) 260c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly , an d f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io n s ab o v e t h o s e i ndic a t e d i n t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . a b s o l u te m a x i m u m r a t i n g s a p ply indivi d u a l ly o n ly , n o t i n co m b in a t io n . u n l e ss o t her w is e sp e c if ie d , a l l o t h e r volt age s are re fe re nc e d to g n d . esd c a ution esd (electrostatic discharge) se nsiti ve device. electrostatic charges as hi gh as 4000 v readily accumulate on the human body and test eq ui pment and can discharge wi thout detection. although this product features proprietary esd protection circ uitry, permane n t dama ge may occur on devices subj ected to high energy electrostatic discharge s . ther efore, pr oper esd precautio n s ar e rec o m m ended to av oid perform a n c e degradation or l o ss of functiona l ity. adp3188 r e v. a | pa ge 7 o f 2 8 pin conf igura t ion and fu nction descriptions adp3188 top view (not to scale) vid4 vid3 vid2 vid1 vid0 vid5 fbrtn fb comp pwrgd en delay rt rampadj vcc pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 gnd cscomp cssum csref ilimit 1 2 3 28 27 26 4 8 10 12 14 5 6 7 21 24 23 22 9 11 17 18 19 13 15 16 20 25 04835-005 f i gure 5. pin config ur ation ta ble 3. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic description 1 to 6 vid4 to vi d0, vid5 voltage identifi cation dac inputs. these six pins are pulle d up to an internal reference, prov iding a logic 1 if left open. when in normal oper a tion mode, the dac o utput programs the fb r e gulation voltage from 0.8375 v to 1.6 v (see ta ble 4). leaving all the vid pins open re sults in the adp3188 g o ing into no cpu mode, shutting off its pwm ou t p uts and pulling the pwrgd ou t p ut low. 7 fbrtn feedback return. vid dac and error amplifier r e ference for re mote sensi n g of the output volt age. 8 fb feedback input. error amplifier i n put for remote sensing of the output vo ltage. an external re sist or between this pin and the output voltage sets the no-l oad offset point. 9 c o m p error amplifier outp ut and co mpensation point. 10 pwrgd power good output. open-drain output that si gnals when the output voltage is outside the proper operating range . 11 en power supply enable in put. pulling this pin to gnd d i sables the pwm o utputs and pulls the pwrgd output low. 12 delay soft-start delay and current-limit latch-off d e lay setting inp ut. an external resistor and capacitor conne cted between this pin and gnd sets the soft-start ramp-up time and the o vercurrent latch-off delay time. 13 rt frequency setting resistor inpu t. an external resist or co nnecte d between this pin and gnd sets the oscil l ator frequency of the device. 14 rampadj pwm ramp curr ent input. an exte rnal resi stor from the convert e r input voltage to this pin sets the internal pwm ramp. 1 5 i l i m i t current-limit se tpoint/e nable output. an extern al resi stor from this pin to gnd sets the current-limit threshold of the converter . this pin is activ e ly pulled low when the adp3188 en input is low, or when vcc is below its uvlo threshold, to signal to the driver ic that th e driver high-s id e and low-s i d e outputs should go low. 16 csref current-sense reference voltag e input. the voltage on this pin i s used as the reference for the c u rrent-sense amplifier a n d the power go od and crowbar fun c tions. t h is pi n s h ould be conne cted to the common poi nt of the output ind u ctors. 17 cssum current-sense summing node. external resi stor s from each switch node to this pin sum the ave r age inductor currents together to measur e the total output c u rrent. 18 cscomp current-sense compensation p o in t. a resistor a n d a capacitor fr om this pin to c ssum determin e the slope of the load line an d the positionin g loop res pon se time. 19 gnd ground. all internal biasing and the logic output si gnals of the device are refer e nced to this ground. 20 to 23 sw4 to sw1 current-balan ce inputs. in puts for measuring th e current level i n each ph ase. t h e sw pins of unused phase s should be left o p en. 24 to 27 pwm4 to pmw1 logic-level pwm outputs. eac h output is connected to the input of an external mosfet driver such as the adp3418. connecting the pwm3 and/or pwm4 outputs to gnd ca uses that phase to turn off, allowing the adp3188 to operate as a 2-, 3-, or 4-phase contr o ller. 28 vcc supply voltage for the device. adp3188 r e v. a | pa ge 8 o f 2 8 typical perf orm ance cha r acte ristics 4 3 2 1 0 m a ster c l oc k fr equ e n c y ( m h z) r t value (k ? ) 0 5 0 100 150 200 250 300 04835-006 f i gure 6. m a ster cl ock f r equ e nc y v s . rt 0 0.5 1 1.5 2 2.5 3 3.5 4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 s u p p l y curre nt (ma) oscillator frequency (mhz) t a = 25 c 4-phase operation 04835-007 f i gure 7. su p p ly cu rr e n t v s . o s cil l a t o r f r equ e nc y adp3188 rev. a | page 9 of 28 theory of operation the adp3188 combines a mulitmode, fixed frequency pwm control with mulitphase logic outputs for use in 2-, 3-, and 4 - phase synchronous buck cpu core supply power converters. the internal vid dac is designed to interface with the intel 6-bit vrd/vrm 10-and 10.1-compatible cpus. multiphase operation is important for producing the high currents and low voltages demanded by todays microprocessors. handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and mosfets. the multimode control of the adp3188 ensures a stable, high performance topology for ? balancing currents and thermals between phases ? high speed response at the lowest possible switching frequency and output decoupling ? minimizing thermal switching losses due to lower frequency operation ? tight load line regulation and accuracy ? high current output for up to 4-phase operation ? reduced output ripple due to multiphase cancellation ? pc board layout noise immunity ? ease of use and design due to independent component selection ? flexibility in operation for tailoring design to low cost or high performance start-up sequence during start-up, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the pwm outputs. normally, the adp3188 operates as a 4-phase pwm controller. grounding the pwm4 pin pro- grams 3-phase operation, and grounding the pwm3 and pwm4 pins programs 2-phase operation. when the adp3188 is enabled, the controller outputs a voltage on pwm3 and pwm4, which is approximately 675 mv. an internal comparator checks each pins voltage vs. a threshold of 300 mv. if the pin is grounded, it is below the threshold, and the phase is disabled. the output resistance of the pwm pin is approximately 5 k ? during this detection time. any external pull-down resistance connected to the pwm pin should not be less than 25 k ? to ensure proper operation. pwm1 and pwm2 are disabled during the phase detection interval, which occurs during the first two clock cycles of the internal oscillator. after this time, if the pwm output is not grounded, the 5 k ? resistance is removed, and it switches between 0 v and 5 v. if the pwm output is grounded, it remains off. the pwm outputs are logic-level devices intended for driving external gate drivers such as the adp3418. because each phase is monitored independently, operation approaching 100% duty cycle is possible. also, more than one output can be on at the same time for overlapping phases. master clock frequency the clock frequency of the adp3188 is set with an external resistor connected from the rt pin to ground. the frequency follows the graph in figure 6. to determine the frequency per phase, the clock is divided by the number of phases in use. if pwm4 is grounded, divide the master clock by 3 for the fre- quency of the remaining phases. if pwm3 and 4 are grounded, divide by 2. if all phases are in use, divide by 4. output voltage differential sensing the adp3188 combines differential sensing with a high accuracy vid dac and reference and a low offset error amplifier. this maintains a worst-case specification of 9.5 mv differential sensing error over its full operating output voltage and tem- perature range. the output voltage is sensed between the fb and fbrtn pins. fb should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. fbrtn should be connected directly to the remote sense ground point. the internal vid dac and precision reference are referenced to fbrtn, which has a minimal current of 100 a to allow accurate remote sensing. the internal error amplifier compares the output of the dac to the fb pin to regulate the output voltage. output current sensing the adp3188 provides a dedicated current-sense amplifier (csa) to monitor the total output current for proper voltage positioning vs. load current and for current-limit detection. sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side mosfet. this amplifier can be configured several ways depending on the objectives of the system: ? output inductor dcr sensing without a thermistor for lowest cost ? output inductor dcr sensing with a thermistor for improved accuracy with tracking of inductor temperature ? sense resistors for highest accuracy measurements adp3188 rev. a | page 10 of 28 the positive input of the csa is connected to the csref pin, which is connected to the output voltage. the inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, cssum. the feedback resistor between cscomp and cssum sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. the gain of the amplifier is programmable by adjusting the feedback resistor to set the load line required by the microprocessor. the current information is then given as the difference of csref C cscomp. this difference signal is used internally to offset the vid dac for voltage positioning and as a differential input for the current-limit comparator. to provide the best accuracy for sensing current, the csa is designed to have a low offset input voltage. also, the sensing gain is determined by external resistors, so that it can be made extremely accurate. active impedance control mode for controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the cscomp pin can be scaled to equal the droop impedance of the regulator multiplied by the output current. this droop voltage is then used to set the input control voltage to the system. the droop voltage is subtracted from the dac reference input voltage directly to tell the error amplifier where the output voltage should be. this differs from previous imple- mentations and allows enhanced feed-forward response. current-control mode and thermal balance the adp3188 has individual inputs for each phase, which are used for monitoring the current in each phase. this information is combined with an internal ramp to create a current balancing feedback system, which has been optimized for initial current balance accuracy and dynamic thermal balancing during opera- tion. this current-balance information is independent of the average output current information used for positioning described previously. the magnitude of the internal ramp can be set to optimize the transient response of the system. it also monitors the supply voltage for feed-forward control for changes in the supply. a resistor connected from the power input voltage to the rampadj pin determines the slope of the internal pwm ramp. detailed information about programming the ramp is given in the application information section. external resistors can be placed in series with individual phases to create, if desired, an intentional current imbalance such as when one phase may have better cooling and can support higher currents. resistors r sw1 through r sw4 (see the typical appli- cation circuit in figure 10) can be used for adjusting thermal balance. it is best to have the ability to add these resistors during the initial design, so make sure that placeholders are provided in the layout. to increase the current in any given phase, make r sw for this phase larger (make r sw = 0 for the hottest phase, and do not change during balancing). increasing r sw to only 500 ? makes a substantial increase in phase current. increase each r sw value by small amounts to achieve balance, starting with the coolest phase first. voltage control mode a high gain bandwidth voltage mode error amplifier is used for the voltage-mode control loop. the control input voltage to the positive input is set via the vid logic according to the voltages listed in table 4. this voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. the output of the amplifier is the comp pin, which sets the termi- nation voltage for the internal pwm ramps. the negative input (fb) is tied to the output sense location with a resistor (r b ) and is used for sensing and controlling the output voltage at this point. a current source from the fb pin flowing through r b is used for setting the no-load offset voltage from the vid voltage. the no-load voltage is negative with respect to the vid dac. the main loop compensation is incorporated into the feedback network between fb and comp. soft start the power-on ramp-up time of the output voltage is set with a capacitor and resistor in parallel from the delay pin to ground. the rc time constant also determines the current-limit latch- off time as explained in the following section. in uvlo, or when en is a logic low, the delay pin is held at ground. after the uvlo threshold is reached and en is a logic high, the delay capacitor is charged with an internal 20 a current source. the output voltage follows the ramping voltage on the delay pin, limiting the inrush current. the soft-start time depends on the value of the vid dac and c dly , with a secondary effect from r dly . refer to the application information section for detailed information on setting c dly . if either en is taken low, or vcc drops below uvlo, the delay capacitor is reset to ground to be ready for another soft-start cycle. figure 8 shows a typical soft-start sequence for the adp3188. adp3188 rev. a | page 11 of 28 04835-008 fi g u r e 8 . t y p i c a l s t a r t - u p w a v e f o r m s chann e l 1: pwr g d , chan nel 2: csr e f , chann e l 3: del a y , chann e l 4: c o m p current -limit , short - circuit , and l a t c h- o ff pro t ec t i o n the ad p3188 c o m p a r es a p r og ra mma b l e c u r r en t-l i mi t s e t p o i n t t o t h e v o l t a g e f r o m t h e o u t p u t of t h e c u r r en t-s e n s e am plif ier . the l e vel o f c u r r en t li mi t i s s e t w i t h t h e resi s t or f r o m t h e i l i m i t pi n to g r ou nd. d u r i ng nor m a l op e r a t i o n , t h e v o lt age on i l i m i t is 3 v . th e c u r r en t t h r o ug h t h e ext e r n al r e sis t o r is in t e r n al l y s c ale d t o g i v e a c u r r en t-limi t thr e s h old o f 10.4 mv/ a. i f t h e dif f er en ce in v o l t a g e b e tw e e n c s ref a nd csc o mp r i s e s a b o v e t h e c u r r en t-l i mi t t h r e sh old , t h e in t e r n al c u r r en t - limi t am pli- f i e r co n t r o ls t h e i n ter n al c o mp v o l t age t o mai n t a i n t h e a ver a g e o u t p ut c u r r en t a t t h e l i mi t. af t e r t h e l i mi t i s r e ach e d , t h e 3 v p u l l -u p o n t h e d e l a y p i n is dis c o n n e c t e d , and t h e ex ter n a l dela y c a p a ci to r is dis c ha rge d t h r o ug h t h e exte r n al r e si st o r . a c o m p a r a t o r m o ni t o rs t h e d e l a y v o l t a g e an d s h uts o f f t h e co n t r o l l er w h e n t h e v o l t a g e dr o p s b e lo w 1.8 v . the c u r r en t-l i mi t l a t c h-o f f de l a y t i m e is t h er efo r e s e t b y t h e r c t i m e con s tan t dis c ha rg in g f r o m 3 v t o 1.8 v . the a p plic a t ion i n fo r m a t ion s e c t io n di s c uss e s t h e s e le c t io n o f c dl y a nd r dl y . b e ca us e t h e co n t r o l l er co n t in ue s t o c y cle t h e phas es d u r i n g t h e l a tc h - of f d e l a y t i m e , i f t h e s h or t i s re mo ve d b e f o re t h e 1 . 8 v t h re sho l d i s re a c he d, t h e c o n t ro l l e r re tu r n s to nor m a l op e r a t i o n . the r e co v e r y cha r ac t e r i s t ic de p e n d s on t h e st a t e o f pwr g d . i f t h e ou t p u t v o l t ag e is w i t h i n t h e pwr g d w i n d o w , t h e con t r o l l er r e s u m e s n o r m al o p era t io n. h o we v e r , if a sh o r t cir c ui t has ca us e d t h e o u t p u t v o l t a g e t o dro p b e l o w t h e p w r g d t h r e sh - old , a s o f t - s t a r t c y cle is ini t i a t e d. th e la t c h - o f f fun c ti o n c a n be r e set b y ei th e r r e m o vi n g a n d r e a p p l y i ng v cc t o t h e ad p 318 8, o r b y p u l l i n g t h e e n p i n lo w fo r a sh o r t t i me . t o dis a ble t h e sh o r t- circ u i t l a tch-o f f f u nc t i o n , t h e e x t e r n a l r e s i stor t o g r ou n d s h ou l d b e l e f t o p e n , and a hi g h va l u e (>1 m ? ) resis t o r sho u l d be conn e c te d f r om d e l a y t o v c c . th i s p r ev en ts t h e d e la y ca paci t o r f r o m di s c ha rg i n g , s o t h e 1 . 8 v t h r e sh o l d is ne ve r r e ache d. t h e r e sisto r h a s a n i m pa ct o n th e so ft - s ta rt ti m e be ca use th e cu rr e n t t h r o ugh i t ad ds t o t h e in t e rnal 20 a curr en t so ur ce . dur i n g s t a r t-u p when t h e o u t p u t v o l t a g e is b e l o w 200 mv , a s e conda r y c u r r en t lim i t is ac t i v e . this is n e ce ss a r y b e ca us e t h e v o l t a g e s w ing o f csc o mp c a nn ot g o b e lo w g r o u n d . this s e conda r y c u r r en t limi t con t r o ls t h e i n t e r n a l c o mp v o l t a g e t o t h e p w m co m p a r a t ors t o 2 v . this l i mi ts t h e v o l t a g e dr o p acros s t h e lo w-side mos f et s t h r o ug h t h e c u r r en t b a lan c e cir c ui t r y . an in h e r e n t p e r phas e c u r r en t li mi t p r o t e c ts i n di vi d u a l phas es, i f one or more ph a s e s stop s f u nc t i on i n g b e c a u s e of a f a u l t y co m p on e n t. thi s limi t is b a s e d o n t h e max i m u m n o r m a l m o d e c o m p vol t age. 04835-0-009 f i gu r e 9 . o v er cu rr en t la t c h - o ff w a v e fo rm s chann e l 1: csref , chann e l 2: del a y , chann e l 3: c o m p , chann e l 4: p h as e 1 switch nod e dy n a m i c v i d the ad p3188 has the a b il i t y t o d y na mical l y c h a n g e t h e vi d in p u t w h i l e t h e co n t r o l l er is r u nning. this al lo ws t h e o u t p u t v o l t a g e t o cha n g e w h ile t h e s u ppl y is r u nnin g a nd s u p p l y in g c u r r en t t o t h e l o ad . this is comm onl y r e f e r r ed t o as vid on- th e-f l y (o t f ). a vid ot f can o c c u r under ei t h er lig h t o r he a v y lo ad condi t ion s . the p r o c ess o r s i g n al s t h e con t r o l l er b y c h a n g i n g t h e vid in p u ts in m u l t i p le s t e p s f r o m t h e s t a r t co de t o th e fi n i s h co de . this c h an g e c a n b e p o si ti ve or n e ga t i v e . w h en a vi d in p u t c h a n g e s sta t e , t h e ad p3188 det e c t s t h e c h a n g e an d ig no r e s th e d a c in p u ts f o r a minim u m o f 400 n s . this t i me p r e v e n ts a fals e co de d u e t o log i c s k e w w h i l e t h e six v i d i n put s are ch ang i n g . a d d i t i on a l ly , t h e f i rst v i d ch ange i n i t i a te s t h e p w rg d a n d c r o w b a r bl an k i ng f u nc t i o n s for a minim u m o f 100 s t o p r ev en t a fals e p w r g d o r cr o w ba r ev e n t . e a ch v i d c h a n g e r e se ts th e i n t e rn al tim e r . adp3188 rev. a | page 12 of 28 table 4. vid codes for the adp3188 vid4 vid3 vid2 vid1 vid0 vid5 output 1 1 1 1 1 1 no cpu 1 1 1 1 1 0 no cpu 0 1 0 1 0 0 0.8375 v 0 1 0 0 1 1 0.8500 v 0 1 0 0 1 0 0.8625 v 0 1 0 0 0 1 0.8750 v 0 1 0 0 0 0 0.8875 v 0 0 1 1 1 1 0.9000 v 0 0 1 1 1 0 0.9125 v 0 0 1 1 0 1 0.9250 v 0 0 1 1 0 0 0.9375 v 0 0 1 0 1 1 0.9500 v 0 0 1 0 1 0 0.9625 v 0 0 1 0 0 1 0.9750 v 0 0 1 0 0 0 0.9875 v 0 0 0 1 1 1 1.0000 v 0 0 0 1 1 0 1.0125 v 0 0 0 1 0 1 1.0250 v 0 0 0 1 0 0 1.0375 v 0 0 0 0 1 1 1.0500 v 0 0 0 0 1 0 1.0625 v 0 0 0 0 0 1 1.0750 v 0 0 0 0 0 0 1.0875 v 1 1 1 1 0 1 1.1000 v 1 1 1 1 0 0 1.1125 v 1 1 1 0 1 1 1.1250 v 1 1 1 0 1 0 1.1375 v 1 1 1 0 0 1 1.1500 v 1 1 1 0 0 0 1.1625 v 1 1 0 1 1 1 1.1750 v 1 1 0 1 1 0 1.1875 v 1 1 0 1 0 1 1.2000 v vid4 vid3 vid2 vid1 vid0 vid5 output 1 1 0 1 0 0 1.2125 v 1 1 0 0 1 1 1.2250 v 1 1 0 0 1 0 1.2375 v 1 1 0 0 0 1 1.2500 v 1 1 0 0 0 0 1.2625 v 1 0 1 1 1 1 1.2750 v 1 0 1 1 1 0 1.2875 v 1 0 1 1 0 1 1.3000 v 1 0 1 1 0 0 1.3125 v 1 0 1 0 1 1 1.3250 v 1 0 1 0 1 0 1.3375 v 1 0 1 0 0 1 1.3500 v 1 0 1 0 0 0 1.3625 v 1 0 0 1 1 1 1.3750 v 1 0 0 1 1 0 1.3875 v 1 0 0 1 0 1 1.4000 v 1 0 0 1 0 0 1.4125 v 1 0 0 0 1 1 1.4250 v 1 0 0 0 1 0 1.4375 v 1 0 0 0 0 1 1.4500 v 1 0 0 0 0 0 1.4625 v 0 1 1 1 1 1 1.4750 v 0 1 1 1 1 0 1.4875 v 0 1 1 1 0 1 1.5000 v 0 1 1 1 0 0 1.5125 v 0 1 1 0 1 1 1.5250 v 0 1 1 0 1 0 1.5375 v 0 1 1 0 0 1 1.5500 v 0 1 1 0 0 0 1.5625 v 0 1 0 1 1 1 1.5750 v 0 1 0 1 1 0 1.5875 v 0 1 0 1 0 1 1.6000 v power good monitoring the power good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified in table 4. these limits are based on the vid voltage setting. pwrgd goes low if the output voltage is outside of this specified range, if all of the vid dac inputs are high, or when- ever the en pin is pulled low. pwrgd is blanked during a vid otf event for a period of 250 s to prevent false signals during the time the output is changing. the pwrgd circuitry also incorporates an initial turn-on delay time based on the delay ramp. the pwrgd pin is held low until the delay pin reaches 2.6 v. the time between when the pwrgd undervoltage threshold is reached and when the delay pin reaches 2.6 v provides the turn-on delay time. this time is incorporated into the soft-start ramp. to ensure a 1 ms delay time on pwrgd, the soft-start ramp must also be >1 ms. refer to the application information section for detailed information on setting c dly . adp3188 rev. a | page 13 of 28 output crowbar as part of the protection for the load and output components of the supply, the pwm outputs are driven low (turning on the low-side mosfets) when the output voltage exceeds the upper crowbar threshold. this crowbar action stops once the output voltage falls below the release threshold of approximately 550 mv. turning on the low-side mosfets pulls down the output as the reverse current builds up in the inductors. if the output over- voltage is due to a short in the high-side mosfet, this action current-limits the input supply or blows its fuse, protecting the microprocessor from being destroyed. output enable and uvlo for the adp3188 to begin switching, the input supply (vcc) to the controller must be higher than the uvlo threshold, and the en pin must be higher than its logic threshold. if uvlo is less than the threshold or the en pin is a logic low, the adp3188 is disabled. this holds the pwm outputs at ground, shorts the delay capacitor to ground, and holds the ilimit pin at ground. in the application circuit, the ilimit pin should be connected to the od pins of the adp3418 drivers. the ilimit being grounded disables the drivers such that both drvh and drvl are grounded. this feature is important in preventing the dis- charge of the output capacitors when the controller is shut off. if the driver outputs were not disabled, a negative voltage could be generated during output due to the high current discharge of the output capacitors through the inductors. adp3188 rev. a | page 14 of 28 04835-010 v in 12v v in rt n enabl e po w e r good r li m 150k ? 1% r ph4 158k ? 1% fr om c p u r2 357k ? 1% q3 nt d110n02 q1 nt d40n03 q7 nt d110n02 q5 nt d40n03 q11 nt d110n02 q9 nt d40n03 q4 nt d110n02 c dl y 39n f v cc( c ore) 0. 8375v ? 1. 6v 95a t d c, 119a p k v cc( c ore) rt n 560 f/4 v 8 sanyo sepc seri e s 5m ? each l2 320n h/ 1. 4m ? l1 370n h 18a c1 r t 137k ? 1% c10 10n f c22 c31 l3 320n h/ 1. 4m ? u3 adp 3418 1 2 3 8 7 6 4 5 drvh sw pg nd drvl c9 4. 7 f d2 1n4148 d3 1n4148 d4 1n4148 c6 10 n f c5 4. 7 f c7 4. 7 f c11 4. 7 f u2 adp 3418 1 2 3 8 7 6 4 5 bst in od vcc drvh sw pg nd drvl vi d4 vi d3 vi d2 vi d1 vi d0 vi d5 f brt n fb co m p pw rg d en del a y rt ram p adj vcc pw m 1 pw m 2 pw m 3 pw m 4 sw 1 sw 2 sw 3 sw 4 gnd cscom p cssum csref ilimit 3 1 4 5 26 25 24 2 28 27 6 10 14 7 8 9 19 22 21 20 23 11 12 15 18 17 16 u1 a d p 3188 c14 10n f l4 320n h/ 1. 4m ? u4 adp 3418 1 2 3 8 7 6 4 5 drvh sw pg nd drvl c13 4. 7 f c4 1 f c3 100 f r1 10 ? r a 12. 1k ? c fb 22p f c a 470p f c cs1 560p f c cs2 1. 5n f c2 2700 f/1 6 v /3 .3 a 2 sanyo m v -w x seri e s + + 10 f 18 mlc c in socket rt h1 100k ? , 5 % nt c c8 15n f r3 2. 2 ? c12 15n f r4 2. 2 ? c20 15n f r6 2. 2 ? c16 15n f r5 2. 2 ? d1 1n4148 r b 1. 21k ? r cs1 35. 7k ? c b 470p f r ph3 158k ? 1% r ph2 158k ? 1% r ph1 158k ? 1% r dl y 470k ? q12 nt d110n02 q10 nt d40n03 q6 nt d40n03 q2 nt d40n03 q14 nt d40n03 q15 nt d110n02 q13 nt d40n03 d5 1n4148 c19 4. 7 f c15 4. 7 f c18 10 n f l5 320n h/ 1. 4m ? u5 adp 3418 1 2 3 8 7 6 4 5 drvh sw pg nd drvl c17 4. 7 f q16 nt d110n02 q8 nt d110n02 r sw1 * r sw2 * r sw3 * r sw4 * + + r cs2 84 . 5 k ? c21 100p f + bst in od vcc bst in od vcc bst in od vcc *for a description of optional r sw resistors, see the theory of operation section. 13 c22 1000p f c23 0. 01 f r7 10 ? f i g u re 10. t y pic a l v r 10. 1 a p p l i c at i o n circuit adp3188 rev. a | page 15 of 28 appli c a t ion inf o rma t ion t h e d e sig n p a ra m e t e r s f o r a typ i cal i n te l vrd 10.1-co m p l ian t cpu a p plic a t ion a r e as fol l o w s: ? inp u t v o l t a g e ( v in ) = 12 v ? vid s e t t in g v o l t a g e (v vi d ) = 1.3 00 v ? du ty c y c l e (d) = 0.108 ? n o minal o u t p u t v o l t a g e a t n o lo ad (v onl ) = 1.281 v ? n o minal o u t p u t v o l t a g e a t 101 a lo ad (v of l ) = 1.180 v ? st a t i c output vo lt age d r op b a s e d on a 1 . 0 m ? l o a d l i ne ( r o ) f r o m n o lo ad t o f u l l lo ad (v d ) = v onl ? v of l = 1.281 v ? 1.180 v = 101 mv ? ma x i mu m o u tp u t c u r r e n t ( i o ) = 119 a ? m a xi m u m o u t p u t c u r r en t st ep (?i o ) = 95 a ? n u m b er o f phas es (n) = 4 ? sw it c h i n g f r e q u e n c y p e r p h a s e ( f sw ) = 330 kh z se t t ing the cl ock fr equenc y the ad p3188 u s es a f i xed-f r eq uen c y co n t r o l a r c h i t ec t u r e . the f r eq uen c y is s e t b y a n ext e r n al timin g r e sis t o r (r t ). t h e c l o c k f r e q uen c y a n d t h e n u m b er o f phas es de t e r m i n e t h e s w i t chin g f r e q u e nc y p e r ph a s e, w h i c h rel a te s di re c t ly to s w itch i n g l o ss e s a nd t h e si zes o f t h e i n d u c t o r s and/o r t h e i n p u t a nd o u tp u t ca p a ci t o rs. w i t h n = 4 fo r fo ur phas es, a clo c k f r e q uen c y o f 1.32 mh z s e ts t h e s w i t c h in g f r eq uen c y (f sw ) o f eac h p h as e t o 330 kh z, whic h r e p r es en ts a p r ac tical trade-o f f betw een t h e swi t chi n g los s es a nd t h e si zes o f t h e o u t p u t f i l t e r co m p on en ts. e q ua tion 1 sh o w s tha t t o ac hie v e a n 1.32 m h z os cil l a t o r f r e- q u en c y , t h e co r r e c t val u e fo r r t is 137 k?. al t e r n a t i v e l y , t h e val u e fo r r t ca n be c a lc u l a t e d usin g ? ? = k pf 27 7 . 4 1 sw t f n r ( 1 ) w h er e 4.7 pf a nd 27 k? a r e i n t e r n al i c co m p onen t v a l u es. f o r go o d ini t i a l acc u rac y a n d f r e q uen c y st ab i l i t y , a 1% re s i stor i s re c o m m e n d e d. soft st art and curre nt -limit l a t c h- off del a y time s b e ca us e t h e s o f t s t a r t a nd c u r r en t-l i mi t l a t c h-o f f de l a y f u n c t i o n s s h a r e t h e d e l a y p i n, t h es e tw o p a ra m e t e rs m u s t b e co n s ider e d t o g e t h er . th e f i rs t s t ep is t o s e t c dl y f o r th e so ft- s ta r t ra m p . t h is r a m p i s g e n e ra t e d w i th a 2 0 a i n t e rn al cu rr e n t so u r c e . t h e val u e o f r dl y h a s a sec o n d - o r d er i m pa ct o n t h e so ft - s ta r t tim e be c a us e i t sin k s p a r t o f th e c u r r en t s o ur ce t o g r o u nd . h o w e ver , as lo ng as r dl y is k e p t g r ea t e r tha n 20 0 k?, this ef f e c t is mi n o r . th e v a l u e fo r c dl y can b e a p p r o x im a t e d usin g vid ss dly vid dly v t r v c ? ? ? ? ? ? ? ? ? = 2 a 20 ( 2 ) w h er e t ss i s th e d e si r e d so ft- s ta r t tim e . a s s u m i n g a n r dl y of 390 k? a nd a d e sir e d s o f t -st a r t t i m e o f 3 m s , c dl y is 36 nf . the clos es t st anda r d val u e fo r c dl y is 39 nf . once c dl y is cho s e n , r dl y can b e calc u l a t e d fo r t h e c u r r en t-l i mi t l a t c h-o f f tim e usi n g dl y delay dly c t r = 96 . 1 ( 3 ) if t h e r e s u l t f o r r dl y is les s tha n 200 k?, a smal l e r s o f t -s ta r t time s h o u l d be co n s ider ed b y r e calc u l a t in g t h e e q u a tio n f o r c dl y , o r a lo n g er la t c h-o f f tim e sh o u l d b e us e d . r dl y sh o u l d n e v e r be les s tha n 200 k?. i n this exa m p l e , a dela y time o f 9 m s r e s u l t s in r dl y = 452 k?. the c l os es t standa r d 5 % val u e is 470 k?. i n d u ct o r s e l e ct i o n t h e c h oi c e of i n d u c t a n c e f o r t h e i n du c t or d e t e r m i n e s t h e r i ppl e cu rr en t in th e in d u ct o r . l e s s in d u cta n ce l e a d s t o m o r e r i p p le curr en t , whi c h in cr e a s e s t h e o u t p u t r i p p l e v o l t a g e a n d co n d uc tio n l o s s e s in th e mo s f et s, b u t allo ws u s i n g sm al le r in d u ct o r s a n d , fo r a sp e c if ie d p e a k -to-p e a k t r an sie n t de v i a t ion, less t o t a l ou t p u t c a p a ci t a nc e. c o n v ers e ly , a h i g h e r i n d u c t ance me a n s l o wer r i p p le c u r r e n t and r e d u ce d cond uc t i on lo ss es , b u t r e quir e s la rger in d u ct o r s a n d mo r e o u t p u t ca pa ci ta n c e f o r th e sa m e p e ak- t o- pe ak t r a n s i en t de via t i o n. i n a n y m u l t i p h a se co n v e r t e r , a p r act i cal va l u e fo r t h e p e a k -t o - p e a k i n d u c t o r r i p p l e c u r r e n t i s le s s t h an 5 0 % o f th e m a x i m u m d c cu rr e n t i n th e sa m e i n d u ct o r . eq ua ti o n 4 sho w s t h e re l a t i o n s h i p be t w e e n t h e ind u c t anc e , os ci l l a t o r fr eq uen c y , a n d peak - t o - peak ri p p l e cu rr en t i n th e i n d u ct o r . ( ) l f d v i sw vid r ? = 1 ( 4 ) e q ua tion 5 can be us e d t o det e r m in e t h e minim u m in d u c t an c e b a s e d on a g i ve n output r i ppl e vol t age. ( ) ( ) ripple sw o vid v f d n r v l ? 1 ( 5 ) s o l v in g e q u a tion 5 f o r a 10 mv p-p o u t p u t r i p p le v o l t a g e yie l ds () nh 224 mv 10 khz 330 0.432 1 m ? 1.0 v 1.3 = ? l i f t h e r e s u l t ing r i pple v o l t a g e i s l e s s t h an i t was desig n e d fo r , ma ke t h e in d u c t o r s m all e r un ti l t h e ri p p le val u e i s m e t . th is all o ws o p t i ma l t r a n si e n t r e sp o n s e and mi n i m u m o u tpu t d e cou p l i ng. adp3188 rev. a | page 16 of 28 the smal les t p o s s i b le in d u c t o r sh o u ld be us e d to minimize t h e n u mb e r of output c a p a c i tor s . for t h i s e x am pl e, cho o s i ng a 320 nh ind u c t or is a g o o d s t a r tin g p o in t an d g i v e s a calc u l a t ed r i p p le c u r r en t of 11 a. th e ind u c t o r s h o u l d not s a t u ra t e a t t h e p e ak c u r r en t o f 35.5 a a nd sh ou ld be a b le t o ha n d l e t h e s u m of t h e p o w e r dis s i p a t io n c a us e d b y t h e a v era g e c u r r en t o f 30 a in t h e w i n d in g and co r e lo ss. a n ot he r i m p o r t an t f a c t or i n t h e i n d u c t or d e s i g n i s t h e d c r , w h ich is us e d fo r m e as ur i n g t h e phas e c u r r en ts. a la rg e d c r ca n ca us e excessi v e p o w e r los s e s , w h i l e t o o sma l l a val u e ca n lead t o in cr eas e d m e as ur em en t er r o r . a g o o d r u le is t o ha v e t h e d c r be abo u t 1 t o 1? tim e s t h e dr o o p r e sis t a n c e (r o ). f o r this desig n , an i n d u c t o r wi t h a d c r o f 1.4 m? is us e d . designing an induc t or on ce t h e i n d u c t a n ce and d c r a r e kn o w n, t h e n e xt st ep is t o e i t h e r d e s i g n an i n d u c t or , or to f i nd a st a n d a rd i n d u c t or t h a t co m e s as clos e as p o s s i b le t o m e et in g t h e o v eral l desig n g o als. i t is als o im p o r t a n t t o ha v e t h e ind u c t a n c e an d d c r t o lera n c e s p ecif ie d t o co n t r o l th e acc u rac y o f th e sys t em. 15% ind u c t an ce a nd 8% d c r (a t r o o m t e m p era t ur e) a r e r e as o n a b le t o lera nces t h a t m o st man u fac t ur ers can me et. the f i rs t de cision i n desig n in g t h e i n d u c t o r is t o ch o o s e t h e co r e ma t e r i al . s e v e ral p o s s i b il i t ies f o r p r o v iding lo w co r e los s a t hig h f r e q ue n c ie s in cl ude t h e p o w d er co r e s (fo r exa m ple , k o ol- m ? f r om m a g n e t i c s , inc . or f r om m i c r ome t a l s ) and t h e g a pp e d s o f t f e r r i t e co r e s (f o r exa m p l e , 3 f 3 o r 3f4 f r o m p h ili p s). l o w f r e q uen c y p o w d er e d ir o n co r e s s h o u l d b e a v oide d d u e t o t h eir h i g h c o re l o s s , e s p e c i a l l y w h e n t h e i n d u c t o r va l u e i s rel a t i ve l y lo w , and t h e r i pple c u r r e n t is hi g h . the bes t ch o i ce f o r a co r e g e o m etr y is a c l os ed-lo o p typ e s u ch a s a p o te n t i o me te r c o re, p q , u , or e c o re or tor o i d . a go o d co m p r o mis e b e t w e e n p r ice and p e r f o r ma n c e is a co r e w i t h a toroi d a l sh a p e. m a n y us ef u l mag n et ic s desig n r e fer e n c es a r e a v a i la b l e fo r q u ick l y desig n i n g a p o w e r i n d u c t o r , such as ? m a gn e t i c d e s i gn e r so f t w a r e intu s o f t ( w w w . i ntu s o f t . c o m ) ? de s i g n i n g m a gne t i c co m p o n e n ts f o r h i g h -f r e q u en c y d c - dc c o n v e r t e r s , b y w i lli a m t . m c l y m a n , k g m a g n e t i c s , i n c., is bn 1883 107008 selecting a st an da rd in du ct or the fol l o w i ng p o wer i n d u c t or man u fac t urers c a n p r o v i d e des i g n c o nsu l t a t i on a n d d e l i ve r p o we r i n d u c t or s opt i m i z e d f o r h i g h po w e r a p p l ica t io n s u p o n r e q u es t : ? co i l c r a f t (847) 639-6400 ww w . c o i l c r a f t . co m ? co i l t r o n i c s (561) 752-5000 ww w . c o i l t r o n i c s. c o m ? su m i d a e l e c t r i c c o m p a n y (847) 545-6700 ww w . s u m i d a .c o m ? vi s h a y i n t e r t e c h n o l o g y (402) 563-6866 ww w . v i s h a y . c o m outpu t droop resist ance the desig n r e q u ir es t h e r e gu la t o r o u t p u t v o l t a g e m e as ur e d a t t h e cpu pin s t o dr o p w h en t h e o u t p ut c u r r en t i n cr e a s e s. th e s p eci f ie d v o l t a g e d r o p co rr es p o n d s t o a d c o u t p u t r e si s t a n ce (r o ). the o u t p u t c u r r en t is m e as ur e d b y s u mmin g t h e v o l t a g e acr o s s ea c h in d u ct o r a n d pa s s i n g th e s i gn al th r o u g h a l o w - pa s s f i l t e r . this sum m er f i l t er is t h e cs am plif ier co nf igur e d w i t h r e sist o r s r ph (x) (s umm e r s ), a n d r cs a nd c cs (f il t e r). t h e o u t p u t r e sis t a n ce o f t h e r e gu l a t o r is s e t b y t h e fol l o w in g e q ua t i o n s, w h er e r l is t h e d c r of t h e output i n d u c t or s : () l x ph cs o r r r r = ( 6 ) cs l cs r r l c = ( 7 ) the us er has t h e f l exi b i l i t y o f ch o o sin g e i t h er r cs or r ph (x ) . i t is be s t t o se lec t r cs eq u a l t o 100 k?, a nd t h en s o l v e f o r r ph (x ) by re ar r a ng i n g e q u a t i o n 6 . () () ? k 140 ? k 100 m ? 0 . 1 ? m 4 . 1 = = = x ph cs o l x ph r r r r r n e xt, us e e q ua t i o n 6 t o s o l v e f o r c cs . nf 8 2 . 2 ? k 100 ? m 4 . 1 nh 320 = = cs c i t is bes t t o ha v e a d u al lo c a tion f o r c cs in t h e l a yo u t , s o tha t s t anda r d v a l u es ca n b e us e d i n p a ral l e l t o g e t as clos e t o t h e v a lu e d e s i re d. for a c c u r a c y , c cs shou l d b e a 5 % or 1 0 % n p o ca p a ci t o r . this exa m ple us es a 5% com b ina t io n fo r c cs o f 1.5 nf a nd 560 pf in p a ral l e l . recalc u l a t in g r c s an d r ph ( x ) usin g t h is ca p a ci t o r co m b ina t io n yie l ds 110 k? a nd 154 k?. the c l os es t st andard 1 % v a lu e for r ph (x) is 158 k?. adp3188 rev. a | page 17 of 28 induc t or dcr temper a t ure c o rrec t ion w i th th e i n d u ct o r s d c r b e i n g u s e d a s th e se n s e e l e m e n t a n d co p p er w i r e b e i n g t h e s o ur ce o f t h e d c r , co m p en s a t i o n is n e e d e d fo r t e m p era t ur e cha n g e s o f t h e i n d u c t or s w i ndi n g . f o r t una t e l y , co pp er has a we l l -k n o w n t e m p er a t ur e co ef f i cien t (t c) o f 0.39%/c. if r cs is desig n e d t o ha ve a n o p p o si t e an d eq u a l p e r c en t a g e cha n g e i n r e sis t a n ce t o t h a t o f t h e wire , i t can c els t h e t e m p era - t u r e va r i a t io n o f t h e i n d u c t o r s d c r . d u e t o t h e n o nl i n e a r na t u r e o f nt c t h er mist o r s, r e sis t o r s r cs 1 a nd r cs 2 a r e n e ed ed . s e e f i gur e 11 to line a r i z e t h e n t c an d p r o d uc e t h e desir e d t e m p era t ur e t r acking. cssum 18 cscomp place as close as possible to nearest inductor or low-side mosfet 17 csref 16 adp3188 c cs1 c cs2 r cs1 r th r cs2 keep this path as short as possible and well away from switch node lines to switch nodes to v out sense r ph1 r ph3 r ph2 04835- 011 f i gure 11. t e mpe r a t ur e com p ensat i o n circuit v a l u es the fol l o w in g pr o c e d ur e an d ex p r es sio n s yie l d val u es t o us e fo r r cs 1 , r cs 2 , and r th (t he t h er mis t o r val u e a t 25c) fo r a gi v e n r cs val u e . 1. s e le c t an nt c b a s e d on typ e and val u e . b e c a us e t h er e isn t a v a l u e y e t, s t a r t w i th a t h e r m i s t o r w i t h a val u e c l ose t o r cs . th e n t c s h ou l d a l s o h a v e an i n i t i a l tol e r a nc e of b e tte r th a n 5% . 2. b a s e d o n t h e ty p e o f ntc, f i nd i t s r e la t i v e r e sista n c e val u e a t t w o t e m p era t ur es. the t e m p e r a t ur es t h a t w o rk w e l l a r e 50c an d 90c. th es e r e sis t an c e val u es a r e c a l l ed a (r th(50 c) /r th(25 c) ) a n d b (r th(90 c) /r th(25 c) ). n o t e : the nt c s r e la t i v e val u e is al wa ys 1 a t 25c. 3. f i n d t h e r e l a t i ve val u es o f r cs r e q u i r ed f o r ea ch o f th ese t e m p era t ur es. this is b a s e d o n t h e p e r c en t a g e cha n g e n e e d e d , w h ich i n t h is exam ple i s ini t i a l l y 0.39% /c. the r e la t i ve val u es a r e cal l e d r 1 (1/(1 + tc ( t 1 ? 25))) a nd r 2 (1/(1 + t c ( t 2 ? 25))), wher e tc = 0.0 039 f o r co p p er . t 1 = 50c a nd t 2 = 90 c a r e c h os e n . f r o m t h is, c a l c u l at e t h at r 1 = 0.9112 a n d r 2 = 0.7978. 4. c o m p u t e t h e r e la t i ve val u es fo r r cs 1 , r cs 2 , an d r t h usin g ( )( ) ( ) () ( ) ( ) b a r a b r b a r a b r b a r r b a r 2 1 1 2 2 1 cs2 ? ? ? ? ? ? + ? ? ? = ( ) cs2 1 cs2 cs1 r r a r a r ? ? ? ? = cs1 cs2 th r r r 1 1 1 1 ? ? = ( 8 ) 5. cal c ula t e r th = r th r cs , t h e n s e le c t t h e clos est val u e o f t h er mi st o r a v ai l a b l e. als o co m p u t e a s c a l in g f a c t o r k b a s e d o n t h e ra t i o o f t h e ac t u al t h er mis t o r val u e us e d r e la t i v e t o t h e co m p ut e d on e: ( ) () calculated th actual th r r k = ( 9 ) 6. c a lc u l a t e val u es fo r r cs 1 and r cs 2 usin g e q ua t i o n 10: cs1 cs cs1 r k r r = ( ) ( ) ( ) cs2 cs cs2 r k k r r + ? = ( 1 0 ) fo r t h i s e x a m p l e , r cs has been calc u l a t e d t o b e 110 k?. s t a r t wi t h a ther mis t o r val u e o f 100 k?. n e xt, l o ok thr o ug h t h e a v ailab l e 06 03-size t h er misto r s, a n d f i nd a v i s h a y nths0603n01 n1003jr nt c t h er mist o r wi th a = 0.3602 a nd b = 0.09174. f r o m t h es e , com p u t e r cs 1 = 0.3795, r cs 2 = 0.7195, a nd r th = 1.075. s o l v e f o r r th , whic h y i e l ds118.28 k?. then, ch o o s e 100 k?, which mak e s k = 0.8455 . f i nal l y , r cs 1 a nd r cs 2 a r e 35.3 k? a nd 83.9 k?. ch o o s e t h e clos es t 1% r e sis t o r val u es, which yie l ds a ch o i ce o f 35.7 k? o r 84.5 k?. outpu t o f fse t the i n te l sp e c if i c a t ion r e q u ir es t h a t a t n o lo ad t h e n o m i na l o u t p ut v o l t a g e of t h e r e gu la t o r b e o f fs et t o a val u e lo w e r t h a n t h e n o minal v o l t a g e co r r es p o n d in g t o t h e vid c o de . the o f fs et is s e t b y a co n s t a n t c u r r en t s o ur ce f l o w i n g o u t of t h e fb p i n (i fb ) a nd f l o w i n g t h ro ug h r b . the va l u e o f r b ca n b e fo un d usin g e q ua tion 11: fb onl vid b i v v r ? = ? = ? = b r ( 1 1 ) the clos es t st anda r d 1 % r e sis t or val u e is 1.21 k?. adp3188 rev. a | page 18 of 28 c ou t selec t ion t h e re qu i r e d ou tput d e c o up l i ng f o r t h e re g u l a tor i s t y pi c a l l y r e co mm e nde d b y i n tel fo r va r i o u s p r o c ess o rs a nd pla t fo r m s. a l s o , to d e te r m i n e w h a t i s re qu i r e d , u s e s o me s i m p l e de s i g n guide l i n es. th e s e guide l i n es a r e b a s e d o n ha v i n g b o t h b u l k a nd cera mic ca p a ci t o rs in t h e s y s t em. the f i rs t t h in g i s t o s e le c t t h e t o t a l am o u n t o f cera mic ca p a c i - ta n c e . this is bas e d o n t h e n u m b er an d typ e o f ca p a ci t o r t o be us e d . the bes t lo c a tio n f o r cera mic ca p a c i t o rs is in side the s o c k et, wi t h 12 t o 18 o f size 120 6 bein g t h e ph ysical limi t. o t he r s c a n b e p l a c e d a l ong t h e oute r e d ge of t h e s o cke t a s wel l . c o m b in ed ceramic val u es o f 20 0 f t o 300 f a r e r e co m- m e nded , usual l y made u p o f m u l t i p le 10 f o r 22 f ca p a ci t o rs. s e lec t t h e n u m b er o f cera mic ca p a ci t o rs an d f i nd t h e t o t a l cera mic c a p a ci t a n c e (c z ). n e x t , t h e r e i s a n upp e r l i m i t i m p o s e d on t h e tot a l a m ou n t of bu l k c a p a c i t a n c e ( c x ) w h en con s ider ing t h e v i d o n -t he-f l y v o l t a g e s t ep p i n g o f t h e o u t p ut (v ol t a g e s t ep v v in tim e t v wi t h er r o r o f v err ). a lo w e r limi t is bas e d on m e et in g t h e c a p a ci - t a n c e fo r lo ad r e le as e fo r a g i ve n maxi m u m lo ad st ep ? i o an d a maxim u m al lo wa b l e o versh o o t. th e t o tal am oun t o f lo ad r e le as e v o l t a g e i s g i v e n as ? v o = ? i o r o + ? v rl , w h er e ? v rl is t h e max i m u m a l lo w a b l e o v e r sh o o t vol t a g e. () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + z vid o rl o o min x c v i v r n i l c ? ( 1 2 ) () max x c z o v vid v vid v 2 o 2 c l nkr v v t v v r nk l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 1 1 2 (13) ? ? ? ? ? ? ? ? = v err v v n k 1 where t o m e e t t h e condi t i on s o f t h es e exp r es sio n s a n d t r a n sien t re sp ons e , t h e e s r of t h e bu l k c a p a c i tor b a n k ( r x ) shou l d b e l e ss th a n t w o tim e s th e d r oo p r e si s t a n ce (r o ). i f th e c x(min) is la rger th a n c x(ma x) , t h e s y ste m c a n n ot me e t t h e v i d on-t he -f ly sp e c i- f i c a t i on a n d m a y re qu i r e t h e u s e of a s m a l l e r i n d u c t or or more p h a s e s (a n d ma y n eed th e sw i t ch i n g f r eq uen c y t o i n cr ease t o k e e p th e o u t p u t ri p p l e th e s a m e ). this exa m p l e us es 18, 10 f 1206 ml c ca p a c i t o rs (c z = 180 f). the vid on-t h e -f l y s t ep cha n g e is 450 mv in 230 s wi t h a s e t t in g er r o r o f 2.5 mv . the maxim u m al lo wab l e lo ad r e le as e o v ersh o o t fo r t h is exa m ple is 50 mv , s o s o l v in g fo r t h e b u l k ca p a ci tan c e yie l ds () mf 65 . 3 f 180 v 3 . 1 a 95 mv 50 m ? 0 . 1 4 a 95 nh 320 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + min x c () () v 3 . 1 ? m 0 . 1 6 . 4 4 mv 450 nh 320 2 2 max x c mf 48.5 f 180 1 nh 320 mv 450 ? m 1.0 4.6 4 v 1.3 s 230 1 2 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + w h er e k = 4.6. u s in g eig h t 560 f al-p ol y ca p a ci t o rs wi t h a typ i cal es r o f 5 m? eac h y i e l ds c x = 4.48 mf wi th an r x = 0. 63 m?. on e las t ch e c k sh o u ld b e made t o en s u r e t h a t t h e es l o f t h e bu l k c a p a c i t o r s ( l x ) is lo w en o u g h t o limi t the hig h f r e q ue n c y r i n g in g d u r i n g a lo ad cha n ge . this is t e st e d us in g () ph 360 2 m ? 1 f 180 2 2 2 = x o z x l q r c l (14) w h er e q is limi te d t o t h e s q ua r e r o o t o f 2 t o en s u r e a cr i t ic al l y dam p e d sys t e m . i n t h is exa m ple, l x is a p p r o x ima t e l y 350 ph f o r th e e i g h t a 1 - p o l ys ca pa ci t o rs, wh i c h sa ti sf i e s th i s li mi t a - ti o n . i f t h e l x o f t h e ch o s en b u l k c a p a c i t o r b a nk is to o l a rg e, t h e n u m b e r o f ceramic ca p a c i t o rs ma y need t o be in cr eas e d if t h er e is exces s i v e r i n g ing. n o te for t h i s m u lt i m o d e c o n t rol te ch ni qu e , a l l c e r a mi c de s i g n s ca n be us e d as l o n g as the con d i t io n s o f e q u a tio n s 11, 12, a nd 13 a r e s a tisf ied . po wer mosfe t s f o r t h is exa m ple , t h e n-cha n nel p o w e r mos f et s ha ve b e en se l e ct e d f o r o n e h i gh- s i d e swi t c h a n d t w o l o w- s i d e sw i t c h e s pe r p h ase . th e ma in s e lectio n p a ram e t e r s f o r th e p o w e r m o s f e t s are v gs(th ) , q g , c is s , c rs s , a n d r ds( o n ) . the mi ni m u m g a te dr i v e v o l t a g e (t h e s u p p l y v o l t a g e t o the ad p3418) dic t a t es w h et h e r st andard t h re shol d or l o g i c - l e ve l t h re shol d mo s f et s m u st b e us ed . w i t h v ga t e ~10 v , log i c-le v e l thr e sh old mos f e t s (v gs( t h ) < 2.5 v) a r e r e co mm ended . adp3188 rev. a | page 19 of 28 the max i m u m o u t p ut c u r r en t ( i o ) det e r m i n es t h e r ds(o n ) r e q u ir emen t fo r t h e lo w-si de (s yn chr o n o us) mos f et s. w i t h th e ad p3188, c u r r en ts a r e ba lan c e d betw een p h as es, th us t h e c u r r en t in e a ch lo w-side mos f et is t h e o u t p u t c u r r en t divi de d b y th e t o ta l n u m b e r o f m o s f e t s ( n sf ). w i t h co nd uc tio n loss es bein g do minan t , th e fol l o w in g e x p r es sio n sh o w s th e t o tal p o w e r bein g dis s i p a t e d in e a ch sy n c hro n o u s mos f et in t e r m s o f the r i ppl e c u r r e n t p e r ph as e ( i r ) and a v er a g e t o t a l out p u t c u r r e n t (i o ): () ( ) sf ds sf r sf o sf r n i n n i d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? = 2 2 12 1 1 (15) kn ow i n g t h e m a x i m u m output c u r r e n t b e i n g d e s i g n e d f o r and t h e max i m u m a l lo w e d p o w e r di ssi p a t ion, i t is p o ssi b le to f i n d th e r e q u i r ed r ds (o n ) fo r t h e mosf et . f o r d-p a k mos f et s u p t o a n am b i en t t e m p era t ur e o f 50 c, a s a fe li mi t fo r p sf is 1 w t o 1.5 w a t 120 c j u n c tion t e m p er a t ur e . th us, f o r this exa m p l e (119 a maxim u m), r ds(s f) (p er m o s f e t ) < 7.5 m?. t h is r ds( s f ) is als o a t a j u n c t i o n t e m p er a t ur e o f a b o u t 120c, s o be cer t a i n t o acco un t fo r t h is t e m p era t ur e w h en mak i n g t h is se l e cti o n . t h i s e x a m p l e u s e s t w o l o w e r - s i d e m o s f e t s a t 4.8 m? eac h a t 120 c. a n ot he r i m p o r t an t f a c t or f o r t h e s y nc h r onou s m o sf e t i s t h e i n p u t ca pa ci ta n c e a n d f eed ba c k ca pa ci ta n c e . th e ra ti o o f th e f eed ba ck t o in p u t n e ed s t o be sm all (l e s s th a n 10% i s r e co m - m e nde d) to p r e v en t acc i de n t a l t u r n -on o f t h e s y n c hr on o u s mos f et s w h e n t h e s w i t ch n o de g o es hi g h . als o , t h e t i m e to swi t ch t h e sy nc hr o n o u s mos f et s o f f s h o u l d not e x c e e d t h e no no ve r l a p d e a d t i me of t h e m o sf et d r ive r (40 n s typ i c a l f o r th e adp3418). the o u t p u t im p e dan c e o f t h e dr i v er is a p p r o x ima t e l y 2 ?, and t h e ty p i ca l mos f et in pu t ga t e r e sis t a n ces a r e abo u t 1 ? t o 2 ? , s o a t o tal g a t e ca p a ci tan c e o f les s tha n 6000 p f s h o u ld b e ad her e d t o . b e ca us e th er e a r e tw o mos f et s in p a ral l e l , t h e in p u t c a p a ci t a nc e fo r e a ch sy nchr on ous m o s f e t sh o u l d b e limi t e d t o 3000 pf . the hi g h -si d e ( m a i n) mos f et has t o b e ab le to ha n d le tw o ma in p o w e r di ssi p a t i o n com p on e n ts: cond uc t i o n a nd s w i t chi n g los s es. th e s w i t chin g los s is r e l a t e d t o t h e am oun t o f t i m e i t t a kes fo r t h e main mos f e t to tu r n o n and o f f, and to t h e c u r r e n t and v o l t a g e t h a t a r e b e ing s w i t che d . b a s i n g t h e s w i t ching s p e e d on t h e r i s e a nd fal l t i m e of t h e ga t e dr i v er im p e dan c e and m o sf e t i n put c a p a c i t a nc e, t h e f o l l ow i n g e x pre s s i on prov i d e s a n a p p r o x i m a t e val u e fo r t h e s w i t chin g los s p e r ma in mos f et , w h er e n mf is the t o tal n u m b er o f ma in m o s f et s: () iss mf g m f o cc sw mf s c n n r n i v f p = 2 (16) w h er e r g is th e t o tal ga te r e sis t an ce (2 ? f o r th e ad p3418 a nd a b o u t 1 ? fo r typ i ca l h i g h sp e e d swi t chi n g mosfet s, ma k i n g r g = 3 ? ) , and c iss is t h e i n p u t c a p a ci t a nc e o f t h e mai n mos f et . n o t e t h a t adding m o r e main mos f e t s ( n mf ) do es n o t r e all y he l p t h e s w i t chin g los s p e r mos f et b e c a us e t h e addi t i o n al ga t e ca p a ci tan c e s l o w s swi t c h ing. th e best wa y t o r e d u ce s w i t c h in g los s is t o us e lo w e r ga t e c a p a ci t a n c e de vices. the con d uc t i o n los s o f th e ma in m o s f e t is g i v e n b y the fol l o w in g, w h ere r ds(m f) i s t h e on re s i st a n c e of t h e m o sf e t : () ( ) mf ds mf r mf mf c r n i n n d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = 2 2 o 12 1 i (17) t y p i c a l l y , fo r main mos f e t s, t h e h i g h est sp e e d ( l o w c is s ) de vice is p r efer r e d , b u t t h es e us ual l y ha v e hig h e r o n r e sis t a n c e . se l e ct a d e v i c e th a t m e e t s th e t o t a l po w e r d i s s i p a t i o n ( a b o u t 1.5 w f o r a sin g le d-p a k) w h en com b inin g t h e swi t c h in g and co nd uc tio n loss es. f o r t h i s e x am pl e, an n t d 4 0 n 0 3 l w a s s e l e c t e d a s t h e m a i n mos f et ( e ig h t to t a l ; n mf = 8), wi th a c is s = 584 pf (max) a n d r ds(m f) = 19 m? (max a t t j = 12 0c), a nd an ntd110 n02l was s e le c t e d as t h e syn c hr on o u s mos f et (eig h t to tal; n sf = 8), wi th c is s = 2710 pf ( m ax) a nd r ds(s f) = 4.8 m? (max a t t j = 120c). the sy n c hr o n ous mos f et c is s is les s than 30 00 pf , s a tisf yin g tha t r e q u i r em en t . s o l v in g f o r t h e p o w e r d i s s i p a t io n p e r m o s f et a t i o = 119 a and ir = 1 1 a y i e l ds 9 58 mw f o r e a ch s y n c hr ono u s mos f et and 8 7 2 mw fo r e a ch main mos f e t . the s e n u mb ers c o m p l y w i t h th e g u i d e l i n e t o l i m i t th e po w e r d i s s i p a t i o n t o 1 w pe r m o s f e t . on e las t t h i n g to co n s ider is t h e p o w e r di s s i p a t io n i n t h e dr i v e r fo r e a ch phas e . this is b e st des c r i b e d i n t e r m s o f t h e q g fo r t h e mos f et s an d i s g i ven b y t h e fol l o w i n g e q ua t i on, w h er e q gmf is th e t o tal ga t e c h a r g e f o r ea c h m a i n m o s f et , a n d q gs f is t h e tot a l g a te charge for e a ch s y nch r onou s mo s f et : ( ) cc cc gsf sf gmf mf sw drv v i q n q n n f p ? ? ? ? ? ? ? ? + + = 2 (18) als o sh o w n is t h e st andb y dissi p a t io n fac t o r (i cc v cc ) f o r th e dr i v er . f o r th e ad p3418, t h e maxim u m dis s i p a t io n sh o u l d b e les s tha n 400 mw . i n this exa m p l e , wi th i cc = 7 ma, q gmf = 5.8 nc, and q gs f = 48 nc, 297 mw is f o u n d in eac h dr iv er , which is b e lo w t h e 400 mw dis s i p a t ion limi t. s e e the ad p3418 da ta sh ee t f o r m o r e d e ta ils. adp3188 rev. a | page 20 of 28 r a mp resist or selec t ion the r a m p r e sisto r ( r r ) i s u s e d f o r s e t t i n g th e s i z e o f th e i n t e rn a l pwm ra m p . the val u e o f this resis t o r is c h os en t o p r o v ide t h e b e st com b i n a t ion o f t h er m a l b a l a n c e, st ab i l i t y , and t r a n sie n t r e sp o n s e . t h e fol l o w in g exp r essio n is us e d fo r det e r m ini n g t h e opt i m u m v a lu e : k ? 356 pf 5 ? m 2.4 5 3 nh 320 0.2 3 = = = r r ds d r r r c r a l a r (19) w h er e a r is t h e in t e r n a l ra m p am plif ier ga in, a d is t h e c u r r en t bala n c in g a m p l if i e r ga i n , r ds i s th e t o tal lo w - sid e m o s f e t o n re s i st anc e , a n d c r is the in t e r n al ra m p ca p a ci to r val u e . th e c l os es t s t anda r d 1% r e sis t o r val u e is 357 k?. the i n t e r n al ram p v o l t a g e ma g n i t ude ca n b e c a lc u l a t e d b y usin g () () v m 390 khz 330 pf 5 ? k 357 v 1.3 0.108 1 0.2 1 = ? = ? = r sw r r vid r r v f c r v d a v ( 2 0 ) the size o f t h e in t e r n al ram p can b e made la rg er o r smal ler . i f i t is made la rger , st a b i l i t y a nd t r a n sien t r e sp on s e i m p r o ve, b u t t h er ma l bal a n c e deg r ades. l i k e wis e , if t h e ram p is made smal ler , t h er ma l b a lan c e i m p r o v es a t t h e s a cr if i c e o f t r a n sien t re sp ons e a n d st abi l it y . t h e f a c t or of t h re e i n t h e d e nom i n a tor of eq ua ti o n 19 sets a ra m p siz e tha t gi v e s a n o p tim a l ba la n c e f o r g o o d s t ab il i t y , t r a n sien t r e sp o n s e , an d ther mal balan c e . c o mp pin r a mp a ra m p sig n al on t h e c o mp pi n is d u e t o t h e dr o o p v o l t a g e a nd o u tp u t vol t a g e r a m p s. this r a m p a m pli t u d e adds to t h e in t e r n al ra m p to p r o d uce t h e fol l o w in g o v eral l ra m p sig n al at t h e p w m i n p u t : ( ) ? ? ? ? ? ? ? ? ? ? = o x sw r rt r c f n d n v v 1 2 1 ( 2 1 ) i n this exa m p l e , th e o v eral l ra m p sig n al is 0.49 v . current -limit se tpoi nt t o s e le c t t h e c u r r en t-li mi t s e t p o i n t , f i rst f i nd t h e r e sist o r val u e fo r r lim . th e c u r r en t-l i mi t thr e s h ol d f o r th e ad p3188 is s e t wit h a 3 v so u r ce (v li m ) ac r o s s r lim wi th a g a in o f 10.4 mv/ a (a li m ). r lim can b e fo und usin g o lim lim lim lim r i v a r = (22) fo r v a lu e s o f r lim gr ea t e r th a n 500 k ? , th e curr e n t lim i t m a y b e l o w e r th a n e x pe ct e d , so so m e ad j u s t m e n t o f r lim ma y b e n e e d e d . he r e , i li m is t h e a ver a g e c u r r e n t li mi t fo r t h e o u t p ut o f t h e s u p p ly . i n this exa m p l e , c h o o sin g a p e a k c u r r en t limi t o f 200 a f o r i lim , re su lt s i n r lim = 156 k?, f o r whic h 150 k? is chos en as t h e ne are s t 1 % v a lu e. the limi t o f t h e p e r - phas e c u r r en t li mi t des c r i b e d e a rlier is deter m i n e d b y () () 2 r max ds d bias r max comp phlim i r a v v v i + ? ? ? (23) f o r t h e ad p31 88, t h e maxi m u m c o mp v o l t ag e (v co m p ( m ax ) ) is 3.3 v , t h e co mp p i n b i as v o l t a g e (v bi a s ) is 1.2 v , an d t h e c u r r e n t - b a la n c in g a m p l i f ie r ga in (a d ) is 5 . u s ing v r o f 0. 49 v and r ds(max ) o f 3 m? (lo w -side o n r e sis t a n c e a t 150c), calc u l a t e a p e r - p h as e p e a k c u r r en t limi t o f 100 a. al t h oug h this n u m b er ma y s e e m hig h , this c u r r en t le vel ca n be r e ach e d o n l y wi t h an a b s o l u t e sh o r t a t th e o u t p u t , a n d th e cu rr e n t - li m i t la t c h - o f f fun c - t i on sh u t s do wn t h e re g u l a t o r b e f o re ov e r he at i n g c a n o c c u r . this limi t ca n b e ad j u s t e d b y c h a n g i n g t h e ra m p v o l t a g e (v r ), b u t ma k e sur e no t t o s e t t h e p e r - phas e li mi t lo wer t h a n t h e a v era g e p e r - phas e c u r r en t (i lim /n ). the p e r - phas e ini t ial d u ty c y cle limi t is de t e r m in e d b y () rt bias max comp max v v v d d ? = ( 2 4 ) i n t h is exa m ple , t h e maxim u m d u ty c y cle is 0.46. feedba ck l o op c o m p e n sa tion de sign o p ti m i z e d c o m p e n sa ti o n o f th e a d p 3 18 8 a llo w s th e be s t p o ss i b l e re s p ons e of t h e re g u l a tor s output to a l o a d ch a n ge . t h e basis fo r deter m inin g t h e o p t i m u m com p e n s a t i o n is t o make t h e r e gu l a t o r and out p ut de co upl i ng a p p e a r as an out p ut i m p e d a n c e t h a t is e n t i rely resist iv e o v er t h e w i de st p o ss ib le f r e q u e n c y r a n g e, i n cl u d ing dc , and e q u a l to t h e dro o p resi st an c e ( r o ). w i th th e r e s i s t i v e o u t p u t i m ped a n c e , th e o u t p u t v o l t a g e d r oo p s i n prop or t i on t o t h e l o a d c u r r e n t at a n y l o a d c u r r e n t - sl e w r a te . t h i s e n s u r e s th e o p ti m a l posi tio n i n g a n d allo ws th e mini mi za t i o n of t h e o u t p ut de c o u p lin g . w i t h t h e m u l t im o d e f eedbac k s t r u c t ur e o f th e ad p3188, t h e f eed ba ck co m p en sa ti o n m u s t b e se t t o m a k e t h e co n v e r t e r s o u t p ut i m p e dance, w o rk i n g i n p a r a l l el w i t h t h e o u t p ut de co u p - lin g , t o me et t h is g o al . s e v e ral p o les a n d zer o s cr e a t e d b y t h e o u t p ut i n d u c t o r a nd de co u p l i n g ca p a ci to rs (o u t p u t f i l t er ) n e e d to b e c o m p e n s a te d for . adp3188 rev. a | page 21 of 28 a t y pe- t h r ee co m p en sa t o r o n t h e v o l t a g e f e e d b a c k i s a d e q ua t e f o r prop e r c o m p e n s a t i on of t h e output f i lte r . e q u a t i ons 2 5 to 2 9 y i el d an op t i ma l s t a r tin g p o in t fo r th e d e si g n ; so m e ad j u s t m e n t s ma y b e n e ces s a r y to a c c o u n t for p c b an d c o m p one n t p a r a s i t i c e f f e ct s ( s ee th e s e cti o n ) . the f i rs t st ep is t o co m p u t e t h e t i m e co n s t a n t s fo r al l o f t h e p o les a nd zer o s in t h e sys t em ( ) vid o x rt vid rt l ds d o e v r c n v d n l v v r r a r n r ? + + + = 1 2 ( ) ? m 24.2 v 1.3 ? m 1 mf 4.45 4 v 0.49 0.432 1 nh 320 2 v 1.3 v 0.49 ? m 1.4 ? m 2.4 5 ? m 1 4 = ? + + + = e r ( 2 5 ) () () s 2.50 ? m 10.63 ? m 0.65 ? m 1 ? m 1 ph 350 ? m 0.5 ? m 1 mf 4.45 = ? + ? = ? + ? = x o o x o x a r r r r l r r c t (26) () ( ) ns 580 mf 4.45 ? m 1 ? m 0.5 ? m 0.63 = ? + = ? + = x o x b c r r r t ( 2 7 ) s 4.7 ? m 24.2 v 1.3 khz 330 2 ? m 2.4 5 nh 320 v 0.49 2 = ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? = e vid sw ds d rt c r v f r a l v t ( 2 8 ) () ( ) () ns 333 ? m 1 f 180 ? m 0.5 ? m 1 mf 4.45 ? m 1 f 180 mf 4.45 ' 2 2 = + ? = + ? = o z o x o z x d r c r r c r c c t (29) wher e , f o r th e ad p3188, r' is the pcb r e sis t an c e f r o m th e b u l k c a p a ci t o rs t o th e cera mics a nd w h er e r ds is th e t o tal lo w - side m o s f et o n r e sis t an ce p e r p h as e . i n this ex a m p l e , a d is 5, v rt eq uals 0.49 v , r' is a p p r o x ima t e l y 0.5 m? (as s u min g a 4-l a yer , 1 o u n c e m o t h er b o a r d), a nd l x is 350 p h f o r th e eig h t al-p ol y c a p a ci to rs. the c o m p ens a t i o n v a l u es c a n t h en b e s o l v e d usi n g t h e fol l o w i ng : pf 342 ? k 1.21 ? m 24.2 s 2.50 ? m 1 4 = = = ca r r t r n c b e a o a ( 3 0 ) ? k 13.7 pf 342 s 4.7 = = = a c a c t r (31) nf 479 ? k 1.21 ns 580 = = = b b b r t c ( 3 2 ) f p 24.3 ? k 13.7 ns 333 = = = a d fb r t c ( 3 3 ) th e s e a r e t h e s t a r t i n g val u es, p r io r t o t u nin g t h e desig n , t o acco un t f o r la y o u t a n d o t h e r p a rasi tic ef f e cts (see the sect io n ) . the f i nal v a l u es s e le c t e d a f t e r t u nin g a r e pf 22 pf 470 ? k 1 . 12 pf 470 = = = = fb b a a c c r c adp3188 rev. a | page 22 of 28 f i gur e 12 an d f i gur e 13 sh o w t h e typ i c a l tra n sien t r e s p o n s e us i n g th ese co m p e n sa t i o n val u es . 04835-0-012 f i gur e 1 2 . t y pi c a l t r a n sient respo n se f o r des i gn ex am p l e l oad st ep 04835-0-013 f i gur e 1 3 . t y pi c a l t r a n sient respo n se f o r des i gn ex am p l e l oad r e le as e c in selec t ion and inpu t current d i /d t r e duc t io n i n con t in uo us ind u c t o r c u r r en t m o de , t h e s o ur ce c u r r en t o f t h e hig h -sid e mosfet is a p p r o x i m a t e l y a s q ua r e wa v e w i t h a d u t y ra tio eq ual t o n v ou t /v in an d a n a m pl i t ude o f o n e- n t h t h e maxim u m o u t p u t c u r r en t. t o pr e v en t la rg e v o l t a g e t r a n sie n ts, a lo w es r i n p u t ca pa ci t o r , si z e d f o r th e m a xim u m rm s curr e n t, m u s t be u s ed . th e ma xi m u m r m s c a pa ci t o r curr e n t i s gi v e n b y a 14.7 1 0.108 4 1 a 19 1 108 . 0 1 1 = ? = ? = crms o crms i d n i d i (34) n o t e t h a t t h e c a p a ci t o r ma n u f a c t ur er s r i p p le c u r r en t ra t i n g s ar e o f t e n bas e d o n o n l y 2,000 h o urs o f lif e . this mak e s i t advis a b l e to f u r t he r de r a t e t h e c a p a c i tor , or to cho o s e a c a p a c i tor r a te d a t a hig h er t e m p era t ur e t h a n r e q u ir e d . s e v e ra l ca p a ci t o rs ma y b e place d in p a ra l l e l t o m e et s i z e o r h e ig h t r e q u ir e m e n ts in t h e d e s i gn . i n th i s e x a m p l e , th e i n p u t c a pa ci t o r b a nk i s f o rm e d b y tw o 2,700 f , 16 v al umin u m e l ec tr ol ytic ca p a ci t o rs a nd eig h t 4.7 f cera mic ca p a ci t o rs. t o r e d u ce t h e i n p u t c u r r en t di /d t t o a le ve l b e lo w t h e r e co m- m e nde d m a x i m u m o f 0.1 a/s, a n ad di t i o n a l s m a l l i n d u c t o r (l > 370 nh a t 18 a) s h o u l d be in s e r t e d b e tw e e n t h e con v er t e r a nd t h e s u p p l y b u s. tha t ind u c t o r als o ac ts as a f i l t er betw een t h e co n v er t e r and t h e p r ima r y p o w e r s o ur ce . 0 2 0 4 0 6 0 8 0 100 120 100 80 60 40 20 0 e fficie ncy (%) output current (a) v out = 1.3 v t a = 25 04835-014 f i gure 14. e fficienc y of the c i rcuit of f i gur e 10 v s . o u tput current adp3188 rev. a | page 23 of 28 tuning the adp3188 1. bui l d a c i r c ui t b a s e d o n t h e com p e n s a t i on va lues c o m p u t e d f r om t h e de s i g n sp re a d she e t. 2. h o ok u p t h e dc lo ad t o cir c ui t, t u r n i t on, an d ver i f y i t s o p era t ion. als o , ch e c k fo r ji t t e r a t n o lo ad an d f u l l lo ad . dc loadline s e tting 3. m e as ur e t h e o u t p u t v o l t a g e a t no lo ad (v nl ). v e r i f y tha t i t is wi t h i n t o leran c e. 4. m e as ur e t h e o u t p u t v o l t a g e a t f u l l lo ad cold (v fl c o l d ). let th e boa r d si t f o r ~1 0 mi n u t e s a t f u ll l o ad , a n d th en m e as u r e th e o u t p u t (v flh o t ). i f th er e is a c h a n g e o f m o r e tha n a f e w mi l l i v ol ts, a d j u st r cs 1 a nd r cs 2 usin g e q u a tio n s 35 a nd 36. () ( ) flhot nl flcold nl old cs2 new cs2 v v v v r r ? ? = (35) 5. rep e a t st ep 4 u n t i l t h e col d and h o t v o l t a g e me as ur emen t s r e ma in t h e s a me. 6. m e as ur e t h e o u t p u t v o l t a g e f r o m n o -lo a d t o f u l l -lo a d usin g 5 a s t eps. c o m p u t e t h e lo adl i ne s l o p e fo r e a ch cha n g e , an d t h e n a v era g e t o g e t t h e o v eral l l o adli n e s l op e ( r om e a s ). 7. if r om e a s i s of f f r om r o b y m o r e tha n 0.05 m?, us e the fol l o w ing to a d ju st t h e r ph val u es: () () o omeas old ph new ph r r r r = ( 3 6 ) 8. rep e a t st eps 6 and 7 t o ch e c k t h e lo ad li n e , and r e p e a t adj u st me n t s if ne c e ss ar y . 9. on ce dc lo adline ad j u s t m e n t is co m p let e , do n o t c h a n g e r ph , r cs 1 , r cs 2 , o r r th f o r r e ma in der o f p r o c ed ur e . 10. m e as ur e t h e o u t p u t r i p p le a t n o lo ad a nd f u l l lo ad wi t h a s c o p e , an d m a k e sur e i t is w i t h in sp e c if i c a t ion s . () () ( ) () ( ) ( ) ( ) () () ( ) () () c 25 c 25 c 25 c 25 1 1 ? ? ? + + = th th old cs1 new cs2 old cs1 th old cs1 th old cs1 new cs1 r r r r r r r r r r (37) adp3188 rev. a | page 24 of 28 ac loadline s e tting 11. re m o v e t h e dc l o ad f r o m t h e c i r c ui t and ho ok up t h e dy n a m i c l o a d . 12. h o ok u p t h e s c o p e t o t h e o u t p u t v o l t a g e and s e t i t t o dc co u p ling, wi t h t h e t i m e s c ale a t 100 s/div . 13. s e t t h e d y na mic lo ad fo r a t r a n sien t s t ep o f ab ou t 40 a a t 1 khz wi t h a 50 % d u ty c y cle. 14. m e as ur e t h e o u t p u t w a v e fo r m (i f n o t visib l e , us e dc o f fs et o n s c o p e t o vie w ). t r y t o us e a v e r t ical s c ale o f 100 mv/div o r f i n e r . this wa v e f o r m sh o u ld lo ok simil a r t o f i gur e 15. v acdrp v dcdrp 04835-015 f i g u re 15. a c l oad l i ne w a vef o r m 15. u s e t h e h o r i zo n t al c u rs o r s t o me as ur e v ac d r p a nd v dc d r p as shown. d o n o t m e a s ure t h e un d e r s h o ot or ov e r sh o o t t h a t ha ppens im med i a t e l y a f ter th i s s t ep . 16. if v ac d r p a nd v dc d r p a r e dif f er en t b y m o r e t h an a fe w mil l i v ol ts, us e e q ua t i o n 38 t o ad j u s t c cs . it m a y b e n e c - es s a r y t o p a ral l e l dif f er en t val u e s t o g e t t h e co r r e c t o n e as t h er e a r e l i mi t e d s t anda rd ca p a ci t o r val u es a v a i la b l e . i t is a g o o d idea t o ha v e lo ca t i o n s f o r tw o c a p a ci t o rs in t h e l a yo u t fo r t h is. () () dcdrp acdrp old cs new cs v v c c = ( 3 8 ) 17. rep e a t s t eps 11 t o 13, a nd r e p e a t the ad j u s t men t s if n e cess a r y . on c e co m p let e , do no t c h a n g e c cs fo r t h e r e ma inder o f t h e p r o c e d ur e. 18. s e t t h e d y na mic lo ad s t ep t o maxim u m s t ep s i ze (do n o t us e a s t ep si ze larg er t h a n n e e d e d ) a nd v e r i f y t h a t t h e o u t p u t wa v e f o rm i s sq ua r e , whi c h m e a n s th a t v ac d r p a nd v dc d r p are e q u a l . initial t r a n sient s e tting 19. w i th th e d y n a m i c l o a d s t i l l s e t a t th e m a x i m u m s t e p s i z e , exp a n d t h e s c op e t i m e s c al e t o s e e 2 s/ d i v t o 5 s/div . th e w a ve for m m a y ha ve t w o o v e r s h o o t s and one m i nor un d e r - sho o t ( s e e f i g u re 1 6 ) . h e re, v dr o o p i s t h e f i nal desi r e d va l u e. v droop v tran1 v tran2 04835-0-016 f i gure 1 6 . t r a n sient setti ng w a v e f o rm 20. i f b o t h o v ersho o ts a r e la rg er t h a n desir e d , t r y making t h es e a d j u s t m e n t s : n o t e th a t i f th e s e a d j u s t m e n t s do n o t cha n ge t h e r e sp o n s e , t h e ou t p u t d e c o u p li n g i s th e li m i ti n g f a ct o r . ch ec k th e output re sp on s e e v e r y t i m e a c h a n g e i s m a d e , o r n o d e s are s w itc h e d , to m a ke su re t h e re sp ons e re m a i n s st abl e . ? m a k e t h e ram p r e sis t o r la rg er b y 25% (r ra mp ). ? fo r v tran 1 , in cre a s e c b , o r in c r ea se t h e swi t c h in g fr e q u e n c y . ? fo r v tran 2 , in cre a s e r a , an d de cr e a s e c a by 2 5 % . 21. f o r lo ad r e le as e (s e e f i gur e 17), if v tran re l is la rger th a n v tran 1 (see f i gur e 16), th e r e i s n o t en o u gh o u t p u t ca pa ci ta n c e . ei t h e r m o r e ca pa ci ta n c e i s n eed e d , o r th e ind u c t o r val u es n e e d t o be smal ler . (i f ind u c t o r s a r e ch ange d, s t ar t t h e d e s i g n ag ai n u s i n g t h e spre a d sh e e t a nd t h is t u n i n g p r o c e d ur e.) v droop v tranrel 04835-0-017 f i gure 1 7 . t r a n sient setti ng w a v e f o rm adp3188 rev. a | page 25 of 28 because the adp3188 turns off all of the phases (switches inductors to ground), there is no ripple voltage present during load release. thus, headroom does not need to be added for ripple, allowing load release v tranrel to be larger than v tran1 by the amount of ripple, and still meet specifications. if v tran1 and v tranrel are less than the desired final droop, this implies that capacitors can be removed. when removing capaci- tors, also check the output ripple voltage to make sure it is still within specifications. adp3188 rev. a | page 26 of 28 layout and component placement the following guidelines are recommended for optimal performance of a switching regulator in a pc system. general recommendations for good results, a pcb with at least four layers is recommended. this allows the needed versatility for control circuitry inter- connections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 m? at room temperature. whenever high currents must be routed between pcb layers, vias should be used liberally to create several parallel current paths. then, the resistance and inductance introduced by these current paths is minimized, and the via current rating is not exceeded. if critical signal lines (including the output voltage sense lines of the adp3188) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the signals at the expense of making signal ground noisier. an analog ground plane should be used around and under the adp3188 as a reference for the components associated with the controller. this plane should be tied to the nearest output decoupling capacitor ground and not tied to any other power circuitry to prevent power currents from flowing in it. the components around the adp3188 should be located close to the controller with short traces. the most important traces to keep short, and away from other traces, are the fb and cssum pins. the output capacitors should be connected as close as possible to the load (or connector), for example, a micro- processor core, that receives the power. if the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. avoid crossing any signal lines over the switching power path loop, as described next. power circuitry recommendations the switching power path should be routed on the pcb to encompass the shortest possible length in order to minimize radiated switching noise energy (emi) and conduction losses in the board. failure to take proper precautions often results in emi problems for the entire pc system as well as noise-related operational problems in the power converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors and the power mosfets, including all interconnecting pcb traces and planes. using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. whenever a power dissipating component, for example, a power mosfet, is soldered to a pcb, the liberal use of vias, both directly on the mounting pad and immediately surround- ing it, is recommended. this improves current rating through the vias and also improves thermal performance from vias extended to the opposite side of the pcb, where a plane can more readily transfer the heat to the air. make a mirror image of any pad being used to heat-sink the mosfets on the opposite side of the pcb to achieve the best thermal dissipation to the air around the board. to further improve thermal performance, use the largest possible pad area. the output power path should also be routed to encompass a short distance. the output power path is formed by the current path through the inductor, the output capacitors, and the load. for best emi containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. signal circuitry recommendations the output voltage is sensed and regulated between the fb pin and the fbrtn pin, which connect to the signal ground at the load. to avoid differential-mode noise pickup in the sensed signal, the loop area should be small. thus, the fb and fbrtn traces should be routed adjacent to each other on top of the power ground plane back to the controller. the feedback traces from the switch nodes should be con- nected as close as possible to the inductor. the csref signal should be connected to the output voltage at the nearest inductor to the controller. adp3188 rev. a | page 27 of 28 outline dimensions compliant to jedec standards mo-153ae 28 15 14 1 8 0 seating plane coplanarity 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 f i gure 18. 2 8 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 28) di me nsio ns sho w n i n mi ll im e t e r s 28 1 5 14 1 pin 1 sea t i n g pl a n e 8 0 0. 236 bs c 0 . 154 bs c 0. 0 1 2 0. 0 0 8 0. 025 bs c 0. 010 0. 004 coplanarity 0.004 0. 065 0. 049 0. 069 0. 053 0. 010 0. 006 0. 050 0. 016 0. 390 bs c compliant to jedec standards mo-137af f i gure 19. 2 8 -l ead shrink sm al l o u t lin e p a ckage [qs o p ] (r q - 28) d i mensions sh o w n in inc h es ordering guide model temperature r a nge package descri pt ion package option quantity per r eel ADP3188JRUZ-REEL 1 0c to 85c thin shrink small o utline package 13 reel ru-28 2500 adp3188jrqz-reel 1 0c to 85c shrink small ou tline package 13 reel rq-28 2500 1 z = pb-free part. adp3188 rev. a | page 28 of 28 notes ? 2005 analo g d e vices, inc. all rights reser v ed. tra d emarks and r e gistered trad e m arks are t h e pr op e r ty o f th eir r e spectiv e o w n e rs. d04835C0C 4/05(a) |
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