View CYPSI2G50P456-1MGC_3896038.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary programmable bandwidth programmable serial interface device family (high speed) cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-02021 rev. ** revised april 2001 features ? 200 mbps ? 1.5 gbps, 2.5 gbps serial signaling rate flexible parallel-to-serial conversion in transmit path flexible serial-to-parallel conversion in receive path multiple selectable loopback/loop-through modes 50k to 200k usable gates of cpld logic 120k to 480 kb of integrated memory ? 96k to 384 kb of synchronous or asynchronous sram ? 24k to 96 kb of true dual-port or fifo ram internal transmit and receive plls logic dedicated spread aware pll transmit fifo for flexible variable phase clocking differential cml serial input with internal termination and dc-restoration differential cml serial output with source matched im- pedance of 50 ? 160?240 user programmable i/os any volt i/o interface ? programmable as 1.8v, 2.5v, 3.3v multiple i/o standards ? lvcmos, lvttl, 3.3v pci, sstl2(i-ii), sstl3(i-ii), hstl(i-iv), and gtl+ direct interface to standard fiber-optic modules designed to drive: ? fiberoptic modules ? copper cables ? circuit board traces ? backplane links ? box-to-box links ? chip-to-chip communication extremely flexible clocking options ? four global clocks ? up to 192 additional product term clocks ? clock polarity at every register carry chain logic for fast and efficient arithmetic operations fully pci compliant (rev. 2.2) jtag programming interface with boundary scan sup- port high-speed (hs) or frequency agile (fa) programma- ble serial interface (psi) versions available high-speed psi features 2.5 gbps/channel serial signaling rate full bellcore and itu jitter compliance power-saving mode up to two serial channels available to allow: ? high-bandwidth ? redundancy supported standards: ? infiniband? ? sonet oc-48 frequency agile psi features [1] 200 mbps?1.5 gbps serial signaling rate per channel up to eight serial channels available to allow: ? frequency agile ? redundancy selectable input and output clocking options multiframe? receive framer provides alignment to: ? bit, byte, half-word, word, multi-word ? comma or full k28.5 detect ? single or multi-byte framer for byte alignment ? low-latency option skew alignment support for multiple bytes of offset selectable parity check/generate serial built-in-self-test (bist) for at-speed link testing per-channel link quality indicator ? analog signal detect ? digital signal detect ? frequency range detect supported standards: ?fibre channel ? gigabit ethernet ?escon ?dvb ?smpte development software ?warp? ? ieee 1076/1164 vhdl or ieee 1364 verilog context sensitive editing ? active-hdl fsm graphical finite state machine editor ? active-hdl sim post-synthesis timing simulator ? architecture explorer for detailed design analysis ? static timing analyzer for critical path analysis ? available on windows 95, 98 & nt for $99 ? supports all cypress programmable logic products note: 1. for detailed data sheet see ? frequency agile psi data sheet. ?
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 2 of 59 psi quick reference selection guide note: 2. s-sonet (oc-48) 3. standby i cc values are with pll not utilized, no output load, and stable inputs. logic gate density high-speed ? psi serial bandwidth frequency-agile ? psi serial bandwidth 1 x 2.5 gbps 2 x 2.5 gbps 4 x 200 mbps ? 1.5 gbps 8 x 200 mbps ? 1.5 gbps 50k psi2g50(s) [2] 100k psi2g100(s) psi5g100(s) psi6g100 200k psi5g200(s) psi6g200 psi12g200 psi family standards supported psi device infiniband sonet (s) (oc-48) fibre channel gigabit ethernet escon dvb smpte high speed psi2g50(s) xx psi2g100(s) xx psi5g100(s) xx frequency agile psi6g100 xxxxx psi6g200 xxxxx psi12g200 xxxxx high speed psi family general selection guide device typical gates macrocells cluster memory (kbits) channel memory (kbits) maximum user programmable i/o package offering psi2g50(s) 23k ? 72k 768 96 24 160 456-bga (35x35 mm, 1.27 mm pitch) psi2g100(s) 46k ? 144k 1536 192 48 240 456-bga (35x35 mm, 1.27 mm pitch) psi5g100(s) 46k ? 144k 1536 192 48 194 456-bga (35x35 mm, 1.27 mm pitch) high speed psi family performance selection guide device channels & link speed total bandwidth f max2 (mhz) logic speed ? t pd pin-to-pin (ns) standby i cc [3] psi2g50(s) 1 x 2.5 gbps 2.5 gbps 222 7.0 11 ma psi2g100(s) 1 x 2.5 gbps 2.5 gbps 200 7.5 11 ma psi5g100(s) 2 x 2.5 gbps 5.0 gbps 200 7.5 11 ma
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 3 of 59 figure 1. high-speed psi block diagram (cypsi5g100) with i/o bank structure xcvr cntrl & i/o 2 gclk[1:0] 2 2 2 channel ram 2 gclk[1:0] 2 2 2 2 gclk[1:0] 2 2 2 4 2 gclk[1:0] pll & clock mux gctl[3:0] i/o bank i/o bank i/o bank i/o bank i/o bank i/o bank lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram tx rx serial signal bank phase align buffer serializer deserializer tx rx phase align buffer serializer deserializer
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 4 of 59 figure 2. high-speed psi block diagram (cypsi2g100) with i/o bank structure 2 gclk[1:0] 2 2 2 channel ram 2 gclk[1:0] 2 2 2 2 gclk[1:0] 2 2 2 4 2 gclk[1:0] pll & clock mux gctl[3:0] i/o bank i/o bank i/o bank i/o bank i/o bank i/o bank lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram tx rx xcvr cntrl & i/o serial signal bank phase align buffer serializer deserializer
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 5 of 59 functional description the programmable serial interface (psi) family is a point-to- point or point-to-multipoint programmable communications building block allowing the manipulation and transfer of data over high-speed serial links at signaling speeds ranging from 200 mbps-to-1.5, and 2.5 gbps per serial link. the psi family is designed to combine the high speed, predictable timing, high density, low power, and ease of use of complex program- mable logic devices (cpld) with the serializing/deserializing (serdes) capability of high-speed serial transceivers. the family is divided into two groups: high-speed psi and fre- quency ? agile psi. both groups have unique transceiver characteristics that define the specific transceiver block oper- ation of a given psi device. the architecture of the device is based on logic block clusters (lbc) and serial transceiver blocks that are connected by hor- izontal and vertical routing channels. each lbc features eight individual logic blocks (lb) of 16 marcrocells and two cluster memory blocks. adjacent to each lbc is a channel memory block which is externally accessible through the i/o interface. each transmit channel of the transceiver accepts parallel char- acters, encodes each character for transport and converts it to serial data. each receive channel accepts serial data and con- verts it to parallel data, decoding the data into characters and presents these characters to the routing channels of the psi unit. high-speed psi the transceiver operation of the high-speed programmable serial interface devices is self-contained in a single block. it has separate transmit and receive plls and a clock and data recovery (cdr) unit for flexible clocking. the transmit chan- nel accepts a 16-bit input character from the routing channels and passes the character to an elasticity buffer. this character is then serialized and output on dual differential transmission- line drivers at the required bit-rate. the receive channel ac- cepts a serial bit-stream from the two differential line receivers. this bit-stream is deserialized and a 16-bit character is pre- sented to the routing channels in the psi device. the block also features loop-back and loop-through modes for simplified design debugging. global routing description the routing architecture in the pld block of a psi device is made up of horizontal and vertical (h&v) routing channels. these routing channels allow signals to move among i/os, logic blocks and memories. in addition to the horizontal and vertical routing channels that interconnect the i/o banks, channel memory blocks, transceiver blocks and logic block clusters, each lbc contains a programmable interconnect matrix (pim ? ), which is used to route signals among the logic blocks and the cluster memory blocks in the lbc. figure 5 is a block diagram of the routing channels that inter- face within the psi architecture. the lbc is exactly the same for every member of the psi family. transceiver block each transceiver block of a given psi device will have one serializer transmit path and one deserializer receive path op- erating at a speed from 200 mbps to 1.5 or 2.5 gbps. the transceiver block interfaces to the routing channels of the psi device through highly configurable datapath cells. for specific architecture and operation of the transceiver blocks please re- fer to the serial transceiver operation section (page 17). high-speed psi transceiver blocks high-speed psi devices include one or two transceiver blocks operating at 2.5 gbps per channel. both channels operate in- dependently of each other. they use the same reference clock. the internal interfacing to the transceiver blocks of the high- speed device occur through the port definition of the high- speed transceiver block. the internal signals and their defini- tion are described in the ? pin & signal description ? section (page 46). standard datapath cell figure 4 is a block diagram of the psi datapath cell. the data- path cell contains a three-state transmit buffer, a receive buff- er, and a register that can be configured as an transmit or receive register. the transceiver enable (te) can be selected from one of the four global control signals or from one of two output control channel (occ) signals. the transmit enable can be config- ured as always enabled or always disabled or it can be con- trolled by one of the remaining inputs to the mux. the selection is done via a mux that includes v cc and gnd as inputs. one of the global clocks can be selected as the clock for the datapath cell register. the clock mux output is an input to a clock polarity mux that allows the transmit/receive register to be clocked on either edge of the clock. figure 3. high-speed psi system connections with an optical interface serial data optical transceiver rd+ rd ? td ? td+ in+ in ? out ? out+ serial data cypsi refclk optical fiber links sd sd host bus interface system bus programmable ? +
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 6 of 59 logic block cluster (lbc) the psi architecture consists of several logic block clusters, each of which have 8 logic blocks (lb) and 2 cluster memory blocks connected via a programmable interconnect matrix (pim) as shown in figure 6 . each cluster memory block con- sists of 8-kbit single-port ram, which is configurable as syn- chronous or asynchronous. the cluster memory blocks can be cascaded with other cluster memory blocks within the same lbc as well as other lbcs to implement larger memory func- tions. if a cluster memory block is not specifically utilized by the designer, cypress ? s warp software can automatically use it to implement large blocks of logic. all lbcs interface with each other via horizontal and vertical routing channels. figure 4. block diagram of a standard datapath cell dq res e global control signals output control channel occ global clock signals signal from output pim to routing channel te mux register receive mux register enable mux transmit mux clock mux clock polarity mux register reset mux receive mux dq res c registered te mux c c c 3 c 3 c 2 3 c c c figure 5. psi routing interface lb cluster pim cluster memory block lb lb lb lb cluster memory block lb lb lb channel memory block i/o block i/o block channel memory outputs drive dedicated tracks in the horizontal and vertical routing channels h-to-v pim v-to-h pim pin inputs from the i/o cells drive dedicated tracks in the horizontal and vertical routing channels 72 72 64 64
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 7 of 59 logic block (lb) the logic block is the basic building block of the psi architec- ture. it consists of a product term array, an intelligent product- term allocator, and 16 macrocells. product term array each logic block features a 72 x 83 programmable product term array. this array accepts 36 inputs from the pim. these inputs originate from device pins and macrocell feedbacks as well as cluster memory and channel memory feedbacks. ac- tive low and active high versions of each of these inputs are generated to create the full 72-input field. the 83 product terms in the array can be created from any of the 72 inputs. of the 83 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. two of the remaining three product terms in the logic block are used as asynchronous set and asynchronous reset product terms. the final product term is the product term clock (ptclk) and is shared by all 16 macrocells within a logic block. product term allocator through the product term allocator, warp software automati- cally distributes the 80 product terms as needed among the 16 macrocells in the logic block. the product term allocator pro- vides two important capabilities without affecting performance: product term steering and product term sharing. product term steering product term steering is the process of assigning product terms to macrocells as needed. for example, if one macrocell requires ten product terms while another needs just three, the product term allocator will ? steer ? ten product terms to one macrocell and three to the other. on psi devices, product terms are steered on an individual basis. any number between 1and 16 product terms can be steered to any macrocell. product term sharing product term sharing is the process of using the same product term among multiple macrocells. for example, if more than one function has one or more product terms in its equation that are common to other functions, those product terms are only created once. the psi product term allocator allows sharing across groups of four macrocells in a variable fashion. the software automatically takes advantage of this capability so that the user does not have to intervene. note that neither product term sharing nor product term steer- ing have any effect on the speed of the product. all steering and sharing configurations have been incorporated in the tim- ing specifications for the psi devices. . figure 6. psi logic block cluster diagram logic block 0 logic block 1 logic block 3 logic block 2 cluster memory 0 pim logic block 7 logic block 6 logic block 4 logic block 5 cluster memory 1 64 inputs from horizontal routing channel 64 inputs from vertical routing channel 144 outputs to horizontal and vertical cluster-to-channel pims clock inputs gclk[3:0] cc cc cc cc cc cc cc = carry chain 16 36 16 36 16 36 16 36 16 36 16 36 16 36 8 25 8 25 4 16 36
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 8 of 59 macrocell within each logic block there are 16 macrocells. each macrocell accepts a sum of up to 16 product terms from the product term array. the sum of these 16 product terms can be output in either registered or combinatorial mode. figure 7 displays the block diagram of the macrocell. the register can be asynchronously preset or asynchronously reset at the mac- rocell level with the separate preset and reset product terms. each of these product terms features programmable polarity. this allows the registers to be preset or reset based on an and expression or an or expression. an xor gate in the psi macrocell allows for many different types of equations to be realized. it can be used as a polarity mux to implement the true or complement form of an equation in the product term array or as a toggle to turn the d flip-flop into a t flip-flop. the carry-chain input mux allows additional flexibility for the implementation of different types of logic. the macrocell can utilize the carry chain logic to implement adders, subtractors, magnitude comparators, parity tree, or even ge- neric xor logic. the output of the macrocell is either regis- tered or combinatorial. carry chain logic the psi macrocell features carry chain logic which is used for fast and efficient implementation of arithmetic operations. the carry logic connects macrocells in up to 4 logic blocks for a total of 64 macrocells. effective data path operations are im- plemented through the use of carry-in arithmetic, which drives through the circuit quickly. figure 7 shows that the carry chain logic within the macrocell consists of two product terms (cpt0 and cpt1) from the pta and an input carry-in for carry logic. the inputs to the carry chain mux are connected directly to the product terms in the pta. the output of the carry chain mux generates the carry-out for the next macrocell in the logic block as well as the local carry input that is connected to an input of the xor input mux. carry-in and a configuration bit are inputs to an and gate. this and gate provides a method of segment- ing the carry chain in any macrocell in the logic block. macrocell clocks clocking of the register is highly flexible. four global synchro- nous clocks (gclk[3:0]) and a product term clock (ptclk) are available at each macrocell register. furthermore, a clock polarity mux within each macrocell allows the register to be clocked on the rising or the falling edge (see macrocell dia- gram in figure 7 ). preset/reset configurations the macrocell register can be asynchronously preset and re- set using the preset and reset mux. both signals are ac- tive high and can be controlled by either of two preset/reset product terms (prc[1:0] in figure 7 ) or gnd. in situations where the preset and reset are active at the same time, reset takes priority over preset. figure 7. psi macrocell d q pset res gclk[3:0] ptclk from ptm cpt0 cpt1 prc[1:0] 0 1 0 1 to pim c carry out (to macrocell n+1) carry in (from macrocell n-1) up to 16 pts preset mux clock polarity mux reset mux clock mux carry chain mux xor input mux output mux q c 3 3 2 3 c c c c c c
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 9 of 59 embedded memory each member of the psi family contains two types of embed- ded memory blocks. the channel memory block is placed at the intersection of horizontal and vertical routing channels. each channel memory block is 4096 bits in size and can be configured as asynchronous or synchronous dual-port ram, single-port ram, read-only memory (rom), or synchronous fifo memory. the memory organization is configurable as 4kx1, 2kx2, 1kx4 and 512x8. the second type of memory block is located within each lbc and is referred to as a cluster memory block. each lbc contains two cluster memory blocks that are 8192 bits in size. similar to the channel memory blocks, the cluster memory blocks can be configured as 8kx1, 4kx2, 2kx4 and 1kx8 and can be configured as either asyn- chronous or synchronous single-port ram or rom. cluster memory each logic block cluster of the psi device contains two 8192- bit cluster memory blocks. figure 8 is a block diagram of the cluster memory block and the interface of the cluster memory block to the cluster pim. the output of the cluster memory block can be optionally reg- istered to perform synchronous pipelining or to register asyn- chronous read and write operations. the output registers con- tain an asynchronous reset which can be used in any type of sequential logic circuits (e.g., state machines). there are four global clocks (gclk[3:0]) and one local clock available for the input and the output registers. the local clock for the input registers is independent of the one used for the output registers. the local clock is generated in the user-de- sign in a macrocell or comes from an i/o pin. cluster memory initialization the cluster memory powers up in an undefined state, but is set to a user-defined known state during configuration. to fa- cilitate the use of look-up-table (lut) logic and rom applica- tions, the cluster memory blocks can be initialized with a given set of data when the device is configured at power up. for lut and rom applications, the user cannot write to memory blocks. channel memory the psi architecture includes an embedded memory block at each crossing point of horizontal and vertical routing channels. the channel memory is a 4096-bit embedded memory block that can be configured as asynchronous or synchronous sin- gle-port ram, dual-port ram, rom, or synchronous fifo memory. data, address, and control inputs to the channel memory are driven from horizontal and vertical routing channels. all data and fifo logic outputs drive dedicated tracks in the horizontal and vertical routing channels. the clocks for the channel mem- ory block are selected from four global clocks and pin inputs from the horizontal and vertical channels. the clock muxes also include a polarity mux for each clock so that the user can choose an inverted clock. dual-port (channel memory) configuration each port has distinct address inputs, as well as separate data and control inputs that can be accessed simultaneously. the inputs to the dual-port memory are driven from the horizontal and vertical routing channels. the data outputs drive dedicat- ed tracks in the routing channels. the interface to the routing is such that port a of the dual-port interfaces primarily with the horizontal routing channel and port b interfaces primarily with the vertical routing channel. . figure 8. block diagram of cluster memory block 5:1 din[7:0] dq addr[12:0] dq cluster pim dq we write pulse write control logic 1024x8 asynchronous sram read control logic row decode (1024 rows) dout[7:0] 8 3 3 8 10 c c d q gclk[3:0] 5:1 r reset gclk[3:0] c local clk 2 local clk 3 2 3 c c c c c c c
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 10 of 59 the clocks for each port of the dual-port configuration are selected from four global clocks and two local clocks. one lo- cal clock is sourced from the horizontal channel and the other from the vertical channel. the data outputs of the dual-port memory can also be registered. clocks for the output registers are also selected from four global clocks and two local clocks. one clock polarity mux per port allows the use of true or com- plement polarity for input and output clocking purposes. arbitration the dual-port configuration of the channel memory block pro- vides arbitration when both ports access the same address at the same time. depending on the memory operation being at- tempted, one port always gets priority. see table 1 for details on which port gets priority for read and write operations. an active-low ? address match ? signal is generated when an ad- dress collision occurs. fifo (channel memory) configuration the channel memory blocks are also configurable as synchro- nous fifo ram. in the fifo mode of operation, the channel memory block supports all normal fifo operations without the use of any general-purpose logic resources in the device. the fifo block contains all of the necessary fifo flag logic, including the read and write address pointers. the fifo flags include an empty/full flag (ef ), half-full flag (hf ), and program- mable almost-empty/full (paef ) flag output. the fifo config- uration has the ability to perform simultaneous read and write operations using two separate clocks. these clocks may be tied together for a single operation or may run independently for asynchronous read/write (w.r.t. each other) applications. the data and control inputs to the fifo block are driven from the horizontal or vertical routing channels. the data and flag outputs are driven onto dedicated routing tracks in both the horizontal and vertical routing channels. this allows the fifo blocks to be expanded by using multiple fifo blocks on the same horizontal or vertical routing channel without any speed penalty. in fifo mode, the write and read ports are controlled by sep- arate clock and enable signals. the clocks for each port are selected from four global clocks and two local clocks. one local clock is sourced from the horizontal channel and the other from the vertical channel. the data outputs from the read port of the fifo can also be registered. one clock polarity mux per port allows using true or complement polarity for read and write operations. the write operation is controlled by the clock and the write enable pin. the read operation is controlled by the clock and the read enable pin. the enable pins can be sourced from horizontal or vertical channels. channel memory initialization the channel memory powers up in an undefined state, but is set to a user-defined known state during configuration. to fa- cilitate the use of look-up-table (lut) logic and rom applica- tions, the channel memory blocks can be initialized with a giv- en set of data when the device is configured at power up. for lut and rom applications, the user cannot write to memory blocks. channel memory routing interface similar to lbc outputs, the channel memory blocks feature dedicated tracks in the horizontal and vertical routing channels for the data outputs and the flag outputs, as shown in figure 9 . this allows the channel memory blocks to be ex- panded easily. these dedicated lines can be routed to i/o pins as chip outputs or to other logic block clusters to be used in logic equations. figure 9. block diagram of channel memory block table 1. arbitration result: address match signal becomes active port a port b result of arbitration comment read read no arbitration required both ports read at the same time write read port a gets priority if port b requests first then it will read the cur- rent data. the output will then change to the newly written data by port a read write port b gets priority if port a requests first then it will read the cur- rent data. the output will then change to the newly written data by port b write write port a gets priority port b is blocked until port a is finished writing 4096-bit dual port array configurable as async/sync dual port or sync fifo configurable as 4kx1, 2kx2, 1kx4 and 512x8 block sizes horizontal channel all channel memory inputs are driven from the routing channels all channel memory outputs drive dedicated tracks in the routing channels gclk[3:0] global clock signals vertical channel
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 11 of 59 i/o banks the psi interfaces the horizontal and vertical routing channels to the pins through i/o banks. there are several i/o banks per device as shown in figure 10 and all i/os from an i/o bank are located in the same section of a package for pcb layout con- venience. there exist two kinds of i/o banks; fixed-signal i/o banks and user programmable i/o banks. the first fixed signal bank is the serial signal bank. this bank includes all differential serial data transmission and receive signals. the second bank is the transceiver control bank. this bank includes all static signal pins required for the config- uration and operation of the transceiver blocks in each of the psi devices. each psi device has several types of user programmable i/o banks. the table on the following page indicates the availabil- ity of each type of programmable bank by device. supported i/o standards for each bank are addressed by the appropriate v ref and v ccio voltages. all the v ref and v ccio pins in an i/o bank must be connected to the same v ref and v ccio volt- age respectively. this requirement restricts the number of i/o standards supported by an i/o bank at any given time. it also dictates the i/o standard used for the gctl[3:0] pins. the architecture defining each programmable i/o bank con- sists of several i/o cells, where each i/o cell contains an in- put/output register, an output enable register, programmable slew rate control and programmable bus hold control logic. each i/o cell drives a pin output of the device; the cell also supplies an input to the device that connects to a dedicated track in the associated routing channel. there are four dedicated inputs (gctl[3:0]) that are used as global control signals available to every i/o cell. these global control signals may be used as output enables, register resets and register clock enables as shown in figure 11 . figure 10. psi i/o bank block diagram psi i/o bank i/o bank xcvr cntl & i/o serial bank i/o bank i/o bank i/o bank i/o bank i/o bank i/o bank psi programmable i/o banks device flexible semi- flexible specific v ccio v ref psi2g100(s) bank[0:3, 5] bank[4] v ccio =3.3v bank[6:7] 1.5v 0.68-0.90v psi5g100(s) bank[0:3] bank[4] v ccio =3.3v bank[5:7] 1.5v 0.68-0.90v io standards i/o standard v ref (v) v ccio termination voltage (v tt ) min max lvttl n/a 3.3 v n/a lvcmos 3.3 v n/a lvcmos3 3.0 v n/a lvcmos2 2.5 v n/a lvcmos18 1.8 v n/a 3.3v pci 3.3 v n/a gtl+ 0.9 1.1 n/a 1.5 sstl3 i 1.3 1.7 3.3 v 1.5 sstl3 ii 1.3 1.7 3.3 v 1.5 sstl2 i 1.15 1.35 2.5 v 1.25 sstl2 ii 1.15 1.35 2.5 v 1.25 hstl i 0.68 0.9 1.5 v 0.75 hstl ii 0.68 0.9 1.5 v 0.75 hstl iii 0.68 0.9 1.5 v 1.5 hstl iv 0.68 0.9 1.5 v 1.5
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 12 of 59 . i/o cell figure 11 is a block diagram of the psi i/o cell. the i/o cell contains a three-state input buffer, an output buffer, and a reg- ister that can be configured as an input or output register. the output buffer has a slew rate control option that can be used to configure the output for a slower slew rate. the input of the device and the pin output can each be configured as regis- tered or combinatorial, however only one path can be config- ured as registered in a given design. the output enable can be selected from one of the four global control signals or from one of two output control channel (occ) signals. the output enable can be configured as always enabled or always disabled or it can be controlled by one of the remaining inputs to the mux. the selection is done via a mux that includes v cc and gnd as inputs. one of the global clocks can be selected as the clock for the i/o cell register. the clock mux output is an input to a clock polarity mux that allows the input/output register to be clocked on either edge of the clock. slew rate control the output buffer has a slew rate control option. this allows the ouput buffer to slew at a fast rate (3 v/ns) or a slow rate (1 v/ns). all i/os default to fast slew rate. for designs con- cerned with meeting fcc emissions standards the slow edge provides for lower system noise. for designs requiring very high performance the fast edge rate provides maximum sys- tem performance. programmable bus hold on each i/o pin, user-programmable-bus-hold is included. bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device ? s performance. as a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in bus-in- terface applications. bus-hold additionally allows unused de- vice pins to remain unconnected on the board, which is partic- ularly useful during prototyping as designers can route new signals to the device without cutting trace connections to v cc or gnd. for more information, see the application note ? un- derstanding bus-hold ? a feature of cypress cplds. ? clocks psi has four primary global clock trees in the cpld portion of the device (intclk[3:0]). each of these clock trees distributes a clock signal to every cluster, channel memory, and i/o cell in the cpld. the global clock trees are designed such that the clock skew is minimized while maintaining an acceptable clock delay. each of the intclks can choose from two input sourc- es for the clock signal: a pll derived output or another one as shown in the table below: gclk[0] and gclk[1] are accessible through pins on the de- vice package. txclk and rxclk are provided internally to the device. txclk (transmit clock) is intended for data trans- fer from the cpld block to the transmit channel of the trans- ceiver block. rxclk (receive clock) is intended for data trans- fer from the receive channel of the transceiver block to the cpld block. the txclk and rxclk can also be used for figure 11. block diagram of i/o cell dq res e global control signals output control channel occ global clock signals slew rate control c i/o from output pim to routing channel oe mux register input mux register enable mux output mux clock mux clock polarity mux register reset mux input mux bus hold c dq res c registered oe mux c c c 3 c 3 c 2 3 c c c device in- tclk[0] in- tclk[1] in- tclk[2] in- tclk[3] cypsi2g100(s) gclk[0] gclk[1] txclk rxclk cypsi5g100(s) gclk[0] rxclk txclk rxclk_b
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 13 of 59 logic inside the cpld block e.g. for data processing. rxclk_b is the rxclk for the second transceiver block. clock tree distribution the global clock tree performs two primary functions. first, the clock tree generates the four internal global clocks by multi- plexing four reference clocks derived from the transceiver blocks and from the package pins and four pll driven clocks. second, the clock tree distributes the four global clocks to ev- ery cluster, channel memory, i/o block, and datapath cell on the die. the global clock tree is designed such that the clock skew is minimized while maintaining an acceptable clock de- lay. spread aware ? pll each device in the psi family features an on-chip pll de- signed using spread aware technology for low emi applica- tions. in general, plls are used to implement time-division- multiplex circuits to achieve higher performance with fewer de- vice resources. for example, a system that operates on a 32-bit data path that runs at 40 mhz can be implemented with 16-bit circuitry that runs internally at 80 mhz. plls can also be used to take ad- vantage of the positioning of the internally generated clock edges to shift performance towards improved setup, hold or clock-to-out times. there are several frequency multiply (x1, x2, x4) and divide (/1, /2, /3, /4, /5, /6, /8, /16) options available to create a wide range of clock frequencies from a single clock input (gclk[0]). for increased flexibility, there are seven phase shifting options which allow clock skew/de-skew by 45 , 90 , 135 , 180 , 225 , 270 or 315 . the voltage controlled oscillator (vco), the core of the psi pll is designed to operate within the frequency range of 100 mhz to 266 mhz. hence, the multiply option combined with input (gclk[0]) frequency should be selected such that this vco operating frequency requirement is met. this is dem- onstrated in table 2 (columns 1, 2, and 3). another feature of this pll is the ability to drive the output clock (intclk) off the psi chip to clock other devices on the board, as shown in figure 12 and figure 13 . this off-chip clock is half the frequency of the output clock as it has to go through a register (i/o register or a macrocell register). this pll can also be used for board de-skewing purpose by driving a pll output clock off-chip, routing it to the other de- vices on the board and feeding it back to the pll ? s external feedback input (gclk[1]). when this feature is used only lim- ited multiply, divide and phase shift options can be used. table 2 describes the valid multiply and divide options that can be used without an external feedback. table 3 describes the valid multiply & divide options that can be used with an exter- nal feedback. figure 12. block diagram of spread aware pll for cypsi2g100(s) gclk[1:0] gclk0 gclk1 fb source clock clock tree delay lock pll x1, x2, x4 gclk0 gclk1 txclk intclk0 intclk1 intclk2 normal i/o signal path lock detect/io pin any register intclk0, intclk1, intclk2, intclk3 send a global clock off chip c c c c c c clk 0 0 clk 90 0 clk 180 0 clk 270 0 clk 225 0 clk 135 0 clk 45 0 clk 315 0 divide rxclk intclk3 2 2 2 2 2 fb off-chip signal (external feedback) phase selection phase selection phase selection phase selection 1-6,8,16 divide 1-6,8,16 divide 1-6,8,16 divide 1-6,8,16
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 14 of 59 figure 13. block diagram of spread aware pll for cypsi5g100(s) gclk[0] intclk1 fb source clock clock tree delay lock pll x1, x2, x4 gclk0 rxclk txclk intclk0 intclk1 intclk2 normal i/o signal path lock detect/io pin any register intclk0, intclk1, intclk2, intclk3 send a global clock off chip c c c c c c clk 0 0 clk 90 0 clk 180 0 clk 270 0 clk 225 0 clk 135 0 clk 45 0 clk 315 0 divide rxclk_b intclk3 2 2 2 2 2 fb phase selection phase selection phase selection phase selection 1-6,8,16 divide 1-6,8,16 divide 1-6,8,16 divide 1-6,8,16 table 2. pll multiply and divide options ? without intclk1 feedback input frequency (gclk[0]) f plli (mhz) valid multiply options valid divide options value vco output frequency (mhz) value output frequency (intclk[3:0]) f pllo (mhz) off-chip clock frequency 25 ? 33 4 100 ? 133 1 ? 6, 8, 16 6.25 ? 133 3.12 ? 66 33 ? 50 4 133 ? 200 1 ? 6, 8, 16 8.33 ? 200 4.16 ? 100 50 ? 66 4 200 ? 266 1 ? 6, 8, 16 12.5 ? 266 6.25 ? 133 2 100 ? 133 1 ? 6, 8, 16 6.25 ? 133 3.12 ? 66 66 ? 100 2 133 ? 200 1 ? 6, 8, 16 8.3 ? 200 4.16 ? 100 100 ? 133 2 200 ? 266 1 ? 6, 8, 16 12.5 ? 266 6.25 ? 133 1 100 ? 133 1 ? 6, 8, 16 6.25 ? 133 3.12 ? 66 table 3. pll multiply and divide options ? with external feedback input (gclk) frequency f plli (mhz) valid multiply options valid divide options value vco output frequency (mhz) value output (intclk) frequency f pllo (mhz) off-chip clock frequency 50 ? 66 1 100 ? 133 1 100 ? 133 50 ? 66 66 ? 100 1 133 ? 200 1 133 ? 200 66 ? 100 100 ? 133 1 200 ? 266 1 200 ? 266 100 ? 133
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 15 of 59 table 4 describes the valid phase shift options that can be used with or without an external feedback. table 5 is an example of the effect of all the available divide and phase shift options on a vco output of 250 mhz. it also shows the effect of division on the duty cycle of the resultant clock. note that the duty cycle is 50-50 when a vco output is divided by an even number. also note that the phase shift ap- plies to vco output and not to the divided output for more details on the architecture and operation of this pll please refer to the application note entitled ? psi pll and clock tree. ? table 4. pll phase shift options ? with and without intclk1 feedback without external feedback with external feedback 0 ,45 , 90 , 135 , 180 , 225 , 270 , 315 0 table 5. timing of clock phases for all divide options for a vco output frequency of 250 mhz divide factor period (ns) duty cy- cle% 0 (ns) 45 (ns) 90 (ns) 135 (ns) 180 (ns) 225 (ns) 270 (ns) 315 (ns) 1 4 40-60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2 8 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3 12 33-67 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4 16 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5 20 40-60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 6 24 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 8 32 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 16 64 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 16 of 59 timing model one important feature of the psi family is the simplicity of its timing. all combinatorial and registered/synchronous delays are worst case and system performance is static (as shown in the ac specs section) as long as data is routed through the same horizontal and vertical channels. figure 14 illustrates the true timing model for the 200-mhz devices. for synchronous clocking of macrocells, a delay is incurred from macrocell clock to macrocell clock of separate logic blocks within the same cluster, as well as separate logic blocks within different clusters. this is shown as t scs and t scs2 in figure 14. for combinatorial paths, any input to any output (from corner to corner on the device), incurs a worst-case delay in the 100k gate psi regardless of the amount of logic or which horizontal and vertical channels are used. this is the t pd shown in figure 14. for synchronous systems, the input set-up time to the out- put macrocell register and the clock to output time are shown as the parameters t mcs and t mcco shown in the figure 14. these measurements are for any output and synchronous clock, regardless of the logic placement. psi features: no dedicated vs. i/o pin delays no penalty for using 0 ? 16 product terms no added delay for steering product terms no added delay for sharing product terms no output bypass delays the simple timing model of the psi family eliminates unex- pected performance penalties. figure 14. timing model for 100k gate psi devices channel ram 4 gclk[3:0] lb 0 pim ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim 8 kb sram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 8 kb sram channel ram 4 gclk[3:0] lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram 4 lb 0 pim ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 gclk[3:0] lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram channel ram cluster cluster cluster t mcs t pd t scs t mcco t scs2
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 17 of 59 serial transceiver operation the psi transceiver block is a highly configurable transceiver designed to support reliable transfer of large quantities of data, using high-speed serial links, from one or multiple sources to one or multiple destinations. this block supports either a sin- gle 16-bit wide channel in the case of high-speed psi devices or four single-byte or single-character channels, that may be combined to support transfer of wider buses, in the case of frequency agile psi devices. high-speed psi transceiver operation transmit data path operating modes the transmit path of the high-speed psi supports 16-bit-wide data paths. phase-align buffer data from the input register is passed to a phase-align buffer (fifo). this buffer is used to absorb clock phase differences between the transmit input clock and the internal character clock. initialization of the phase-align buffer takes place when the fifo_rst signal is asserted low. when fifo_rst is re- turned high, the present input clock phase relative to txclk is set. once set, the input clock is allowed to skew in time up to half a character period in either direction relative to refclk; i.e. 180. this time shift allows the delay path of the character clock (relative to refclk) to change due to operat- ing voltage and temperature while not effecting the desired operation. fifo_rst is an asynchronous signal. fifo_err is the transmit fifo error indicator. when high, the transmit fifo has either under or overflowed. the fifo can be exter- nally reset or logically reset by psi logic to clear the error indi- cation or if no action is taken, the internal clearing mechanism will clear the fifo in 9 clock cycles. when the fifo is being reset, the output data is 1010. transmit pll clock multiplier the transmit pll clock multiplier accepts a 156.25-mhz ex- ternal clock at the refclk input, and multiplies that clock by 16 to generate a bit-rate clock for use by the transmit shifter. the operating serial signaling rate and allowable range of refclk frequencies are listed in the high-speed psi trans- ceiver timing parameter values table under ? refclk timing parameters ? (see page 33). the refclk input is a standard lvpecl input. serializer the parallel data from the phase-align buffer is passed to the serializer which converts the parallel data to serial data using the bit-rate clock generated by the transmit pll clock multi- plier. txd[15] is the most significant bit of the output word, and is transmitted first on the serial interface. serial output driver the serial interface output driver makes use of high-perfor- mance differential cml (current mode logic) to provide a source-matched driver for the transmission lines. this driver receives its data from the transmit shifters or the receive loop- back data. the outputs have signal swings equivalent to that of standard lvpecl drivers, and are capable of driving ac- coupled optical modules or transmission lines. receive data path serial line receivers a differential line receiver, in , is available for accepting the input serial data stream. the serial line receiver inputs can accommodate high wire interconnect and filtering losses or transmission line attenuation (v dif > 25 mv, or 50 mv peak- to-peak differential), and can be ac-coupled to +3.3v or +5v powered fiber-optic interface modules. the common-mode tolerance of these line receivers accommodates a wide range of signal termination voltages. lock to data control line receiver routed to the clock and data recovery pll is monitored for status of signal detect (sd) pin status of lockref pin received data stream outside normal frequency range (200 ppm) this status is presented on the lfi (line fault indicator) output signal, which changes asynchronously in the cases when sd or lockref goes from high to low. otherwise, it changes synchronously to the refclk. clock/data recovery the extraction of a bit-rate clock and recovery of data bits from received serial stream is performed by a clock/data recovery (cdr) block. the clock extraction function is performed by high-performance embedded phase-locked loop (pll) that tracks the frequency of the incoming bit stream and aligns the phase of the internal bit-rate clock to the transitions in the se- lected serial data stream. cdr accepts a character-rate (bit-rate 16) reference clock on the refclk input. this refclk input is used to ensure that the vco (within the cdr) is operating at the correct fre- quency (rather than some harmonic of the bit-rate), to improve pll acquisition time, and to limit unlocked frequency excur- sions of the cdr vco when no data is present at the serial inputs. regardless of the type of signal present, the cdr will attempt to recover a data stream from it. if the frequency of the recov- ered data stream is outside the limits set by the range controls, the cdr pll will track refclk instead of the data stream. when the frequency of the selected data stream returns to a valid frequency, the cdr pll is allowed to track the received data stream. the frequency of refclk is required to be within 200 ppm of the frequency of the clock that drives the refclk signal of the remote transmitter to ensure a lock to the incoming data stream. for systems using multiple or redundant connections, the lfi output can be used to select an alternate data stream. when an lfi indication is detected, psi logic can toggle selection of the input device. when such a port switch takes place, it is necessary for the pll to re-acquire lock to the new serial stream. external filter the cdr circuit uses external capacitors for the pll filter. a 0.1- f capacitor needs be connected between rxcn1 and
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 18 of 59 rxcp1. similarly a 0.1- f capacitor needs to be connected between rxcn2 and rxcp2. the recommended packages and dielectric material for these capacitors are 0805 x7r or 0603 x7r. deserializer the cdr circuit extracts bits from the serial data stream and clocks these bits into the deserializer at the bit-clock rate. the deserializer converts serial data into parallel data. rxd[15] is the most significant bit of the output word and is received first on the serial interface. loopback/timing modes high-speed psi supports various loopback modes as de- scribed below. facility loopback (line loopback with retiming) when the lineloop signal is set high, the facility loopback mode is activated and the high-speed serial receive data (in) is presented to the high-speed transmit output (out) after retiming. in facility loopback mode, the high-speed receive data (in) is also converted to parallel data and presented to the low-speed receive data output pins (rxd[15:0]). the re- ceive recovered clock is also divided down and presented to the low speed clock output (rxclk). equipment loopback (diagnostic loopback with retiming) when the diagloop signal is set high, transmit data is looped back to the rx pll, replacing in. data is looped back from the parallel tx inputs to the parallel rx outputs. the data is looped back at the internal serial interface and goes through transmit shifter and the receive cdr. sd is ignored in this mode. line loopback mode (non-retimed data) when the loopa signal is set high, the rx serial data is directly buffered out to the transmit serial data. the data at the serial output is not retimed. loop timing mode when the looptime signal is set high, the tx pll is by- passed and receive bit-rate clock is used for transmit side shifter. reset modes all logic circuits in the device can be reset using reset and fifo_rst signals. when reset is set low, all logic circuits except fifo are internally reset. when fifo_rst is set low, the fifo logic is reset. power-down mode high-speed psi transceiver blocks provide a global power- down signal pwrdn . when low, this signal powers down the entire device to a minimal power dissipation state. reset and fifo_rst signals should be asserted low along with pwrdn signal to ensure low power dissipation.
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 19 of 59 figure 15. high speed-psi transceiver logic block diagram 16 txd[15:0] input register shifter txclk lockref tx pll x16 fifo in out 16 (156.25 mhz) looptime tx bit-clock refclk diagloop lineloop loopa 16 output register rxd[15:0] shifter rx cdr pll 16 rxclk (156.25 mhz) recovered bit-clock retimed data (156.25 mhz) lock-to-data/ clock control logic lock-to-ref lfi sd fifo_err txclk fifo_rst reset pwrdn
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 20 of 59 ieee 1149.1 compliant jtag operation the psi family has an ieee std 1149.1 jtag interface for both boundary scan and isr operations. four dedicated pins are reserved on each device for use by the test access port (tap). boundary scan the psi family supports bypass, sample/preload, extest, in- test, idcode and usercode boundary scan instructions. the jtag interface is shown in figure 16 . frequency agile devices also allow system level diagnosis of transceiver interface and interconnect. boundary scan is sup- ported on the lvcmos signals, inputs and outputs. the high- speed serial inputs are not part of the jtag test chain. in-system reprogramming (isr) in-system reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. this combination means design changes during debug or field upgrades do not cause board respins. the psi family implements isr by providing a jtag compliant interface for on-board programming, robust routing resources for pinout flexibility, and a simple timing model for consistent system performance. configuration the cpld block in each device of the psi family is designed with self-boot capability. an embedded on-chip eeprom is used to store configuration data. for psi devices, program- ming is defined as the loading of a user ? s design into the inter- nal eeprom. configuration, on the other hand, is defined as the loading of a user ? s design into the volatile cpld block. configuration can begin in two ways. it can be initiated by tog- gling the reconfig pin from low to high, or by issuing the appropriate ieee std 1149.1 jtag instruction to the psi de- vice via the jtag interface. there are two ieee std 1149.1 jtag instructions that initiate configuration of the psi. the self config instruction causes the psi to (re)configure with data store in the internal eeprom. the load config instruction causes the psi to (re)configure with data provided by other sources such as a pc, automatic test equipment (ate), or an embedded micro-controller/processor via the jtag port. there are multiple configuration options available for issuing the ieee std 1149.1 jtag instructions to the psi. the first method is to use a pc with the c3 isr programming cable and software. with this method, the isr pins of the psi devices in the system are routed to a connector at the edge of the printed circuit board. the c3 isr programming cable is then connect- ed between the pc and this connector. a simple configuration file instructs the isr software of the programming operations to be performed on the psi devices in the system. the isr software then automatically completes all of the necessary data manipulations required to accomplish configuration, reading, verifying, and other isr functions. for more informa- tion on the cypress isr interface, see the programming/isr application notes at http://www.cypress.com/pld/pldapp- notes.html. for systems with embedded controllers/processors, a control- ler/processor may be used to configure the psi. the psi isr software assists in this method by converting the device hex file into the isr serial stream that contains the isr instruction information and the addresses and data of locations to be con- figured. the controller/processor then simply directs this isr stream to the chain of psi devices to complete the desired reconfiguration or diagnostic operations. contact your local sales office for information on availability of this option. programming the on-chip eeprom device of the cpld block is pro- grammed by issuing the appropriate ieee std 1149.1 jtag instruction. this can be done automatically using isr/stapl software. the configuration bits are sent from a pc through the jtag port into the psi via the c3 isr programming cable. the data is then passed to the internal eeprom through the non- volatile (nv) port of the cpld block. for more information on how to program the psi through isr/stapl, please refer to the isr/stapl user guide. third-party programmers cypress support is available on a wide variety of third-party programmers. all major programmers (including bp micro, system general, hi-lo) support the psi family. development software support warp warp is a state-of-the-art design environment for designing with cypress programmable logic. warp utilizes a subset of ieee 1076/1164 vhdl and ieee 1364 as the hardware de- scription language (hdl) for design entry. warp accepts vhdl or verilog input, synthesizes and optimizes the entered design, and outputs a configuration bitstream for the desired delta39k device. for simulation, warp provides a graphical waveform simulator as well as vhdl and verilog timing mod- els. vhdl and verilog are open, powerful, non-proprietary hard- ware description languages (hdls) that are standards for be- havioral design entry and simulation. hdl allows designers to learn a single language that is useful for all facets of the design process. third-party software cypress products are supported in a number of third-party de- sign entry and simulation tools. refer to the third-party soft- ware data sheet or contact your local sales office for a list of currently supported third party vendors. figure 16. jtag interface instruction register boundary scan idcode usercode isr prog. bypass reg. data registers jtag tap controller tdo tdi tms tclk
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 21 of 59 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c soldering temperature...................................................220 c ambient temperature with power applied............................................... ? 40 c to +85 c junction temperature....................................................135 c v cc relative to ground potential...................... ? 0.5v to 4.2v v ccio relative to ground potential................... ? 0.5v to 4.6v dc voltage applied to outputs in high z state ? 0.5v to 4.5v output current into lvcmos outputs (low)............. 30 ma dc input voltage......................... ...................... ? 0.5v to 4.5v dc current into outputs...................... ................... 20 ma [4] static discharge voltage ................................................> 2001v (per mil-std-883, method 3015) latch-up current ...........................................................> 200 ma operating range range ambient temperature v cc v ddq commercial 0 c to +70 c 3.3v 10% 1.4v to 1.6v operating range range ambient temperature junction temperature output condition v ccio v cc v ccjtag / v cccnfg v ccpll v ccprg commercial 0 c to +70 c 0 c to +85 c 3.3v 3.3v 0.3v 3.3v 0.3v same as v ccio same as v cc 3.3v 0.3v 2.5v 2.5v 0.2v 1.8v 1.8v 0.15v 1.5v 1.5v 0.1v notes: 4. dc current into outputs is 36 ma with hstl iii and 48 ma with hstl iv
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 22 of 59 ac test loads and waveforms to high-speed psi transceiver block 3.3v output (a) ttl ac test load (b) cml ac test load r1 r2 c l r l r1=330 ? r2=510 ? (includes fixture and probe capacitance) r l =100 ? c l 10 pf out+ out ? 2.0v 0.8v 3.0v gnd 2.0v 0.8v <1ns <1ns 80% 20% 80% 20% v ichh 3.0v v icll v th =1.4v v th =1.4v 250 ps 250 ps 80% 20% 80% 20% v iehh v iell 250 ps 250 ps (a) lvttl input test waveform (b) cml input test waveform (c) lvpecl input test waveform
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 23 of 59 electrical characteristics over the operating range dc characteristics parameter description test conditions v ccio = 3.3v v ccio = 2.5v v ccio = 1.8v unit min. max. min. max. min. max. v drint data retention v cc voltage (config data may be lost below this) 1.5 1.5 1.5 v v drio data retention v ccio voltage (config data may be lost below this) 1.2 1.2 1.2 v i ix input leakage current gnd v i 3.6v ? 10 10 ? 10 10 ? 10 10 a i oz output leakage current gnd v o v ccio ? 10 10 ? 10 10 ? 10 10 a i os [5] output short circuit current v ccio = max., v out = 0.5v ? 160 ? 160 ? 160 ma i bhl input bus hold low sustaining current v cc = min., v pin = v il +40 +30 +25 a i bhh input bus hold high sustaining current v cc = min., v pin = v ih ? 40 ? 30 ? 25 a i bhlo input bus hold low overdrive current v cc = max. +250 +200 +150 a i bhho input bus hold high overdrive current v cc = max. ? 250 ? 200 ? 150 a capacitance parameter description test conditions min. max. unit c i/o input/output capacitance v in = v ccio @ f = 1 mhz 25 c 10 pf c pci pci compliant i/o capacitance v in = v ccio @ f = 1 mhz 25 c 8 pf c clk clock signal capacitance v in = v ccio @ f = 1 mhz 25 c 5 12 pf c inpecl pecl input capacitance v cc = 3.3v @ f = 1 mhz 25 c 4 pf c sd1 sd pin input capacitance v cc = 3.3v @ f = 1 mhz 25 c 5 pf c inc1 cml input capacitance v cc = 3.3v @ f = 1 mhz 25 c 4 pf dc specifications - power parameter device description test conditions standby typical unit i cc2 [6] psi2g50(s) active power supply current frequency = max commercial 11 600 ma psi2g100(s) active power supply current frequency = max commercial 11 800 ma psi5g100(s) active power supply current frequency = max commercial 11 1200 ma notes: 5. not more than one output should be tested at a time. duration of the short circuit should not exceed 1 second. v out =0.5v has been chosen to avoid test problems caused by tester ground degradation. tested initially and after any design or process changes that may affect these pa rameters. 6. typical i cc is measured with v cc = 3.3v, t a = 25 c, rfen = low, and outputs unloaded.
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 24 of 59 dc characteristics (i/o) input/ output standard v ref (v) v ccio (v) v oh (v) v ol (v) v ih (v) v il (v) min. max. @ i oh =v oh (min.) @ i ol = v ol (max.) min. max. min. max. lvttl 3.3 ? 4 ma 2.4 4 ma 0.4 2.0v v ccio +0.3 ? 0.3v 0.8v lvcmos 3.3 ? 0.1 ma v ccio ? 0.2v 0.1 ma 0.2 2.0v v ccio +0.3 ? 0.3v 0.8v lvcmos3 3.0 ? 0.1 ma v ccio ? 0.2v 0.1 ma 0.2 2.0v v ccio +0.3 ? 0.3v 0.8v lvcmos2 2.5 ? 0.1 ma 2.1 0.1 ma 0.2 1.7v v ccio +0.3 ? 0.3v 0.7v ? 1.0 ma 2.0 1.0 ma 0.4 ? 2.0 ma 1.7 2.0 ma 0.7 lvcmos18 1.8 ? 0.1 ma v ccio ? 0.2v 0.1 ma 0.2 0.65v ccio v ccio +0.3 ? 0.3v 0.35v ccio ? 2 ma v ccio ? 0.45v 2.0 ma 0.45 3.3v pci 3.3 ? 0.5 ma 0.9v ccio 1.5 ma 0.1v ccio 0.5v ccio v ccio +0.5 ? 0.5v 0.3v ccio gtl+ 0.9 1.1 note 7 note 8 0.6 v ref +0.2 v ref ? 0.2 sstl3 i 1.3 1.7 3.3 ? 8 ma v ccio ? 1.1v 8 ma 0.7 v ref +0.2 v ccio +0.3 ? 0.3v v ref ? 0.2 sstl3 ii 1.3 1.7 3.3 ? 16 ma v ccio ? 0.9v 16 ma 0.5 v ref +0.2 v ccio +0.3 ? 0.3v v ref ? 0.2 sstl2 i 1.15 1.35 2.5 ? 7.6 ma v ccio ? 0.62v 7.6 ma 0.54 v ref +1.8 v ccio +0.3 ? 0.3v v ref ? 0.18 sstl2 ii 1.15 1.35 2.5 ? 15.2 ma v ccio ? 0.43v 15.2 ma 0.35 v ref +1.8 v ccio +0.3 ? 0.3v v ref ? 0.18 hstl i 0.68 0.9 1.5 ? 8 ma v ccio ? 0.4v 8 ma 0.4 v ref +1.0 v ccio +0.3 ? 0.3v v ref ? 0.1 hstl ii 0.68 0.9 1.5 ? 16 ma v ccio ? 0.4v 16 ma 0.4 v ref +1.0 v ccio +0.3 ? 0.3v v ref ? 0.1 hstl iii 0.68 0.9 1.5 ? 8 ma v ccio ? 0.4v 24 ma 0.4 v ref +1.0 v ccio +0.3 ? 0.3v v ref ? 0.1 hstl iv 0.68 0.9 1.5 ? 8 ma v ccio ? 0.4v 48 ma 0.4 v ref +1.0 v ccio +0.3 ? 0.3v v ref ? 0.1 parameter description test conditions min. max. unit sd pin lvttl inputs v iht input high voltage low = 2.0v, high = v cc + 0.5v 2.0 v cc ? 0.3 v v ilt input low voltage low = ? 3.0v, high = 0.8v ? 0.3 0.8 v i iht input high current v cc = max., v in = v cc 50 a i ilt input low current v cc = max., v in = 0v ? 50 a refclk lvpecl compatible inputs v insgle input single-ended swing 200 600 mv v diffe input differential voltage 400 1200 mv v iehh highest input high voltage v cc ? 1.2 v cc ? 0.3 v v iell lowest input low voltage v cc ? 2.0 v cc ? 1.45 v i ieh input high current v in = v iehh max. 750 a i iel input low current v in = v iell min. ? 200 a general transmitter differential cml compatible outputs (all high-speed psi) v ohc output high voltage (v cc referenced) 100 ? differential load v cc ? 0.5 v cc ? 0.15 v v olc output low voltage (v cc referenced) 100 ? differential load v cc ? 1.2 v cc ? 0.7 v v sglco output single-ended voltage 100 ? differential load 280 800 mv notes: 7. see ? power-up sequence requirements ? for v ccio requirement. 8. 25 ? resistor terminated to termination voltage of 1.5v.
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 25 of 59 power-up sequence requirements upon power-up, all the outputs remain three-stated until all the v cc pins have powered-up to the nominal voltage and the part has completed configuration. the part will not start configuration until v cc , v ccio , v ccjtag , v cccnfg , v ccpll and v ccprg have reached nominal voltage. v cc pins can be powered up in any order. this includes v cc , v ccio , v ccjtag , v cccnfg , v ccpll and v ccprg . all v ccio s on a bank should be tied to the same potential and powered up together. all v ccio s (even the unused banks) need to be powered up to at least 1.5v before configuration has completed. maximum ramp time for all v cc s should be 0v to nominal voltage in 100 ms. transmitter differential cml compatible outputs (psi2g50, psi2g100, psi5g100 only) v diff differential output 100 ? differential load 1000 1600 mv i accm ac common mode current 5 a v accm ac common mode voltage 25 mv z d differential output impedance 75 125 ? z se single ended output imped- ance 30 75 ? z mse single ended output imped- ance matching within a single lane 10 % i dshort short circuit current ? 100 100 ma transmitter differential cml compatible outputs (psi2g50s, psi2g100s, psi5g100s only) v diffoc output differential swing 100 ? differential load 560 1500 mv general receiver differential cml compatible inputs (all high-speed psi) v insglc input single-ended swing 25 600 mv v ichh highest input high voltage v cc v v icll lowest input low voltage 1.2 v i ich input high current v in = v ichh max. 47 a i icl input low current v in = v icll min. 20 a receiver differential cml compatible inputs (psi2g50, psi2g100, psi5g100 only) v rsense input sensitivity 175 mv z vtt v tt impedance 30 ? l dr differential return loss 10 db l cmr common mode return loss 6 db v rsd signal threshold 85 mv v rmax maximum input voltage (p-p) 1.6 v receiver differential cml compatible inputs (psi2g50s, psi2g100s, psi5g100s only) v diffc input differential voltage 50 1200 mv parameter description test conditions min. max. unit configuration parameters parameter description min. unit t reconfig reconfig pin low time before it goes high 200 ns
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 26 of 59 switching characteristics timing parameter values parameter description 200 min. max. unit combinatorial mode parameters t pd delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the horizontal or vertical channel associated with that cluster 7.5 ns t ea global control to output enable 5.0 ns t er global control to output disable 5.0 ns t prr asynchronous macrocell reset or preset recovery time from any pin input on the horizontal or vertical channel associated with the cluster the macrocell is in 6.0 ns t pro asynchronous macrocell reset or preset from any pin input on the horizontal or vertical channel associated with the cluster that the macrocell is in to any pin output on those same channels 10 ns t prw asynchronous macrocell reset or preset minimum pulse width, from any pin input to a macrocell in the farthest cluster on the horizontal or vertical channel the pin is associated with 3.6 ns synchronous clocking parameters t mcs set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock 3.0 ns t mch hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock 0.0 ns t mcco global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the cluster that macrocell is in 6.0 ns t ios set-up time of any input pin to the i/o cell register associated with that pin, relative to a global clock 1.0 ns t ioh hold time of any input pin to the i/o cell register associated with that pin, relative to a global clock 1.0 ns t ioco clock to output of an i/o cell register to the output pin associated with that register 4.0 ns t scs macrocell clock to macrocell clock through array logic within the same cluster 4.0 ns t scs2 macrocell clock to macrocell clock through array logic in different clusters on the same channel 5.0 ns t ics i/o register clock to any macrocell clock in a cluster on the channel the i/o register is associated with 5.0 ns t ocs macrocell clock to any i/o register clock on the horizontal or vertical channel asso- ciated with the cluster that the macrocell is in 5.0 ns t chz clock to output disable (high-impedance) 3.5 ns t clz clock to output enable (low-impedance) 2.0 ns f max maximum frequency with internal feedback ? within the same cluster 250 mhz f max2 maximum frequency with internal feedback ? within different clusters at the opposite ends of a horizontal or vertical channel 200 mhz product term clocking parameters t mcspt set-up time for macrocell used as input register, from input to product term clock 3.0 ns t mchpt hold time of macrocell used as an input register 1.0 ns t mccopt product term clock to output delay from input pin 8.0 ns note: 9. add t chsw to signals making a horizontal to vertical channel switch or vice-versa.
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 27 of 59 t scs2pt register to register delay through array logic in different clusters on the same chan- nel using a product term clock 6.5 ns channel interconnect parameters t chsw adder for a signal to switch from a horizontal to vertical channel and vice-versa 1.0 ns t cl2cl cluster to cluster delay adder (through channels and channel pim) 2.0 ns miscellaneous parameters t cpld delay from the input of a cluster pim, through a macrocell in the cluster, back to a cluster pim input. this parameter can be added to the t pd and t scs parameters for each extra pass through the and/or array required by a given signal path 3.0 ns t mccd adder for carry chain logic per macrocell 0.25 ns pll parameters t mccj maximum cycle to cycle jitter time 0.50 ns t dwsa pll delay with skew adjustment 0.35 ns t dwosa pll delay without any skew adjustment 0.35 ns t lock lock time for the pll 3.0 ms f pllo [10] output frequency of the pll 6.2 266 mhz f plli [10] input frequency of the pll 25 133 mhz switching characteristics timing parameter values (continued) parameter description 200 min. max. unit cluster memory timing parameter values description 200 parameter min. max. unit asynchronous mode parameters t clmaa cluster memory access time. delay from address change to read data out 11 ns t clmpwe write enable pulse width 6.0 ns t clmsa address set-up to the beginning of write enable 2.0 ns t clmha address hold after the end of write enable with both signals from the same i/o block 1.0 ns t clmsd data set-up to the end of write enable 6.0 ns t clmhd data hold after the end of write enable 0.5 ns synchronous mode parameters t clmcyc1 clock cycle time for flow-through read and write operations (from macrocell register through cluster memory back to a macrocell register in the same cluster) 10 ns t clmcyc2 clock cycle time for pipelined read and write operations (from cluster memory input register through the memory to cluster memory output register) 5.0 ns t clms address, data, and we set-up time of pin inputs, relative to a global clock 3.0 ns t clmh address, data, and we hold time of pin inputs, relative to a global clock 0.0 ns t clmdv1 global clock to data valid on output pins for flow through data 11 ns t clmdv2 global clock to data valid on output pins for pipelined data 7.5 ns note: 10. refer to page 15 and the application note titled ? psi pll and clock tree ? for details on the pll operation & specification.
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 28 of 59 t clmmacs1 cluster memory input clock to macrocell clock in the same cluster 8.0 ns t clmmacs2 cluster memory output clock to macrocell clock in the same cluster 5.0 ns t macclms1 macrocell clock to cluster memory input clock in the same cluster 4.0 ns t macclms2 macrocell clock to cluster memory output clock in the same cluster 6.5 ns internal parameters t clmclaa asynchronous cluster memory access time from input of cluster to output of cluster 6.0 ns cluster memory timing parameter values (continued) channel memory timing parameter values description 200 unit parameter min. max. dual-port asynchronous mode parameters t chmaa channel memory access time. delay from address change to read data out 11 ns t chmpwe write enable pulse width 6.0 ns t chmsa address set-up to the beginning of write enable 2.0 ns t chmha address hold after the end of write enable with both signals from the same i/o block 1.0 ns t chmsd data set-up to the end of write enable 6.0 ns t chmhd data hold after the end of write enable 0.5 ns t chmba channel memory asynchronous dual port address match (busy access time) 9.0 ns dual-port synchronous mode parameters t chmcyc1 clock cycle time for flow through read and write operations (from macrocell register through channel memory back to a macrocell register in the same cluster) 10 ns t chmcyc2 clock cycle time for pipelined read and write operations (from channel memory input register through the memory to channel memory output register) 5.0 ns t chms address, data, and we set-up time of pin inputs, relative to a global clock 3.3 ns t chmh address, data, and we hold time of pin inputs, relative to a global clock 0.0 ns t chmdv1 global clock to data valid on output pins for flow through data 11 ns t chmdv2 global clock to data valid on output pins for pipelined data 7.5 ns t chmbdv channel memory synchronous dual-port address match (busy, clock to data valid) 9.0 ns t chmmacs1 channel memory input clock to macrocell clock in the same cluster 9.0 ns t chmmacs2 channel memory output clock to macrocell clock in the same cluster 5.0 ns t macchms1 macrocell clock to channel memory input clock in the same cluster 5.0 ns t macchms2 macrocell clock to channel memory output clock in the same cluster 7.0 ns synchronous fifo data parameters t chmclk read and write minimum clock cycle time 5.0 ns t chmfs data, read enable, and write enable set-up time relative to pin inputs 4.0 ns t chmfh data, read enable, and write enable hold time relative to pin inputs 0.0 ns t chmfrdv data access time to output pins from rising edge of read clock (read clock to data valid) 7.0 t chmmacs channel memory fifo read clock to macrocell clock for read data 5.0 ns t macchms macrocell clock to channel memory fifo write clock for write data 5.0 ns
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 29 of 59 synchronous fifo flag parameters t chmfo read or write clock to respective flag output at output pins 11 ns t chmmacf read or write clock to macrocell clock with fifo flag 9 ns t chmfrs master reset pulse width 5.0 ns t chmfrsr master reset recovery time 4.0 ns t chmfrsf master reset to flag and data output time 10.0 ns t chmskew1 read/write clock skew time for full flag 2.0 ns t chmskew2 read/write clock skew time for empty flag 2.0 ns t chmskew3 read/write clock skew time for boundary flags 5.0 ns internal parameters t chmchaa asynchronous channel memory access time from input of channel memory to output of channel memory 7.0 ns channel memory timing parameter values (continued) high-speed psi transceiver timing parameter values parameter description min. max. unit transceiver interfacing timing parameters t ts txclk frequency (must be frequency coherent to refclk) 154.5 156.5 mhz t txclk txclk period 6.38 6.47 ns t txclkd txclk duty cycle 40 60 % t txclkr txclk rise time 0.3 1.5 ns t txclkf txclk fall time 0.3 1.5 ns t txds write data set-up to of txclk 1.5 ns t txdh write data hold from of txclk .5 ns t rs rxclk frequency 154.5 156.5 mhz t rxclk rxclk period 6.38 6.47 ns t rxclkd rxclk duty cycle 43 57 % t rxclkr rxclk rise time [11] 0.1 1.5 ns t rxclkf rxclk fall time [11] 0.1 1.5 ns t rxds recovered data set-up w.r.t. of rxclk 2.2 ns t rxdh recovered data hold w.r.t. of rxclk 2.2 ns t rxpd valid propagation delay -1.0 1.0 ns note: 11. for ? slow slew rate ? output delay adjustments, refer to warp software ? s static timing analyzer results.
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 30 of 59 transmit interface timing for high-speed psi refclk timing parameters t ref refclk input frequency 154.5 156.5 mhz t refp refclk period 6.38 6.47 ns t refd refclk duty cycle 35 65 % t reft refclk frequency tolerance (relative to received serial data) ? 100 +100 ppm t refr refclk rise time 0.3 1.5 ns t reff refclk fall time 0.3 1.5 ns cml serial outputs (psi2g50, psi2g100, psi5g100 only) t drf driver rise/fall time (20 ? 80% rise, 80 ? 20% fall, 100 ? balanced load) 100 ps t jd deterministic jitter 0.17 ui t jt total jitter 0.35 ui t uid unit interval 400 400 ps cml serial outputs (psi2g50s, psi2g100s, psi5g100s only) t rise cml output rise time (20 ? 80%, 100 ? balanced load) 60 170 ps t fall cml output fall time (80 ? 20%, 100 ? balanced load) 60 170 ps t tj total output jitter (p-p) 0.05 ui total output jitter (rms) 0.007 ui cml serial inputs (psi2g50, psi2g100, psi5g100 only) t jdr deterministic jitter at receiver 0.41 ui t jtr total jitter at receiver 0.65 ui high-speed psi transceiver timing parameter values parameter description min. max. unit txclk txd[15:0] t txds t txdh t txclkdl t txclkdh t txclk
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 31 of 59 receive interface timing for high-speed psi input & output standard timing delay adjustments all the timing specifications in this data sheet are specified based on 3.3v pci compliant inputs and outputs (fast slew rates [12] ). apply following adjustments if the inputs and outputs are configured to operate at other standards. input/output standard output delay adjustments input delay adjustments t iod t ea t er t ioin t ckin t ioregpin lvttl0.200000 lvcmos0.200000 lvcmos3 0.3 0.05 0 0.1 0.1 0.2 lvcmos2 0.5 0.1 0 0.2 0.2 0.4 lvcmos18 2.1 0.7 0.1 0.5 0.4 0.3 3.3v pci 0 0 0 0 0 0 gtl+ 0.6 [13] 0.6 [13] 0.9 [13] 0.5 0.4 0.2 sstl3 i ? 0.3 0.3 0.1 0.5 0.3 0.3 sstl3 ii ? 0.4 0.2 0 0.5 0.3 0.3 sstl2 i ? 0.1 0.4 0 0.9 0.5 0.6 sstl2 ii ? 0.2 0.2 0 0.9 0.5 0.6 hstl i 0.6 0.9 0.5 0.5 0.5 0.3 hstl ii 0.4 0.8 0.5 0.5 0.5 0.3 hstl iii 0.6 0.5 0.1 0.5 0.5 0.3 hstl iv 0.7 0.6 0 0.5 0.5 0.3 notes: 12. these delays are based on falling edge output. the rising edge delay depends on the size of pull up resistor and termination voltage. 13. rxclk rise time and fall time are measured at the 20-80 percentile region of the rising and falling edge of the clock signal rxclk rxd[15:0] t rxds t rxdh t rxclkdl t rxclkdh t rxclk t rxpd rxclk rxd[15:0] t rxds t rxds t rxdh t rxdh t rxclkdl t rxclkdl t rxclkdh t rxclkdh t rxclk t rxclk t rxpd t rxpd
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 32 of 59 switching waveforms general switching waveforms t pd input combinatorial output combinatorial output psi-1 registered output with synchronous clocking (macrocell) t mcs input synchronous t mcco registered output t mch clock psi-2 registered input in i/o cell t ios data input input register clock t ioco registered output t ioh psi-3
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 33 of 59 switching waveforms (continued) clock to clock input register clock macrocell register clock t scs t ics psi-4 pt clock to pt clock data pt clock t scs2pt t mcspt psi-5 input asynchronous reset/preset input t pro registered output clock t prr t prw psi-6 reset/preset output enable/disable global control t er outputs t ea psi-7 input
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 34 of 59 switching waveforms (continued) cluster memory asynchronous timing address (at read write read write enable t clmpwe input output t clmclaa t clmclaa cluster memory asynchronous timing 2 address (at the read write read write enable t clmpwe input t clmsd t clmhd output t clmsa t clmha t clmaa t clmaa the cluster input) i/o pin) psi-8 psi-9
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 35 of 59 switching waveforms (continued) cluster memory synchronous timing global address write enable registered input registered output t clms t clms t clms t clmh t clmh t clmh read write read t clmdv1 t clmdv1 t clmdv1 clock psi-10 t clmcyc1 cluster memory internal clocking macrocell cluster memory input clock cluster memory output clock t clmmacs2 t macclms2 t clmmacs1 t macclms1 psi-11 input clock
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 36 of 59 switching waveforms (continued) cluster memory output register timing (asynchronous inputs) address t clmcyc2 t clmdv2 write enable input global clock (output register) egistered output psi-12 cluster memory output register timing (synchronous inputs) address t clmdv2 write enable input global clock (output register) registered output (input register) global clock t clmcyc2 psi-13 t clms t clmh
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 37 of 59 switching waveforms (continued) channel memory dp asynchronous timing write t chmpwe t chmsa t chmha t chmaa t chmhd address data output t chmaa psi-14 a n-1 a n a n+1 a n+2 d n d n-1 d n d n+1 t chmsd enable input channel memory internal clocking clock input clock output clock t chmmacs1 t macchms2 t chmmacs2 t macchms1 psi-15 macrocell input channel memory channel memory
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 38 of 59 switching waveforms (continued) channel memory internal clocking 2 macrocell input clock fifo read fifo write clock fifo read or write clock t chmmacs t chmmacf t macchms psi-16 clock channel memory dp sram flow through r/w timing clock t chmcyc1 t chmh t chms write d n+1 t chms t chmh output a n+1 a n+2 a n+3 a n psi-17 address t chmdv1 t chmdv1 t chmdv1 d n-1 d n+3 d n-1 a n-1 data t chmdv1 d n+3 d n+2 d n+1 d n enable input
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 39 of 59 switching waveforms (continued) channel memory dp sram pipeline r/w timing a n+1 a n+2 d n+1 t chmcyc2 t chmh t chms t chms t chmh a n t chms t chmh psi-18 a n+3 a n-1 d n+3 d n-1 d n-1 t chmdv2 t chmdv2 d n d n+1 d n+2 t chmdv2 clock write output address data enable input dual-port asynchronous address match busy signal address a a n a n-1 a n a n+1 address t chmba t chmba b n address b psi-19 match
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 40 of 59 switching waveforms (continued) clock a n a n b n-1 b n+1 t chmbdv a n-1 t chmbdv t chms t chms address b address dual-port synchronous address match busy signal address a psi-20 match
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 41 of 59 switching waveforms (continued) channel memory synchronous fifo empty/write timing write enable t chmclk t chmfs t chmfh d n+1 registered input empty flag port a clock read enable t chmskew2 t chmfo t chmfo t chmfrdv port b clock re registered output psi-21 (active low)
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 42 of 59 switching waveforms (continued) channel memory synchronous fifo full/read timing port a clock read enable t chmclk t chmfs registered output full flag port b clock t chmfh t chmskew1 t chmfo t chmfo write enable t chms t chmh t chmfrdv registered input psi-22 (active low)
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 43 of 59 switching waveforms (continued) channel memory synchronous fifo programmable flag timing t chmclk t chmfs t chmfh port b clock programmable write enable almost-empty flag port a clock t chmskew3 t chmfo t chmfo read enable psi-23 (active low) t chmfs t chmfh t chmclk port b clock programmable write enable almost-full flag port a clock t chmskew3 t chmfo t chmfo read enable (active low)
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 44 of 59 switching waveforms (continued) channel memory synchronous fifo master reset timing master reset input read enable / write enable empty/full t chmfrs t chmfrsr t chmfrsf t chmfrsf t chmfrsf half-full/ registered output psi-24 flags programmable flags almost full programmable almost empty
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 45 of 59 figure 17. serial input termination figure 18. serial output termination out+ out ? limiting amp in+ in ? 100 ? 0.1 f 0.1 f high-speed psi zo=50 ? zo=50 ? out+ out ? cy7b9532 100 ? zo=50 ? zo=50 ? 0.1 f 0.1 f out+ out ? cy7b9532 100 ? zo=50 ? zo=50 ? zo=50 ? zo=50 ? 0.1 f 0.1 f 0.1 f f 0.1 f 0.1 f f high-speed psi psi-26
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 46 of 59 pin and signal description high-speed psi name function signal description standard device signals cclk output configuration clock for serial interface with the external boot prom config_done output flag indicating that configuration is complete data input pin to receive configuration data from the external boot prom gclk0-3 input global input clock signals 0 through 3 cce output chip select for the external boot prom gctl0-3 input global control signals 0 through 3 io/v ref0 input/output dual function pin: i/o or reference voltage for bank 0 io/v ref1 input/output dual function pin: i/o or reference voltage for bank 1 io/v ref2 input/output dual function pin: i/o or reference voltage for bank 2 io/v ref3 input/output dual function pin: i/o or reference voltage for bank 3 io/v ref4 input/output dual function pin: i/o or reference voltage for bank 4 io/v ref5 input/output dual function pin: i/o or reference voltage for bank 5 io/v ref6 input/output dual function pin: i/o or reference voltage for bank 6 io/v ref7 input/output dual function pin: i/o or reference voltage for bank 7 io input/output input or output pin io6/lock input/output dual function pin: i/o in bank 6 or pll lock output signal msel input mode select pin reconfig input pin to start configuration of psi reset output reset signal to interface with the external boot prom tclk input jtag test clock tdi input jtag test data in tdo output jtag test data out tms input jtag test mode select transmit path signals txd[15:0] internal parallel transmit data inputs. a 16-bit word, sampled by txclk . txd[15] is the most significant bit (the first bit transmitted) txclk internal parallel transmit data input clock. divide by 16 of the selected transmit bit-rate clock receive path signals rxd[15:0] internal parallel receive data output. these outputs change following rxclk . rxd[15] is the most significant bit of the output word, and is received first on the serial interface rxclk internal receive clock output. divide by 16 of the bit-rate clock extracted from the received serial stream cm_ser analog common mode termination. capacitor shunt to v ss for common mode noise rxcn1 analog receive loop filter capacitor (negative) rxcn2 analog receive loop filter capacitor (negative) rxcp1 analog receive loop filter capacitor (positive) rxcp 2 analog receive loop filter capacitor (positive) transceiver control and status signals refclk differential lvpecl input reference clock. this clock input is used as the timing reference for the transmit and receive plls. a derivative of this input clock may also be used to clock the transmit parallel interface
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 47 of 59 lfi internal line fault indicator output signal. when low, this signal indicates that the selected receive data stream has been detected as invalid by either a low input on sd, or by the receive vco being operated outside its specified limits reset internal reset for all logic functions except the transmit fifo lockref internal receive pll lock to reference input signal. when low, the receive pll locks to refclk instead of the received serial data stream sd lvttl input signal detect. when low, the receive pll locks to refclk instead of the received serial data stream fifo_err internal transmit fifo error output signal. when high the transmit fifo has either under or overflowed. the fifo must be reset to clear the error indication fifo_rst internal transmit fifo reset input signal. when low, the in and out pointers of the transmit fifo are set to maximum separation pwrdn internal device power down input signal. when low, the logic and drivers are all disabled and placed into a standby condition where only minimal power is dissipated transceiver loop control signals diagloop internal diagnostic loopback control input signal. when high, transmit data is routed through the receive clock and data recovery and presented at the rxd[15:0] outputs. when low, received serial data is routed through the receive clock and data recovery and presented at the rxd[15:0] outputs lineloop internal line loopback control input signal. when high, received serial data is looped back from receive to transmit after being reclocked by a recovered clock. when lineloop is low, the data passed to the out line driver is controlled by loopa. when both lineloop and loopa are low, the data passed to the out line driver is generated in the transmit shifter loopa internal analog line loopback input signal. when lineloop is low and loopa is high, received serial data is looped back from receive input buffer to transmit output buffer, but is not routed through the clock and data recovery pll. when loopa is low, the data passed to the out line driver is controlled by lineloop looptime internal loop time mode input signal. when high, the extracted receive bit-clock replaces transmit bit-clock. when low, the refclk input is multiplied by 16 to generate the transmit bit clock serial i/o out differential cml output differential serial data output. this differential cml output (+3.3v referenced) is capa- ble of driving terminated 50 ? transmission lines or commercial fiber-optic transmitter modules in differential cml input differential serial data input. this differential input accept the serial data stream for deserialization and clock extraction power v cc power +3.3v supply (operating voltage) gnd ground signal and power ground v ccq +3.3v quiet power v ssq quiet ground v ddq +1.5v supply for hstl outputs v ccio0 power v cc for i/o bank 0 v ccio1 power v cc for i/o bank 1 v ccio2 power v cc for i/o bank 2 v ccio3 power v cc for i/o bank 3 v ccio4 power v cc for i/o bank 4 v ccio5 power v cc for i/o bank 5 v ccio6 power v cc for i/o bank 6 high-speed psi (continued) name function signal description
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 48 of 59 v ccio7 power v cc for i/o bank 7 v ccjtag power v cc for jtag pins v cccnfg power v cc for configuration port v ccpll power v cc for logic pll v ccprg power v cc for the self-boot ? solution embedded boot prom high-speed psi (continued) name function signal description
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 49 of 59 pin configurations 456-ball bga (cypsi2g100) top view 1234567891011121314151617181920212223242526 a gnd hstl- ref io7io7io7io7hstl- ref io7 io7 io7 hstl- ref hstl- ref io6 io6 io6 hstl- ref io5 io5 io5 io/vre f5 io5 io5 io5 io/vre f5 io5 gnd a b hstl- ref hstl- ref io7 hstl- ref io7 io7 io7 vddq io7 hstl- ref io6io6io6io6io6io6io5io5io5io5io5io/vre f5 io5 io5 io5 io5 b c io0 io7 io7 io7 vddq vccn vccn io7 gctl3 io7 vddq vddq vddq hstl- ref io6 io6 io5 io5 io5 gctl2 gctl1 io5 io5 io5 tdo tck c d io0 io0 io0 io7 vddq vddq vddq gnd hstl- ref io7 nc vddq vcc io6 io6 io6 vcpll vddq vddq vddq vcc nc gclk1 io5 tms tdi d e io0 io0 io0 gctl0 gnd gnd io7 gnd gnd hstl- ref io6 io6 io6 iop6 io6 io6 io/vre f5 io5 io5 io5 io5 io5 vcco5 vcco5 vcco5 vcjtg e f io/vre f0 io0 io0 vcc gnd nc nc nc nc nc f g io0 io/vre f0 vccn vcco0 gclk0 nc nc nc nc nc g h io0 io0 vccn vcco0 gnd nc vssq vssq nc nc h j io0 io0 vcc vcco0 gnd nc vssq vssq vssq nc j k io0io0io0io0vccn vssq vssq vssq nc nc k l io0 io0 io0 gnd io0 gnd gnd gnd gnd gnd gnpll nc nc nc nc nc l m io0 io/vre f0 io0 gnd io0 gnd gnd gnd gnd gnd gnd sd rxcn1 rxcp1 rxcn2 rxcp2 m n vcc io0 io0 gnd io/vre f0 gnd gnd gnd gnd gnd gnd nc vccq vccq vccq vccq n p io1 io1 io1 io1 io0 gnd gnd gnd gnd gnd gnd nc vssq vssq inp inn p r io1 io1 io1 vcco1 gnd gnd gnd gnd gnd gnd gnd nc vssq vssq vssq cmser r t io/vre f1 io/vre f1 io1 io1 io1 gnd gnd gnd gnd gnd gnd vssq vssq vssq outp outn t u io1 io1 io1 gnd gnd nc vccq vccq vccq vccq u v io1 io1 io/vre f1 io1 gnd ref- clkp vcco4 io4 io4 vcco4 v w io1io1io1io1gnd ref- clkn vcco4 io4 io4 io4 w y io1 io1 vcep io1 io1 io4 vcep io4 io4 io/vre f4 y aa io1 io1 vcco1 io/vre f1 gnd io4 nc io4 io4 io4 aa ab gnd cdone vcco1 io1 io2 gnd gnd gnd io2 io/vre f2 io2 io2 io3 io3 gnd io3 gnd gnd gnd io3 io3 io3 io4 io4 io4 io4 ab ac cdata cfgb io2 io2 vccfg vcco2 vcco2 vcco2 vcco2 nc io2 io2 io2 vddq vcco3 vcco3 io3 io3 io/vre f3 nc nc vcco4 io/vre f4 io/vre f4 io4 io4 ac ad crst cclk io2 io2 io2 io2 io2 nc vddq vddq io2 io2 io/vre f2 io2 io3 io3 io3 io3 io3 vcc vcco3 vcco3 io/vre f3 io3 io3 io3 ad ae cce msel io/vre f2 io2 io/vre f2 io2io2io2io2io2io/vre f2 io2 io2 io2 io3 io3 io3 io3 io3 io3 io/vre f3 io3 io3 io3 io/vre f3 io3 ae af gnd io2 io2 io2 io2 io2 io/vre f2 io2 io2 io2 io2 io2 vcc io/vre f3 io3 io3 io/vre f3 io3io3io3io3io3io3io3io3gnd af 1234567891011121314151617181920212223242526
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 50 of 59 456-ball bga (cypsi5g100) top view 1234567891011121314151617181920212223242526 a gnd io/ vref7 nc nc nc nc io/ vref7 nc nc io7 io/ vref6 io/ vref6 nc nc nc io/ vref6 io5 io5 io5 io/vre f5 io5 io5 io5 io/vre f5 io5 gnd a b io/ vref7 io/ vref7 nc io/ vref7 nc nc nc vddq io7 io/ vref6 nc nc io6 nc nc nc io5 io5 io5 io5 io5 io/vre f5 io5 io5 io5 io5 b c io0 nc nc nc vddq vccn vccn nc gctl3 io7 vddq vddq vddq io/ vref6 nc nc io5 io5 io5 gctl2 gctl1 io5 io5 io5 tdo tck c d io0 io0 io0 nc vddq vddq vddq gnd io/ vref7 io7 vccn vddq vcc nc nc io6 vcpll vddq vddq vddq vcc vddq nc io5 tms tdi d e io0 io0 io0 gctl0 gnd gnd nc gndo gnd io/ vref6 nc nc nc iop6 nc io6 io/vre f5 io5 io5 io5 io5 io5 vcco5 vcco5 vcco5 vcjtg e f io/vre f0 io0 io0 vcc gnd sd_b rxcp2 _b rxcn2 _b rxcp1 _b rxcn1 _b f g io0 io/vre f0 vccn vcco0 gclk0 vddq vccq vccq vccq vccq g h io0 io0 vccn vcco0 gnd nc vssq vssq inp_b inn_b h j io0 io0 vcc vcco0 gnd nc vssq vssq vssq cmser _b j k io0io0io0io0vccn vssq vssq vssq outn_ b outp_ b k l io0 io0 io0 gnd io0 gnd gnd gnd gnd gnd gnpll vddq vccq vccq vccq vccq l m io0 io/vre f0 io0 gnd io0 gnd gnd gnd gnd gnd gnd sd rxcn1 rxcp1 rxcn2 rxcp2 m n vcc io0 io0 gnd io/vre f0 gnd gnd gnd gnd gnd gnd vddq vccq vccq vccq vccq n p io1 io1 io1 io1 io0 gnd gnd gnd gnd gnd gnd nc vssq vssq inp inn p r io1 io1 io1 vcco1 gndo gnd gnd gnd gnd gnd gnd nc vssq vssq vssq cmser r t io/vre f1 io/vre f1 io1 io1 io1 gnd gnd gnd gnd gnd gnd vssq vssq vssq outp outn t u io1 io1 io1 gnd gnd vddq vccq vccq vccq vccq u v io1 io1 io/vre f1 io1 gnd ref- clkp vcco4 io4 io4 vcco4 v w io1io1io1io1gnd ref- clkn vcco4 io4 nc nc w y io1 io1 vcep io1 io1 io4 vcep io4 nc nc y aa io1 io1 vcco1 io/vre f1 gndo io4 vccn io4 nc nc aa ab cnfg1 cdone vcco1 io1 io2 gnd gnd gnd io2 io/vre f2 io2 io2 io3 io3 gnd io3 gnd gnd gnd io3 io3 io3 io4 io4 nc nc ab ac cdata cfgb io2 io2 vccfg vcco2 vcco2 vcco2 vcco2 vccn io2 io2 io2 vddq vcco3 vcco3 io3 io3 io/vre f3 vccn vddq vcco4 io/vre f4 io/vre f4 nc nc ac ad crst cclk io2 io2 io2 io2 io2 vccn vddq vddq io2 io2 io/vre f2 io2io3io3io3io3io3vccvcco3vcco3io/vre f3 io3 io3 io3 ad ae cce cnfg0 io/vre f2 io2 io/vre f2 io2io2io2io2io2io/vre f2 io2 io2 io2 io3 io3 io3 io3 io3 io3 io/vre f3 io3 io3 io3 io/ vref3 io3 ae af gnd io2 io2 io2 io2 io2 io/vre f2 io2 io2 io2 io2 io2 vcc io/vre f3 io3 io3 io/vre f3 io3 io3 io3 io3 io3 io3 io3 io3 gnd af 1234567891011121314151617181920212223242526
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 51 of 59 456-ball bga pin table pin cypsi2g100(s) cypsi5g100(s) a1 gnd gnd a2 hstlref io/vref7 a3 io7 nc a4 io7 nc a5 io7 nc a6 io7 nc a7 hstlref io/vref7 a8 io7 nc a9 io7 nc a10 io7 io7 a11 hstlref io/vref6 a12 hstlref io/vref6 a13 io6 nc a14 io6 nc a15 io6 nc a16 hstlref io/vref6 a17 io5 io5 a18 io5 io5 a19 io5 io5 a20 io/vref5 io/vref5 a21 io5 io5 a22 io5 io5 a23 io5 io5 a24 io/vref5 io/vref5 a25 io5 io5 a26 gnd gnd b1 hstlref io/vref7 b2 hstlref io/vref7 b3 io7 nc b4 hstlref io/vref7 b5 io7 nc b6 io7 nc b7 io7 nc b8 vddq vcco6 b9 io7 io7 b10 hstlref io/vref6 b11 io6 nc b12 io6 nc b13 io6 io6 b14 io6 nc b15 io6 nc b16 io6 nc b17 io5 io5 b18 io5 io5 b19 io5 io5 b20 io5 io5 b21 io5 io5 b22 io/vref5 io/vref5 b23 io5 io5 b24 io5 io5 b25 io5 io5 b26 io5 io5 c1 io0 io0 c2 io7 nc c3 io7 nc c4 io7 nc c5 vddq vcco6 c6 vccn vccn c7 vccn vccn c8 io7 nc c9 gctl3 gctl3 c10 io7 io7 c11 vddq vcco6 c12 vddq vcco6 c13 vddq vcco6 c14 hstlref io/vref6 c15 io6 nc c16 io6 nc c17 io5 io5 c18 io5 io5 c19 io5 io5 c20 gctl2 gctl2 c21 gctl1 gctl1 c22 io5 io5 c23 io5 io5 c24 io5 io5 c25 tdo tdo c26 tck tck d1 io0 io0 d2 io0 io0 d3 io0 io0 456-ball bga pin table (continued) pin cypsi2g100(s) cypsi5g100(s)
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 52 of 59 d4 io7 nc d5 vddq vcco6 d6 vddq vcco6 d7 vddq vcco6 d8 gnd gnd d9 hstlref io/vref7 d10 io7 io7 d11 nc vccn d12 vddq vcco6 d13 vcc vcc d14 io6 nc d15 io6 nc d16 io6 io6 d17 vcpll vcpll d18 vddq vddq d19 vddq vddq d20 vddq vddq d21 vcc vcc d22 nc vddq d23 gclk1 nc d24 io5 io5 d25 tms tms d26 tdi tdi e1 io0 io0 e2 io0 io0 e3 io0 io0 e4 gctl0 gctl0 e5 gnd gnd e6 gnd gnd e7 io7 nc e8 gnd gndo e9 gnd gnd e10 hstlref io/vref6 e11 io6 nc e12 io6 nc e13 io6 nc e14 iop6 iop6 e15 io6 nc e16 io6 io6 e17 io/vref5 io/vref5 e18 io5 io5 456-ball bga pin table (continued) pin cypsi2g100(s) cypsi5g100(s) e19 io5 io5 e20 io5 io5 e21 io5 io5 e22 io5 io5 e23 vcco5 vcco5 e24 vcco5 vcco5 e25 vcco5 vcco5 e26 vcjtg vcjtg f1 io/vref0 io/vref0 f2 io0 io0 f3 io0 io0 f4 vcc vcc f5 gnd gnd f22 nc sd_b f23 nc rxcp2_b f24 nc rxcn2_b f25 nc rxcp1_b f26 nc rxcn1_b g1 io0 io0 g2 io/vref0 io/vref0 g3 vccn vccn g4 vcco0 vcco0 g5 gclk0 gclk0 g22 nc vddq g23 nc vccq g24 nc vccq g25 nc vccq g26 nc vccq h1 io0 io0 h2 io0 io0 h3 vccn vccn h4 vcco0 vcco0 h5 gnd gnd h22 nc nc h23 vssq vssq h24 vssq vssq h25 nc inp_b h26 nc inn_b j1 io0 io0 j2 io0 io0 j3 vcc vcc 456-ball bga pin table (continued) pin cypsi2g100(s) cypsi5g100(s)
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 53 of 59 j4 vcco0 vcco0 j5 gnd gnd j22 nc nc j23 vssq vssq j24 vssq vssq j25 vssq vssq j26 nc cmser_b k1 io0 io0 k2 io0 io0 k3 io0 io0 k4 io0 io0 k5 vccn vccn k22 vssq vssq k23 vssq vssq k24 vssq vssq k25 nc outn_b k26 nc outp_b l1 io0 io0 l2 io0 io0 l3 io0 io0 l4 gnd gnd l5 io0 io0 l11 gnd gnd l12 gnd gnd l13 gnd gnd l14 gnd gnd l15 gnd gnd l16 gnpll gnpll l22 nc vddq l23 nc vccq l24 nc vccq l25 nc vccq l26 nc vccq m1 io0 io0 m2 io/vref0 io/vref0 m3 io0 io0 m4 gnd gnd m5 io0 io0 m11 gnd gnd m12 gnd gnd m13 gnd gnd 456-ball bga pin table (continued) pin cypsi2g100(s) cypsi5g100(s) m14 gnd gnd m15 gnd gnd m16 gnd gnd m22 sd sd m23 rxcn1 rxcn1 m24 rxcp1 rxcp1 m25 rxcn2 rxcn2 m26 rxcp2 rxcp2 n1 vcc vcc n2 io0 io0 n3 io0 io0 n4 gnd gnd n5 io/vref0 io/vref0 n11 gnd gnd n12 gnd gnd n13 gnd gnd n14 gnd gnd n15 gnd gnd n16 gnd gnd n22 nc vddq n23 vccq vccq n24 vccq vccq n25 vccq vccq n26 vccq vccq p1 io1 io1 p2 io1 io1 p3 io1 io1 p4 io1 io1 p5 io0 io0 p11 gnd gnd p12 gnd gnd p13 gnd gnd p14 gnd gnd p15 gnd gnd p16 gnd gnd p22 nc nc p23 vssq vssq p24 vssq vssq p25 inp inp p26 inn inn r1 io1 io1 456-ball bga pin table (continued) pin cypsi2g100(s) cypsi5g100(s)
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 54 of 59 r2 io1 io1 r3 io1 io1 r4 vcco1 vcco1 r5 gnd gndo r11 gnd gnd r12 gnd gnd r13 gnd gnd r14 gnd gnd r15 gnd gnd r16 gnd gnd r22 nc nc r23 vssq vssq r24 vssq vssq r25 vssq vssq r26 cmser cmser t1 io/vref1 io/vref1 t2 io/vref1 io/vref1 t3 io1 io1 t4 io1 io1 t5 io1 io1 t11 gnd gnd t12 gnd gnd t13 gnd gnd t14 gnd gnd t15 gnd gnd t16 gnd gnd t22 vssq vssq t23 vssq vssq t24 vssq vssq t25 outp outp t26 outn outn u1 io1 io1 u2 io1 io1 u3 io1 io1 u4 gnd gnd u5 gnd gnd u22 nc vddq u23 vccq vccq u24 vccq vccq u25 vccq vccq u26 vccq vccq 456-ball bga pin table (continued) pin cypsi2g100(s) cypsi5g100(s) v1 io1 io1 v2 io1 io1 v3 io/vref1 io/vref1 v4 io1 io1 v5 gnd gnd v22 refclkp refclkp v23 vcco4 vcco4 v24 io4 io4 v25 io4 io$ v26 vcco4 vcco4 w1 io1 io1 w2 io1 io1 w3 io1 io1 w4 io1 io1 w5 gnd gnd w22 refclkn refclkn w23 vcco4 vcco4 w24 io4 io4 w25 io4 io4 w26 io4 io4 y1 io1 io1 y2 io1 io1 y3 vcep vcep y4 io1 io1 y5 io1 io1 y22 io4 io4 y23 vcep vcep y24 io4 io4 y25 io4 io1 y26 io/vref4 io1 aa1 io1 io1 aa2 io1 io1 aa3 vcco1 vcco1 aa4 io/vref1 io/vref1 aa5 gnd gndo aa22 io4 io4 aa23 nc vccn aa24 io4 io4 aa25 io4 nc aa26 io4 nc ab1 gnd cnfg1 456-ball bga pin table (continued) pin cypsi2g100(s) cypsi5g100(s)
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 55 of 59 ab2 cdone cdone ab3 vcco1 vcco1 ab4 io1 io1 ab5 io2 io2 ab6 gnd gnd ab7 gnd gnd ab8 gnd gnd ab9 io2 io2 ab10 io/vref2 io/vref2 ab11 io2 io2 ab12 io2 io2 ab13 io3 io3 ab14 io3 io3 ab15 gnd gnd ab16 io3 io3 ab17 gnd gnd ab18 gnd gnd ab19 gnd gnd ab20 io3 io3 ab21 io3 io3 ab22 io3 io3 ab23 io4 io4 ab24 io4 io4 ab25 io4 nc ab26 io4 nc ac1 cdata cdata ac2 cfgb cfgb ac3 io2 io2 ac4 io2 io2 ac5 vccfg vccfg ac6 vcco2 vcco2 ac7 vcco2 vcco2 ac8 vcco2 vcco2 ac9 vcco2 vcco2 ac10 nc vccn ac11 io2 io2 ac12 io2 io2 ac13 io2 io2 ac14 vddq vddq ac15 vcco3 vcco3 ac16 vcco3 vcco3 456-ball bga pin table (continued) pin cypsi2g100(s) cypsi5g100(s) ac17 io3 io3 ac18 io3 io3 ac19 io/vref3 io/vref3 ac20 nc vccn ac21 nc vddq ac22 vcco4 vcco4 ac23 io/vref4 io/vref4 ac24 io/vref4 io/vref4 ac25 io4 nc ac26 io4 nc ad1 crst crst ad2 cclk cclk ad3 io2 io2 ad4 io2 io2 ad5 io2 io2 ad6 io2 io2 ad7 io2 io2 ad8 nc vccn ad9 vddq vddq ad10 vddq vddq ad11 io2 io2 ad12 io2 io2 ad13 io/vref2 io/vref2 ad14 io2 io2 ad15 io3 io3 ad16 io3 io3 ad17 io3 io3 ad18 io3 io3 ad19 io3 io3 ad20 vcc vcc ad21 vcco3 vcco3 ad22 vcco3 vcco3 ad23 io/vref3 io/vref3 ad24 io3 io3 ad25 io3 io3 ad26 io3 io3 ae1 cce cce ae2 msel cnfg0 ae3 io/vref2 io/vref2 ae4 io2 io2 ae5 io/vref2 io/vref2 456-ball bga pin table (continued) pin cypsi2g100(s) cypsi5g100(s)
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 56 of 59 ae6 io2 io2 ae7 io2 io2 ae8 io2 io2 ae9 io2 io2 ae10 io2 io2 ae11 io/vref2 io/vref2 ae12 io2 io2 ae13 io2 io2 ae14 io2 io2 ae15 io3 io3 ae16 io3 io3 ae17 io3 io3 ae18 io3 io3 ae19 io3 io3 ae20 io3 io3 ae21 io/vref3 io/vref3 ae22 io3 io3 ae23 io3 io3 ae24 io3 io3 ae25 io/vref3 io/vref3 ae26 io3 io3 af1 gnd gnd af2 io2 io2 af3 io2 io2 af4 io2 io2 af5 io2 io2 af6 io2 io2 af7 io/vref2 io/vref2 af8 io2 io2 af9 io2 io2 af10 io2 io2 af11 io2 io2 af12 io2 io2 af13 vcc vcc af14 io/vref3 io/vref3 af15 io3 io3 af16 io3 io3 af17 io/vref3 io/vref3 af18 io3 io3 af19 io3 io3 af20 io3 io3 456-ball bga pin table (continued) pin cypsi2g100(s) cypsi5g100(s) af21 io3 io3 af22 io3 io3 af23 io3 io3 af24 io3 io3 af25 io3 io3 af26 gnd gnd 456-ball bga pin table (continued) pin cypsi2g100(s) cypsi5g100(s)
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 57 of 59 compliance s = sonet compliant c y p s i 5 g 1 0 0 s p 4 5 6 - 1 m g c cypress semiconductor id family type psi = programmable serial interface family device bandwidth 2g = 1 x 2.5 gbps 5g = 2 x 2.5 gbps pin count 456 = 456 balls speed 1 = prime speed grade package type mg - ball grid array gate density 100 = 100k gates operating conditions commercial 0 c to +70 c ordering information device channels & link speed ordering code package name package type operating range psi2g50 1 x 2.5 gbps CYPSI2G50P456-1MGC 456mgc 456-ball ball grid array commercial 1 x 2.5 gbps cypsi2g50sp456-1mgc 456mgc 456-ball ball grid array psi2g100 1 x 2.5 gbps cypsi2g100p456-1mgc 456mgc 456-ball ball grid array 1 x 2.5 gbps cypsi2g100sp456-1mgc 456mgc 456-ball ball grid array psi5g100 2 x 2.5 gbps cypsi5g100p456-1mgc 456mgc 456-ball ball grid array 2 x 2.5 gbps cypsi5g100sp456-1mgc 456mgc 456-ball ball grid array
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 58 of 59 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. nobl, pim, spread aware, warp , anyvolt, self-boot, in-system reprogrammable, isr, and psi are trademarks of cypress semiconductor corporation. zbt is a trademark of idt. infiniband is a trademark of the infiniband trade association. qdr is a trademark of micron, idt, an d cypress semiconductor corporation. speedwave, and viewdraw are trademarks of viewlogic. package diagrams 456-lead ball grid array (35 x 35 x 2.33 mm) bg456 51-85133
programmable serial interface device family (high speed) preliminary document #: 38-02021 rev. ** page 59 of 59 ac document title: programmable serial interface device family (high speed) programmable bandwidth document number: 38-02021 rev. ecn no. issue date orig. of change description of change ** 106745 05/25/01 szv change from spec #38-01093 to 38-02021

▲Up To Search▲

Price & Availability of CYPSI2G50P456-1MGC

	To Download CYPSI2G50P456-1MGC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .