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quad 12-bit serial voltage output dac dac8420 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features guaranteed monotonic over temperature excellent matching between dacs unipolar or bipolar operation buffered voltage outputs high speed serial digital interface reset-to-zero scale or midscale wide supply range, +5 v only to 15 v low power consumption (35 mw maximum) available in 16-lead pdip, soic, and cerdip packages applications software controlled calibration servo controls process control and automation ate functional block diagram 9 gnd 16 15 4 8 14 13 11 12 10 5 1 2 3 6 7 reg d dac d reg c dac c reg b dac b reg a dac a shift register decode sdi cs clk nc ld clsel clr vreflo vss vouta voutb voutc voutd v refhi v dd 12 4 2 00275-001 dac8420 figure 1. general description the dac8420 is a quad, 12-bit voltage-output dac with serial digital interface in a 16-lead package. utilizing bicmos tech- nology, this monolithic device features unusually high circuit density and low power consumption. the simple, easy-to-use serial digital input and fully buffered analog voltage outputs require no external components to achieve a specified per- formance. the 3-wire serial digital input is easily interfaced to micro- processors running at 10 mhz with minimal additional circuitry. each dac is addressed individually by a 16-bit serial word consisting of a 12-bit data word and an address header. the user-programmable reset control clr forces all four dac outputs to either zero scale or midscale, asynchronously overriding the current dac register values. the output voltage range, determined by the inputs vrefhi and vreflo, is set by the user for positive or negative unipolar or bipolar signal swings within the supplies, allowing considerable design flexibility. the dac8420 is available in 16-lead pdip, soic, and cerdip packages. operation is specified with supplies ranging from +5 v only to 15 v, with references of +2.5 v to 10 v, respec- tively. power dissipation when operating from 15 v supplies is less than 255 mw (maximum) and only 35 mw (maximum) with a +5 v supply.
dac8420 rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristics............................................................. 3 absolute maximum ratings............................................................ 6 thermal resistance ...................................................................... 6 esd caution.................................................................................. 6 pin configurations and function descriptions ........................... 8 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 14 introduction ................................................................................ 14 digital interface operation ....................................................... 14 correct operation of cs and clk........................................... 14 using clr and clsel .............................................................. 14 programming the analog outputs .......................................... 14 vrefhi input requirements................................................... 16 power-up sequence ................................................................... 16 applications..................................................................................... 17 power supply bypassing and grounding................................ 17 analog outputs .......................................................................... 17 reference configuration ........................................................... 18 isolated digital interface ........................................................... 19 dual window comparator ....................................................... 20 mc68hc11 microcontroller interfacing................................ 20 dac8420 to m68hc11 interface assembly program .......... 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 23 revision history 5/07rev. a to rev. b updated format..................................................................universal changes to endnote 3 ...................................................................... 4 changes to table 3............................................................................ 6 changes to table 4............................................................................ 2 updated outline dimensions ....................................................... 22 changes to ordering guide .......................................................... 23 9/03rev. 0 to rev. a changes to general description .................................................... 1 deleted wafer test limits table ...................................................... 4 deleted dice characteristics........................................................... 4 updated ordering guide................................................................. 4 added power-up sequence section ............................................. 12 updated outline dimensions ....................................................... 17
dac8420 rev. b | page 3 of 24 specifications electrical characteristics 1 @ v dd = +5.0 v 5%, v ss = 0 v, v vrefhi = +2.5 v, v vrefld = 0 v, and v ss = ?5.0 v 5%, v vreflo = ?2.5 v, ?40c t a +85c unless otherwise noted. 2 table 1. parameter symbol condition min typ max unit static accuracy integral linearity e grade inl ? 1 lsb integral linearity e grade inl v ss = 0 v 3 ? 3 lsb integral linearity f grade inl ? 2 lsb integral linearity f grade inl v ss = 0 v 3 1 4 lsb differential linearity dnl monotoni c over temperature ? 1 lsb zero-scale error zse r l = 2 k, v ss = ?5 v 4 lsb full-scale error fse r l = 2 k, v ss = ?5 v 4 lsb zero-scale error zse r l = 2 k, v ss = 0 v 3 8 lsb full-scale error fse r l = 2 k, v ss = 0 v 3 8 lsb zero-scale temperature coefficient tc zse r l = 2 k, v ss = ?5 v 4 10 ppm/c full-scale temperature coefficient tc fse r l = 2 k, v ss = ?5 v 4 10 ppm/c matching performance linearity matching 1 lsb reference positive reference input range 5 v vrefhi v vreflo + 2.5 v dd ? 2.5 v negative reference input range 5 v vreflo v ss v vrefhi ? 2.5 v negative reference input range v vreflo v ss = 0 v 5 0 v vrefhi ? 2.5 v reference high input current i vrefhi code 0x000, code 0x555 ?0.75 0.25 +0.75 ma reference low input current i vreflo code 0x000, code 0x555, v ss = ?5 v ?1.0 ?0.6 ma amplifier characteristics output current i out v ss = ?5 v ?1.25 +1.25 ma settling time t s to 0.01% 6 8 s slew rate sr 10% to 90% 6 1.5 v/s logic characteristics logic input high voltage v inh 2.4 v logic input low voltage v inl 0.8 v logic input current i in 10 a input capacitance 4 c in 13 pf logic timing characteristics 4 , 7 data setup time t ds 25 ns data hold t dh 55 ns clock pulse width high t ch 90 ns clock pulse width low t cl 120 ns select time t css 90 ns deselect delay t csh 5 ns load disable time t ld1 130 ns load delay t ld2 35 ns load pulse width t ldw 80 ns clear pulse width t clrw 150 ns
dac8420 rev. b | page 4 of 24 parameter symbol condition min typ max unit supply characteristics power supply sensitivity psrr 0.002 0.01 %/% positive supply current i dd 4 7 ma negative supply current i ss ?6 ?3 ma power dissipation p diss v ss = 0 v 20 35 mw 1 typical values indicate performance measured at 25c. 2 all supplies can be varied 5% and operation is guaranteed. device is tested with v dd = 4.75 v. 3 for single-supply operation (v vreflo = 0 v, v ss = 0 v), due to internal offs et errors inl and dnl are meas ured beginning at code 0x005. 4 guaranteed, but not tested. 5 operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 6 v out swing between +2.5 v and ?2.5 v with v dd = 5.0 v. 7 all input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v.
dac8420 rev. b | page 5 of 24 @ v dd = +15.0 v 5%, v ss = ?15.0 v 5%, v vrefhi = +10.0 v, v vreflo = ?10.0 v, ?40c t a +85c unless otherwise noted. 1 , 2 table 2. parameter symbol condition min typ max unit static accuracy integral linearity e grade inl ? ? lsb integral linearity f grade inl ? 1 lsb differential linearity dnl monotonic over temperature ? 1 lsb zero-scale error zse r l = 2 k 2 lsb full-scale error fse r l = 2 k 2 lsb zero-scale temperature coefficient tc zse r l = 2 k 3 4 ppm/c full-scale temperature coefficient tc fse r l = 2 k 3 4 ppm/c matching performance linearity matching 1 lsb reference positive reference input range 4 v vrefhi v vreflo + 2.5 v dd ? 2.5 v negative reference input range 4 v vreflo ?10 v vrefhi ? 2.5 v reference high input current i vrefhi code 0x000, code 0x555 ?2.0 1.0 +2.0 ma reference low input current i vreflo code 0x000, code 0x555 ?3.5 ?2.0 ma amplifier characteristics output current i out ?5 +5 ma settling time t s to 0.01% 5 13 s slew rate sr 10% to 90% 5 2 v/s dynamic performance analog crosstalk 3 >64 db digital feedthrough 3 >72 db large signal bandwidth 3 db, v vrefhi = 5 v + 10 v p-p, v vreflo = ?10 v 3 90 khz glitch impulse code transition = 0x7ff to 0x800 3 6 v-s logic characteristics logic input high voltage v inh 2.4 v logic input low voltage v inl 0.8 v logic input current i in 10 a input capacitance 3 c in 13 pf logic timing characteristics 3 , 6 data setup time t ds 25 ns data hold t dh 20 ns clock pulse width high t ch 30 ns clock pulse width low t cl 50 ns select time t css 55 ns deselect delay t csh 15 ns load disable time t ld1 40 ns load delay t ld2 15 ns load pulse width t ldw 45 ns clear pulse width t clrw 70 ns supply characteristics power supply sensitivity psrr 0.002 0.01 %/% positive supply current i dd 6 9 ma negative supply current i ss ?8 ?5 ma power dissipation p diss 255 mw 1 typical values indicate performance measured at 25c. 2 all supplies can be varied 5% and operation is guaranteed. 3 guaranteed, but not tested. 4 operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 5 v out swing between +10 v and ?10 v. 6 all input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v.
dac8420 rev. b | page 6 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd ?0.3 v, +18.0 v v ss to gnd +0.3 v, ?18.0 v v ss to v dd ?0.3 v, +36.0 v v ss to v vreflo ?0.3 v, v ss ? 2.0 v v vrefhi to v vreflo +2.0 v, v dd ? v ss v vrefhi to v dd +2.0 v, +33.0 v i vrefhi , i vreflo 10 ma digital input voltage to gnd ?0.3 v, v dd + 0.3 v output short-circuit duration indefinite operating temperature range ep, fp, es, fs, eq, fq C40c to +85c dice junction temperature 150c storage temperature range C65c to +150c power dissipation 1000 mw lead temperature jedec industry standard soldering j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 4. package type ja jc unit 16-lead pdip (n) 70 1 27 c/w 16-lead cerdip (q) 82 1 9 c/w 16-lead soic (rw) 86 2 22 c/w 1 ja is specified for worst case mounting conditions, that is, ja is specified for device in socket. 2 ja is specified for device on board. esd caution
dac8420 rev. b | page 7 of 24 cs sdi clk ld data load sequence sdi clk cs ld voutx data load timing clsel clr v out clear timing t clrw 1lsb t s t ld2 t csh t css t ld1 a1 a0 x x d11 d10 d9 d8 d4 d3 d2 d1 d0 t ds t dh t ch t cl t csh t ld2 t ldw t s 1lsb 0 0275-002 figure 2. timing diagram 10k ? 10f 0.1f +10 v 1n4001 + 10k ? 10f 0.1f ?10v 1n4001 + 10k ? 10f 0.1f +15 v 1n4001 + 10k ? 10f 0.1f ?15v 1n4001 + 5k ? 5k? 10k? nc nc nc nc nc nc = no connect dut 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 0 0275-003 figure 3. burn-in diagram
dac8420 rev. b | page 8 of 24 pin configurations and function descriptions vdd 1 voutd 2 voutc 3 v reflo 4 clsel 16 clr 15 ld 14 nc 13 vrefhi 5 voutb 6 vouta 7 cs 12 clk 11 sdi 10 vss 8 gnd 9 nc = no connect dac8420 top view (not to scale) 00275-004 figure 4. pdip and cerdip vdd 1 voutd 2 voutc 3 v reflo 4 clsel 16 clr 15 ld 14 nc 13 vrefhi 5 cs 12 voutb 6 clk 11 vouta 7 sdi 10 vss 8 gnd 9 nc = no connect dac8420 top view (not to scale) 00275-005 figure 5. soic table 5. pin function descriptions pin no. mnemonic description 1 vdd positive power supply, 5 v to 15 v. 4 vreflo reference input. lower dac ladder reference voltag e input, equal to zero-s cale output. allowable range is v ss to (v vrefhi ? 2.5 v). 5 vrefhi reference input. upper dac ladder reference voltage input. allowable range is (v dd ? 2.5 v) to (v vreflo + 2.5 v). 7, 6, 3, 2 vouta through voutd buffered dac analog voltage outputs. 8 vss negative power supply, 0 v to ?15 v. 9 gnd power supply, digital ground. 10 sdi serial data input. data pr esented to this pin is loaded into the internal serial-parallel shift register, which shifts data in, beginning with dac ad dress bit a1. this input is ignored when cs is high. sdi is cmos/ttl compatible. the format of the 16-bit serial word is shown in table 8 . 11 clk system serial data clock input, ttl/cmos levels. data presented to the input sdi is shifted into the internal serial-parallel input register on the ri sing edge of clock. this input is logically ored with cs . 12 cs control input, device chip select, active low. this input is logically ored with the clock and disables the serial data register input when high . when low, data input clocking is enabled (see table 6 ). cs is cmos/ttl compatible. 13 nc no connect = dont care. 14 ld control input, asynchronous dac register load co ntrol, active low. the data currently contained in the serial input shift register is shifted out to the dac data registers on the falling edge of ld , independent of cs . input data must remain stable while ld is low. ld is cmos/ttl compatible. 15 clr control input, asynchronous clear, active low. sets internal data register a through register d to zero or midscale, depending on current state of cls el. the data in the serial input shift register is unaffected by this control. clr is cmos/ttl compatible. 16 clsel control input, determines action of clr . if high, a clear command sets the internal dac register a through register d to midscale (0x800). if low, the registers are set to zero (0x000). clsel is cmos / ttl compatible.
dac8420 rev. b | page 9 of 24 table 6. control function logic table clk 1 cs 1 ld clr clsel serial input shift register dac register a to dac register d nc 2 high high low high no change loads midscale value (0x800) nc 2 high high low low no change loads zero-scale value (0x000) nc 2 high high high /low no change latches value low high high nc 2 shifts register one bit no change low high high nc 2 shifts register one bit no change high nc ( ) 2 high nc 2 no change loads the serial data-word 3 high nc 2 low high nc 2 no change transparent 4 nc 2 high high high nc 2 no change no change 1 clk and cs are interchangeable. 2 nc = dont care. 3 returning cs high while clk is high avoids an additional false clock of serial input data. clk and cs are interchangeable. 4 do not clock in serial data while ld is low.
dac8420 rev. b | page 10 of 24 typical performance characteristics 0.3 ?0.3 14 0 ?0.2 ?4 ?0.1 ?6 0.2 0.1 1210 86420 ?2 t a = +25c v dd = +15v v ss = ?15v v vreflo = ?10v dnl (lsb) v vrefhi (v) 00275-007 figure 6. dnl vs. v vrefhi (15 v) 0.10 ?0.30 ?0.20 ?0.25 1.5 ?0.10 ?0.15 ?0.05 0 0.05 3.5 3.0 2.5 2.0 dnl (lsb) v vrefhi (v) t a = +25c v dd = +5v v ss = 0v v vreflo = 0v 00275-008 figure 7. dnl vs. v vrefhi (+5 v) 0.3 ?0.3 14 0 ?0.2 ?4 ?0.1 ?6 0.2 0.1 12 10 86420 ?2 t a = +25c v dd = +15v v ss = ?15v v vreflo = ?10v inl (lsb) v vrefhi (v) 00275-009 figure 8. inl vs. vrefhi (15 v) 0.4 ?0.4 ?0.2 ?0.3 1.5 0 ?0.1 0.1 0.2 0.3 3.5 3.0 2.5 2.0 inl (lsb) v vrefhi (v) t a = +25c v dd = +5v v ss = 0v v vreflo = 0v 00275-010 figure 9. inl vs. v vrefhi (+5 v) 0.5 0.7 0.3 0.1 ?0.1 ?0.3 ?0.5 full-scale e r ror with r l = 2k ? (lsb) t = hours of operation at 125c curves not normalized 0 200 400 600 800 1000 v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v x x + 3 x ? 3 00275-011 figure 10. full-scale error vs. time accelerated by burn-in 1.0 1.2 0.8 0.6 0.4 0.2 0 full-scale e r ror with r l = 2k ? (lsb) t = hours of operation at 125c curves not normalized 0 200 400 600 800 1000 v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v x x + 3 x ? 3 00275-012 figure 11. zero-scale error vs. time accelerated by burn-in
dac8420 rev. b | page 11 of 24 0.2 ?0.6 125 ?0.4 ?0.5 ?50 ?75 ?0.2 ?0.3 ?0.1 0 0.1 100 755025 0 ?25 temperature ( c) full-scale error (lsb) v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v dac a dac b dac c dac d 00275-013 figure 12. full-scale error vs. temperature 1.2 ?0.4 125 0 ?0.2 ?50 ?75 0.4 0.2 0.6 0.8 1.0 100 75 5025 0 ?25 temperature ( c) zero-scale error (lsb) v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v dac a dac b dac c dac d 00275-014 figure 13. zero-scale error vs. temperature 0.9 ?0.9 4500 ?0.5 ?0.7 500 0 ?0.1 ?0.3 0.1 0.3 0.5 0.7 4000 3500 3000 2500 2000 1500 1000 digital input code t a = +25c v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v error (lsb) 00275-015 figure 14. channel-to-channel matching 1.5 4500 ?1.5 500 0 ?0.5 ?1.0 0 0.5 1.0 4000 3500 3000 2500 2000 1500 1000 digital input code t a = +25c v dd = +5v v ss = 0v v vrefhi = +2.5v v vreflo = 0v error (lsb) 00275-016 figure 15. channel-to-channel matching 13 4 13 6 5 ?5?7 8 7 9 10 11 12 11 97531 ?1?3 0 i dd (ma) v vrefhi (v) t a = +25c v dd = +15v v ss = ?15v v vreflo = ?10v 00275-017 figure 16. i dd vs. v vrefhi , all dacs high 0.8 ?0.1 4500 0.1 0 500 0 0.3 0.2 0.4 0.5 0.6 0.7 4000 3500 3000 2500 2000 1500 1000 digital input code inl (lsb) 00275-018 ?0.4 ?0.2 ?0.3 t a = +25c, ?55c, 125c v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v figure 17. inl vs. code
dac8420 rev. b | page 12 of 24 1.5 ?1.0 4500 ?0.5 500 0 0 0.5 1.0 4000 3500 3000 2500 2000 1500 1000 digital input code t a = +25c v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v i vrefhi (ma) 00275-019 figure 18. i vrefhi vs. code t a = +25c v dd = +5v v ss = ?5v v vrefhi = +2.5v v vreflo = ?2.5v 1.22mv 1 lsb 0mv ?10.25mv ? 2.50 v 00275-020 ?4.9s 5s/div 45.1s t sett 8s ld figure 19. positive settling time (5 v) 00275-021 0mv 1 lsb 1.22m v 3.5mv 6.5m v clr ?4.9s 5s/div 45.1s t sett 8s t a = +25c v dd = +5v v ss = ?5v v vrefhi = +2.5v v vreflo = ?2.5v figure 20. negative settling time (5 v) 00275-022 4.88mv 1 lsb 0mv ?18.75mv 31.25m v ld ?9.8s 10s/div 90.2s t sett 13s t a = +25c v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v figure 21. positive settling time (15 v) 00275-023 0mv 1 lsb ?4.88mv ?6.25mv 43.75m v clr ?9.8s 10s/div 90.2s t sett 13s t a = +25c v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v figure 22. negative settling time (15 v) 00275-024 +1v/div ?5v 5 v ?47.6s 20s/div 152.4s t a = +25c v dd = +5v v ss = ?5v v vrefhi = +2.5v v vreflo = ?2.5v 0 sr rise = 1.65 v s sr fall = 1.17 v s figure 23. slew rate (5 v)
dac8420 rev. b | page 13 of 24 00275-025 +5v/di v ?25v 25 v ld ?33.6s 20s/div 166.4s t a = +25c v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v 0 sr rise = 1.9 v s sr fall = 2.02 v s clr figure 24. slew rate (15 v) 10 0 ?10 ?20 ?30 gain (db) 10 100 1k 10k 100k 1m 10m frequency (hz) t a = +25c v dd = +15v v ss = ?15v v vrefhi = 0 100mv v vreflo = ?10v all bits high 200mv p-p 00275-026 figure 25. small-signal response 100 90 80 70 60 50 40 30 20 10 0 psrr (db) 10 100 1k 10k 100k 1m frequency (hz) t a = +25c data = 0x000 v dd = +15v 1v v ss = ?15v v vrefhi = +10v v vreflo = ?10v 00275-027 figure 26. psrr vs. frequency 6 4 2 0 ?2 ?4 ?6 power supply current (ma) ?75 0 75 150 temperature (c) i dd i ss v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v all dacs high (full scale) 00275-028 figure 27. power supply current vs. temperature 5v/div 10ma/di v 00275-029 vouta through voutd t a = +25c v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v data = 0x800 figure 28. dac output current vs. voutx 10 8 6 4 2 0 | v out peak| (v) 10 100 1k 10k load resistance ( ? ) t a = +25c v dd = +15v v ss = ?15v v vrefhi = +10v v vreflo = ?10v data = 0xfff or 0x000 00275-030 figure 29. output swing vs. load resistance
dac8420 rev. b | page 14 of 24 theory of operation introduction the dac8420 is a quad, voltage-output 12-bit dac with a serial digital input capable of operating from a single 5 v supply. the straightforward serial interface can be connected directly to most popular microprocessors and microcontrollers, and can accept data at a 10 mhz clock rate when operating from 15 v supplies. a unique voltage reference structure ensures maximum utilization of the dac output resolution by allowing the user to set the zero-scale and full-scale output levels within the supply rails. the analog voltage outputs are fully buffered, and are capable of driving a 2 k load. output glitch impulse during major code transitions is a very low 64 nv-s (typ). digital interface operation the serial input of the dac8420, consisting of cs , sdi, and ld , is easily interfaced to a wide variety of microprocessor serial ports. while cs is low, the data presented to the input sdi is shifted into the internal serial-to-parallel shift register on the rising edge of the clock, with the address msb first, data lsb last, as shown in table 6 and in the timing diagram ( figure 2 ). the data format, shown in tabl e 8 , is two bits of dac address and two dont care fill bits, followed by the 12-bit dac data- word. once all 16 bits of the serial data-word have been input, the load control ld is strobed and the word is parallel-shifted out onto the internal data bus. the two address bits are decoded and used to route the 12-bit data-word to the appropriate dac data register (see the applications section). correct operation of cs and clk in table 6 , the control pins clk and cs require some attention during a data load cycle. since these two inputs are fed to the same logical or gate, the operation is in fact identical. the user must take care to operate them accordingly to avoid clocking in false data bits. in the timing diagram, clk must be halted high or cs must be brought high during the last high portion of the clk following the rising edge that latched in the last data bit. otherwise, an additional rising edge is generated by cs rising while clk is low, causing cs to act as the clock and allowing a false data bit into the serial input register. the same issue must also be considered in the beginn ing of the data load sequence. using clr and clsel the clear ( clr ) control allows the user to perform an asyn- chronous reset function. asserting clr loads all four dac data-word registers, forcing the dac outputs to either zero scale (0x000) or midscale (0x800), depending on the state of clsel as shown in table 6 . the clear function is asynchronous and totally independent of cs . when clr returns high, the dac outputs remain latched at the reset value until ld is strobed, reloading the individual dac data-word registers with either the data held in the serial input register prior to the reset or with new data loaded through the serial interface. table 7. dac address word decode table a1 a0 dac addressed 0 0 dac a 0 1 dac b 1 0 dac c 1 1 dac d programming the analog outputs the unique differential reference structure of the dac8420 allows the user to tailor the output voltage range precisely to the needs of the application. instead of spending dac resolu- tion on an unused region near the positive or negative rail, the dac8420 allows the user to determine both the upper and lower limits of the analog output voltage range. thus, as shown in table 9 and figure 30 , the outputs of dac a through dac d range between vrefhi and vreflo, within the limits specified in the specifications section. note also that vrefhi must be greater than vreflo. 1 lsb 2.5v min 0v min v dd v vrefhi v vreflo v ss ?10v min 2.5v min 0x000 0xfff 00275-006 figure 30. output voltage range programming table 8. (first) (last) b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 a1 a0 nc nc d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address word (msb) dac data-word (lsb)
dac8420 rev. b | page 15 of 24 table 9. analog output code dac data-word (hex) v out note 0xfff 4095 4096 ) ( ? + vreflo vrefhi vreflo full-scale output 0x801 2049 4096 ) ( ? + vreflo vrefhi vreflo midscale + 1 0x800 2048 4096 ) ( ? + vreflo vrefhi vreflo midscale 0x7ff 2047 4096 ) ( ? + vreflo vrefhi vreflo midscale ? 1 0x000 0 4096 ) ( ? + vreflo vrefhi vreflo zero scale
dac8420 rev. b | page 16 of 24 vrefhi input requirements the dac8420 utilizes a unique, patented dac switch driver circuit that compensates for different supply, reference voltage, and digital code inputs. this ensures that all dac ladder switches are always biased equally, ensuring excellent linearity under all conditions. thus, as shown in table 1 , the vrefhi input of the dac8420 requires both sourcing and sinking current capabili- ties from the reference voltage source. many positive voltage references are intended as current sources only and offer little sinking capability. the user should consider references such as the ad584 , ad586 , ad587 , ad588 , ad780 , and ref43 for such an application. power-up sequence to prevent a cmos latch-up condition, power up vdd, vss, and gnd prior to any reference voltages. the ideal power-up sequence is gnd, vss, vdd, vrefhi, vreflo, and digital inputs. noncompliance with the power-up sequence over an extended period can elevate the reference currents and eventually damage the device. on the other hand, if the noncompliant power-up sequence condition is as short as a few milliseconds, the device can resume normal operation without being damaged once vdd/vss is powered.
dac8420 rev. b | page 17 of 24 applications power supply bypassing and grounding in any circuit where accuracy is important, careful consid- eration of the power supply and ground return layout helps to ensure the rated performance. the dac8420 has a single ground pin that is internally connected to the digital section as the logic reference level. the first thought may be to connect this pin to digital ground; however, in large systems digital ground is often noisy because of the switching currents of other digital circuitry. any noise that is introduced at the ground pin can couple into the analog output. thus, to avoid error-causing digital noise in the sensitive analog circuitry, the ground pin should be connected to the system analog ground. the ground path (circuit board trace) should be as wide as possible to reduce any effects of parasitic inductance and ohmic drops. a ground plane is recommended if possible. the noise immunity of the on-board digital circuitry, typically in the hundreds of milli- volts, is well able to reject the common-mode noise typically seen between system analog and digital grounds. finally, the analog and digital ground should be connected to each other at a single point in the system to provide a common reference. this is preferably done at the power supply. good grounding practice is also essential to maintaining analog performance in the surrounding analog support circuitry. with two reference inputs and four analog outputs capable of moderate bandwidth and output current, there is a significant potential for ground loops. again, a ground plane is recommended as the most effective solution to minimizing errors due to noise and ground offsets. 00275-031 v dd v ss gnd +v s ?v s 10f 0.1f 10f 0.1f 1 89 10f = tantalum 0.1f = ceramic figure 31. recommended supply bypassing scheme the dac8420 should have ample supply bypassing, located as close to the package as possible. figure 31 shows the recom- mended capacitor values of 10 f in parallel with 0.1 f. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi) (such as any common ceramic type capacitor), which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. to preserve the specified analog performance of the device, the supply should be as noise free as possible. in the case of 5 v only systems, it is desirable to use the same 5 v supply for both the analog circuitry and the digital portion of the circuit. unfortunately, the typical 5 v supply is extremely noisy due to the fast edge rates of the popular cmos logic families, which induce large inductive voltage spikes, and busy microcontroller or microprocessor buses, and therefore commonly have large current spikes during bus activity. however, by properly filtering the supply as shown in figure 32 , the digital 5 v supply can be used. the inductors and capacitors generate a filter that not only rejects noise due to the digital circuitry, but also filters out the lower frequency noise of switch mode power supplies. the analog supply should be connected as close as possible to the origin of the digital supply to minimize noise pickup from the digital section. + + ttl/cmos logic circuits +5v power supply ferrite beads: 2 turns, fair-rite #2677006301 100f elect. 10f to 22f tant. 0.1f cer. +5v +5v return 00275-032 figure 32. single-supply analog supply filter analog outputs the dac8420 features buffered analog voltage outputs capable of sourcing and sinking up to 5 ma when operating from 15 v supplies, eliminating the need for external buffer amplifiers in most applications while maintaining specified accuracy over the rated operating conditions. the buffered outputs are simply an op amp connected as a voltage follower, and thus have output characteristics very similar to the typical operational amplifier. these amplifiers are short-circuit protected. the user should verify that the output load meets the capabilities of the device, in terms of both output current and load capacitance. the dac8420 is stable with capacitive loads up to 2 nf typically. however, any capacitive load will increase the settling time, and should be minimized if speed is a concern. the output stage includes a p-channel mosfet to pull the output voltage down to the negative supply. this is very important in single-supply systems where vreflo usually has the same potential as the negative supply. with no load, the zero-scale output voltage in these applications is less than 500 v typically, or less than 1 lsb when v vrefhi = 2.5 v. however, when sinking current, this voltage does increase because of the finite imped- ance of the output stage. the effective value of the pull-down resistor in the output stage is typically 320 . with a 100 k resistor connected to 5 v, the resulting zero-scale output voltage
dac8420 rev. b | page 18 of 24 is 16 mv. thus, the best single-supply operation is obtained with the output load connected to ground, so the output stage does not have to sink current. like all amplifiers, the dac8420 output buffers do generate voltage noise, 52 nv/hz typically. this is easily reduced by adding a simple rc low-pass filter on each output. reference configuration the two reference inputs of the dac8420 allow a great deal of flexibility in circuit design. the user must take care, however, to observe the minimum voltage input levels on vrefhi and vreflo to maintain the accuracy shown in the data sheet. these input voltages can be set anywhere across a wide range within the supplies, but must be a minimum of 2.5 v apart in any case (see figure 30 ). a wide output voltage range can be obtained with 5 v references, which can be provided by the ad588 as shown in figure 33 . many applications utilize the dacs to synthesize symmetric bipolar waveforms, which require an accurate, low drift bipolar reference. the ad588 provides both voltages and needs no external components. additionally, the part is trimmed in production for 12-bit accuracy over the full temperature range without user calibra- tion. performing a clear with the reset select clsel high allows the user to easily reset the dac outputs to midscale, or 0 v in these applications. when driving the reference inputs vrefhi and vreflo, it is important to note that vrefhi both sinks and sources current, and that the input currents of both are code dependent. many voltage reference products have a limited current sinking capability and must be buffered with an amplifier to drive vrefhi in order to maintain overall system accuracy. the input vreflo, however, has no such requirement. 8 9 16 15 14 12 11 10 dac8420 1 5 9 10 8 12 11 13 3 4 6 7 1 14 15 2 16 0.1f 0.1f +15v supply ?15v supply system ground +5v ?5v a3 a4 +v s ?v s ad588 r4 r5 r6 r2 r1 r b r3 1f a1 a2 dac a dac b dac c dac d 4 5 digital controls gnd digital inputs vrefhi +5v vreflo ?5v 2 3 6 7 +15v supply 0.1f ?15v supply 0.1f vouta voutb voutc voutd 00275-033 figure 33. 10 v bipolar reference configuration using the ad588
dac8420 rev. b | page 19 of 24 for a single 5 v supply, v vrefhi is limited to at most 2.5 v, and must always be at least 2.5 v less than the positive supply to ensure linearity of the device. for these applications, the ref43 is an excellent low drift 2.5 v reference that consumes only 450 a (max). it works well with the dac8420 in a single 5 v system as shown in figure 34 . 8 9 16 15 14 12 11 10 dac8420 1 dac a dac b dac c dac d 4 5 digital controls gnd digital inputs vrefhi vreflo 2 3 6 7 +5v supply 0.1f vouta voutb voutc voutd 00275-034 ref43 v in gnd 4 2 v out 6 0 .1f +5v supply 2.5v figure 34. 5 v single-su pply operation using ref43 isolated digital interface because the dac8420 is ideal for generating accurate voltages in process control and industrial applications, due to noise, from the central controller; it may be necessary to isolate it from the central controller. this can be easily achieved by using opto-isolators, which are commonly used to provide electrical isolation in excess of 3 kv. figure 35 shows a simple 3-wire interface scheme for controlling the clock, data, and load pulse. for normal operation, cs is tied permanently low so that the dac8420 is always selected. the resistor and capacitor on the clr pin provide a power-on reset with 10 ms time constant. the three opto-isolators are used for the sdi, clk, and ld lines. one opto-isolated line ( ld ) can be eliminated from this circuit by adding an inexpensive 4-bit ttl counter to generate the load pulse for the dac8420 after 16 clock cycles. the counter is used to count the number of clock cycles loading serial data to the dac8420. after all 16 bits have been clocked into the converter, the counter resets, and a load pulse is generated on clock 17. in either circuit, the serial interface of the dac8420 provides a simple, low cost method of isolating the digital control. 10k ? 5v 10k ? 5v 10k ? 5v 5v reg 5v high voltage isolation power ld sclk sdi ref43 v in gnd 4 2 v out 6 +5v 10k ? 5v 0.1f 5v 0.1f vouta voutb voutc voutd 8 9 16 15 14 12 11 10 1 4 5 gnd vreflo 2 3 6 7 vss vdd vrefhi clr clsel dac8420 clk sdi cs ld 2.5v 00275-035 figure 35. opto-lsolated 3-wire interface
dac8420 rev. b | page 20 of 24 8 9 16 15 14 12 11 10 dac8420 dac a dac b dac c dac d 4 5 digital controls gnd digital inputs vrefhi vreflo 2 3 6 7 5v supply vouta voutb voutc voutd 00275-036 ref43 v in gnd 4 2 v out 6 0.1f 5v supply 2.5v vss 0.1f 1 5v 0.1f 3 c1 c2 c3 c4 2 1 14 13 5 7 9 11 4 6 8 10 12 cmp04 604 ? 5v red led 604 ? 5v red led out a out b vina vinb figure 36. dual programmable window comparator dual window comparator often a comparator is needed to signal an out-of-range warning. combining the dac8420 with a quad comparator such as the cmp04 provides a simple dual window comparator with adjustable trip points as shown in figure 36 . this circuit can be operated with either a dual supply or a single supply. for the a input channel, dac b sets the low trip point, and dac a sets the upper trip point. the cmp04 has open-collector outputs that are connected together in a wire-ored configuration to generate an out-of-range signal. for example, when vina goes below the trip point set by dac b, comparator c2 pulls the output down, turning on the red led. the output can also be used as a logic signal for further processing. mc68hc11 microcontroller interfacing figure 37 shows a serial interface between the dac8420 and the mc68hc11 8-bit microcontroller. the sck output of the port outputs the serial data to load into the sdi input of the dac. the port lines (pd5, pc0, pc1, and pc2) provide the controls to the dac as shown. 00275-037 dac8420* clsel clk sdi clr cs ld pc2 sck mosi pc1 pc0 (pd5) ss mc68hc11* *additional pins omitted for clarity. figure 37. mc68hc11 microcontroller interface for correct operation, the mc68hc11 should be configured such that its cpol bit and cpha bit are both set to 1. in this configuration, serial data on mosi of the mc68hc11 is valid on the rising edge of the clock, which is the required timing for the dac8420. data is transmitted in 8-bit bytes (msb first), with only eight rising clock edges occurring in the transmit cycle. to load data to the input register of the dac8420, pc0 is taken low and held low during the entire loading cycle. the first eight bits are shifted in address first, immediately followed by another eight bits in the second least-significant byte to load the complete 16-bit word. at the end of the second byte load, pc0 is then taken high. to prevent an additional advancing of the internal shift register, sck must already be asserted before pc0 is taken high. to transfer the contents of the input shift register to the dac register, pd5 is then taken low, asserting the ld input of the dac and completing the loading process. pd5 should return high before the next load cycle begins. the clr input of the dac8420 (controlled by the output pc1) provides an asynchronous clear function.
dac8420 rev. b | page 21 of 24 dac8420 to m68hc11 interface assembly program * m68hc11 register definitions portc equ $1003 port c control register * ?0,0,0,0;0,clsel,clr,cs? ddrc equ $1007 port c data direction portd equ $1008 port d data register * ?0,0,ld,sclk;sdi,0,0,0? ddrd equ $1009 port d data direction spcr equ $1028 spi control register * ?spie,spe,dwom,mstr;cpol,cpha,spr1,spr0? spsr equ $1029 spi status register * ?spif,wcol,0,modf;0,0,0,0? spdr equ $102a spi data register; read-buffer; write-shifter * * sdi ram variables: sdi1 is encoded from 0 (hex) to cf (hex) * to select: dac a ? set sdi1 to $0x dac b ? set sdi1 to $4x dac c ? set sdi1 to $8x dac d ? set sdi1 to $cx sdi2 is encoded from 00 (hex) to ff (hex) * dac requires two 8-bit loads ? address + 12 bits sdi1 equ $00 sdi packed byte 1 ?a1,a0,0,0;msb,db10,db9,db8? sdi2 equ $01 sdi packed byte 2 ?db7,db6,db5,db4;db3,db2,db1,db0? * main program org $c000 start of user?s ram in evb init lds #$cfff top of c page ram * initialize port c outputs ldaa #$07 0,0,0,0;0,1,1,1 * clsel-hi, clr-hi, cs-hi * to reset dac to zero-scale, set clsel-lo ($03) * to reset dac to mid-scale, set clsel-hi ($07) staa portc initialize port c outputs ldaa #$07 0,0,0,0;0,1,1,1 staa ddrc clsel, clr, and cs are now enabled as outputs * initialize port d outputs ldaa #$30 0,0,1,1;0,0,0,0 * ld-hi,sclk-hi,sdi-lo staa portd initialize port d outputs ldaa #$38 0,0,1,1;1,0,0,0 staa ddrd ld,sclk, and sdi are now enabled as outputs * initialize spi interface ldaa #$5f staa spcr spi is master,c pha=1,cpol=1,clk rate=e/32 * call update subroutine bsr update xfer 2 8-bit words to dac-8420 jmp $e000 restart buffalo * subroutine update update pshx save registers x, y, and a pshy psha * enter contents of sdi1 data register (dac# and 4 msbs) ldaa #$80 1,0,0,0;0,0,0,0 staa sdi1 sdi1 is set to 80 (hex) * enter contents of sdi2 data register ldaa #$00 0,0,0,0;0,0,0,0 staa sdi2 sdi2 is set to 00 (hex) ldx #sdi1 stack pointer at 1st byte to send via sdi ldy #$1000 stack pointer at on-chip registers * clear dac output to zero bclr portc,y $02 assert clr bset portc,y $02 deassert clr * get dac ready for data input bclr portc,y $01 assert cs tfrlp ldaa 0,x get a byte to transfer via spi staa spdr write sdi data reg to start xfer wait ldaa spsr loop to wait for spif bpl wait spif is the msb of spsr * (when spif is set, spsr is negated) inx increment counter to next byte for xfer cpx #sdi2+ 1 are we done yet ? bne tfrlp if not, xfer the second byte * update dac output with contents of dac register bclr portd,y 520 assert ld bset portd,y $20 latch dac register bset portc,y $01 de-assert cs pula when done, restore registers x, y & a puly pulx rts ** return to main program **
dac8420 rev. b | page 22 of 24 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001-ab 073106-b 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 16 1 8 9 0.100 (2.54) bsc 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 38. 16-lead plastic dual in-line package [pdip] narrow body (n-16) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 032707-b 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 39. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches)
dac8420 rev. b | page 23 of 24 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.840 (21.34) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 0 .200 (5.08) max 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.098 (2.49) max 0.100 (2.54) bsc pin 1 1 8 9 16 seating plane 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) figure 40. 16-lead ceramic dual in-line package [cerdip] (q-16) dimensions shown in inches and (millimeters) ordering guide model temperature range package description package option inl 1 (lsb) dac8420ep ?40c to +85c 16-lead plastic dual in-line package [pdip] n-16 0.5 dac8420epz 2 ?40c to +85c 16-lead plastic dual in-line package [pdip] n-16 0.5 dac8420es ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 0.5 dac8420es-reel ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 0.5 dac8420esz 2 ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 0.5 dac8420esz-reel 2 ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 0.5 dac8420fp ?40c to +85c 16-lead plastic dual in-line package [pdip] n-16 1.0 dac8420fpz 2 ?40c to +85c 16-lead plastic dual in-line package [pdip] n-16 1.0 dac8420fq ?40c to +85c 16-lead ceramic dual in-line package [cerdip] q-16 1.0 dac8420fs ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 1.0 dac8420fs-reel ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 1.0 dac8420fsz 2 ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 1.0 DAC8420FSZ-REEL 2 ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 1.0 1 inl measured at vdd = +15 v and vss = ?15 v. 2 z = rohs compliant part.
dac8420 rev. b | page 24 of 24 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c00275-0-5/07(b)

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