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preliminary W79E834 data sheet 8-bit microcontroller publication release date: october 12, 2006 - 1 - revision a13 table of contents- 1. general des cription ......................................................................................................... 4 2. features ....................................................................................................................... .......... 4 3. parts informat ion list ..................................................................................................... 5 3.1 lead free (rohs) parts informati on list ......................................................................... 5 4. pin config urati on .............................................................................................................. .6 pin descri ption ................................................................................................................ ................. 7 5. functional des cription ................................................................................................... 8 5.1 on-chip flas h eprom .................................................................................................. 8 5.2 i/o ports...................................................................................................................... .... 8 5.3 serial i/o ..................................................................................................................... .... 8 5.4 timers ......................................................................................................................... .... 8 5.5 interr upts..................................................................................................................... .... 9 5.6 data po inters .................................................................................................................. 9 5.7 architec ture................................................................................................................... .. 9 5.8 power m anagement ...................................................................................................... 10 6. memory orga nizati on ..................................................................................................... 11 6.1 program me mory .......................................................................................................... 11 6.2 data me mory ................................................................................................................ 11 6.3 register map ................................................................................................................ 12 6.4 working regi sters ........................................................................................................ 14 6.5 bit addressable locati ons ............................................................................................ 14 6.6 stack .......................................................................................................................... ... 14 7. special function registers ......................................................................................... 15 7.1 sfr location table ...................................................................................................... 15 7.2 sfr detail bit descripti ons .......................................................................................... 16 8. instruct ion.................................................................................................................... ...... 44 8.1 instruction timing................................................................................................ 44 9. power mana gement .......................................................................................................... 48 9.1 idle mode ...................................................................................................................... 48 9.2 power down mode ....................................................................................................... 48 10. reset condi tions............................................................................................................... 49 10.1 external reset .............................................................................................................. 49 10.2 power-on rese t (por) ................................................................................................ 49
preliminary W79E834 data sheet - 2 - 10.3 watchdog timer reset ................................................................................................. 49 10.4 s/w reset ...................................................................................................................... 49 10.5 reset state ................................................................................................................... 4 9 11. interrup ts ..................................................................................................................... ...... 51 11.1 interrupt s ources .......................................................................................................... 51 11.2 priority level structure ................................................................................................. 52 11.3 interrupt res ponse ti me .............................................................................................. 55 11.4 interrupt inputs.............................................................................................................. 5 5 12. programmable time rs/count ers ............................................................................... 57 12.1 timer/counter s 0 & 1 ............................................................................................ 57 12.2 time-base se lection..................................................................................................... 57 12.3 mode 0 ........................................................................................................................ 5 7 12.4 mode 1 ........................................................................................................................ 5 8 12.5 mode 2 ........................................................................................................................ 5 9 12.6 mode 3 ........................................................................................................................ 5 9 13. watchdog timer................................................................................................................. 61 13.1 watchdog co ntrol.............................................................................................. 62 13.2 clock control of watc hdog ................................................................................. 63 14. timer2/input capt ure modul es .................................................................................... 64 14.1 capture mode ............................................................................................................... 64 14.2 compare mode ............................................................................................................. 69 14.3 reload m ode ................................................................................................................ 69 15. serial port (uar t) ............................................................................................................. 70 15.1 mode 0 ........................................................................................................................ 7 0 15.2 mode 1 ........................................................................................................................ 7 1 15.3 mode 2 ........................................................................................................................ 7 3 15.4 mode 3 ........................................................................................................................ 7 4 15.5 framing error detection ............................................................................................... 75 15.6 multiprocessor co mmunicati ons .................................................................................. 75 16. serial pheripheral in terface ( spi) ............................................................................ 77 16.1 general descr iptions ..................................................................................................... 77 16.2 block descr iptions ......................................................................................................... 77 16.3 functional de scripti ons ................................................................................................. 78 17. timed access pr otection .............................................................................................. 88 18. keyboard interrup t (kbi) ............................................................................................... 90 19. i/o port conf iguration ................................................................................................... 91 19.1 quasi-bidirectional out put configur ation ..................................................................... 91
preliminary W79E834 data sheet publication release date: october 12, 2006 - 3 - revision a13 19.2 open drain output configurat ion ................................................................................. 92 19.3 push-pull output configurat ion .................................................................................... 92 20. oscilla tor ..................................................................................................................... ...... 94 20.1 on-chip rc oscilla tor opti on ...................................................................................... 94 20.2 external clock input op tion .......................................................................................... 94 20.3 cpu clock rate select ................................................................................................. 95 21. power monitoring functio n ........................................................................................ 95 21.1 power on detect .......................................................................................................... 95 21.2 brownout de tect ........................................................................................................... 95 22. pulse width modulated outputs (pwm) ................................................................... 96 23. analog-to-digital conver ter ...................................................................................... 99 23.1 adc resolution and analog s upply:.......................................................................... 100 24. icp (in-circuit program ) flash pr ogram ............................................................... 102 25. config bits .................................................................................................................... ..... 103 25.1 config 1 .................................................................................................................... 103 25.2 config 2 .................................................................................................................... 104 26. absolute maximu m rating s ......................................................................................... 105 27. dc electrical cha racteris tics ................................................................................ 106 27.1 the adc converter dc electr ical charact eristi cs ................................... 107 28. ac electrical cha racteris tics................................................................................. 108 29. external clock cha racteris tics ............................................................................ 108 30. ac specific ation............................................................................................................... 109 31. typical applicat ion circui ts ...................................................................................... 109 32. package dime nsions ....................................................................................................... 110 32.1 28-lead sop ( 300 mil) ............................................................................................... 110 32.2 48l lqfp (7x7x1.4mm f ootprint 2. 0mm) ................................................................... 111 33. revision hi story .............................................................................................................. 1 12
preliminary W79E834 data sheet - 4 - 1. general description W79E834 is an 8-bit turbo 51 microcontroller wh ich has flash eprom which flash eprom can program by icp (in circuit program) or by writer . the instruction sets of the W79E834 are fully compatible with the standard 8052. W79E834 contains a 8k bytes of main flash eprom; a 256 bytes of ram; 256 bytes aux-ram; three 8-bit bi-direc tional, one 2-bit bi-directional and bit-addressable i/o ports; two 16-bit timer/counters; 8-channel multiplexed 10-bit a/d c onverter; 4-channel 10-bit pwm; one timer with input capture units; two serial ports that include a spi and an enhanced full duplex serial port. these peripherals are supported by 13 sour ces four-level interrupt capability. to facilitate programming and verification, the flash eprom in side W79E834 allow the program memory to be programmed and read electronically. once the code is confirmed, the user can protect the code for security. 2. features ? fully static design 8-bit turbo 51 cmos micr ocontroller up to 16mhz when vdd=4.5v to 5.5v, 12mhz when vdd=2.7v to 5.5v ? 8k bytes of flash eprom (ap flash eprom), with icp and external writer programmable mode ? 256 bytes of on-chip ram ? 256 bytes of on-chip aux-ram ? instruction-set compatible with msc-51 ? three 8-bit bi-directional and one 2-bit bi-directional port ? two 16-bit timer/counters ? one timer with three input captures capability ? 13 interrupts source with four levels of priority ? one enhanced full duplex serial port with frami ng error detection and automatic address recognition ? the 4 outputs mode and ttl/schmitt trigger selectable port ? programmable watchdog timer ? four-channel 10-bit pwm (pulse width modulator) ? eight-channel multiplexed with 10-bits a/d converter ? one spi with master/slave capability ? eight keypad interrupt inputs ? configurable on-chip oscillator ? built-in power management ? led drive capability (20ma) on all port pins ? low voltage detect interrupt and reset ? code protection ? packages: ? lead free (rohs) sop 28: W79E834asg ? lead free (rohs) lqfp 48: W79E834alg
preliminary W79E834 data sheet publication release date: october 12, 2006 - 5 - revision a13 3. parts information list 3.1 lead free (rohs) parts information list part no. eprom flash size ram aux ram adc pwm package remark W79E834asg 8kb 256b 256b 8x10bit 4x10bit lqfp-48 pin W79E834asg 8kb 256b 256b 8x10bit 4x10bit sop-28 pin
preliminary W79E834 data sheet - 6 - 4. pin configuration 1 nc 2 3 4 5 6 7 33 32 31 30 29 28 27 26 25 8 9 pwm1, p1.7 pwm0, p1.6 rst, p1.5 avss xtal1, p3.1 clkout, xtal2, p3.0 stadc, int1, p1.4 t1, kb7, p0.7 adc5, kb6, p0.6 vdd adc4, kb5, p0.5 adc3, kb4, p0.4 adc2, kb3, p0.3 adc1, kb2, p0.2 W79E834alg lqfp 48-pin 10 11 12 34 35 36 nc nc nc nc nc vdd avdd vss vss
preliminary W79E834 data sheet publication release date: october 12, 2006 - 7 - revision a13 pin description symbol type descriptions st r (p1.5) i reset: a low on this pin for two machine cycles while the oscillator is running resets the device. xtal1(p3.1) i/o crystal1: this is the crystal oscilla tor input. this pin may be driven by an external clock or configurable i/o pin. xtal2(p3.0) i/o crystal2: this is the crystal oscillato r output. it is the inversion of xtal1 or configurable i/o pin. vss p ground: ground potential vdd p power: supply: supply voltage for operation. p0.0 ? p0.7 i/o port 0: port 0 is four mode output pin and two mode input. multifunction pins for t1, pwm2, adc0-5 and kb0-kb7. p1.0 ? p1.7 i/o port 1: port 1 is four mode output pin and two mode input. multifunction pins for /rst, txd & rxd, t0, int0 , int1 , pwm0-1 and stadc. p2.0 ? p2.7 i/o port 2: port 2 is four mode output pin and two mode input. multifunction pins for t2, pwm3, mosi, miso, ss , sclk and adc6-7. * type: p: power, i: input, o: output, i/o: bi-directional.
preliminary W79E834 data sheet - 8 - 5. functional description W79E834 architecture consist of a 4t 8051 core c ontroller surrounded by various registers, 8k bytes flash eprom, 256 bytes of ram, 256 bytes au x ram, three general purpose i/o ports, two timer/counters, one uart serial port, one spi, one time r with input capture units, 4 channel pwm with 10-bit counter, 8-channel multiplexed with 10-bit adc analog input, flash eprom program by writer and icp. 5.1 on-chip flash eprom W79E834 includes one 8k bytes of main flash epr om for application program when operating the in-circuit programming features by the flash eprom itself which need writer or icp program board to program the flash eprom. this icp (in-circui t programming) feature makes the job easy and efficient in which the application needs to update fi rmware frequently. in some applications, the in- circuit programming feature makes it possible that the end-user is able to easily update the system firmware by themselves without opening the chassis. 5.2 i/o ports W79E834 has three 8-bit and one 2-bit port, up to 25 i/o pins and 1 input pin (/rst is input only) using on-chip oscillator & /rst is input only by reset options. all ports can be used as four outputs mode when it may set by pxm1.y and pxm2.y regi sters, it has strong pull-ups and pull-downs, and does not need any external pull-ups. otherwise it can be used as general i/o port as open drain circuit. all ports can be used bi-directional and these are as i/o ports. these por ts are not true i/o, but rather are pseudo-i/o ports. this is because these ports have str ong pull-downs and weak pull-ups. 5.3 serial i/o W79E834 has one serial port that is functionally simila r to the serial port of the original 8032 family. however the serial port on W79E834 can operate in diffe rent modes in order to obtain timing similarity as well. the serial port has the enhanced features of automatic address recognition and frame error detection. the device also consists of another serial in terface, spi. this is a full duplex, synchronous communication bus supporting 2 operating modes: mast er and slave mode. it has a transfer complete flag. it also support overrun and mode fault st atus, and write collision protection mechanism. 5.4 timers the device has total three 16-bit time rs; two 16-bit timers that have func tions similar to the timers of the 8032 family, and third timer is capable to func tion as timer and also provide capture support. when used as timers, user has a choice to set 12 or 4 clocks per count that emulates the timing of the original 8032. each timer?s count value is stored in two sfr locations that can be written or read by software. there are also some other sfrs associ ated with the timers that control their mode and operation.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 9 - revision a13 5.5 interrupts the interrupt structure in W79E834 is slightly di fferent from that of the standard 8052. due to the presence of additional features and peripherals, t he number of interrupt sources and vectors has been increased. 5.6 data pointers the data pointer of W79E834 is similar to standard 8052 that have dual 16-bit data pointers (dptr) by setting dps of auxr1.0. the figure of dual dprt is as below diagram. dptr dptr dps auxr1.0 dps=0 dps=1 5.7 architecture W79E834 is based on the standard 8052 device. it is bu ilt around an 8-bit alu that uses internal registers for temporary storage and control of t he peripheral devices. it can execute the standard 8052 instruction set. 5.7.1 alu the alu is the heart of the W79E834. it is responsib le for the arithmetic and logical functions. it is also used in decision making, in case of jump in structions, and is also used in calculating jump addresses. the user cannot directly use the alu, but the instruction decoder reads the op-code, decodes it, and sequences the data through the alu and its associated registers to generate the required result. the alu mainly uses the acc which is a special function register (sfr) on the chip. another sfr, namely b register is also used in multiply and divide instructions. the alu generates several status signals which are stored in t he program status word register (psw). 5.7.2 accumulator the accumulator (acc) is the primary register us ed in arithmetic, logical and data transfer operations in W79E834. since the accumulator is directly accessible by the cpu, most of the high speed instructions make use of the acc as one argument. 5.7.3 b register this is an 8-bit register that is used as the se cond argument in the mul and div instructions. for all other instructions it can be used si mply as a general purpose register.
preliminary W79E834 data sheet - 10 - 5.7.4 program status word: this is an 8-bit sfr that is used to store the stat us bits of the alu. it holds the carry flag, the auxiliary carry flag, general purpose flags, the register bank select, the overflow flag, and the parity flag. 5.7.5 scratch-pad ram W79E834 has a 256 bytes on-chip scratch-pad ram. these can be used by the user for temporary storage during program execution. a certain section of this ram is bit addressable, and can be directly addressed for this purpose. 5.7.6 stack pointer W79E834 has an 8-bit stack pointer which points to t he top of the stack. this stack resides in the scratch pad ram in W79E834. hence the size of t he stack is limited by the size of this ram. 5.7.7 movx aux ram W79E834 has a 256 bytes aux ram of data space sram which is read/write accessible and is memory mapped. this on-chip sram is reached by the movx instruction. it is not used for executable memory. there is no conflict or over lap as they use different addressing modes and separate instructions. 5.8 power management power management like the standard 8051/52, the W79E834 has idle and power down modes of operation. in the idle mode, the clock to t he cpu is stopped while the timers, serial ports and interrupt lock continue to operate. in power down mode, all of the peripheral clocks are stopped, and chip operation stops completely. this mode consumes the least amount of power.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 11 - revision a13 6. memory organization W79E834 separates the memory into two separat e sections, the program memory and the data memory. the program memory is used to store the instruction op-codes, while the data memory is used to store data or for memory mapped devices. 6.1 program memory the program memory on W79E834 can be up to 8k bytes long. all instructions are fetched for execution from this memory area. the movc in struction can also access this memory region. 6.2 data memory W79E834 can read/write 256 bytes aux ram by the movx instruction. the data memory region is from 0000h to 00ffh. 0000h external data memory space on-chip code memory space 0000h 8k bytes on-chip code memory unused code memory config 1 1fffh 2000h ffffh ffffh config 2 unused data memory 256 bytes on-chip aux ram 0000h 00ffh
preliminary W79E834 data sheet - 12 - 6.3 register map as mentioned before, W79E834 has separate progr am and data memory areas. the on-chip 256 bytes scratch pad ram is in addition to the external memory. there are also several special function registers (sfrs) which can be accessed by softw are. the sfrs can be accessed only by direct addressing, while the on-chip ram can be accessed by either direct or indirect addressing. since the scratch-pad ram is only 256 bytes it c an be used only when data contents are small. there are several other special purpose areas within t he scratch-pad ram. these are described as follows.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 13 - revision a13 bank 0 bank 1 bank 2 bank 3 03 02 01 00 04 05 06 07 0b 0a 09 08 0c 0d 0e 0f 13 12 11 10 14 15 16 17 1b 1a 19 18 1c 1d 1e 1f 23 22 21 20 24 25 26 27 2b 2a 29 28 2c 2d 2e 2f 33 32 31 30 34 35 36 37 3b 3a 39 38 3c 3d 3e 3f 43 42 41 40 44 45 46 47 4b 4a 49 48 4c 4d 4e 4f 53 52 51 50 54 55 56 57 5b 5a 59 58 5c 5d 5e 5f 63 62 61 60 64 65 66 67 6b 6a 69 68 6c 6d 6e 6f 73 72 71 70 74 75 76 77 7b 7a 79 78 7c 7d 7e 7f direct ram indirect ram 00h 07h 28h 08h 0fh 10h 17h 18h 1fh 20h 21h 22h 23h 24h 25h 26h 27h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 7fh 80h ffh
preliminary W79E834 data sheet - 14 - 6.4 working registers there are four sets of working registers, each cons isting of eight 8-bit registers. these are termed ads banks 0, 1, 2, and 3. individual registers within these banks can be directly accessed by separate instructions. these individual registers are named as r0, r1, r2, r3, r4, r5, r6 and r7. however, at any one time W79E834 can work with only one particular bank. the bank selection is done by setting rs1-rs0 bits in the psw. the r0 and r1 regi sters are used to store the address for indirect accessing. 6.5 bit addressable locations the scratch-pad ram area from location 20h to 2fh is byte as well as bit addressable. this means that a bit in this area can be individually address ed. in addition some of the sfrs are also bit addressable. the instruction decoder is able to disti nguish a bit access from a byte access by the type of the instruction itself. in the sfr area, any existing sfr whose address ends in a 0 or 8 is bit addressable. 6.6 stack the scratch-pad ram can be used for the stack. this area is selected by the stack pointer (sp), which stores the address of the t op of the stack. whenever a jump, call or interrupt is invoked the return address is placed on the stack. there is no re striction as to where the stack can begin in the ram. by default however, the stack pointer contai ns 07h at reset. the user can then change this to any value desired. the sp will point to the last used value. therefore, the sp will be incremented and then address saved onto the stack. conversely, while popping from t he stack the contents will be read first, and then the sp is decreased.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 15 - revision a13 7. special function registers W79E834 uses special function registers (sfrs) to control and monitor peripherals and their modes. the sfrs reside in the register locations 80-ffh and are accessed by direct addressing only. some of the sfrs are bit addressable. this is ve ry useful in cases where we wish to modify a particular bit without changing the others. the sf rs that are bit addressable are those whose addresses end in 0 or 8. W79E834 contains all the sfrs present in the standard 8052. however some additional sfrs are added. in some cases the unused bits in the original 8052, have been given new functions. the list of the sfrs is as follows. 7.1 sfr location table table 1 special function register location table f8 ip1 f0 b spcr spsr spdr padids ip1h e8 ie1 e0 acc adccon adch ccl0 cch0 ccl1 cch1 d8 wdcon pwmpl pwm0l pwm1l pwmcon1 pwm2l pwm3l d0 psw pwmph pwm0h pwm1h pwm2h pwm3h pwmcon3 c8 t2con t2mod rcap2l rcap2h tl2 th2 c0 ta b8 ip0 saden b0 p3 p0m1 p0m2 p1m1 p1m2 p2m1 p2m2 ip0h a8 ie saddr a0 p2 kbi auxr1 capcon0 capcon1 ccl2 cch2 98 scon sbuf p3m1 p3m2 90 p1 divm 88 tcon tmod tl0 tl1 th0 th1 ckcon 80 p0 sp dpl dph pcon note: 1. the sfrs in the column with dark borders are bit-addressable 2. the table is condensed with eight loca tions per row. empty locations indicate that these are no registers at these addresses.
preliminary W79E834 data sheet - 16 - 7.2 sfr detail bit descriptions port 0 bit: 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 mnemonic: p0 address: 80h p0.7-0: general purpose input/output port. most instru ctions will read the port pins in case of a port read access, however in case of read-modify-write in structions, the port latch is read. these alternate functions are described below: bit name function 7 p0.7 t1 or kb7 pin 6 p0.6 adc5 or kb6 5 p0.5 adc4 or kb5 or clock (icp function) pin 4 p0.4 adc3 or kb4 or data (icp function) pin 3 p0.3 adc2 or kb3 pin 2 p0.2 adc1 or kb2 pin 1 p0.1 adc0 or kb1 pin 0 p0.0 pwm 2 or kb0 pin stack pointer bit: 7 6 5 4 3 2 1 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 mnemonic: sp address: 81h the stack pointer stores the scratchpad ram addre ss where the stack begins. in other words, it always points to the top of the stack. data pointer low bit: 7 6 5 4 3 2 1 0 dpl.7 dpl.6 dpl.5 dpl.4 dpl.3 dpl.2 dpl.1 dpl.0 mnemonic: dpl address: 82h this is the low byte of the standard 8052 16-bit data pointer. data pointer high bit: 7 6 5 4 3 2 1 0 dph.7 dph.6 dph.5 dph.4 dph.3 dph.2 dph.1 dph.0 mnemonic: dph address: 83h this is the high byte of the standard 8052 16-bit data pointer. this is the high byte of the dptr1 16-bit data pointer.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 17 - revision a13 power control bit: 7 6 5 4 3 2 1 0 smod smod0 bof por gf1 gf0 pd idl mnemonic: pcon address: 87h bit name function 7 smod 1: this bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1. 6 smod0 0: framing error detection disable. scon.7 (sm0/fe) bit is used as sm0 (standard 8052 function). 1: framing error detection enable. scon.7 (sm0/fe) bit is used as fe status flag. 5 bof 0: cleared by software. 1: set automatically when a brownout reset or interrupt has occurred. also set at power on. 4 por 0: cleared bit software. 1: set automatically when a power-on reset has occurred. 3 gf1 these two bits are general purpose user flags. 2 gf0 these two bits are general purpose user flags. 1 pd 1: setting this bit causes the W79E834 to go into the power down mode. in this mode all the clocks are stopped and pr ogram execution is frozen. 0 idl 1: setting this bit causes the W79E834 to go into the idle mode. in this mode the clock to the cpu is stopped, so program ex ecution is frozen. but the clock to the serial, timer and interrupt blocks is not stopped, and these blocks continue operating. timer control bit: 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 mnemonic: tcon address: 88h bit name function 7 tf1 timer 1 overflow flag: this bit is se t when timer 1 overflows. it is cleared automatically when the program does a time r 1 interrupt service routine. software can also set or clear this bit. 6 tr1 timer 1 run control: this bit is set or cl eared by software to turn timer/counter on or off. 5 tf0 timer 0 overflow flag: this bit is set when timer 0 overflows. it is cleared automatically when the program does a time r 0 interrupt service routine. software can also set or clear this bit. 4 tr0 timer 0 run control: this bit is set or cl eared by software to turn timer/counter on or off.
preliminary W79E834 data sheet - 18 - continued. 3 ie1 interrupt 1 edge detect: set by har dware when an edge/level is detected on int1 . this bit is cleared by hardware when the se rvice routine is vectored to only if the interrupt was edge triggered. otherwise, it follows the inverse of the pin. 2 it1 interrupt 1 type control: set/cleared by software to specify falling edge/ low level triggered external inputs. 1 ie0 interrupt 0 edge detect: set by har dware when an edge/level is detected on int0 . this bit is cleared by hardware when the se rvice routine is vectored to only if the interrupt was edge triggered. otherwise it follows the inverse of the pin. 0 it0 interrupt 0 type control: set/cleared by software to specify falling edge/ low level triggered external inputs. timer mode control bit: 7 6 5 4 3 2 1 0 gate t c/ m1 m0 gate t c/ m1 m0 timer/counter 1 timer/counter 0 mnemonic: tmod address: 89h bit name function 7 gate timer/counter 1 gating control: when this bit is set, timer/counter 1 is enabled only while int1 pin is high and tr1 control bit is set. when cleared, timer 1 is enabled whenever tr1 control bit is set. 6 t c/ timer/counter 1 select: when cleared, the ti mer is incremented by internal clocks. when set, the timer counts high-to-low edges of the t1 pin. 5 m1 timer1 mode select bit1: see table below. 4 m0 timer1 mode select bit0: see table below. 3 gate timer/counter 0 gating control: when this bit is set, timer/counter 0 is enabled only while int0 pin is high and tr0 control bit is set. when cleared, timer 0 is enabled whenever tr0 control bit is set. 2 t c/ timer/counter 0 select: when cleared, the ti mer is incremented by internal clocks. when set, the timer counts high-to-low edges of the t0 pin. 1 m1 timer0 mode select bit1: see table below. 0 m0 timer0 mode select bit0: see table below. m1, m0: mode select bits: m1 m0 mode 0 0 mode 0: 8-bits with 5-bit pre-scale. 0 1 mode 1: 18-bits, no pre-scale. 1 0 mode 2: 8-bits with auto-reload from thx 1 1 mode 3: (timer 0) tl0 is an 8-bit timer/ counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only cont rolled by timer 1 control bits. (timer 1) timer/counter is stopped.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 19 - revision a13 timer 0 lsb bit: 7 6 5 4 3 2 1 0 tl0.7 tl0.6 tl0.5 tl0.4 tl0.3 tl0.2 tl0.1 tl0.0 mnemonic: tl0 address: 8ah tl0.7-0: timer 0 lsb timer 1 lsb bit: 7 6 5 4 3 2 1 0 tl1.7 tl1.6 tl1.5 tl1.4 tl1.3 tl1.2 tl1.1 tl1.0 mnemonic: tl1 address: 8bh tl1.7-0: timer 1 lsb timer 0 msb bit: 7 6 5 4 3 2 1 0 th0.7 th0.6 th0.5 th0.4 th0.3 th0.2 th0.1 th0.0 mnemonic: th0 address: 8ch th0.7-0: timer 0 msb timer 1 msb bit: 7 6 5 4 3 2 1 0 th1.7 th1.6 th1.5 th1.4 th1.3 th1.2 th1.1 th1.0 mnemonic: th1 address: 8dh th1.7-0: timer 1 msb clock control bit: 7 6 5 4 3 2 1 0 - ccdiv[1:0] t1m t0m - - - mnemonic: ckcon address: 8eh
preliminary W79E834 data sheet - 20 - bit name function 7 - reserved 6:5 ccdiv.1-0 timer 2 clock select: ccdiv[1] ccdiv[0] 0 0 : timer 2 clock = fosc 0 1 : timer 2 clock = fosc/4 1 0 : timer 2 clock = fosc/16 1 1 : timer 2 clock = fosc/32 4 t1m timer 1 clock select: 0: timer 1 uses a divide by 12 clocks. 1: timer 1 uses a divide by 4 clocks. 3 t0m timer 0 clock select: 0: timer 0 uses a divide by 12 clocks. 1: timer 0 uses a divide by 4 clocks. 2:0 - reserved port 1 bit: 7 6 5 4 3 2 1 0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 mnemonic: p1 address: 90h p1.7-0: general purpose input/output port. most instru ctions will read the port pins in case of a port read access, however in case of read-modify-write in structions, the port latch is read. these alternate functions are described below: bit name function 7 p1.7 pwm 1 pin 6 p1.6 pwm 0 pin 5 p1.5 rst pin or input pin by alternative 4 p1.4 int1 interrupt or stadc 3 p1.3 int0 interrupt 2 p1.2 timer 0 1 p1.1 rxd of serial port 0 p1.0 txd of serial port
preliminary W79E834 data sheet publication release date: october 12, 2006 - 21 - revision a13 divider clock bit: 7 6 5 4 3 2 1 0 divm.7 divm.6 divm.5 divm.4 divm.3 divm.2 divm.1 divm.0 mnemonic: divm address: 95h the divm register is clock divider of uc. serial port control bit: 7 6 5 4 3 2 1 0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri mnemonic: scon address: 98h bit name function 7 sm0/fe serial port 0, mode 0 bit or framing error flag: the smod0 bit in pcon sfr determines whether this bit ac ts as sm0 or as fe. the operation of sm0 is described below. when used as fe, this bit will be set to indicate an invalid stop bit. this bit must be manually cleared in software to clear the fe condition. 6 sm1 serial port mode bit 1: mode: sm0 sm1 description length baud rate 0 0 0 synchronous 8 4/12 tclk 1 0 1 asynchronous 10 variable 2 1 0 asynch ronous 11 64/32 tclk 3 1 1 asynchronous 11 variable 5 sm2 multiple processors communication. setting this bit to 1 enables the multiprocessor communication feature in mode 2 and 3. in mode 2 or 3, if sm2 is set to 1, then ri will not be activated if the received 9th data bit (r b8) is 0. in mode 1, if sm2 = 1, then ri will not be activated if a valid stop bit wa s not received. in mode 0, the sm2 bit controls the serial port clock. if set to 0, t hen the serial port runs at a divide by 12 clock of the oscillator. this gives compatibilit y with the standard 8052. when set to 1, the serial clock become divide by 4 of the o scillator clock. this results in faster synchronous serial communication. 4 ren receive enable: when set to 1 serial rec eption is enabled, otherwise reception is disabled. 3 tb8 this is the 9th bit to be transmitted in m odes 2 and 3. this bit is set and cleared by software as desired. 2 rb8 in modes 2 and 3 this is the received 9th dat a bit. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0 it has no function. 1 ti transmit interrupt flag: this flag is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in all other modes during serial transmission. this bit must be cleared by software. 0 ri receive interrupt flag: this flag is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bits time in the other modes during serial reception. however the restrictions of sm 2 apply to this bit. this bit can be cleared only by software.
preliminary W79E834 data sheet - 22 - serial data buffer bit: 7 6 5 4 3 2 1 0 sbuf.7 sbuf.6 sbuf.5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0 mnemonic: sbuf address: 99h bit name function 7~0 sbuf serial data on the serial port is read from or wr itten to this location. it actually consists of two separate internal 8-bit registers. one is the receive resister, and the other is the transmit buffer. any read access gets data fr om the receive data buffer, while write access is to the transmit data buffer. port 3 output mode 1 bit: 7 6 5 4 3 2 1 0 p3s p2s p1s p0s t1oe t0oe p3m1.1 p3m1.0 mnemonic: p3m1 address: 9eh bit name function 7 p3s 1: enables schmitt trigger inputs on port 3. 6 p2s 1: enables schmitt trigger inputs on port 2. 5 p1s 1: enables schmitt trigger inputs on port 1. 4 p0s 1: enables schmitt trigger inputs on port 0. 3 t1oe 1: the p0.7 pin is toggled whenever ti mer 1 overflows. the output frequency is therefore one half of the timer 1 overflow rate. 2 t0oe 1: the p1.2 pin is toggled whenever ti mer 0 overflows. the output frequency is therefore one half of the timer 0 overflow rate. 1 p3m1.1 to control the output configuration of p3.1. 0 p3m1.0 to control the output configuration of p3.0. port 3 output mode 2 bit: 7 6 5 4 3 2 1 0 - - - - - enclk p3m2.1 p3m2.0 mnemonic: p3m2 address: 9fh bit name function 7~3 - reserved 2 enclk 1: to use the on-chip rc oscillator, a clock output is enabled on the xtal2 pin. 1 p3m2.1 see as below table. 0 p3m2.0 see as below table.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 23 - revision a13 port output configuration settings: p3m1.y p3m2.y port input/output mode 0 0 quasi-bidirectional 0 1 push-pull 1 0 input only (high impedance) 1 1 open drain port 2 bit: 7 6 5 4 3 2 1 0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 mnemonic: p2 address: a0h p2.7-0: general purpose input/output port. most instru ctions will read the port pins in case of a port read access, however in case of read-modify-write in structions, the port latch is read. these alternate functions are described below: keyboard interrupt bit: 7 6 5 4 3 2 1 0 kbi.7 kbi.6 kbi.5 kbi.4 kbi.3 kbi.2 kbi.1 kbi.0 mnemonic: kbi address: a1h keyboard interrupt enable. bit name function 7 kbi.7 1: enable p0.7 as a cause of a keyboard interrupt. 6 kbi.6 1: enable p0.6 as a cause of a keyboard interrupt. 5 kbi.5 1: enable p0.5 as a cause of a keyboard interrupt. 4 kbi.4 1: enable p0.4 as a cause of a keyboard interrupt. 3 kbi.3 1: enable p0.3 as a cause of a keyboard interrupt. 2 kbi.2 1: enable p0.2 as a cause of a keyboard interrupt. 1 kbi.1 1: enable p0.1 as a cause of a keyboard interrupt. 0 kbi.0 1: enable p0.0 as a cause of a keyboard interrupt. aux function register 1 bit: 7 6 5 4 3 2 1 0 kbf bod boi lpbov srst adcen rcclk dps mnemonic: auxr1 address: a2h
preliminary W79E834 data sheet - 24 - bit name function 7 kbf keyboard interrupt flag: 1: when any pin of port 0 that is enabled fo r the keyboard interrupt function goes low. must be cleared by software. 6 bod brown out disable: 0: enable brownout detect function. 1: disable brownout detect function and save power. 5 boi brown out interrupt: 0: disable brownout detect interrupt function. 1: this prevents brownout detection from causing a chip reset and allows the brownout detect function to be used as an interrupt. 4 lpbov low power brown out detect control: 0: when bod is enable, the brown out detec t is always turned on by normal run or power down mode. 1: when bod is enable, the 1/16 time will be turned on brown out detect circuit by power down mode. when uc is entry power down mode, the bod will enable internal rc osc(2mhz~0.5mhz) 3 srst software reset: 1: reset the chip as if a hardware reset occurred. 2 adcen 0: disable adc circuit. 1: enable adc circuit. 1 rcclk 0: the cpu clock is used as adc clock. 1: the internal rc clock is used as adc clock. 0 dps dual data pointer select 0: to select dptr of standard 8051. 1: to select dptr1 capture control 0 register bit: 7 6 5 4 3 2 1 0 cct2 cct1 cct0 ccld mnemonic: capcon0 address: a3h
preliminary W79E834 data sheet publication release date: october 12, 2006 - 25 - revision a13 bit name function 7-6 cct2[1:0] capture 2 edge select. cct2[1:0] : 00 : rising edge trigger 01 : falling edge trigger 10 : both rising and falling edge trigger 11 : reserved 5-4 cct1[1:0] capture 1 edge select. cct1[1:0] : 00 : rising edge trigger 01 : falling edge trigger 10 : both rising and falling edge trigger 11 : reserved 3-2 cct0[1:0] capture 0 edge select. cct0[1:0] : 00 : rising edge trigger 01 : falling edge trigger 10 : both rising and falling edge trigger 11 : reserved 1-0 ccld[1:0] reload trigger select. ccld[1:0] : 00 : timer 2 overflow 01 : reload by capture 0 block 10 : reload by capture 1 block 11 : reload by capture 2 block capture control 1 register bit: 7 6 5 4 3 2 1 0 - enf2 enf1 enf0 cptf2 cptf1 cptf0 mnemonic: capcon1 address: a4h bit name function 7-6 reserved 5 enf2 enable filter for capture input 2. 4 enf1 enable filter for capture input 1. 3 enf0 enable filter for capture input 0. 2 cptf2 external capture/reload 2 interrupt flag 1 cptf1 external capture/reload 1 interrupt flag 0 cptf0 external capture/reload 0 interrupt flag
preliminary W79E834 data sheet - 26 - input capture 2 low register mnemonic: ccl2 address: a6h bit name function 7-0 ccl2[7:0] capture 2 low byte input capture 2 high register mnemonic: cch2 address: a7h bit name function 7-0 cch2[7:0] capture 2 high byte interrupt enable bit: 7 6 5 4 3 2 1 0 ea eadc ebo es et1 ex1 et0 ex0 mnemonic: ie address: a8h bit name function 7 ea global enable. enable/disable all interrupts. 6 eadc enable adc interrupt. 5 ebo enable brown out interrupt. 4 es enable serial port 0 interrupt. 3 et1 enable timer 1 interrupt. 2 ex1 enable external interrupt 1. 1 et0 enable timer 0 interrupt. 0 ex0 enable external interrupt 0. slave address bit: 7 6 5 4 3 2 1 0 saddr. 7 saddr. 6 saddr. 5 saddr. 4 saddr. 3 saddr. 2 saddr. 1 saddr. 0 mnemonic: saddr address: a9h bit name function 7 saddr the saddr should be programmed to the given or broadcast address for serial port 0 to which the slave processor is designated.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 27 - revision a13 port 3 bit: 7 6 5 4 3 2 1 0 - - - - - - p3.1 p3.0 mnemonic: p3 address: b0h p3.1-0: general purpose input/output port. most instru ctions will read the port pins in case of a port read access, however in case of read-modify-write in structions, the port latch is read. these alternate functions are described below: bit name function 7:2 - reserved. 1 p3.1 x1 or i/o pin by alternative 0 p3.0 x2 or clkout or i/o pin by alternative. port 0 output mode 1 bit: 7 6 5 4 3 2 1 0 p0m1.7 p0m1.6 p0m1.5 p0m1 .4 p0m1.3 p0m1.2 p0m1.1 p0m1.0 mnemonic: p0m1 address: b1h port 0 output mode 2 bit: 7 6 5 4 3 2 1 0 p0m2.7 p0m2.6 p0m2.5 p0m2 .4 p0m2.3 p0m2.2 p0m2.1 p0m2.0 mnemonic: p0m2 address: b2h port 1 output mode 1 bit: 7 6 5 4 3 2 1 0 p1m1.7 p1m1.6 - p1m1.4 p1m1.31 p1m1.2 p1m1.1 p1m1.0 mnemonic: p1m1 address: b3h port 1 output mode 2 bit: 7 6 5 4 3 2 1 0 p1m2.7 p1m2.6 - p1m2.4 p1m2.3 p1m2.2 p1m2.1 p1m2.0 mnemonic: p1m2 address: b4h port 2 output mode 1 bit: 7 6 5 4 3 2 1 0 p2m1.7 p2m1.6 p2m1.5 p2m1 .4 p2m1.3 p2m1.2 p1m1.1 p1m1.0 mnemonic: p2m1 address: b5h
preliminary W79E834 data sheet - 28 - port 2 output mode 2 bit: 7 6 5 4 3 2 1 0 p2m2.7 p2m2.6 p2m2.5 p2m2 .4 p2m2.3 p2m2.2 p2m2.1 p2m2.0 mnemonic: p2m2 address: b6h port output configuration settings: p2m1.y p2m2.y port input/output mode 0 0 quasi-bidirectional 0 1 push-pull 1 0 input only (high impedance) 1 1 open drain interrupt high priority bit: 7 6 5 4 3 2 1 0 - padch pboh psh pt1h px1h pt0h px0h mnemonic: ip0h address: b7h bit name function 7 - this bit is un-implemented and will read high. 6 padch 1: to set interrupt high priority of adc is highest priority level. 5 pboh 1: to set interrupt high priority of br own out detector is highest priority level. 4 psh 1: to set interrupt high priority of serial port 0 is highest priority level. 3 pt1h 1: ro set interrupt high priority of timer 1 is highest priority level. 2 px1h 1: to set interrupt high priority of ex ternal interrupt 1 is highest priority level. 1 pt0h 1: to set interrupt high priority of timer 0 is highest priority level. 0 px0h 1: to set interrupt high priority of ex ternal interrupt 0 is highest priority level. interrupt priority0 bit: 7 6 5 4 3 2 1 0 - padc pbo ps pt1 px1 pt0 px0 mnemonic: ip0 address: b8h bit name function 7 - this bit is un-implemented and will read high. 6 padc 1: to set interrupt priority of adc is higher priority level. 5 pbo 1: to set interrupt priority of brow n out detector is higher priority level. 4 ps 1: to set interrupt priority of se rial port 0 is higher priority level. 3 pt1 1: to set interrupt priority of timer 1 is higher priority level. 2 px1 1: to set interrupt priority of exte rnal interrupt 1 is higher priority level. 1 pt0 1: to set interrupt priority of timer 0 is higher priority level. 0 px0 1: to set interrupt priority of exte rnal interrupt 0 is higher priority level.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 29 - revision a13 slave address mask enable bit: 7 6 5 4 3 2 1 0 mnemonic: saden address: b9h bit name function 7~0 saden this register enables the automatic address recognition feature of the serial port 0. when a bit in the saden is set to 1, the same bit location in saddr will be compared with the incoming serial data. when saden is 0, then the bit becomes a "don't care" in the comparison. this register enables the automatic address recognition feature o f the serial port 0. when all the bits of saden are 0, interrupt will occur for any incoming address. timed access bit: 7 6 5 4 3 2 1 0 ta.7 ta.6 ta.5 ta.4 ta.3 ta.2 ta.1 ta.0 mnemonic: ta address: c7h bit name function 7~0 ta the timed access register: the timed access register cont rols the access to protected bits. to access protected bits, the user must first write aah to the ta. this must be immediately followed by a write of 55h to ta. now a window is opened in the protected bits for three machine cycles, during which the user can write to these bits. timer 2 control bit: 7 6 5 4 3 2 1 0 tf2 - - - - tr2 - 2 rl cp / mnemonic: t2con address: c8h bit name function 7 tf2 timer 2 overflow flag. this bit is set when timer 2 overflows. it is also set when the count is equal to the capture register in compare mode. it is cleared only by software. software can also set this bit. 6~3 - reserved 2 tr2 timer 2 run control. this bit enables/disables the operation of timer 2. halting this will preserve the current count in th2, tl2. 1 - reserved
preliminary W79E834 data sheet - 30 - 0 2 rl cp / capture/reload select. this bit determines whether the compare or reload function will be used for timer 2. if the bit is 0 then auto reload will occur when timer 2 overflows. and reload will be from rcap regist er if enld = 1, else the timer 2 will be reloaded with 0. if this bit is 1, when time r 2 value matches rcap value, timer 2 will reset to 0. timer 2 mode control bit: 7 6 5 4 3 2 1 0 enld icen2 icen1 icen0 t2cr - - - mnemonic: t2mod address: c9h bit name function 7 enld enable reload from rcap2 registers to timer 2 counters. 6 icen2 capture 2 external enable. this bit enables the capture/reload function on the t2 pin. a n edge trigger (programmable by capcon0. cct2[1:0] bits) detected on the t2 pin will result in capture from free running time r 2 counters to input capture 2 registers, and reload from rcap2 registers to timer 2 counters if enld = 1 and cmp/rl2 = 0. 5 icen1 capture 1 external enable. this bit enables the capture/reload function on the t1 pin. an edge trigger (programmable by capcon0. cct1[1:0] bits) detected on the t1 pin will result in capture from free running time r 2 counters to input capture 1 registers, and reload from rcap2 registers to timer 2 counters if enld = 1 and cmp/rl2 = 0. 4 icen0 capture 0 external enable. this bit enables the capture/reload function on the t0 pin. a n edge trigger (programmable by capcon0. cct0[1:0] bits) detected on the t0 pin will result in capture from free running time r 2 counters to input capture 0 registers, or and reload from rcap2 registers to timer 2 counters if enld = 1 and cmp/rl2 = 0. 3 t2cr timer 2 capture reset. in the timer 2 capture mode this bit enables/disables hardware automatically reset timer 2 while the value in tl2 and th2 have been transferred into the capture register. 2~0 - reserved timer 2 reload lsb bit: 7 6 5 4 3 2 1 0 rcap2l. 7 rcap2l. 6 rcap2l. 5 rcap2l. 4 rcap2l. 3 rcap2l. 2 rcap2l. 1 rcap2l. 0 mnemonic: rcap2l address: cah rcap2l timer 2 reload lsb: this register is lsb of a 16-bit reload value when timer 2 is configured in reload mode. during compare mode, this register is a compare register. see cmp/rl2 for reload/compare mode. timer 2 reload msb bit: 7 6 5 4 3 2 1 0 rcap2h .7 rcap2h .6 rcap2h .5 rcap2h .4 rcap2h .3 rcap2h .2 rcap2h .1 rcap2h .0
preliminary W79E834 data sheet publication release date: october 12, 2006 - 31 - revision a13 mnemonic: rcap2h address: cbh rcap2h timer 2 reload msb: this register is msb of a 16-bit reload value when timer 2 is configured in reload mode. during compare mode, this register is a compare register. see cmp/rl2 for reload/compare mode. timer 2 lsb bit: 7 6 5 4 3 2 1 0 tl2.7 tl2.6 tl2.5 tl2.4 tl2.3 tl2.2 tl2.1 tl2.0 mnemonic: tl2 address: cch tl2 timer 2 lsb timer 2 msb bit: 7 6 5 4 3 2 1 0 th2.7 th2.6 th2.5 th2.4 th2.3 th2.2 th2.1 th2.0 mnemonic: th2 address: cdh th2 timer 2 msb program status word bit: 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p mnemonic: psw address: d0h bit name function 7 cy carry flag: set for an arithmetic operation which result s in a carry being generated from the alu. it is also used as the accumulator for the bit operations. 6 ac auxiliary carry: set when the previous operation resulted in a carry from the high order nibble. 5 f0 user flag 0: the general purpose flag that can be set or cleared by the user. 4 rs1 register bank select bits: 3 rs0 register bank select bits: 2 ov overflow flag: set when a carry was generated from the sev enth bit but not from the 8th bit as a result of the previous operation, or vice-versa. 1 f1 user flag 1: the general purpose flag that can be set or cleared by the user by software. 0 p parity flag: set/cleared by hardware to indicate odd/ev en number of 1's in the accumulator.
preliminary W79E834 data sheet - 32 - rs.1-0: register bank select bits: rs1 rs0 register bank address 0 0 0 00-07h 0 1 1 08-0fh 1 0 2 10-17h 1 1 3 18-1fh pwm counter high bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwmp.9 pwmp.8 mnemonic: pwmph address: d1h bit name function 7~2 - reserved 1~0 pwmp.9 ~ pwmp.8 the pwm counter register bit9~8. pwm 0 high bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwm0.9 pwm0.8 mnemonic: pwm0h address: d2h bit name function 7~2 - reserved 1~0 pwm0.9 ~ pwm0.8 the pwm 0 register bit 9~8. pwm 1 high bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwm1.9 pwm1.8 mnemonic: pwm1h address: d3h bit name function 7~2 - reserved 1~0 pwm1.9 ~ pwm1.8 the pwm1 register bit 9~8.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 33 - revision a13 pwm 2 high bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwm2.9 pwm2.8 mnemonic: pwm2h address: d5h bit name function 7~2 - reserved 1~0 pwm2.9 ~ pwm2.8 the pwm2 register bit 9~8. pwm 3 high bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwm3.9 pwm3.8 mnemonic: pwm3h address: d6h bit name function 7~2 - reserved 1~0 pwm3.9 ~ pwm3.8 the pwm3 register bit 9~8. pwm control register 3 bit: 7 6 5 4 3 2 1 0 pwm3oe pwm2oe pwm1oe pwm0oe - - - - mnemonic: pwmcon3 address: d7h bit name function 7 pwm3oe pwm3 output enable bit. 0: pwm3 output disabled. 1: pwm3 output enabled. 6 pwm2oe pwm2 output enable bit. 0: pwm2 output disabled. 1: pwm2 output enabled. 5 pwm1oe pwm1 output enable bit. 0: pwm1 output disabled. 1: pwm1 output enabled. 4 pwm0oe pwm0 output enable bit. 0: pwm0 output disabled. 1: pwm0 output enabled. 3~0 - reserved
preliminary W79E834 data sheet - 34 - watchdog control bit: 7 6 5 4 3 2 1 0 wdrun - wd1 wd0 wdif wtrf ewrst wdclr mnemonic: wdcon address: d8h bit name function 7 wdrun 0: the watchdog is stopped 1: the watchdog is running. 6 - reserved. 5 wd1 watchdog timer times selected. 4 wd0 watchdog timer times selected. 3 wdif watchdog timer interrupt flag 0: if the interrupt is not enabled, then this bit indicates that the time-out period has elapsed. this bit must be cleared by software. 1: if the watchdog interrupt is enabled, hardware will set this bit to indicate that the watchdog interrupt has occurred. 2 wtrf watchdog timer reset flag 1: hardware will set this bit when the watchdog timer causes a reset. software can read it but must clear it manually. a power-f ail reset will also clear the bit. this bit helps software in determining the cause of a reset. if ewrst = 0, the watchdog timer will have no affect on this bit. 1 ewrst 0: disable watchdog timer reset. 1: enable watchdog timer reset. 0 wdclr reset watchdog timer this bit helps in putting the watchdog timer into a know state. it also helps in resetting the watchdog timer before a time-out occurs. failing to set the ewrst before time-out will cause an interrupt (if ewdi (ie.4) is set), and 512 clocks after that a watchdog timer reset will be generated (i f ewrst is set). this bit is self- clearing by hardware. the wdcon sfr is set to a 0x000000b on a reset. wtrf (wdcon.2) is set to a 1 on a watchdog timer reset, but to a 0 on power on/down resets. wt rf (wdcon.2) is not altered by an external reset. ewrst (wdcon.1) is set to 0 on all resets. all the bits in this sfr have unrestricted r ead access. ewrst, wdif and wdclr require timed access procedure to write. the remaining bits hav e unrestricted write accesses. please refer ta register description. ta reg c7h wdcon reg d8h mov ta, #aah
preliminary W79E834 data sheet publication release date: october 12, 2006 - 35 - revision a13 mov ta, #55h setb wdcon.0 ; reset watchdog timer orl wdcon, #00110000b ; select 26 bits watchdog timer mov ta, #aah mov ta, #55h orl wdcon, #00000010b ; enable watchdog pwm counter low bits register bit: 7 6 5 4 3 2 1 0 pwmp.7 pwmp.6 pwmp.5 pwmp .4 pwmp.3 pwmp.2 pwmp.1 pwmp.0 mnemonic: pwmpl address: d9h bit name function 7~0 pwmp.7 ~ pwmp.0 pwm counter low bits register. pwm 0 low bits register bit: 7 6 5 4 3 2 1 0 pwm0.7 pwm0.6 pwm0.5 pwm0 .4 pwm0.3 pwm0.2 pwm0.1 pwm0.0 mnemonic: pwm0l address: dah bit name function 7~0 pwm0.7 ~ pwm0.0 pwm 0 low bits register. pwm 1 low bits register bit: 7 6 5 4 3 2 1 0 pwm1.7 pwm1.6 pwm1.5 pwm1 .4 pwm1.3 pwm1.2 pwm1.1 pwm1.0 mnemonic: pwm1l address: dbh bit name function 7~0 pwm1.7 ~ pwm1.0 pwm 1 low bits register. pwm control register 1 bit: 7 6 5 4 3 2 1 0 pwmrun load pwmf clrpwm pwm3i pwm2i pwm1i pwm0i mnemonic: pwmcon1 address: dch
preliminary W79E834 data sheet - 36 - bit name function 7 pwmrun 0: the pwm is not running. 1: the pwm counter is running. 6 load 0: the registers value of pwmp and co mparators are never loaded to counter and comparator registers. 1: the pwmp register will be load value to counter register after counter underflow, and hardware will clear by next clock cycle. 5 pwmf pwm underflow flag. 0: no underflow. 1: pwm 10-bit down counter underflows (p wm interrupt is requested if pwm interrupt is enabled). 4 clrpwm 1: clear 10-bit pwm counter to 000h. 3 pwm3i 0: pwm3 output is non-inverted. 1: pwm3 output is inverted. 2 pwm2i 0: pwm2 output is non-inverted. 1: pwm2 output is inverted. 1 pwm1i 0: pwm1 output is non-inverted. 1: pwm1 output is inverted. 0 pwm0i 0: pwm0 output is non-inverted. 1: pwm0 output is inverted. pwm 2 low bits register bit: 7 6 5 4 3 2 1 0 pwm2.7 pwm2.6 pwm2.5 pwm2 .4 pwm2.3 pwm2.2 pwm2.1 pwm2.0 mnemonic: pwm2l address: ddh bit name function 7:0 pwm2.7 ~ pwm2.0 pwm 2 low bits register. pwm 3 low bits register bit: 7 6 5 4 3 2 1 0 pwm3.7 pwm3.6 pwm3.5 pwm3 .4 pwm3.3 pwm3.2 pwm3.1 pwm3.0 mnemonic: pwm3l address: deh bit name function 7~0 pwm3.7 ~ pwm3.0 pwm 3 low bits register.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 37 - revision a13 accumulator bit: 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 acc. 4 acc.3 acc.2 acc.1 acc.0 mnemonic: acc address: e0h acc.7-0: the a (or acc) register is the standard 8052 accumulator. adc control register bit: 7 6 5 4 3 2 1 0 adc.1 adc.0 adcex a dci adcs aadr2 aadr1 aadr0 mnemonic: adccon address: e1h bit name function 7 adc.1 the adc conversion result. 6 adc.0 the adc conversion result. 5 adcex 0: disable external start of conversion by p1.4. 1: enable external start of conversion by p1.4. the stadc signal al least 1 machine cycle. 4 adci 0: the adc is not busy. 1: the adc conversion result is ready to be read. an interrupt is invoked if it is enabled. it cannot be set by software. 3 adcs 0: the adc is converted. 1: the adc is converting. clear by hardware after adc is converted. 2 aadr2 the adc input select. 1 aadr1 the adc input select. 0 aadr0 the adc input select. adci adcs adc status 0 0 adc not busy; a conversion can be started. 0 1 adc busy; start of a new conversion is blocked 1 0 conversion completed; start of a new conversion requires adci = 0 1 1 conversion completed; start of a new conversion requires adci = 0 if adc is cleared by software while adcs is set at the same time, a new a/d conversion with the same channel number may be started. but it is reco mmended to reset adci before adcs is set. the adc channel selection table: aadr2 aadr1 aadr0 selected analog channel 0 0 0 adc0 0 0 1 adc1 0 1 0 adc2
preliminary W79E834 data sheet - 38 - 0 1 1 adc3 1 0 0 adc4 1 0 1 adc5 1 1 0 adc6 1 1 1 adc7 note: the aadr(n) bits can only be changed when adci and adcs are both zero. adc converter result register bit: 7 6 5 4 3 2 1 0 adc.9 adc.8 adc.7 adc. 6 adc.5 adc.4 adc.3 adc.2 mnemonic: adch address: e2h bit name function 7~0 adc.9 ~adc.2 the adc conversion result. input capture 0 low register mnemonic: ccl0 address: e4h bit name function 7~0 ccl0[7:0] capture 0 low byte input capture 0 high register mnemonic: cch0 address: e5h bit name function 7~0 cch0[7:0] capture 0 high byte input capture 1 low register mnemonic: ccl1 address: e6h bit name function 7~0 ccl1[7:0] capture 1 low byte input capture 1 high register mnemonic: cch1 address: e7h bit name function 7~0 cch1[7:0] capture 1 high byte
preliminary W79E834 data sheet publication release date: october 12, 2006 - 39 - revision a13 interrupt enable register 1 bit: 7 6 5 4 3 2 1 0 ecptf et2 epwm ewdi espi - ekb - mnemonic: ie1 address: e8h bit name function 7 ecptf 0: disable capture interrupts. 1: enable capture interrupts. 6 et2 0: disable timer 2 interrupt. 1: enable timer 2 interrupt. 5 epwm 0: disable pwm interrupt w hen pwm down counter underflow. 1: enable pwm interrupt w hen pwm down counter underflow. 4 ewdi 0: disable watchdog timer interrupt. 1: enable watchdog timer interrupt. 3 espi 0: disable spi interrupt. 1: enable spi interrupt. 2 - reserved. 1 ekb 0: disable keypad interrupt. 1: enable keypad interrupt. 0 - reserved. b register bit: 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 mnemonic: b address: f0h b.7-0: the b register is the standard 8052 regist er that serves as a second accumulator. serial peripheral control register bit: 7 6 5 4 3 2 1 0 ssoe spe lsbfe mstr cpol cpha spr1 spr0 mnemonic: spcr address: f3h
preliminary W79E834 data sheet - 40 - serial peripheral control register (spcr) bit name function 7 ssoe slave select output enable bit. the ss output feature is enabled only in mast er mode by asserting the ssoe bit. ss input not effected by ssoe when the device in slave mode. 0: ss input (with mode fault) 1: ss output (no mode fault) drss ssoe master mode slave mode 0 0 ss input ( with mode fault ) ss input ( not affected by ssoe ) 0 1 reserved ss input ( not affected by ssoe ) 1 0 ss general purpose i/o ( no mode fault ) ss input ( not affected by ssoe ) 1 1 ss output ( no mode fault ) ss input ( not affected by ssoe ) 6 spe serial peripheral system enable bit: when the spe bit is set, spi block func tions is enable. when modf is set, spe always reads 0. 0: spi system disabled. 1: spi system enabled. 5 lsbfe lsb - first enable: this bit does not affect the position of the msb and lsb in the data register. reads and writes of the data register always hav e the msb in bit 7. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0: data is transferred least significant bit first. 1: data is transferred most significant bit first. 4 mstr master mode select bit: it is customary to have an external pull-up resistor on lines that are driven by open- drain devices 0: slave mode. 1: master mode 3 cpol clock polarity bit: when the clock polarity bit is cleared and data is not being transferred, the sck pin of the master device has a steady state low va lue. when cpol is set, sck idles high.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 41 - revision a13 2 cpha clock phase bit: the clock phase bit, in conjunction with the cpol bit, controls the clock-data relationship between master and slave. the cpha bit selects one of two different clocking protocols. 1 spr1 spi baud rate selection bits 1: these bits specify the spi baud rates. 0 spr0 spi baud rate selection bits 0: these bits specify the spi baud rates. note: in master mode, a change of lsbfe, mstr, cpol, cpha and spr [1:0] will abort a transmission in progress and force the spi system into idle state. serial peripheral status register bit: 7 6 5 4 3 2 1 0 spif wcol spovf modf drss - - - mnemonic: spsr address: f4h bit name function 7 spif spi interrupt complete flag: spif is set upon completion of data transfe r between this device and external device or when new data has been received and copi ed to the spdr. if spif goes high, and if espi (located at ie1.3) is set, a serial peripheral interrupt is generated. spif is clear by software, by writing a 0. 6 wcol write collision bit: clearing the wcol bit is accomplished by software writing a 0. 0: no write collision. 1: write collision. 5 spovf spi overrun flag: spiovf is set if a new character is receiv ed before a previously received character is read from spdr. once this bit is set, it w ill prevent spdr register from accepting new data. it must be cleared before any new data can be written. this flag is cleared by software, by writing a 0. 0: no overrun. 1: overrun detected. 4 modf spi mode error interrupt status flag: clearing this bit is by software writing a 0. 0: no mode fault. 1: mode fault. 3 drss data register slave select: refer to above table in spcr register. 2~0 - reserved.
preliminary W79E834 data sheet - 42 - serial peripheral data i/o register bit: 7 6 5 4 3 2 1 0 spd.7 spd.6 spd.5 spd.4 spd.3 spd.2 spd.1 spd.0 mnemonic: spdr address: f5h spd[7:0] spdr is used when transmi tting or receiving data on serial bus. port adc digital input disable bit: 7 6 5 4 3 2 1 0 padids. 7 padids. 6 padids. 5 padids. 4 padids. 3 padids. 2 padids. 1 padids. 0 mnemonic: padids address: f6h bit name function 7 padids.7 p2.7 digital input disable bit. 0: default (with digital/analog input). 1: disable digital input of adc input channel 7. 6 padids.6 p2.6 digital input disable bit. 0: default (with digital/analog input). 1: disable digital input of adc input channel 6. 5 padids.5 p0.6 digital input disable bit. 0: default (with digital/analog input). 1: disable digital input of adc input channel 5. 4 padids.4 p0.5 digital input disable bit. 0: default (with digital/analog input). 1: disable digital input of adc input channel 4. 3 padids.3 p0.4 digital input disable bit. 0: default (with digital/analog input). 1: disable digital input of adc input channel 3. 2 padids.2 p0.3 digital input disable bit. 0: default (with digital/analog input). 1: disable digital input of adc input channel 2. 1 padids.1 p0.2 digital input disable bit. 0: default (with digital/analog input). 1: disable digital input of adc input channel 1. 0 padids.0 p0.1 digital input disable bit. 0: default (with digital/analog input). 1: disable digital input of adc input channel 0.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 43 - revision a13 interrupt high priority 1 bit: 7 6 5 4 3 2 1 0 pcaph pt2h ppwmh pwdih pspih - pkbh - mnemonic: ip1h address: f7h bit name function 7 pcaph 1: to set interrupt high priority of c apture 0/1/2 as highest priority level. 6 pt2h 1: to set interrupt high priority of timer 2 is highest priority level. 5 ppwmh 1: to set interrupt high priority of pw m?s underflow is highest priority level. 4 pwdih 1: to set interrupt high priority of watchdog is highest priority level. 3 pspih 1: to set interrupt high priority of spi is highest priority level. 2 - reserved. 1 pkbh 1: to set interrupt high priority of keypad is highest priority level. 0 - reserved. interrupt priority 1 bit: 7 6 5 4 3 2 1 0 pcap pt2 ppwm pwdi pspi - pkb - mnemonic: ip1 address: f8h bit name function 7 pcap 1: to set interrupt priority of capt ure 0/1/2 as higher priority level. 6 pt2 1: to set interrupt priority of timer 2 is higher priority level. 5 ppwm 1: to set interrupt priority of pwm? s underflow is higher priority level. 4 pwdi 1: to set interrupt priority of watchdog is higher priority level. 3 pspi 1: to set interrupt priority of spi is higher priority level. 2 - reserved. 1 pkb 1: to set interrupt priority of keypad is higher priority level. 0 - reserved.
preliminary W79E834 data sheet - 44 - 8. instruction W79E834 executes all the inst ructions of the standard 8052 fa mily. the operation of these instructions, their effect on the fl ag bits and the status bits is exac tly the same. however, timing of these instructions is different. the reason for this is two fold. firstly, each machine cycle consists of 4 clock periods, while in the standard 8052 it consists of 12 clock periods. also, there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard 8052 there can be two fetches per machine cycle, which works out to 6 clocks per fetch. the advantage it has is that since there is only one fetch per machine cycle, the number of machine cycles in most cases is equal to the number of oper ands that the instruction has. in case of jumps and calls there will be an additional cycle that will be needed to calculate the new address. but overall it reduces the number of dummy fetches and wasted cy cles, thereby improving efficiency as compared to the standard 8052. table: instructions affect flag setting instruction carry overflow auxiliary carry instruction carry overflow auxiliary carry add x x x clr c 0 addc x x x cpl c x subb x x x anl c, bit x mul 0 x anl c, bit x div 0 x orl c, bit x da a x orl c, bit x rrc a x mov c, bit x rlc a x cjne x setb c 1 an "x" indicates that the modification is as per the result of instruction. 8.1 instruction timing the instruction timing for W79E834 is an important as pect, especially for those users who wish to use software instructions to generate timing delays. also, it provides the user with an insight into the timing differences between W79E834 and the standard 8052. in W79E834, each machine cycle is four clock periods long. each clock period is designated a stat e. thus each machine cycle is made up of four states, c1, c2 c3 and c4, in that order. due to t he reduced time for each inst ruction execution, both the clock edges are used for internal timing. hence it is important that the duty cycle of the clock be as close to 50% as possible to avoid timing conf licts. as mentioned earlier, W79E834 does one op-code fetch per machine cycle. therefore, in most of the instru ctions, the number of machine cycl es needed to execute the instruction is equal to the number of bytes in the instructi on. of the 256 available op-codes, 128 of them are single cycle instructions. thus more than half of all op-codes in the W79E834 are executed in just four clock periods. most of the two-cy cle instructions are those that have two byte instruction codes. however there are some instructions that have onl y one byte instructions, yet they are two cycle instructions. one instruction which is of importanc e is the movx instruction. in the standard 8052, the movx instruction is always two machine cycles l ong. however, in W79E834, each machine cycle is made of only 4 clock periods compared to the 12 cl ock periods for the standar d 8052. therefore, even though the number of categories has increased, each inst ruction is at least 1.5 to 3 times faster than the standard 8052 in terms of clock periods.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 45 - revision a13 single cycle c4 c3 c2 c1 cpu clk ale psen ad<7:0> address <15:0> a7-0 address a15-8 data_ in d7-0 single cycle instruction timing instruction fetch c4 c3 c2 c1 op-code address a15-8 address a15-8 ale psen pc ad<7:0> a ddress<15:0> cpu clk operand fetch c4 c3 c2 c1 operand pc+1 two cycle instruction timing
preliminary W79E834 data sheet - 46 - operand operand a7-0 a7-0 a7-0 op-code address a15-8 address a15-8 address a15-8 operand fetch operand fetch instruction fetch c2 c3 c4 c2 c3 c4 c4 c3 c2 c1 c1 c1 cpu clk ale psen ad<7:0> a ddress<15:0> three cycle instruction timing operand operand operand op-code address a15-8 address a15-8 address a15-8 address a15-8 a7-0 a7-0 a7-0 a7-0 operand fetch operand fetch operand fetch instruction fetch c2 c1 c4 c3 c2 c1 cpu clk ale psen ad<7:0> a ddress<15:0> c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 four cycle instruction timing
preliminary W79E834 data sheet publication release date: october 12, 2006 - 47 - revision a13 operand operand operand op-code address a15-8 address a15-8 address a15-8 address a15-8 a7-0 a7-0 a7-0 a7-0 operand fetch operand fetch operand fetch operand fetch instruction fetch c2 c1 c4 c3 c2 c1 cpu clk ale psen ad<7:0> a ddress<15:0> c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 operand a7-0 address a15-8 five cycle instruction timing
preliminary W79E834 data sheet - 48 - 9. power management W79E834 is provided with idle mode and power-dow n mode to control power consumption. these modes are discussed in the next two secti ons, followed by a discussion of resets. 9.1 idle mode the user can put the device into idle mode by writing 1 to the bit pcon.0. the instruction that sets the idle bit is the last instruction that will be execut ed before the device goes into idle mode. in the idle mode, the clock to the cpu is hal ted, but not to the interrupt, timer, watchdog timer and serial port blocks. this forces the cpu state to be frozen; t he program counter, the stack pointer, the program status word, the accumulator and the other regist ers hold their contents. the port pins hold the logical states they had at the time idle was acti vated. the idle mode can be terminated in two ways. since the interrupt controller is still active, the activation of any enabled interrupt can wake up the processor. this will automatically clear the idle bi t, terminate the idle mode, and the interrupt service routine (isr) will be executed. a fter the isr, execution of the program will continue from the instruction which put the device into idle mode. the idle mode can also be exited by activating the reset. the device can put into reset either by applying a low on the external rst pin, a power on reset condition or a watchdog timer reset. the external reset pin has to be held high for at leas t two machine cycles i.e. 8 clock periods to be recognized as a valid reset. in the reset conditi on the program counter is reset to 0000h and all the sfrs are set to the reset condition. since the clo ck is already running there is no delay and execution starts immediately. in the idle mode, the watchdog timer continues to run, and if enabled, a time-out will cause a watchdog timer interrupt which will wa ke up the device. the software must reset the watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out. when W79E834 is exiting from an idle mode with a reset, the instruction following the one which put the device into idle mode is not executed. so there is no danger of unexpected writes. 9.2 power down mode the device can be put into power down mode by writ ing 1 to bit pcon.1. the instruction that does this will be the last instruction to be executed bef ore the device goes into power down mode. in the power down mode, all the clocks are stopped and the devic e comes to a halt. all activity is completely stopped and the power consumption is reduced to the lo west possible value. the port pins output the values held by their respective sfrs. W79E834 will exit the power down mode with a reset or by an external interrupt pin enabled as level detected. an external reset can be used to exit t he power down state. the low on rst pin terminates the power down mode, and restarts the clock. the program execution will restart from 0000h. in the power down mode, the clock is stopped, so the wa tchdog timer cannot be used to provide the reset to exit power down mode. W79E834 can be woken from the power down mode by forcing an external interrupt pin activated, provided the corresponding interrupt is enabled, while the global enable(ea) bit is set and the external input has been set to a level detect mode. if thes e conditions are met, then the high level on the external pin re-starts the oscillator. then device executes the interrupt service routine for the corresponding external interrupt. after the interrupt service routine is completed, the program execution returns to the instruction after one which put the device into power down mode and continues from there. during power down mode, if auxr1.lpbov = 1 and auxr1.bod = 0, the internal rc clock will be enabled and hence save power. the other sources that can wake up from the power down mode are keyboard interrupt (kbi), brownout reset (bor), and adc interrupt, and watchdog timer interrupt (if wdte = 0) .
preliminary W79E834 data sheet publication release date: october 12, 2006 - 49 - revision a13 10. reset conditions the user has several hardware related options fo r placing W79E834 into reset condition. in general, most register bits go to their reset value irrespecti ve of the reset condition, but there are a few flags whose state depends on the source of reset. the user can use these flags to determine the cause of reset using software. the sources of resets are external reset, power-on-reset, watchdog timer reset and software reset (brownout is also able to reset the device if enabled). 10.1 external reset the device continuously samples the /rst pin at stat e c4 of every machine cycle. therefore the /rst pin must be held for at least 2 machine cycles to ensure detection of a valid /rst low. the reset circuitry then synchronously applies the internal reset signal. thus the reset is a synchronous operation and requires the clock to be running to cause an external reset. once the device is in reset condition, it will remain so as long as /rst is 0. even after /rst is deactivated, the device will continue to be in rese t state for up to two machine cycles, and then begin program execution from 0000h. there is no flag associ ated with the external reset condition. however since the other two reset sources have flags, the ex ternal reset can be considered as the default reset if those two flags are cleared. 10.2 power-on reset (por) the software must clear the por flag after reading i t. otherwise it will not be possible to correctly determine future reset sources. if the power fails, i.e. falls below vrst, then the device will once again go into reset state. when the power returns to the proper operating levels, the device will again perform a power on reset delay and set the por flag. 10.3 watchdog timer reset the watchdog timer is a free running timer with progra mmable time-out intervals. the user can clear the watchdog timer at any time, causing it to restar t the count. when the time-out interval is reached an interrupt flag is set. if the watchdog reset is enabled and the watchdog timer is not cleared, then 512 clocks from the flag being set, the watchdog time r will generate a reset. this places the device into the reset condition. the reset condition is ma intained by hardware for two machine cycles. once the reset is removed the devic e will begin execution from 0000h. 10.4 s/w reset user can software reset the device by setting srst bit in sfr auxr1. 10.5 reset state most of the sfrs and registers on the device will go to the same condition in the reset state. the program counter is forced to 0000h and is held ther e as long as the reset condition is applied. however, the reset state does not affect the on- chip ram. the data in the ram will be preserved during the reset. however, the stack pointer is re set to 07h, and therefore the stack contents will be lost. the ram contents will be lost if the v dd falls below approximately 2v, as this is the minimum voltage level required for the ram to operate normally. therefore after a first time power on reset the
preliminary W79E834 data sheet - 50 - ram contents will be indeterminate. during a power fa il condition, if the power falls below 2v, the ram contents are lost. after a reset most sfrs are cleared. interrupt s and timers are disabled. the watchdog timer is disabled if the reset source was a por. the sfrs have ffh written into them which puts the port pins in a high state. for sfr reset value, see sfr description table section. the wdcon sfr bits are set or cleared in reset condition depending on the source of the reset. external reset watchdog reset power on reset wdcon 0x00x000b 0x000100b 0x000000b the wtrf bit wdcon.2 is set when the watchdog ti mer causes a reset. a power on reset will also clear this bit. the ewrst bit wdcon.1 is cleared by all resets. this disables the watchdog timer resets.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 51 - revision a13 11. interrupts W79E834 has four priority level interrupts structure with 13 interrupt sources. each of the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. in addition, the interrupts can be globally enabled or disabled. 11.1 interrupt sources the external interrupts int0 and int1 can be either edge triggered or level triggered, programmable through bits it0 and it1 (sfr tcon). the bits ie0 and ie1 in tcon register are the flags which are checked to generate the interrupt. in the edge trigger ed mode, the intx inputs are sampled in every machine cycle. if the sample is high in one cycle and low in the next, then a high to low transition is detected and the interrupts request flag iex in tcon is set. the flag bit requests the interrupt. since the external interrupts are sampled every machine cy cle, they have to be held high or low for at least one complete machine cycle. the iex flag is automat ically cleared when the service routine is called. if the level triggered mode is selected, then the r equesting source has to hold the pin low till the interrupt is serviced. the iex flag will not be cleared by the hardware on entering the service routine. if the interrupt continues to be held low even after the service routine is comple ted, then the processor may acknowledge another interrupt request from the same source. the timer 0 and 1 interrupts are generated by the tf0 and tf1 flags. these flags are set by the overflow in the timer 0 and timer 1. the tf0 and tf1 flags are automatically cleared by the hardware when the timer interrupt is serviced. t he watchdog timer can be used as a system monitor or a simple timer. in either case, when the time -out count is reached, the watchdog timer interrupt flag wdif (wdcon.3) is set. if the interrupt is enabled by the enable bit ie1.4, then an interrupt will occur. the timer 2 interrupt is generated through tf2 (tim er 2 overflow/compare ma tch). the hardware does not clear these flags when a time r 2 interrupt is executed. the capture interrupt is generated through logical or cptf0-2 flags. cptf0-2 flags are set by capture/reload events. the hardw are does not clear these flags when the capture interrupt is executed. software has to resolve the cause of the interrupt among cptf0-2, and clear the appropriate flag. the serial block can generate interrupt on reception or transmission. there are two interrupt sources from the serial block, which are obtained by the ri and ti bits in t he scon sfr. these bits are not automatically cleared by the hardw are, and the user will have to cl ear these bits using software. spi asserts interrupt flag, spif, upon completion of data transfer with an external device. if spi interrupt is enabled (espi at ie1.3), a serial peri pheral interrupt is generated. spif flag is software clear, by writing a 0. modf and spiovf also will generate interrupt if occur. they share the same vector address as spif. keyboard interrupt is generated when any of the ke ypad connected to p0 pins is pressed. each keypad interrupt can be individually enabled or disabl ed. user will have to software clear the flag bit.
preliminary W79E834 data sheet - 52 - pwm interrupt is generated when its? 10-bit down counter underflows. pwmf flag is set and pwm interrupt is generated if enabled. pwmf is set by hardware and can only be cleared by software. the adc can generate interrupt after finished adc conv erter. there is one interrupt source, which is obtained by the adci bit in the a dccon sfr. this bit is not automat ically cleared by the hardware, and the user will have to clear this bit using software. brownout detect can cause brownout flag, bof, to be asserted if power voltage drop below brownout voltage level. interrupt will occur if boi (auxr1 .5), ebo (ie.5) and global interrupt enable are set. W79E834 interrupt vector table source vector address source vector address external interrupt 0 0003h timer 0 overflow 000bh external interrupt 1 0013h timer 1 overflow 001bh serial port 0023h brownout interrupt 002bh - 0033h kbi interrupt 003bh timer 2 overflow 0043h spi interrupt 004bh watchdog timer 0053h adc interrupt 005bh - 0063h capture interrupt 006bh pwm interrupt 0073h - 007bh 11.2 priority level structure there are four priority levels for the interrupts, highest, high, low and lowest. the interrupt sources can be individually set to either high or low leve ls. naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. howeve r there exists a pre-defined hierarchy amongst the interrupts themselves. this hierarchy comes into play when the interrupt controller has to resolve simultaneous requests having the same priority level. this hierarchy is defined as shown on table. the interrupt flags are sampled every machine cy cle. in the same machine cycle, the sampled interrupts are polled and their priority is resolved. if certain conditions are met then the hardware will execute an internally generated lca ll instruction which will vector the process to the appropriate interrupt vector address. the condi tions for generating the lcall are; 1. an interrupt of equal or higher prio rity is not currently being serviced. 2. the current polling cycle is the last machine cycle of the instruction currently being execute. 3. the current instruction does not involve a write to ie, ie1, ip0, ip0h, ip1 or iph1 registers and is not a reti.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 53 - revision a13 if any of these conditions are not met, then the lcall will not be generated. the polling cycle is repeated every machine cycle, with the interrupts sampled in the same machine cycle. if an interrupt flag is active in one cycle but not responded to, and is not active when the above conditions are met, the denied interrupt will not be serviced. this means that active interrupts are not remembered; every polling cycle is new. the processor responds to a valid interrupt by executing an lcall instruction to the appropriate service routine. this may or may not clear the flag which caused the interrupt. in case of timer interrupts, the tf0 or tf1 flags are cleared by hardware whenever the processor vectors to the appropriate timer service routine. in case of exte rnal interrupt, /int0 and /int1, the flags are cleared only if they are edge triggered. in case of serial in terrupts, the flags are not cleared by hardware. in the case of timer 2 interrupt, the flags are not cleared by hardware. the watchdog timer interrupt flag wdif has to be cleared by software. the hardwar e lcall behaves exactly like the software lcall instruction. this instruction saves the program c ounter contents onto the sta ck, but does not save the program status word psw. the pc is reloaded with the vector address of that interrupt which caused the lcall. these address of vector for the different sources are as shown on table tbd. the vector table is not evenly spaced; this is to acco mmodate future expansions to the device family. execution continues from the vect ored address till an reti instruction is executed. on execution of the reti instruction the processor pops the stack and loads the pc with the contents at the top of the stack. the user must take care that the status of t he stack is restored to what it was after the hardware lcall, if the execution is to return to the interrupted program. the processor does not notice anything if the stack cont ents are modified and will proceed with execution from the address put back into pc. note that a ret instruction woul d perform exactly the same process as a reti instruction, but it would not inform the interrupt controller that the inte rrupt service routine is completed, and would leave the controller still th inking that the service routine is underway. W79E834 uses a four priority level interrupt structur e. this allows great flexibility in controlling the handling of the interrupt sources. table: four-level interrupts priority priority bits ipxh ipx interrupt priority level 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) each interrupt source can be individually enabled or di sabled by setting or clearing a bit in registers ie or ie1. the ie register also contains a global dis able bit, ea, which disables all interrupts at once. each interrupt source can be individually programm ed to one of four priority levels by setting or clearing bits in the ip0, ip0h, ip1, and ip1h regist ers. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the
preliminary W79E834 data sheet - 54 - highest priority interrupt service cannot be interr upted by any other interrupt source. so, if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. this is called the arbitration rank ing. note that the arbitration ranking is only used to resolve simultaneous requests of the same priority level. table below summarizes the interrupt sources, flag bits, vector address, enable bits, priority bits, arbitration ranking, and whether each interrupt may wake up the cpu from power down mode. table: summary of interrupt sources source flag vector address enable bit flag cleared by priority bit arbitration ranking power- down wakeup external interrupt 0 ie0 0003h ex0 (ie.0) hardware, software ip0h.0, ip0.0 1(highest) yes brownout detect bof 002bh ebo (ie.5) hardware ip0h.5, ip0.5 2 yes watchdog timer wdif 0053h ewdi (ie1.4) software ip1h.4, ip1.4 3 yes timer 0 overflow tf0 000bh et0 (ie.1) hardware, software ip0h.1, ip0.1 4 no spi spif + modf + spiovf 004bh espi (ie1.3) software ip1h.3, ip1.3 5 no a/d converter adci 005bh eadc (ie.6) software ip0h.6, ip0.6 6 yes external interrupt 1 ie1 0013h ex1 (ie.2) hardware, software ip0h.2, ip0.2 7 yes kbi kbf 003bh ekb (ie1.1) software ip1h.1, ip1.1 8 yes timer 1 overflow tf1 001bh et1 (ie.3) hardware, software ip0h.3, ip0.3 9 no serial port ri + ti 0023h es (ie.4) software ip0h.4, ip0.4 10 no timer 2 overflow/match tf2 0043h et2 (ie1.6) software ip1h.6, ip1.6 11 no capture cptf0-2 006bh ecptf (ie1.7) software ip1h.7, ip1.7 12 no pwm pwmf 0073h epwm (ie1.5) software ip1h.5, ip1.5 13 (lowest) no note: 1. the watchdog timer and adc converter can wake up powe r down mode when its clock source is used internal rc.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 55 - revision a13 11.3 interrupt response time the response time for each interrupt source depends on several factors, such as the nature of the interrupt and the instruction underway. in the case of external interrupts int0 to ri+ti, they are sampled at c3 of every machine cycle and then t heir corresponding interrupt flags iex will be set or reset. the timer 0 and 1 overflow flags are set at c3 of the machine cycle in which overflow has occurred. these flag values are polled only in the next machine cycle. if a request is active and all three conditions are met, then the hardware generated lcall is executed. this lcall itself takes four machine cycles to be completed. thus there is a minimum time of five machine cycles between the interrupt flag being set and the inte rrupt service routine being executed. a longer response time should be anticipated if any of the three conditions are not met. if a higher or equal priority is being serviced, t hen the interrupt latency time obv iously depends on the nature of the service routine currently being exec uted. if the polling cycle is not the last machine cycle of the instruction being executed, then an additional delay is introduced. the maximum response time (if no other interrupt is in service) occurs if the device is performing a write to ie, ie1, ip0, ip0h, ip1 or ip1h and then executes a mul or div inst ruction. from the time an interr upt source is activated, the longest reaction time is 12 machine cycles. this in cludes 1 machine cycle to detect the interrupt, 2 machine cycles to complete the ie, ie1, ip0, ip0h, ip1 or ip1h access, 5 machine cycles to complete the mul or div instruction and 4 machine cycles to complete the hardware lcall to the interrupt vector location. thus in a single-interrupt system the interrupt response time will always be more than 5 machine cycles and not more than 12 machine cycles. the ma ximum latency of 12 machine cycle is 48 clock cycles. note that in the standard 8051 the maximu m latency is 8 machine cycles which equals 96 machine cycles. this is a 50% reduction in terms of clock periods. 11.4 interrupt inputs W79E834 has two individual interrupt inputs as well as the keyboard interrupt function. the latter is described separately elsewhere in this section. two interrupt inputs are identical to those present on the standard 80c51 microcontroller. the external sources can be programmed to be level- activated or transition-activated by setting or clearing bit it1 or it0 in register tcon. if itn = 0, external interrupt n is triggered by a detected low at the intn pin. if itn = 1, external interrupt n is edge triggered. in this mode if successive samples of the intn pin show a high in one cycle and a low in the next cycle, interrupt request flag ien in tcon is set, causing an interrupt request. since the external interrupt pins are sampled onc e each machine cycle, an input high or low should hold for at least 6 cpu clocks to ensure proper sampli ng. if the external interrupt is high for at least one machine cycle, and then hold it low for at least one machine cycle. this is to ensure that the transition is seen and that interrupt request flag ien is set. ien is automatically cleared by the cpu when the service routine is called.
preliminary W79E834 data sheet - 56 - if the external interrupt is level-activated, the ex ternal source must hold the request active until the requested interrupt is actually gener ated. if the external interrupt is still asserted when the interrupt service routine is completed another interrupt w ill be generated. it is not necessary to clear the interrupt flag ien when the interrupt is level sens itive, it simply tracks the input pin level. if an external interrupt is enabled when the device is put into power down or idle mode, the interrupt will cause the processor to wake up and resume operation. refer to the section on power reduction modes for details. espi es ri + ti et1 tf1 et0 tf0 ea epwm pwmf ie0 ie1 bof kbf wdi f adci eadc ewdi ekb ebo ex1 ex0 interrupt to cpu wakeup (if in power down) et2 tf2 ecptf spif modf spiovf cptf0 cptf1 cptf2 interrupt inputs
preliminary W79E834 data sheet publication release date: october 12, 2006 - 57 - revision a13 12. programmable timers/counters W79E834 has two 16-bit programmable timer/c ounters and one programmable watchdog timer. the watchdog timer is operationally quite di fferent from the other two timers. 12.1 timer/counters 0 & 1 W79E834 has two 16-bit timer/counters. each of t hese timer/counters has two 8 bit registers which form the 16 bit counting register. for timer/counter 0 they are th0, the upper 8 bits register, and tl0, the lower 8 bit register. similarly timer/counter 1 has two 8 bit registers, th1 and tl1. the two can be configured to operate either as timers, counting machine cycles or as counters counting external inputs. when configured as a "timer", the timer counts cl ock cycles. the timer clock can be programmed to be thought of as 1/12 of t he system clock or 1/4 of the system clock. in the "counter" mode, the register is incremented on the falling edge of the external input pin, t0 in case of timer 0, and t1 for timer 1. the t0 and t1 inputs are sampled in every machine cycle at c4. if the sampled value is high in one machine cycle and low in the next, then a valid high to low transition on the pin is recognized and the count register is incremented. since it takes two machine cycles to recognize a negative transition on the pin, the maximum rate at which c ounting will take place is 1/24 of the master clock frequency. in either the "timer" or "counter" mode, the count register will be updated at c3. therefore, in the "timer" mode, the recognized negative transition on pin t0 and t1 can cause the count register value to be updated only in the ma chine cycle following the one in which the negative edge was detected. the "timer" or "counter" function is selected by the " t c/ " bit in the tmod special function register. each timer/counter has one selection bit for its own; bit 2 of tmod selects the function for timer/counter 0 and bit 6 of tmod selects the function for timer/counter 1. in addition each timer/counter can be set to operate in any one of four possible modes. the mode selection is done by bits m0 and m1 in the tmod sfr. 12.2 time-base selection W79E834 provides users with two modes of operation for the timer. the timers can be programmed to operate like the standard 8051 family, c ounting at the rate of 1/12 of the clock speed. this will ensure that timing loops on W79E834 and the standard 8051 c an be matched. this is the default mode of operation of the W79E834 timers. the user also has the option to count in the turbo mode, where the timers will increment at the rate of 1/4 clock speed. this will straight-away increase the counting speed three times. this selection is done by the t0 m and t1m bit in ckcon sfr. a reset sets these bits to 0, and the timers then oper ate in the standard 8051 mode. the user should set these bits to 1 if the timers are to operate in turbo mode. 12.3 mode 0 in mode 0, the timer/counters act as an 8-bit counter with a 5-bit, divide by 32 pre-scale. in this mode we have a 13-bit timer/counter. the 13-bit counter cons ists of 8 bits of thx and 5 lower bits of tlx. the upper 3 bits of tlx are ignored. the negative edge of the clock is incr ements count in the tlx register. when the fifth bit in tlx moves from 1 to 0, then the count in the thx register is incremented. when count in thx moves from ffh to 00h, then the overflow flag tfx in tcon sfr is set. the counted input is enabled only if trx is set
preliminary W79E834 data sheet - 58 - and either gate = 0 or intx = 1. when t c/ is set to 0, then it will count clock cycles, and if t c/ is set to 1, then it will count 1 to 0 transitions on t0 (p1.2) for timer 0 and t1 (p 0.7) for timer 1. when the 13-bit count reaches 1fffh the next count will cause it to roll-over to 0000h. the timer overflow flag tfx of the relevant timer is set and if enabled an interrupts will occur. fcpu 1/12 0 1 047 07 tfx th0 (th1) tl0 (tl1) timer 0/1 mode 0 interrupt t0oe t0=p1.2 (c/t=tmod.6) c/t=tmod.2 gate=tmod.3 (gate=tmod.7) int0=p1.3 (int1=p1.4) t1=(p0.7) p1.2 (p0.7) tf0 (tf1) tr0=tcon.4 tr1=tcon.6 (t1oe) 1/4 t0m=ckcon.3 (t1m=ckcon.4) 0 1 12.4 mode 1 mode 1 is similar to mode 0 except that the counting register form s a 16-bit counter, rather than a 13- bit counter. this means that all the bits of th x and tlx are used. roll-over occurs when the timer moves from a count of ffffh to 0000h. the timer overfl ow flag tfx of the relevant timer is set and if enabled an interrupt will occur. the selection of the ti me-base in the timer mode is similar to that in mode 0. the gate function operates similarly to that in mode 0. fcpu 1/12 0 1 047 07 tfx th0 (th1) tl0 (tl1) timer 0/1 mode 1 interrupt t0oe t0=p1.2 (c/t=tmod.6) c/t=tmod.2 gate=tmod.3 (gate=tmod.7) int0=p1.3 (int1=p1.4) t1=(p0.7) p1.2 (p0.7) tf0 (tf1) tr0=tcon.4 tr1=tcon.6 (t1oe) 1/4 0 1 t0m=ckcon.3 (t1m=ckcon.4)
preliminary W79E834 data sheet publication release date: october 12, 2006 - 59 - revision a13 12.5 mode 2 in mode 2, the timer/counter is in the auto rel oad mode. in this mode, tlx acts as an 8-bit count register, while thx holds the reload value. when the tlx register overflows from ffh to 00h, the tfx bit in tcon is set and tlx is reloaded with the c ontents of thx, and the c ounting process continues from here. the reload operation leaves the cont ents of the thx register unchanged. counting is enabled by the trx bit and proper setting of gate and intx pins. as in the other two modes 0 and 1 mode 2 allows counting of either clock cycles (clock/12 or clock/4) or pulses on pin tn. 0 1 07 07 tfx th0 (th1) tl0 (tl1) timer 0/1 mode 2 : 8-bit auto-reload mode interrupt t0oe t0=p1.2 (c/t=tmod.6) c/t=tmod.2 gate=tmod.3 (gate=tmod.7) int0=p1.3 (int1=p1.4) t1=(p0.7) p1.2 (p0.7) tf0 (tf1) tr0=tcon.4 tr1=tcon.6 (t1oe) fcpu 1/12 0 1/4 0 1 t0m=ckcon.3 (t1m=ckcon.4) timer/counter mode 2. 12.6 mode 3 mode 3 has different operating methods for the two ti mer/counters. for timer/c ounter 1, mode 3 simply freezes the counter. timer/counter 0, however, configures tl0 and th0 as two separate 8 bit count registers in this mode. the logic for this mode is shown in the figure. tl0 uses the timer/counter 0 control bits t c/ , gate, tr0, int0 and tf0. the tl0 can be used to count clock cycles (clock/12 or clock/4) or 1-to-0 transitions on pin t0 as determi ned by c/t (tmod.2). th0 is forced as a clock cycle counter (clock/12 or clock/4) and takes over the us e of tr1 and tf1 from timer/counter 1. mode 3 is used in cases where an extra 8 bit timer is needed. with timer 0 in mode 3, timer 1 can still be used in modes 0-2, but its flexibility is somewhat limited. while its basic functionality is maintained, it no longer has control over its overflow flag tf1 and the enable bit tr1. timer 1 can still be used as a timer/counter and retains the use of gate and int1 pin. in this condition it can be turned on and off by switching it out of and into its own mode 3. it can also be used as a baud rate generator for the serial port.
preliminary W79E834 data sheet - 60 - 0 1 07 07 tf0 th0 tl0 timer 0/1 mode 3 : two 8-bit counters interrupt t0oe t0=p1.2 c/t=tmod.2 gate=tmod.3 int0=p1.3 p1.2 tr0=tcon.4 tr1=tcon.6 tf1 interrupt t1oe p0.7 fcpu 1/12 0 1/4 0 1 t0m=ckcon.3 (t1m=ckcon.4)
preliminary W79E834 data sheet publication release date: october 12, 2006 - 61 - revision a13 13. watchdog timer the watchdog timer is a free-running timer which c an be programmed by the user to serve as a system monitor, a time-base generator or an event timer. it is basically a set of dividers that divide the system clock. the divider output is selectable and determines the time -out interval. when the time-out occurs a flag is set, which can cause an interrupt if enabled, and a system reset can also be caused if it is enabled. the interrupt will occur if the i ndividual interrupt enable and the global enable are set. the interrupt and reset functions are independent of each other and may be used separately or together depending on the user?s software. watchdog timer the watchdog timer should first be restarted by usi ng wdclr. this ensures that the timer starts from a known state. the wdclr bit is used to restart the watchdog timer. this bit is self clearing, i.e. after writing a 1 to this bit the software will autom atically clear it. the watchdog timer will now count clock cycles. the time-out interval is se lected by the two bits wd1 and wd0 (wdcon.5 and wdcon.4). when the selected time-out occurs, t he watchdog interrupt flag wdif (wdcon.3) is set. after the time-out has occurred, the watchdog ti mer waits for an additional 512 clock cycles. if the watchdog reset ewrst (wdcon.1) is enabled, then 512 clocks after the time-out, if there is no wdclr, a system reset due to watchdog timer will o ccur. this will last for two machine cycles, and the watchdog timer reset flag wdrf (wdcon.2) will be set. this indicates to the software that the watchdog was the cause of the reset. when used as a simple timer, the reset and interrupt functions are disabled. the timer will set the wdif flag each time the timer completes the selected time interval. the wdif flag is polled to detect a time-out and the wdclr allows software to restart the timer. the watchdog timer can also be used as a very long timer. the interrupt feature is enabled in this case. every time the time-out occurs an interrupt will occur if the global interrupt enable ea is set. the main use of the watchdog timer is as a system monitor. this is important in real-time control applications. in case of some power glitches or electro-magnetic interference, the processor may begin to execute errant code. if this is left unc hecked the entire system may crash. using the watchdog timer interrupt during software development will allow the user to select ideal watchdog reset locations. the code is first written without the watchdog interrupt or reset. then the watchdog interrupt is enabled to identify code locations wher e interrupt occurs. the user can now insert instructions to reset the watchdog timer, which w ill allow the code to run without any watchdog timer
preliminary W79E834 data sheet - 62 - interrupts. now the watchdog timer reset is enabled and the watchdog interrupt may be disabled. if any errant code is executed now, then the reset wa tchdog timer instructions will not be executed at the required instants and watchdog reset will occur. the watchdog timer time-out selection will result in different time-out values depending on the clock speed. the reset will occur, when enabled, 512 clocks after the time-out has occurred. time-out values for the watchdog timer wd1 wd0 watchdog interval number of clocks time @ 10 mhz 0 0 2 17 131072 13.11 ms 0 1 2 20 1048576 104.86 ms 1 0 2 23 8388608 838.86 ms 1 1 2 26 67108864 6710.89 ms the watchdog timer will de disabled by a power-on/fail reset. the watchdog timer reset does not disable the watchdog timer, but will restart it. in general , software should restart the timer to put it into a known state. the control bits that support the watchdog timer are discussed below. 13.1 watchdog control wdif: wdcon.3 - watchdog timer interrupt flag. this bit is set whenever the time-out occurs in the watchdog timer. if the watchdog interrupt is enabled (ie1 .4), then an interrupt will occur (if the global interrupt enable is set and other interrupt requirement s are met). software or any reset can clear this bit. wtrf: wdcon.2 - watchdog timer reset flag. this bit is set whenever a watchdog reset occurs. this bit is useful for determined the cause of a reset. software must read it, and clear it manually. a power-fail reset will clear this bit. if ewrst = 0, then this bit will not be affected by the watchdog timer. ewrst: wdcon.1 - enable watchdog timer reset. this bit when set to 1 will enable the watchdog timer reset function. setting this bit to 0 will dis able the watchdog timer reset function, but will leave the timer running. wdclr: wdcon.0 - reset watchdog timer. this bit is used to clear the watchdog timer and to restart it. this bit is self-clearing, so after the software writes 1 to it t he hardware will automatically clear it. if the watchdog timer reset is enabled, then the wdclr has to be set by the user within 512 clocks of the time-out. if this is not done then a watchdog timer reset will occur.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 63 - revision a13 13.2 clock control of watchdog wd1, wd0: wdcon.5, wdcon.4 - watchdog timer m ode select bits. these two bits select the time-out interval for the watchdog timer. the reset time is 512 clocks longer than the interrupt time-out value. the default watchdog time-out is 2 17 clocks, which is the shortest time-out period. the ewrst, wdif and wdclr bits are protected by the timed a ccess procedure. this prevents software from accidentally enabling or disabling the watchdog timer. more importantly, it makes it highly improbable that errant code can enable or disable the watchdog timer. the security bit wdte is located at bit 7 of config register. this bit is user to configure the clock source of watchdog timer either it is from the internal rc or from the uc clock.
preliminary W79E834 data sheet - 64 - 14. timer2/input capture modules timer/counter 2 is a 16 bit up counter which is c onfigured by the t2mod r egister and controlled by the t2con register. timer/counter 2 is also equipped with 3 input captures and reloads capability. as with the timer 0 and timer 1 counters, there exists considerable flexibility in selecting and controlling the clock, and in defining the operat ing mode. the clock source for timer/counter 2 crystal oscillator is divided by 1,4,16 or 32 (selectable with ccdiv[ 1:0] in ckcon[6:5]). the clock is then enabled when tr2 is a 1, and disabled when tr2 is a 0. 14.1 capture mode the capture modules are function to detect and m easure pulse width and period of a square wave. it supports 3 capture inputs and digital noise reje ction filter. the modules are configured by capcon0 and capcon1 sfr registers. the input capt ure pins are in the structure with schmitt trigger. for this operation it bas ically consists of; ? 3 capture module function blocks ? timer 2 block each capture module block consists of 2 bytes c apture registers, noise filter and programmable edge triggers. noise filter is used to filter the unw anted glitch or pulse on the trigger input pin. the noise filter can be enabled through bit enfx (c apcon1). if enabled, the capture logic required to sample 4 consecutive same capture input value in order to recognize an edge as a capture event. a possible implementation of digital noise filter is as follow; noise filter the interval between pulses requirement for input capture is 1 machine cycle width, which is the same as the pulse width required to guarantee a trigger for all trigger edge mode. for less than 3 system clocks, anything less than 3 clocks w ill not have any trigger and pulse wi dth of 3 or more but less than 4 clocks will trigger but will not guarantee 100% because input sampling is at stage c3 of the machine cycle. the trigger option is programmable through cct x [1:0] (capcon0). it supports positive edge, negative edge and both edge triggers. each capture module consists of an enable, icen0-2. [note: x=0/1/2, for capture 0/1/2 block]. timer/counter 2 serves as a 16 bit up counter. it supports reload and compared modes. more details are described in next sections.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 65 - revision a13 capture blocks are trigger by external pins t0, t1 and t2, respectively. if icenx is enabled, each time the external pin trigger, the content of the fr ee running 16 bits counter, tl2 & th2 (from timer 2 block) will be captured/transferred into the capture registers, cclx and cchx, depending which external pin trigger. this action also causes the cptfx flag bit in capcon1 to be set, which will also generate an interrupt (if enabled by ecptf bit in sfr ie1.7). the cptf0-2 flags are logical ?or? to the interrupt module. flag is set by hardware and cl ear by software. software will have to resolve on the priority of the interrupt flags. setting the t2cr bit (t2mod.3), will allow hardware to reset timer 2 automatically after the value of tl2 and th2 have been captured. priority is given to t2cr to reset counter after capture the timer value into the capture register. timer2/capture modules
preliminary W79E834 data sheet - 66 - program flow for measurement with t0 between pulses with falling edge detection (acc is incremented in interrupt service routine).
preliminary W79E834 data sheet publication release date: october 12, 2006 - 67 - revision a13 program flow for measurement with t0 between pulses with rising edge detection (acc is incremented in interrupt service routine).
preliminary W79E834 data sheet - 68 - program flow for measurement with t0 pulse widt h with rising and falling edge detection (acc is incremented in interrupt service routine).
preliminary W79E834 data sheet publication release date: october 12, 2006 - 69 - revision a13 14.2 compare mode timer 2 can be configured for compare mode. t he compare mode is enabled by setting the cmp/rl2 bit to 1 in the t2con register. rcap2 will serves as a compare register. as timer 2 counting up, upon matching with rcap2 value, tf2 will be set (which will generate an interrupt request if enable timer 2 interrupt et2 is enabled) and the timer reload from 0 and starts counting again. 14.3 reload mode timer 2 can be also be configured for reload m ode. the reload mode is enabled by clearing the cmp/rl2 bit to 0 in the t2con register. in this mode, rcap serves as a reload register. when timer 2 overflows, a reload is generated that causes t he contents of the rcap2l and rcap2h registers to be reloaded into the tl2 and th2 registers, if enld is set. tf2 flag is set, and interrupt request is generated if enable timer 2 interrupt et2 is enabled. howe ver, if enld = 0, timer 2 will be reload with 0, and count up again. alternatively, other reload source is also possibl e by the input capture pi ns by configuring the ccld[1:0] bit. if the icenx bit is set, then a trigger of external t0, t1 or t2 pin (respectively) will also cause a reload. this action also sets the cp tf0, cptf1 or cptf2 flag bit in sfr capcon1, respectively.
preliminary W79E834 data sheet - 70 - 15. serial port (uart) serial port in the W79E834 is a full duplex port. it prov ides the user with additional features such as the frame error detection and the automatic addre ss recognition. the serial ports are capable of synchronous as well as asynchronous communica tion. in synchronous mode, W79E834 generates the clock and operates in a half duplex mode. in the asynchronous mode, full duplex operation is available. this means that it can simultaneously transmit and receiv e data. the transmit register and the receive buffer are both addressed as sbuf spec ial function register. however any write to sbuf will be to the transmit register, while a read fr om sbuf will be from the receiver buffer register. the serial port can operate in four different modes as described below. 15.1 mode 0 this mode provides synchronous communication with external devices. in this mode serial data is transmitted and received on the rxd line. txd is used to transmit the shift clock. the txd clock is provided whether the device is transmitting or receiv ing. this mode is therefore a half duplex mode of serial communication. in this mode, 8 bits ar e transmitted or received per frame. the lsb is transmitted/received first. the baud rate is fixed at 1/12 or 1/4 of the oscillator frequency. this baud rate is determined by the sm2 bit (scon.5). when this bit is set to 0, then the serial port runs at 1/12 of the clock. when set to 1, the serial port runs at 1/4 of the clock. this additional facility of programmable baud rate in mode 0 is the onl y difference between the standard 8051 and W79E834. the functional block diagram is shown below. data enters and leaves the seri al port on the rxd line. the txd line is used to output the shift clock. the sh ift clock is used to shift data into and out of the device. any instruction that causes a write to sbu f will start the transmission. the shift clock will be activated and data will be shifted out on the rxd pin t ill all 8 bits are transmitted. if sm2 = 1, then the data on rxd will appear 1 clock period before the falli ng edge of shift clock on txd. the clock on txd then remains low for 2 clock periods, and then goes high again. if sm2 = 0, the data on rxd will appear 3 clock periods before the falling edge of shi ft clock on txd. the clock on txd then remains low for 6 clock periods, and then goes high again. this ensures that at the receiving end the data on rxd line can either be clocked on the rising edge of the shift clock on txd or latched when the txd clock is low.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 71 - revision a13 1/12 fcpu 0 tx clock rx clock ti ri tx shift rx start rx shift load sbuf shift clock ri ren sm2 clock sin parout sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus sbuf write to sout transmit shift register serial interrupt rxd txd rxd p1.1 alternate input function p1.1 alternate output function p1.0 alternate output function serial port mode 0 1/4 1 the ti flag is set high in c1 following the end of trans mission of the last bit. the serial port will receive data when ren is 1 and ri is zero. the shift clock (txd) will be activated and the serial port will latch data on the rising edge of shift clock. the external device should therefore present data on the falling edge on the shift clock. this process continues till a ll the 8 bits have been received. the ri flag is set in c1 following the last rising edge of the shift clo ck on txd. this will stop re ception, till the ri is cleared by software. 15.2 mode 1 in mode 1, the full duplex asynchronous mode is us ed. serial communication frames are made up of 10 bits transmitted on txd and received on rxd. the 10 bi ts consist of a start bit (0), 8 data bits (lsb first), and a stop bit (1). on received, the stop bi t goes into rb8 in the sfr scon. the baud rate in this mode is variable. the serial baud can be progra mmed to be 1/16 or 1/32 of the timer 1 overflow. since the timer 1 can be set to different reload values, a wide variation in baud rates is possible. transmission begins with a write to sbuf. the serial data is brought out on to txd pin at c1 following the first roll-over of divide by 16 counter. the nex t bit is placed on txd pin at c1 following the next rollover of the divide by 16 counter. thus the transmission is synchronized to the divide by 16 counters and not directly to the write to sbuf signal. after all 8 bits of data are transmitted, the stop bit is transmitted. the ti flag is set in the c1 st ate after the stop bit has been put out on txd pin. this will be at the 10th rollover of the divide by 16 counters after a write to sbuf. reception is enabled only if ren is high. the serial por t actually starts the re ceiving of serial data, with the detection of a falling edge on the rxd pin. t he 1-to-0 detector continuously monitors the rxd line, sampling it at the rate of 16 times the selected baud rate. when a falling edge is detected, the
preliminary W79E834 data sheet - 72 - divide by 16 counters is immediately reset. this helps to align the bit boundaries with the rollovers of the divide by 16 counters. the 16 states of the counter effect ively divide the bit time into 16 slices. the bit detection is done on a best of three bases. the bit detector samples the rxd pin, at the 8th, 9th and 10th counter states. by using a majority 2 of 3 voting system, the bit val ue is selected. this is done to improve the noise rejection feature of the serial port. if the first bit detected after the falling edge of rxd pin is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. the serial port again looks for a falling edge in the rxd line. if a valid start bit is detected, then the rest of the bits are also detected and shifted into the sbuf. after shifting in 8 data bits, there is one more shift to do, after which the sbuf and rb8 are loaded and ri is set. however certain conditions must be met before the loading and setting of ri can be done. 1. ri must be 0 and 2. either sm2 = 0, or the received stop bit = 1. if these conditions are met, then the stop bit goes to rb8, the 8 data bits go into sbuf and ri is set. otherwise the received frame may be lost. after the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the rxd pin. 1/2 1/16 tx clock rx clock ti ri tx shift rx start rx shift load sbuf smod clock sin d8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus sbuf write to sout transmit shift register serial interrupt txd rxd serial port mode 1 parout rb8 start stop 0 1 bit detector 1-to-0 detector sample 1/16 0 timer 1 overflow 1 receive shift register
preliminary W79E834 data sheet publication release date: october 12, 2006 - 73 - revision a13 15.3 mode 2 this mode uses a total of 11 bits in asynch ronous full-duplex communication. the functional description is shown in the figure below. the frame cons ists of one start bit (0), 8 data bits (lsb first), a programmable 9th bit (tb8) and a stop bit (0). the 9t h bit received is put into rb8. the baud rate is programmable to 1/32 or 1/64 of the oscillator fr equency, which is determined by the smod bit in pcon sfr. transmission begins with a write to sbuf. the serial data is brought out on to txd pin at c1 following the first roll-over of the divide by 16 counter. the next bit is placed on txd pin at c1 following the next rollover of the divide by 16 count er. thus the transmission is synchronized to the divide by 16 counters, and not dire ctly to the write to sbuf signal. after all 9 bits of data are transmitted, the stop bit is transmitted. the ti flag is set in the c1 state after the stop bit has been put out on txd pin. this will be at the 11th rollover of the divide by 16 counters after a write to sbuf. reception is enabled only if ren is high. the serial por t actually starts the re ceiving of serial data, with the detection of a falling edge on the rxd pin. t he 1-to-0 detector continuously monitors the rxd line, sampling it at the rate of 16 times the selected baud rate. when a falling edge is detected, the divide by 16 counters is immediately reset. this helps to align the bit boundaries with the rollovers of the divide by 16 counters. the 16 stat es of the counter effectively divi de the bit time into 16 slices. the bit detection is done on a best of three bases. the bit detector samples the rxd pin, at the 8th, 9th and 10th counter states. by using a ma jority 2 of 3 voting system, the bit value is selected. this is done to improve the noise rejecti on feature of the serial port. 1/2 1/16 tx clock rx clock ti ri tx shift rx start rx shift load sbuf smod clock sin d8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus sbuf write to sout transmit shift register serial interrupt txd rxd serial port mode 2 parout rb8 start stop 0 1 bit detector 1-to-0 detector sample 1/16 0 clock/2 1 d8 tb8 receive shift register
preliminary W79E834 data sheet - 74 - if the first bit detected after the falling edge of rxd pin, is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. the serial port again looks for a falling edge in the rxd line. if a valid start bit is detected, then the rest of t he bits are also detected and shifted into the sbuf. after shifting in 9 data bits, there is one more shift to do, after which the sbuf and rb8 are loaded and ri is set. however certain conditions must be met before the loading and setting of ri can be done. 1. ri must be 0 and 2. either sm2 = 0, or the received stop bit = 1. if these conditions are met, then the stop bit goes to rb8, the 8 data bits go into sbuf and ri is set. otherwise the received frame may be lost. after the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the rxd pin. 15.4 mode 3 this mode is similar to mode 2 in all respects, ex cept that the baud rate is programmable. the user must first initialize the serial related sfr scon before any communication can take place. this involves selection of the mode and baud rate. the ti mer 1 should also be initialized if modes 1 and 3 are used. in all four modes, transmission is started by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by t he condition ri = 0 and ren = 1. this will generate a clock on the txd pin and shift in 8 bits on the rxd pin. reception is initiated in the other modes by the incoming start bit if ren = 1. the external device will start the communication by transmitting the start bit. 1/2 1/16 tx clock rx clock ti ri tx shift rx start rx shift load sbuf smod clock sin d8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus sbuf write to sout transmit shift register serial interrupt txd rxd serial port mode 3 parout rb8 start stop 0 1 bit detector 1-to-0 detector sample 1/16 0 1 d8 tb8 timer 1 overflow receive shift register
preliminary W79E834 data sheet publication release date: october 12, 2006 - 75 - revision a13 serial ports modes sm0 sm1 mode type baud clock frame size start bit stop bit 9th bit function 0 0 0 synch. 4 or 12 tclks 8 bits no no none 0 1 1 asynch. timer 1 10 bits 1 1 none 1 0 2 asynch. 32 or 64 tclks 11 bits 1 1 0, 1 1 1 3 asynch. timer 1 11 bits 1 1 0, 1 15.5 framing error detection a frame error occurs when a valid stop bit is not det ected. this could indicate incorrect serial data communication. typically the frame error is due to noise and contention on the serial communication line. W79E834 has the capability to detect such fr aming errors and set a flag which can be checked by software. the frame error fe bit is located in scon.7. th is bit is normally used as sm0 in the standard 8051 family. however, it serves a dual function and is ca lled sm0/fe. there are actually two separate flags, one for sm0 and the other for fe. the flag that is actually accessed as scon.7 is determined by smod0 (pcon.6) bit. when smod0 is set to 1, then the fe flag is indicated in sm0/fe. when smod0 is set to 0, then the sm0 flag is indicated in sm0/fe. the fe bit is set to 1 by hardware but must be cl eared by software. note that smod0 must be 1 while reading or writing to fe. if fe is set, then any follo wing frames received without any error will not clear the fe flag. the clearing has to be done by software. 15.6 multiprocessor communications multiprocessor communications makes use of the 9th data bit in modes 2 and 3. the ri flag is set only if the received byte corresponds to the given or broadcast address. this hardw are feature eliminates the software overhead required in checking ever y received address, and greatly simplifies the software programmer task. in the multiprocessor communication mode, the addr ess bytes are distinguis hed from the data bytes by transmitting the address with the 9th bit set high. when the master processor wants to transmit a block of data to one of the slaves, it first sends out the address of the target ed slave (or slaves). all the slave processors should have their sm2 bit set high when waiting for an address byte. this ensures that they will be interrupted only by the reception of an address byte. the automatic address recognition feature ensures that only the address ed slave will be interrupted. the address comparison is done in hardware not software. the addressed slave clears the sm2 bit, thereby clear ing the way to receive data bytes. with sm2 = 0, the slave will be interrupted on the reception of every single complete frame of data. the unaddressed slaves will be unaffected, as they will be st ill waiting for their address. in mode 1, the 9th
preliminary W79E834 data sheet - 76 - bit is the stop bit, which is 1 in case of a valid frame. if sm2 is 1, then ri is set only if a valid frame is received and the received byte matches the given or broadcast address. the master processor can selectively communicate wi th groups of slaves by using the given address. all the slaves can be addressed together using t he broadcast address. the addresses for each slave are defined by the saddr and saden sfrs. the slav e address is an 8-bit value specified in the saddr sfr. the saden sfr is actually a mask for the byte value in saddr. if a bit position in saden is 0, then the corresponding bit position in saddr is don't care. only those bit positions in saddr whose corresponding bits in saden are 1 are used to obtain the given address. this gives the user flexibility to address multiple slav es without changing the slave address in saddr. the following example shows how the user can defi ne the given address to address different slaves. slave 1: saddr 1010 0100 saden 1111 1010 given: 1010 0x0x slave 2: saddr 1010 0111 saden 1111 1001 given : 1010 0xx1 the given address for slave 1 and 2 differ in the lsb. for slave 1, it is don't care, while for slave 2 it is 1. thus to communicate only with slave 1, t he master must send an address with lsb = 0 (1010 0000). similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. hence to communicate only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). if the master wishes to communicate with both slaves simult aneously, then the address must have bit 0 = 1 and bit 1 = 0. the bit 3 position is don't care for both the sl aves. this allows two different addresses to select both slaves (1010 0001 and 1010 0101). the master can communicate with all the slaves simultaneously with the broadcast address. this address is formed from the logical or of the sa ddr and saden sfrs. the zeros in the result are defined as don't cares. in most cases the broadcas t address is ffh. in the previous case, the broadcast address is (1111111x) for slave 1 and (11111111) for slave 2. the saddr and saden sfrs are located at address a9h and b9h respectively. on reset, these two sfrs are initialized to 00h. this results in given address and broadcast address being set as xxxx xxxx (i.e. all bits don't care). this effectively re moves the multiprocessor communications feature, since any selectivity is disabled.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 77 - revision a13 16. serial pheripheral interface (spi) 16.1 general descriptions W79E834 consists of spi block to support high speed serial communication. it?s capable of supporting data transfer rates of 4 mbit/s, for 16mhz bus frequency. this device?s spi support the following features; z master and slave mode z slave select output z programmable serial clock?s polarity and phase z receive double buffered data register z lsb first enable z write collision detection z transfer complete interrupt 16.2 block descriptions the following figure shows spi block diagram. it provi des an overview of spi architecture in this device. the main blocks of spi are spi register blocks, control logics, baud rate control, and pin control logics; a. shift register and read data buffer. it is single buffered in the transmit direction and double buffered in the receive direction. transmit data cannot be written to the shifter until the previous transfer is complete. when the spif set, user will not be able to write to the shift register. user has to clear the spif before writing to the shift register. receive logics consist of parallel read data buffer so the shifter is free to accept a second data, as the first received data will be transferred to the read data buffer. b. spi control block. this provi de control functions to configure t he device for spi enable, master or slave, clock phase and polarity, msb/lsb access fi rst selection, and slave select output enable. c. baud rate control. this control logics divide cp u clock to 4 different selectable clocks (1/4, 1/16, 1/64 and 1/128). spi baud rate selection (based on 16 mhz bus clock) spr1 spr0 divider baud rate 0 0 4 4mhz 0 1 16 1mhz 1 0 64 250khz 1 1 128 125khz d. spi registers. there are three spi regi sters to support its operations, they are; ? spi control registers (spcr) ? spi status registers (spsr) ? spi data register (spdr) these registers provide control, status, data storage functions and baud rate selection control. detail bit descriptions are found at sfr section. e. pin control logic. controls behavior of spi interface pins.
preliminary W79E834 data sheet - 78 - spi block diagram 16.3 functional descriptions 16.3.1 master mode the device can configure the spi to operate as a ma ster or as a slave, through mstr bit. when the mstr bit is set, master mode is selected, when ms tr bit is cleared, slave mode is selected. during master mode, only master spi device can initiate transmission. a transmission begins by writing to the master spdr register. the bytes begin shifting out on mosi pin under the control of spclk. the master places data on mosi line a half-cycle befor e spclk edge that the slave device uses to latch the data bit. the ss must stay low before data transactions and stay low for the duration of the transactions.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 79 - revision a13
preliminary W79E834 data sheet - 80 -
preliminary W79E834 data sheet publication release date: october 12, 2006 - 81 - revision a13 16.3.2 slave mode when in slave mode, the spclk pin becomes input and it will be clock by anot her master spi device. the ss pin also becomes input. similarly, before dat a transmissions occurs, and remain low until the transmission completed. if ss goes high, the spi is forced into idle state. data flows from master to slave on mosi pin and fl ows from slave to master on miso pin. the spdr is used when transmitting or receiving data on the serial bus. only a write to this register initiates transmission or reception of a byte, and this only occu rs in the master device. at the completion of transferring a byte of data, the spif status bi t is set in both the master and slave devices. a read of the spdr is actually a read of a buffer. to prevent an overrun and t he loss of the byte that caused the overrun, the first spif must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated.
preliminary W79E834 data sheet - 82 -
preliminary W79E834 data sheet publication release date: october 12, 2006 - 83 - revision a13 16.3.3 slave select the slave select ( ss ) input of a slave device must be exter nally asserted before a master device can exchange data with the slave device. ss must be low before data transactions and must stay low for the duration of the transaction. the ss line of the master must be held high. the other three lines are dedicated to the spi w henever the serial peripheral interface is on. the state of the master and slave cp ha bits affects the operation of ss . cpha settings should be identical for master and slave. when cpha = 0, the shift clock is the or of ss with sck. in this clock phase mode, ss must go high between successive characte rs in an spi message. when cpha = 1, ss can be left low between successive spi characte rs. in cases where there is only one spi slave mcu, its ss line can be tied to vss as long as only cpha = 1 clock mode is used. 16.3.4 ss output enable available in master mode only, the ss output is enabled with the ssoe bit in the spcr register. the ss output pin is connected to the ss input pin of the slave device. the ss output automatically goes low for each transmission when selecting exte rnal device and it goes high during each idling state to deselect external devices.
preliminary W79E834 data sheet - 84 - drss ssoe master mode slave mode 0 0 ss input (with mode fault). see section spi i/o mode section for detail. ss input ( not affected by ssoe ) 0 1 reserved ss input ( not affected by ssoe ) 1 0 ss general purpose i/o ( no mode fault ) ss input ( not affected by ssoe ) 1 1 ss output ( no mode fault ) ss input ( not affected by ssoe ) during master mode (with ssoe=drss= 0), mode fault will be set if ss pin is detected low. when mode fault is detected hardware will clear mstr bi t and spe bit in the meantime it will also generated interrupt request, if espi is enabled. spi interrupt request 16.3.5 spi i/o pins mode when spi is disabled (spe = 0) the corresponding i/o is following the setting determined by port mode setting (sfr p2m1 & p2m2). when spi is enabl ed (spe = 1) the spi pins i/o mode follow the below table. for ss pin it is always at quasi-bidirectional mode whether it is configured as master or slave. miso mosi clk ss master input output output output [1] : drss=0,ssoe=0 input: drss=1, ssoe=1 slave output [2] during ss = low else input mode input input input input = quasi-bidirectional mode; output = push-pull mode output [1] = this output mode in ss is quasi-bidirectional output mode. master needs to detect mode fault during master outputs ss low. output [2] = in slave mode, miso is in output mode only during the time of ss =low. otherwise it must keep in input mode (quasi-bidirectional).
preliminary W79E834 data sheet publication release date: october 12, 2006 - 85 - revision a13 16.3.6 programmable serial clock?s phase and polarity the clock polarity spcr.cpol control bit selects active high or active low sck clock, and has no significant effect on the transfer format. the cl ock phase spcr.cpha control bit selects one of two different transfer protocols by sampling dat a on odd numbered sck edges or on even numbered sck edges. thus, both these bits enable selection of four possible clock formats to be used by spi system. the clock phase and polarity should be identical fo r the master spi device and the communicating slave device. when cpha equals 0, the ss line must be negated and reasserted between each successive serial byte. also, if the slave writes data to the spi data register (spdr) while ss is low, a write collision error results. when cpha equals 1, the ss line can remain low between successive transfers. when cpha = 0, data is sample on the first edge of spclk and when cpha = 1 data is sample on the second edge of the spclk. prior to changing cpol setting, spe must be disabled first. 16.3.7 receive double buffered data register this device is single buffered in the transmit dire ction and double buffered in the receive direction. this means that new data for transmission cannot be wri tten to the shifter until the previous transfer is complete; however, received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial byte. as long as the first by te is read out of the read data buffer before the next byte is ready to be transferr ed, no overrun condition occurs. if overrun occur, spiovf is set. second byte seri al data cannot be transferred successfully into the data register during overrun condition and the data regist er will remains the value of the previous byte.
preliminary W79E834 data sheet - 86 - 16.3.8 lsb first enable by default, this device transfer the spi data most signifi cant bit first. this devic e provides a control bit spcr.lsbfe to allow support of transfer of spi data in least significant bit first. 16.3.9 write collision detection write collision indicates that an attempt was made to write data to the spdr while a transfer was in progress. spdr is not double buffered in the transmit direction, any writes to spdr cause data to be written directly into the spi shift register. this wr ite corrupts any transfer in progress, a write collision error is generated (wcol will be set). the transfe r continues undisturbed, and the write data that caused the error is not written to the shifter. a wr ite collision is normally a slave error because a slave has no control over when a master initiates a transfe r. a master knows when a transfer is in progress, so there is no reason for a master to generate a wr ite-collision error, although the spi logic can detect write collisions in both master and slave devices. wcol flag is clear by software. 16.3.10 transfer complete interrupt this device consists of an interrupt flag at spsr .spif. this flag will be set upon completion of data transfer with external device, or when a new dat a have been received and copied to spdr. if interrupt is enable (through espi located at ie1.3), the spi interrupt request will be generated, if global enable is also enabled. spif is a software clear interrupt. 16.3.11 mode fault error arises in a multiple-master system when more than one spi device simultaneously tries to be a master. this error is called a mode fault. when the spi system is configured as a master and the ss input line goes to active low, a mode fault error has occurred ? usually because two devices have attempted to act as master at the same time. in cases where more than one device is concurrently configured as a master, there is a chance of contention between two pin drivers. for push-pu ll cmos drivers, this contention can cause permanent damage. the mode fault mechanism attemp ts to protect the device by disabling the drivers. the mstr & spe control bits in t he spcr associated with the spi are cleared and an interrupt is generated subject to masking by the espi control bit. other precautions may need to be taken to prevent driver damage. if two devices are made masters at the same time, mode fault does not help protect either one unless one of them selects the other as slave. the amount of damage possibl e depends on the length of time both devices attempt to act as master. modf bit is set automatically by spi hardware, if the mstr control bit is set and the slave select input pin becomes 0. this condition is not per mitted in normal operation. in the case where ss is set, it is an output pin rather than being dedicated as the ss input for the spi system. in this special case, the mode fault function is inhibited and modf rema ins cleared. this flag is cleared by software. the following shows the sample hardware c onnection for multi-master/slave environment.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 87 - revision a13 spi multi-master slave environment
preliminary W79E834 data sheet - 88 - 17. timed access protection W79E834 has a new feature, like the watchdog timer which is a crucial to proper operation of the system. if left unprotected, errant code may write to the watchdog control bits resulting in incorrect operation and loss of control. in order to prevent th is, it has a protection scheme which controls the write access to critical bits. this prot ection scheme is done using a timed access. in this method, the bits which are to be prot ected have a timed write enable window. a write is successful only if this window is active, otherwise the write will be discarded. this write enable window is open for 3 machine cycles if certain conditions are met. after 3 machine cycles, this window automatically closes. the window is opened by writ ing aah and immediately 55h to the timed access (ta) sfr. this sfr is located at address c 7h. the suggested code for opening the timed access window is ta reg 0c7h ; define new register ta, located at 0c7h mov ta, #0aah mov ta, #055h when the software writes aah to the ta sfr, a count er is started. this counter waits for 3 machine cycles looking for a write of 55h to ta. if the second write (55h) occurs within 3 machine cycles of the first write (aah), then the timed access window is opened. it remains open for 3 machine cycles, during which the user may write to the protected bits. once the window closes the procedure must be repeated to access the other protected bits. examples of timed assessing are shown below. example 1: valid access mov ta, #0aah ; 3 m/c note: m/c = machine cycles mov ta, #055h ;3 m/c mov wdcon, #00h ;3 m/c example 2: valid access mov ta, #0aah ; 3 m/c mov ta, #055h ; 3 m/c nop ; 1 m/c setb ewrst ; 2 m/c example 3: valid access mov ta, #0aah ; 3 m/c mov ta, #055h ; 3 m/c orl wdcon, #00000010b ; 3m/c example 4: invalid access mov ta, #0aah ; 3 m/c mov ta, #055h ; 3 m/c nop ; 1 m/c
preliminary W79E834 data sheet publication release date: october 12, 2006 - 89 - revision a13 nop ; 1 m/c clr ewt ; 2 m/c example 5: invalid access mov ta, #0aah ; 3 m/c nop ; 1 m/c mov ta, #055h ; 3 m/c setb ewt ; 2 m/c in the first three examples, the writing to the protected bits is done before the 3 machine cycles? window closes. in example 4, however, the writing to the protected bit occurs after the window has closed, and so there is effectively no change in the status of the protected bit. in example 5, the second write to ta occurs 4 machine cycles after t he first write, therefore the timed access window is not opened at all, and the write to the protected bit fails.
preliminary W79E834 data sheet - 90 - 18. keyboard interrupt (kbi) W79E834 is provided with 8 keyboard interrupt functi on to detect keypad status which key is acted, and allow a single interrupt to be generated when any key is pressed on a keyboard or keypad connected to specific pins of the device, as shown below figure. th is interrupt may be used to wake up the cpu from idle or power down modes, afte r chip is in power down or idle mode. to support keyboard function is by port 0. it can allo w any or all pins of port 0 to be enabled to cause this interrupt. port pins are enabled by the setting of bits of kbi0 ~ kbi7 in the kbi register, as shown below figure. the keyboard interrupt flag (kbf) in the auxr1 register is set when any enabled pin is pulled low while the kbi interrupt function is ac tive, and the low pulse must more than 1 machine cycle, an interrupt will be generated if it has been enabled. the kbf bit set by hardware and must be cleared by software. in order to determine which ke y was pressed, the kbi will allow the interrupt service routine to poll port 0. p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.0 kbi.0 kbi.1 p0.1 kbi.2 kbi.3 kbi.4 kbi.5 kbi.6 kbi.7 ekb (from ie1 register) kbf (kbi interrupt)
preliminary W79E834 data sheet publication release date: october 12, 2006 - 91 - revision a13 19. i/o port configuration W79E834 has three i/o ports, port 0, port 1, port 2, p3.0 and p3.1 . all pins of i/o ports can be configured to one of four types by so ftware except p1.5 is only input pin or set to reset pin. when p1.5 is configured reset pin by rpd=0 in the config 1 register, the device can support 23 pins by use crystal. if used on-chip rc oscillator the p1.5 is configured input pin, t he device can be supported up to 24 pins. the i/o ports confi guration setting as below table. i/o port configuration table pxm1.y pxm2.y port input/output mode 0 0 quasi-bidirectional 0 1 push-pull 1 0 input only (high impedance) 1 1 open drain all port pins can be determined to high or low afte r reset by configure prhi bit in the config1 register. after reset, these pins are in quasi-bidirect ional mode. the port pin of p1.5 only is a schmitt trigger input. enabled toggle outputs from timer 0 and timer 1 by ent0 and ent1 on p2m1 register, the output frequency of timer 0 or timer 1 is by timer overflow. each i/o port of W79E834 may be selected to use ttl level inputs or schmitt inputs by p(n)s bit on p2m1 register; where n is 0, 1 or 2. when p(n)s is set to 1, ports are selected schmitt trigger inputs on port(n). the p2.0 (xtal2) can be configured clock output when used on-chip rc or external oscillator is clock source, and the frequency of clo ck output is divided by 4 on on-chip rc clock or external oscillator. 19.1 quasi-bidirectional output configuration the default port output configuration for standard w 79e834 i/o ports is the quasi-bidirectional output that is common on the 80c51 and most of its deriv atives. this output type can be used as both an input and output without the need to reconfigure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is pulled low, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open drain output except that there are three pull-up trans istors in the quasi-bidirectional output that serve different purposes . one of these pull-ups, called the ?very weak? pull-up, is turned on whenever the port latch for the pin contains a logi c 1. the very weak pull-up sources a very small current that will pull the pin high if it is left floating. a second pull-up, called the ?weak? pull-up, is tur ned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. this pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. if a pin t hat has a logic 1 on it is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and take the voltage on the port pin below its input threshold.
preliminary W79E834 data sheet - 92 - the third pull-up is referred to as the ?strong? pu ll-up. this pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. when this occurs, the strong pull-up turns on for a brie f time, two cpu clocks, in order to pull the port pin high quickly. then it turns off again. the quasi-bi directional port configuration is shown as below. 19.2 open drain output configuration the open drain output configuration turns off all pull- ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. to be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to vdd. the pull-down for this mode is the same as for the quasi-bidirectional m ode. the open drain port configuration is shown as below. 19.3 push-pull output configuration the push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch
preliminary W79E834 data sheet publication release date: october 12, 2006 - 93 - revision a13 contains a logic 1. the push-pull mode may be us ed when more source current is needed from a port output. the push-pull port configuration is shown below. one port pin that cannot be configured is p1.5. p1.5 may be used as a schmitt trigger input if the device has been configured for an internal reset and is not using the external reset input function /rst. the value of port pins at reset is determined by t he prhi bit in the config1 register. ports may be configured to reset high or low as needed for the app lication. when port pins are driven high at reset, they are in quasi-bidirectional mode and therefor e do not source large amounts of current. every output on the device may potentially be used as a 20m a sink led drive output. however, there is a maximum total output current for all ports which must not be exceeded. all ports pins of the device have slew rate cont rolled outputs. this is to limit noise generated by quickly switching output signals. the slew rate is fa ctory set to approximately 10 ns rise and fall times. the unused bits in the p3m1 are used for other purposes. these bits c an enable schmitt trigger inputs on each i/o port, enable toggle outputs from ti mer 0 and timer 1, and enable a clock output if either the internal rc oscillator or external clo ck input is being used. the last two functions are described in the timer/counters and oscillator sections respectively. each i/o port of this device may be selected to use ttl level inputs or schmitt i nputs with hysteresis. a single configuration bit determines this selection for the entire port. port pin p1.5 always has a schmitt trigger input.
preliminary W79E834 data sheet - 94 - 20. oscillator W79E834 provides three oscillator input option. thes e are configured at config register (config1) that include on-chip rc oscillator option, external clock input option and crystal oscillator input option. the crystal oscillator input frequency ma y be supported from 4mhz to 16mhz, and without capacitor or resister. fosc0 fosc1 00h 11h 10h crystal oscillator external clock input internal rc oscillator 16 bits ripple counter divide-by-m (divm register) cpu clock power monitor reset power down 1/4 adcclk peripheral clock 20.1 on-chip rc oscillator option the on-chip rc oscillator is fixed at 6mhz +/- 25% frequency to support clock source. when fosc1, fosc0 = 01h, the on-chip rc oscillator is enabled. a clock output on p3.0 (xtal2) may be enabled when on-chip rc oscillator is used. 20.2 external clock input option the clock source pin (xtal1) is from external clock input by fosc1, fosc0 = 11h, and frequency range is form 0hz up to 16mhz. a clock output on p3.0 (xtal2) may be enabled when external clock input is used. W79E834 supports a clock output function when either the on-chip rc oscillator or the external clock input options is selected. this allows external dev ices to synchronize to the device. when enabled, via the enclk bit in the p3m2 register, the clo ck output appears on the xta l2/clkout pin whenever the on-chip oscillator is running, including in idle mode. the frequency of the cl ock output is 1/4 of the cpu clock rate. if the clock output is not needed in id le mode, it may be turned off prior to entering idle mode, saving additional power. the clock out put may also be enabled when the external clock input option is selected.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 95 - revision a13 20.3 cpu clock rate select the cpu clock of W79E834 may be selected by the di vm register. if divm = 00h, the cpu clock is running at 4 cpu clock pre machine cycle, and wit hout any division from source clock (fosc). when the divm register is set to n value, the cpu cl ock is divided by 2(dvim+1), so cpu clock frequency division is from 4 to 512. the user may use this f eature to set cpu at a lower speed rate for reducing power consumption. this is very similar to the situation when cpu has entered idle mode. in addition this frequency division function affect all peripheral timings as they are all sourcing from the cpu clock(fcpu). 21. power monitoring function power-on detect and brownout are two additional power monitoring functions implemented in W79E834 to prevent incorrect operation during power up and power drop or loss. 21.1 power on detect the power?on detect function is a designed to detect power up after power voltage reaches to a level where brownout detect can work. after power on detect, the por (pcon.4) will be set to ?1? to indicate an initial power up condition. the por flag will be cleared by software. 21.2 brownout detect the brownout detect function is detect power volt age is drops to brownout voltage level, and allows preventing some process work or indicate power warming. W79E834 has two brownout voltage levels to select by bov (config1.4). if bov =0 that brownout voltage level is 3.8v, if bov = 1 that brownout voltage level is 2.5v. when the brownout voltage is drop to select level, the brownout detector will detect and keeps this active until vdd is returns to above brownout detect voltage. the brownout detect block is as follow. drownout detect block boi (enable brownout detect) brownout detect circuit 0 1 bof to reset to brownout interrupt bod when brownout detect is enabled by bod (auxr1.6), the bof (pcon.5) flag will be set that it causes brownout reset or interrupt, and bof will be cleared by software. if boi (auxr1.5) is set to ?1?, the brownout detect will cause interrupt vi a the ea (ie.7) and ebo (ie.5) bits is set. in order to guarantee a correct detection of br ownout, the vdd fail time must be slower than 50mv/us, and rise time is slower t han 2mv/us to ensure a proper reset.
preliminary W79E834 data sheet - 96 - 22. pulse width modulated outputs (pwm) the W79E834 contains four pulse width m odulated (pwm) channels which generate pulses of programmable length and interval. the output for pw m0 is on p1.6, pwm1 on p1.7, pwm2 on p0.0 and pwm3 on p2.1. after chip reset the internal out put of the each pwm channel is a ?1?. note that the state of the pin will not reflect th is if config1.5, prhi, is set to a zero. in this case before the pin will reflect the state of the internal pwm output a ?1 ? must be written to each port bit that serves as a pwm output. a block diagram is shown as below fi gure. the interval between successive outputs is controlled by a 10?bit down counter which uses the internal microcontroller clock as its input. the pwm counter clock, has the same frequency as the clock source f cpwm = f cpu . when the counter reaches underflow it is reloaded with a user selectabl e value. this mechanism allows the user to set the pwm frequency at any integer sub?multiple of the microcontroller clock frequency. the repetition frequency of the pwm is given by: f pwm = f cpwm / (pwmp+1) where pwmp is contained in pwmph and pwmpl sfr. the pwmp register fact that writes are not into t he counter register that c ontrols the counter; rather they are into a holding register. as described below t he transfer of data from this holding register, into the register which contains the actual reload value, is controlled by the user?s program. the width of each pwm output pulse is determined by the value in t he appropriate compare registers, pwm0l through pwm3l and pwm0h through pwm3h. when the counter described above reaches underflow the pwm output is forced high. it remains high until the compare value is reached at which point it goes low until the next underflow. the number of microcontroller clock pulses that the pwmn output is high is given by: t hi = (pwmp ? pwmn+1)
preliminary W79E834 data sheet publication release date: october 12, 2006 - 97 - revision a13 10-bit down counter compare register counter register pwm0 register pwmrun fcpu + - compare register pwm1 register + - compare register pwm2 register + - compare register pwm3 register + - pwm0 (p1.6) + - x x x x y y y y > > > > load pwmp register clrpwm clear counter pwm0oe 0 1 p1.6 pwm1 (p1.7) 0 1 p1.7 pwm2 (p0.0) 0 1 p0.0 pwm3 (p2.1) 0 1 p2.1 pwm1oe pwm2oe pwm3oe pwm1i pwm2i pwm3i pwm0i pwmf pwm period interrupt q q set clr d s/w clear vdd underflow pwm block diagram a compare value greater than the counter re loaded value resulted in the pwm output being permanently low. in addition there are two specia l cases. a compare value of all zeroes, 000h, causes the output to remain permanently high. a co mpare value of all ones, 3ffh, results in the pwm output remaining permanently low. again the compare value is loaded into a compare register. the transfer from this holding register to the actual compare register is under program control. the register assignments are shown below where the num ber immediately following ?pwmn? identifies the pwm output. thus pwm0 controls the width of pwm0, pwm1 the width of pwm1 etc. the overall functioning of the pwm module is cont rolled by the contents of the pwmcon1 register. the operation of most of the control bits is straightforward. there is an invert bit for each output which
preliminary W79E834 data sheet - 98 - causes results in the output to have the opposit e value compared to its non-inverted output. the transfer of the data from the counter and compare regi sters to the control regi sters is controlled by the pwmcon1.6 (load) while pwmcon1.7 (pwmrun) allo ws the pwm to be either in the run or idle state. the user can monitor when underflow causes the transfer to occur by monitoring the transfer bit pwcon1.6 (load) or pwmcon1.5 (pwmf flag) . when the transfer takes place the pwm logic automatically resets those bits by next clock cycle. this device has added an interrupt flag for pwm underflow. when pwm 10-bit down counter underflows, pwmf flag (pwmcon1.5) is asserted and pw m interrupt is requested if pwm interrupt is enabled (ie1.5). pwmf is set by har dware and only be cleared by software. the fact that the transfer from the counter and pwmn register to the working registers (10-bit counter and compare register) only occurs when there is an underflow in the counter results in the need for the user?s program to observe the following precaut ions. if pwmcon1 is written with load set without run being enabled the transfer will never take place. thus if a subsequent write sets run without load the compare and counter values will not be t hose expected. if load and run are set, and prior to underflow there is a subsequent load of pwmcon1 wh ich sets run but not load, the load will never take place. again the compare and counter values that existed prior to the update attempt will be used. as outlined above the load bit can be polled to deter mine when the load occurs. unless there is a compelling reason to do otherwise, it is re commended that both pwmrun (pwmcon1.7), and load (pwmcon1.6) be set when pwmcon1 is written. when the pwmrun bit, pwmcon1.7 is cleared the pwm outputs take on the state they had just prior to the bit being cleared. in general this state is not known. in order to place the outputs in a known state when pwmrun is cleared the compare regi sters can be written to either the ?always 1? or ?always 0? so the output w ill have the output desired when the c ounter is halted. after this pwmcon1 should be written with the load and run bi ts are enabled. after th is is done pwmcon1 is polled to find that the load has taken place. once the load has occurred the run bit in pwmcon1 can be cleared. the outputs will retain the state they had just prior to the run being cleared.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 99 - revision a13 23. analog-to-digital converter the adc contains a dac which converts the cont ents of a successive approx imation register to a voltage (v dac ) which is compared to the analog input voltage (vin). the output of the comparator is fed to the successive approximation control logi c which controls the successive approximation register. a conversion is initiated by setting a dcs in the adccon register. adcs can be set by software only or by either hardware or software. the software only start mode is selected when cont rol bit adccon.5 (adcex) =0. a conversion is then started by setting control bit adccon.3 (adcs ) the hardware or software start mode is selected when adccon.5 =1, and a conversion may be started by setting adcco n.3 as above or by applying a rising edge to external pin stadc. when a conversion is started by applying a rising edge, a low level must be applied to stadc for at least one machine cycle followed by a high level for at least one machine cycle. the low-to-high transition of stadc is recognized at the end of a machine cycle, and the conversion commences at the beginning of the next cycle. when a conversion is initiated by software, the conversion starts at the beginning of the machine cycle which follows the instruction that sets adcs. adcs is actually implemented with tpw flip-fl ops: a command flip-flop which is affected by set operations, and a status flag which is accessed during read operations. the next two machine cycles are used to initiate the converter. at the end of t he first cycle, the adcs status flag is set end a value of ?1? will be returned if the adcs flag is read while the conversion is in progress. sampling of the analog input comm ences at the end of the second cycle. during the next eight machine cycles , the voltage at the previously selected pin of one of analog input pin is sampled, and this input voltage should be stabl e in order to obtain a useful sample. in any event, the input voltage slew rate must be less t han 10v/ms in order to prevent an undefined result. the successive approximation control logic first sets t he most significant bit and clears all other bits in the successive approximation register (10 0000 0000b) . the output of the dac (50% full scale) is compared to the input voltage vin. if the input voltage is greater than v dac , then the bit remains set; otherwise if is cleared. the successive approximation control logic now se ts the next most significant bit (11 0000 0000b or 01 0000 0000b, depending on the previ ous result), and the v dac is compared to vin again. if the input voltage is greater then v dac , then the bit remains set; otherwise it is cleared. this process is repeated until all ten bits have been tested, at which stage the result of the c onversion is held in the successive approximation register. the conversion ta kes four machine cycles per bit. the end of the 10-bit conversion is flagged by contro l bit adccon.4 (adci). the upper 8 bits of the result are held in special function register adch, and the two remaining bits are held in adccon.7 (adc.1) and adccon.6 (adc.0). the user may ignore the two least significant bits in adccon and use the adc as an 8-bit converter (8 upper bits in adch). in any event, the total actual conversion
preliminary W79E834 data sheet - 100 - time is 52 machine cycles. adci will be set and the adcs status flag will be reset after the adcs is set. control bits adccon.0, adccon. 1 and adccon.2 are used to control an analog multiplexer which selects one of eight analog channels. an adc conversion in progress is unaffected by an external or software adc start. the result of a completed conv ersion remains unaffected pr ovided adci = logic 1; a new adc conversion already in progress is abort ed when the idle or power down mode is entered. the result of a completed conv ersion (adci = logic 1) remains unaffected when entering the idle mode. when adcon.5 (adcex) is set by external pin to start adc conversion, afte r W79E834 is entry idle mode, p1.4 can start adc conver sion at least 1 machine cycle. 23.1 adc resolution and analog supply: the adc circuit has its own supply pins (av dd and avss) and one pins (vref+) connected to each end of the dac?s resistance-l adder that the avdd and vref+ are connected to vdd and avss is connected to vss. the ladder has 1023 equally spaced taps, separated by a resistance of ?r?. the first tap is located 0.5 r above avss, and the last tap is located 0.5 r below vref+. this gives a total ladder resistance of 1024 r. this structure ensures that t he dac is monotonic and results in a symmetrical quantization error. for input voltages between avss and [(vref+) + ? lsb ], the 10-bit result of an a/d conversion will be 0000000000b = 000h. for input voltages between [(vref+) ? 3/2 lsb] and vref+, the result of a conversion will be 1111111111b = 3ffh. vref+ and avss may be between av dd + 0.2v and av ss ? 0.2 v. vref+ should be positive with respect to avss, and the input voltage (vin) should be between vref+ and avss. the result can always be calculated from the following formula: result = vref vin 1024 + or result = vdd vin 1024
preliminary W79E834 data sheet publication release date: october 12, 2006 - 101 - revision a13
preliminary W79E834 data sheet - 102 - 24. icp (in-circuit program) flash program the contexts of flash in W79E834 are empty by defaul t. at the first use, you must program the flash eprom by external writer device or by icp (in-circuit program) tool. in the icp tool, the user must be taken icp?s program pins before design in system design board which pins in some application circuits are p1.5, p0.4 and p0.5, as below fi gure. in the icp program, the p1.5 must set to high voltage (~10.5v), and keeping this voltage to update code, data and/or configure two config bits. after finished, the hi gh voltage of p1.5 will be released. so when use icp program to suggest the power need power off then power on after icp program was finished on the system board. after entry icp program mode, all pin will be set to quasi-bidirectional mode, and output to level ?1?. W79E834 support programming of flash eprom that is 8k bytes ap flash eprom. this mode can separate update code or all update at ap flash eprom. note: 1. when use icp to upgrade code, the p1.5, p0.4 and p0.5 must be taken within design system board. 2. after program finished by icp, to suggest system power must power off and remove icp connector then power on.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 103 - revision a13 25. config bits W79E834 has two config bits (config1, config2) that must be defined at power up and can not be set the program after start of execution. those features are configured through the use of two flash eprom bytes, and the flash eprom can be progr ammed and verified repeatedly. until the code inside the flash eprom is confirmed ok, the code can be protected. the protection of flash eprom (config2) and those operations on it are described below. the data of these bytes may be read by the movx instruction at the addresses. 25.1 config1 config register 1 config 1 : 76 54321 0 wdte: watchdog timer clock source bit. rpd: reset pin disable bit. config bit prhi: port reset high or low bit. bov: brownout voltage select bit. fosc1: cpu oscillator type select bit 1. fosc0: cpu oscillator type select bit 0. rpd wdte prhi bov - fosc0 fosc1 - - bit name function 7 wdte clock source of watchdog timer select bit: 0: the internal rc oscillator clock is for watchdog timer clock used. 1: the uc clock is for watchdog timer clock used. 6 rpd reset pin disable bit: 0: enable reset function of pin 1.5. 1: disable reset function of pin 1.5, and it to be used as an input port pin. 5 prhi port reset high or low bit: 0: port reset to low state. 1: port reset to high state. 4 bov brownout voltage select bit: 0: brownout detect voltage is 3.8v. 1: brownout detect voltage is 2.5v.
preliminary W79E834 data sheet - 104 - continued bit name function 3 - reserved. 2 - reserved. 1 fosc1 cpu oscillator type select bit 1 0 fosc0 cpu oscillator type select bit 0 oscillator configuration bits: fosc1 fosc0 osc source 0 0 4mhz ~ 16mhz crystal 0 1 internal rc oscillator 1 0 reserved 1 1 external oscillator in xtal1 25.2 config2 c7: 8k flash eprom lock bit this bit is used to protect the customer's program code. it may be set after the programmer finishes the programming and verifies sequence. once this bi t is set to logic 0, both the flash eprom data and config registers can not be accessed again. bit 7 function description 1 the security of 8kb program code is not locked; it can be erased, programmed or read by writer or icp writer. 0 the 8kb program code area is locked; it can?t be read by writer or icp writer.
preliminary W79E834 data sheet publication release date: october 12, 2006 - 105 - revision a13 26. absolute maximum ratings symbol parameter condition rating unit dc power supply vdd ? vss -0.3 +7.0 v input voltage vin vss-0.3 vdd+0.3 v operating temperature ta -40 +85 c storage temperature tst -55 +150 c note: exposure to conditions beyond those list ed under absolute maximum ratings may adversely affects the lift and reliability of the device.
preliminary W79E834 data sheet - 106 - 27. dc electrical characteristics (ta = -40~85 c, unless otherwise specified.) specification parameter symbol min. max. unit test conditions operating voltage vdd 2.7 5.5 v vdd=4.5v ~ 5.5v @ 16mhz vdd=2.7v ~ 5.5v @ 12mhz - 25 ma no load, rst = vss,vdd = 5.0v @ 16mhz operating current idd - 15 ma no load, rst = vss, vdd= 3.0v @ 12mhz - 20 ma no load, vdd = 5.5v @ 16mhz idle current iidle - 10 ma no load, vdd = 3.0v @ 12mhz - 10 a no load, vdd = 5.5v @ disable bov function power down current ipwdn - 10 ua no load, vdd = 3.0v @ disable bov function input current p0, p1, p2 iin1 -50 +10 a vdd = 5.5v, 0 preliminary W79E834 data sheet publication release date: october 12, 2006 - 107 - revision a13 source current p0, p1, p2 (quasi-bidirectional and weak pull- up mode) isr1 -180 -360 ua vdd = 4.5v, vs = 2.4v - 1.0 v vdd = 2.7v, iol = 20 ma output low voltage p0, p1, p2 (push-pull mode) vol1 - 0.4 v vdd = 2.7v, iol = 3.2 ma output high voltage p0, p1, p2 (push-pull mode) voh vdd- 0.7 - v vdd = 2.7v, ioh = -1ma brownout voltage with bov=1 v bo2.5 2.45 2.65 v ta = -0 to 70 c brownout voltage with bov=0 v bo3.8 3.45 3.90 v ta = -0 to 70 c notes: *1. rst pin is a schmitt trigger input. *2. xtal1 is a cmos input. *3. pins of p0, p1, and p2 can source a transit ion current when they are being externally driven from 1 to 0. the transition current reaches its maximu m value when vin approximates to 2v. 27.1 the adc converter dc electrical characteristics (v dd ? v ss = 3.0~5v, ta = -40~85 c, fosc = 16mhz, unless otherwise specified.) specification parameter symbol min. typ. max. unit test conditions analog input avin v ss -0.2 v dd +0.2 v adc clock adcclk 200khz - 5mhz hz adc block circuit input clock conversion time t c 52t adc 1 us differential non-linearity dnl -1 - +1 lsb integral non-linearity inl -2 - +2 lsb offset error ofe -1 - +1 lsb gain error ge -1 - +1 % absolute voltage error ae -3 - +3 lsb notes: 1. tadc: the period time of adc input clock.
preliminary W79E834 data sheet - 108 - 28. ac electrical characteristics t clcl t clcx t chcx t clch t chcl note: duty cycle is 50%. 29. external clock characteristics parameter symbol min. typ. max. units notes clock high time t chcx 12.5 - - ns clock low time t clcx 12.5 - - ns clock rise time t clch - - 10 ns clock fall time t chcl - - 10 ns
preliminary W79E834 data sheet publication release date: october 12, 2006 - 109 - revision a13 30. ac specification parameter symbol variable clock min. variable clock max. units oscillator frequency 1/t clcl 0 16 mhz 31. typical application circuits crystal c1 c2 r 4mhz ~ 16 mhz without without without the above table shows the reference values for crystal applications.
preliminary W79E834 data sheet - 110 - 32. package dimensions 32.1 28-lead sop (300 mil) l o c e h a1 a e b d seating plane y 0.25 gauge plane e 1 28 15 14 7.60 0.32 0.51 0.30 e c b a1 7.40 0.23 0.33 0.10 0.299 0.013 0.020 0.012 0.291 0.009 0.013 0.004 max. dimension in mm 2.65 a symbol min. 2.35 dimension in inch 0.104 min. 0.093 max. control demensions are in milmeters . 1.27 0.10 10.65 l y h 08 0.40 10.00 e 1.27 bsc 0.050 0.004 0.419 0 0.016 0.394 8 0.050 bsc e d 17.70 18.10 0.697 0.713
preliminary W79E834 data sheet publication release date: october 12, 2006 - 111 - revision a13 32.2 48l lqfp (7x7x1.4mm footprint 2.0mm)
preliminary W79E834 data sheet - 112 - 33. revision history version date page description a1 aug. 15, 2006 - initial issued a11 sep. 05, 2006 revise parts information a13 oct. 12, 2006 6 to add W79E834alg part number important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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