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_______________general description the max1204 is a 10-bit data-acquisition system specifically designed for use in applications with mixed +5v (analog) and +3v (digital) supply voltages. it oper- ates with a single +5v analog supply or dual ?v ana- log supplies, and combines an 8-channel multiplexer, internal track/hold, and serial interface with high con- version speed and low power consumption. a 4-wire serial interface connects directly to spi/microwire devices without external logic, and a serial strobe output allows direct connection to tms320-family digital signal processors. the max1204 uses either the internal clock or an external serial- interface clock to perform successive-approximation analog-to-digital conversions. the serial interface oper- ates at up to 2mhz. the max1204 features an internal 4.096v reference and a reference-buffer amplifier that simplifies gain trim. it also has a vl pin that supplies power to the digital out- puts. output logic levels (3v, 3.3v, or 5v) are determined by the value of the voltage applied to this pin. a hard-wired shdn pin and two software-selectable power-down modes are provided. accessing the serial interface automatically powers up the device. a quick turn-on time allows the max1204 to be shut down between conversions, enabling the user to optimize supply currents. by customizing power-down between conversions, supply current can drop below 10? at reduced sampling rates. the max1204 is available in 20-pin ssop and dip packages, and is specified for the commercial, extend- ed, and military temperature ranges. ________________________applications 5v/3v mixed-supply systems data acquisition process control battery-powered instruments medical instruments ____________________________features ? 8-channel single-ended or 4-channel differential inputs ? operates from +5v single or ?v dual supplies ? user-adjustable output logic levels (2.7v to 5.25v) ? low power: 1.5ma (operating mode) 2? (power-down mode) ? internal track/hold, 133khz sampling rate ? internal 4.096v reference ? spi/microwire/tms320-compatible 4-wire serial interface ? software-configurable unipolar/bipolar inputs ? 20-pin dip/ssop ? pin-compatible 12-bit upgrade: max1202 max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 top view dip/ssop v dd sclk cs din sstrb dout vl gnd refadj ref shdn v ss ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 max1204 __________________pin configuration 19-1179; rev 0; 1/97 ______________ordering information for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 typical operating circuit appears on last page. spi is a registered trademark of motorola, inc. microwire is a registered trademark of national semiconductor corp. ordering information continued at end of data sheet. part max1204acpp max1204bcpp max1204acap 0? to +70? 0? to +70? 0? to +70? temp. range pin-package 20 plastic dip 20 plastic dip 20 ssop max1204bcap 0? to +70? 20 ssop inl (lsb) ?/2 ? ?/2 ?
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v vl ...............................................................-0.3v to (v dd + 0.3v) v ss to gnd...............................................................+0.3v to -6v v dd to v ss ..............................................................-0.3v to +12v ch0?h7 to gnd ............................(v ss - 0.3v) to (v dd + 0.3v) ch0?h7 total input current...........................................?0ma ref to gnd ................................................-0.3v to (v dd + 0.3v) refadj to gnd .........................................-0.3v to (v dd + 0.3v) digital inputs to gnd .................................-0.3v to (v dd + 0.3v) digital outputs to gnd .................................-0.3v to (vl + 0.3v) digital output sink current .................................................25ma continuous power dissipation (t a = +70?) plastic dip (derate 11.11mw/? above +70?) ...........889mw ssop (derate 8.00mw/? above +70?) .....................640mw cerdip (derate 11.11mw? above +70?) .................889mw operating temperature ranges max1204_c_p .....................................................0? to +70? max1204_e_p ..................................................-40? to +85? max1204bmjp ...............................................-55? to +125? storage temperature range .............................-60? to +150? electrical characteristics (v dd = +5v ?%, vl = 2.7v to 3.6v; v ss = 0v or -5v ?%; f sclk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); 4.7? capacitor at ref; t a = t min to t max ; unless otherwise noted.) max1204a v in = 4.096vp-p, 65khz (note 4) external reference, 4.096v max1204b no missing codes over temperature max1204a max1204b conditions db -75 channel-to-channel crosstalk db 70 sfdr spurious-free dynamic range db -70 thd total harmonic distortion (up to the 5th harmonic) db 66 sinad signal-to-noise + distortion ratio lsb ?.5 inl relative accuracy (note 2) bits 10 resolution lsb ?.1 channel-to-channel offset matching ppm/? ?.8 gain temperature coefficient ?.0 lsb ?.0 dnl differential nonlinearity lsb ?.0 offset error ?.0 units min typ max symbol parameter -3db rolloff mhz 4.5 small-signal bandwidth khz 800 full-power bandwidth lsb ?.0 gain error (note 3) ?.0 max1204a max1204b dc accuracy (note 1) dynamic specifications (10khz sine-wave input, 4.096vp-p, 133ksps, 2.0mhz external clock, bipolar input mode)
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +5v ?%, vl = 2.7v to 3.6v; v ss = 0v or -5v ?%; f sclk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); 4.7? capacitor at ref; t a = t min to t max ; unless otherwise noted.) max1204ac t a = +25? external clock, 2mhz, 12 clocks/conversion (note 6) on/off leakage current, v ch_ = ?v bipolar, v ss = -5v unipolar, v ss = 0v 6 used for data transfer only internal compensation mode (note 6) internal clock external compensation mode, 4.7? conditions ppm/? ?0 ?0 v ref temperature coefficient ma 30 ref short-circuit current v 4.076 4.096 4.116 ref output voltage pf 16 input capacitance ? ?.01 ? multiplexer leakage current ? ref /2 v v ref input voltage range, single- ended and differential (note 7) 0 2.0 0.1 0.4 mhz 0.1 2.0 external clock-frequency range mhz 1.7 internal clock frequency ns 10 aperture delay ? 1.5 t acq track/hold acquisition time ? 5.5 10 t conv conversion time (note 5) units min typ max symbol parameter max1204ae ?0 ?0 ?0 max1204b 0ma to 0.5ma output load mv 2.5 load regulation (note 8) internal compensation mode ? 0 capacitive bypass at ref external compensation mode 4.7 ? 0.01 capacitive bypass at refadj % ?.5 refadj adjustment range v 2.50 v dd + 50mv input voltage range ? 200 350 input current k w 12 20 input resistance shdn = 0v ? 1.5 10 ref input current in shutdown v v dd - 50mv refadj buffer disable threshold ps <50 aperture jitter conversion rate internal reference analog input external reference at ref (buffer disabled, v ref = 4.096v)
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface 4 _______________________________________________________________________________________ internal compensation mode fast power-down (note 9) external compensation mode conditions ? 0 capacitive bypass at ref ? 30 70 i dd positive supply current v 0 or -5 ?% v ss negative supply voltage v 5 ?% v dd positive supply voltage 4.7 v/v 1.68 reference-buffer gain ? ?0 refadj input current units min typ max symbol parameter electrical characteristics (continued) v dd = +5v ?%, vl = 2.7v to 3.6v; v ss = 0v or -5v ?%; f sclk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); 4.7? capacitor at ref; t a = t min to t max ; unless otherwise noted.) operating mode ma 1.5 2.5 operating mode and fast power-down ? 50 i ss negative supply current full power-down (note 9) 210 full power-down 10 v 2.70 5.25 vl logic supply voltage vl = v dd = 5v ? 10 i vl logic supply current (notes 6, 10) v dd = 5v ?%; external reference, 4.096v; full-scale input mv ?.06 ?.5 psr positive supply rejection (note 11) v ss = -5v ?%; external reference, 4.096v; full-scale input mv ?.01 ?.5 psr negative supply rejection (note 11) external reference, 4.096v; full-scale input mv ?.06 ?.5 psr logic supply rejection (note 12) ? external reference at refadj power requirements
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface _______________________________________________________________________________________ 5 cs = vl (note 6) cs = vl i source = 1ma i sink = 3ma shdn = open shdn = 0v shdn = v dd (note 6) v in = 0v or v dd conditions pf 15 c out three-state output capacitance ? ?0 i l three-state leakage current v vl - 0.5 v oh output voltage high v 0.4 v ol output voltage low na -100 100 shdn maximum allowed leakage, mid-input ? -4.0 i sl shdn input current, low ? 4.0 i sh shdn input current, high v v dd - 0.5 v sh shdn input high voltage v 0.8 v il v 2.0 v ih din, sclk, cs input high voltage din, sclk, cs input low voltage pf 15 c in din, sclk, cs input capacitance ? ? i in din, sclk, cs input leakage v 0.15 v hyst din, sclk, cs input hysteresis units min typ max symbol parameter electrical characteristics (v dd = +5v ?%, vl = 2.7v to 5.25v; v ss = 0v or -5v ?%; f sclk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); 4.7? capacitor at ref; t a = t min to t max ; unless otherwise noted.) i sink = 5ma v 0.4 v ol output voltage low i sink = 8ma 0.3 i sink = 6ma 0.3 i source = 1ma v 4 v oh output voltage high cs = 5v ? ?0 i l three-state leakage current cs = 5v (note 6) pf 15 c out three-state output capacitance v 1.5 v dd - 1.5 v sm shdn input mid-voltage v 0.5 v sl shdn input low voltage shdn = open v 2.75 v flt shdn voltage, floating digital inputs: din, sclk, cs , shdn digital outputs: dout, sstrb (v l = 2.7v to 3.6v) digital outputs: dout, sstrb (v l = 4.75v to 5.25v)
c load = 100pf max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface 6 _______________________________________________________________________________________ external clock mode only, c load = 100pf ns 240 c load = 100pf ns ns 20 240 t do sclk fall to output data valid conditions 240 t dv cs fall to output enable c load = 100pf ns 240 t tr cs rise to output disable t sdv cs fall to sstrb output enable (note 6) external clock mode only, c load = 100pf ns 240 t str cs rise to sstrb output disable (note 6) internal clock mode only ns 0 t sck sstrb rise to sclk rise (note 6) ns 0 t dh din to sclk hold ? 1.5 t acq acquisition time ns 100 t ds din to sclk setup units min typ max symbol parameter timing characteristics (v dd = +5v ?%, vl = 2.7v to 3.6v, v ss = 0v or -5v ?%, t a = t min to t max , unless otherwise noted.) ns 100 t css cs to sclk rise setup ns 0 t csh cs to sclk rise hold ns 200 t ch sclk pulse width high ns 200 t cl sclk pulse width low c load = 100pf ns 240 t sstrb sclk fall to sstrb c load = 100pf note 1: tested at v dd = 5.0v; v ss = 0v; unipolar input mode. note 2: relative accuracy is the analog value? deviation (at any code) from its theoretical value after the full-scale range is calibrated. note 3: internal reference, offset nulled. note 4: on-channel grounded; sine-wave applied to all off-channels. note 5: conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 6: guaranteed by design. not subject to production testing. note 7: common-mode range for analog inputs is from v ss to v dd . note 8: external load should not change during the conversion for specified accuracy. note 9: shutdown supply current is measured with vl at 3.3v, and with all digital inputs tied to either vl or gnd (figure 12c); refadj = gnd. note 10: logic supply current is measured with the digital outputs (dout and sstrb) disabled ( cs high). when the outputs are active ( cs low), the logic supply current depends on f sclk , and on the static and capacitive load at dout and sstrb. note 11: measured at v supply +5% and v supply -5% only. note 12: measured at vl = 2.7v and vl = 3.6v.
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface _______________________________________________________________________________________ 7 1.0 2.0 1.8 1.6 1.4 1.2 4.5 supply current vs. supply voltage max1204 toc01 supply voltage (v) supply current (ma) 5.3 4.7 5.1 5.5 4.9 1.0 -60 supply current vs. temperature 1.2 max1204 toc02 temperature (?) supply current (ma) 100 1.6 1.4 -20 60 140 2.0 1.8 20 6 5 0 -60 shutdown supply current vs. temperature 4 max1204 toc03 temperature ( c) shutdown supply current ( m a) 60 2 1 -20 20 3 100 140 refadj = gnd __________________________________________typical operating characteristics (v dd = 5v ?%; vl = 2.7v to 3.6v; f sclk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); 4.7? capacitor at ref; t a = +25?; unless otherwise noted.) name function 1? ch0?h7 sampling analog inputs 9 v ss negative supply voltage. tie v ss to -5v ?% or gnd. pin 10 shdn three-level shutdown input. pulling shdn low shuts the max1204 down to 10? (max) supply current; otherwise, the max1204 is fully operational. pulling shdn to v dd puts the reference-buffer amplifier in internal compensation mode. letting shdn float puts the reference-buffer amplifier in external compensation mode. 11 ref reference buffer output/adc reference input. in internal reference mode, the reference buffer provides a 4.096v nominal output, externally adjustable at refadj. in external reference mode, disable the internal buffer by pulling refadj to v dd. 15 dout serial-data output. data is clocked out at sclk? falling edge. high impedance when cs is high. 14 vl supply voltage for digital output pins. voltage applied to vl determines the positive output swing of the digital outputs (dout, sstrb). 13 gnd ground; in- input for single-ended conversions 12 refadj input to the reference-buffer amplifier. tie refadj to v dd to disable the reference-buffer amplifier. 20 v dd positive supply voltage, +5v ?% 19 sclk serial-clock input. sclk clocks data in and out of serial interface. in external clock mode, sclk also sets the conversion speed. (duty cycle must be 40% to 60% in external clock mode.) 18 cs active-low chip select. data is not clocked into din unless cs is low. when cs is high, dout is high impedance. 17 din serial-data input. data is clocked in at sclk? rising edge. 16 sstrb serial-strobe output. in internal clock mode, sstrb goes low when the max1204 begins the analog- to-digital conversion and goes high when the conversion is finished. in external clock mode, sstrb pulses high for one clock period before the msb decision. high impedance when cs is high (external clock mode). ______________________________________________________________pin description
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface 8 _______________________________________________________________________________________ _______________detailed description the max1204 uses a successive-approximation con- version technique and input track/hold (t/h) circuitry to convert an analog signal to a 10-bit digital output. a flexible serial interface provides easy interface to 3v microprocessors (?s). figure 3 is the max1204 block diagram. pseudo-differential input figure 4 shows the analog-to-digital converter? (adc?) analog comparator? sampling architecture. in single-ended mode, in+ is internally switched to ch0?h7 and in- is switched to gnd. in differential mode, in+ and in- are selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7. configure the channels using tables 3 and 4. in differential mode, in- and in+ are internally switched to either of the analog inputs. this configuration is pseudo-differential such that only the signal at in+ is sampled. the return side (in-) must remain stable with- in ?.5lsb (?.1lsb for best results) with respect to gnd during a conversion. to do this, connect a 0.1? capacitor from in- (of the selected analog input) to gnd. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . the acquisition interval spans three sclk cycles and ends on the falling sclk edge after the input control word? last bit is entered. the t/h switch opens at the end of the acquisition interval, retaining charge on c hold as a sample of the signal at in+. the conversion interval begins with the input multiplex- er switching c hold from the positive input (in+) to the negative input (in-). in single-ended mode, in- is sim- ply gnd. this unbalances node zero at the compara- tor? input. the capacitive dac adjusts during the remainder of the conversion cycle to restore node zero to 0v within the limits of 10-bit resolution. this action is equivalent to transferring a charge of 16pf x [(v in +) - (v in -)] from c hold to the binary-weighted capacitive dac, which in turn forms a digital represen- tation of the analog input signal. figure 1. load circuits for enable time figure 2. load circuits for disable time figure 3. block diagram +3.3v 3k c load gnd dout c load gnd 3k dout a. high-z to v oh and v ol to v oh b. high-z to v ol and v oh to v ol +3.3v 3k c load gnd dout c load gnd 3k dout a. v oh to high-z b. v ol to high-z input shift register control logic int clock output shift register +2.44v reference t/h analog input mux sar adc in dout sstrb v dd vl v ss sclk din ch0 ch1 ch3 ch2 ch7 ch6 ch5 ch4 gnd refadj ref out ref clock +4.096v 20k ? 1.68 1 2 3 4 5 6 7 8 10 11 12 13 15 16 17 18 19 max1204 cs shdn a 20 14 9
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface _______________________________________________________________________________________ 9 track/hold the t/h enters tracking mode on the falling clock edge after the fifth bit of the 8-bit control word is shifted in. the t/h enters hold mode on the falling clock edge after the eighth bit of the control word is shifted in. in- is connect- ed to gnd if the converter is set up for single-ended inputs, and the converter samples the ??input. in- con- nects to the ??input if the converter is set up for differen- tial inputs, and the difference of ? |n+ - in- ? is sampled. the positive input connects back to in+ at the end of the conversion, and c hold charges to the input signal. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, acquisition time increases and more time must be allowed between conversions. the acquisition time, t acq , is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. it is calculated by the following: t acq = 7 x (r s + r in ) x 16pf where r in = 9k , r s = the source impedance of the input signal, and t acq is never less than 1.5?. note that source impedances below 4k w do not significantly affect the adc? ac performance. higher source impedances can be used if an input capacitor is connected to the analog inputs, as shown in figure 5. note that the input capacitor forms an rc filter with the input source imped- ance, limiting the adc? signal bandwidth. figure 5. quick-look circuit ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 gnd c switch track t/h switch 9k r in c hold hold capacitive dac ref zero comparator + 16pf single-ended mode: differential mode: in+ = cho?h7, in- = gnd. in+ and in- selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5, ch6/ch7. at the sampling instant, the mux input switches from the selected in+ channel to the selected in?channel. input mux 0.1? v dd gnd v ss cs sclk din dout sstrb shdn +3v n.c. 0.01? ch7 vl refadj ref c2 0.01? c1 4.7? 0v to 4.096v analog input 0.1? +3v oscilloscope ch1 ch2 ch3 ch4 full-scale analog input max1204 +5v 2mhz oscillator sclk sstrb dout figure 4. equivalent input circuit
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface 10 ______________________________________________________________________________________ input bandwidth the adc? input tracking circuitry has a 4.5mhz small-signal bandwidth. therefore, it is possible to digi- tize high-speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog input range and input protection internal protection diodes, which clamp the analog inputs to v dd and v ss , allow the analog input pins to swing from (v ss - 0.3v) to (v dd + 0.3v) without dam- age. however, for accurate conversions near full scale, the inputs must not exceed v dd by more than 50mv, or be lower than v ss by 50mv. if the analog input exceeds 50mv beyond the sup- plies, do not forward bias the protection diodes of off-channels over 2ma, as excessive current degrades on-channel conversion accuracy. the full-scale input voltage depends on the voltage at ref (tables 1a and 1b). quick look use the circuit of figure 5 to quickly evaluate the max1204? analog performance. the max1204 requires that a control byte be written to din before each conver- sion. tying din to +3v feeds in control byte $ff hex, which triggers single-ended unipolar conversions on ch7 in external clock mode without powering down between conversions. in external clock mode, the sstrb output pulses high for one clock period before the most significant bit of the conversion result shifts out of dout. varying the analog input to ch7 alters the sequence of bits from dout. a total of 15 clock cycles per conversion is required. all sstrb and dout output transitions occur on sclk? falling edge. how to start a conversion clocking a control byte into din starts conversion on the max1204. with cs low, each rising edge on sclk clocks a bit from din into the max1204? internal shift register. after cs falls, the first logic ??bit defines the control byte? msb. until this first ?tart?bit arrives, any number of logic ??bits can be clocked into din with no effect. table 2 shows the control-byte format. the max1204 is fully compatible with microwire and spi devices. for spi, select the correct clock polarity and sampling edge in the spi control registers: set cpol = 0 and cpha = 0. microwire and spi both transmit a byte and receive a byte at the same time. using the typical operating circuit , the simplest software interface requires only three 8-bit transfers to perform a con- version (one 8-bit transfer to configure the adc, and two more 8-bit transfers to clock out the conversion result). table 1b. bipolar full scale, zero scale, and negative full scale table 1a. unipolar full scale and zero scale reference external zero scale 0v 0v 0v internal at refadj at ref full scale +4.096v v refadj x 1.68 v ref reference -1/2 v ref -1/2 v refadj x 1.68 -4.096v/2 negative full scale zero scale 0v 0v 0v internal at refadj at ref full scale +4.096v / 2 +1/2 v refadj x 1.68 +1/2 v ref external
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface ______________________________________________________________________________________ 11 table 2. control-byte format table 3. channel selection in single-ended mode (sgl/ dif = 1) sel1 sel0 0 0 0 ch4 ch5 sel2 ch6 ch7 gnd 1 0 0 + 0 0 1 + 1 0 ch0 + 1 + 0 1 ch1 0 + 1 1 ch3 0 + 0 1 ch2 1 + 1 1 1 + table 4. channel selection in differential mode (sgl/ dif = 0) sel1 sel0 0 0 0 ch4 ch5 sel2 ch6 ch7 0 0 1 + 0 1 0 + 0 1 ch0 + 1 + 1 0 ch1 0 + 1 0 ch3 1 + 1 1 ch2 0 + 1 1 1 + pd0 bit 0 (lsb) sgl/ dif bit 2 pd1 bit 1 uni/ bip bit 3 sel 0 bit 4 bit 7 (msb) sel 1 sel 2 start bit 5 bit 6 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, an analog input signal from 0v to v ref can be converted; in bipolar mode, the signal can range from -v ref / 2 to +v ref / 2. 1 = single ended, 0 = differential. selects single-ended or differential conversions. in single- ended mode, input signal voltages are referred to gnd. in differential mode, the voltage dif- ference between two channels is measured. (tables 3 and 4.) selects clock and power-down modes. pd1 pd0 mode 00 full power-down (i dd = 2?, internal reference) 01 fast power-down (i dd = 30?, internal reference) 10 internal clock mode 11 external clock mode these three bits select which of the eight channels is used for the conversion (tables 3 and 4). the first logic 1 bit after cs goes low defines the beginning of the control byte. description name bit uni/ bip 3 sgl/ dif 2 pd1 pd0 1 0 (lsb) sel2 sel1 sel0 6 5 4 start 7 (msb)
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface 12 ______________________________________________________________________________________ simple software interface make sure the cpu? serial interface runs in master mode so the cpu generates the serial clock. choose a clock frequency from 100khz to 2mhz. 1) set up the control byte for external clock mode and call it tb1. tb1? format should be: 1xxxxx11 binary, where the xs denote the particular channel and conversion mode selected. 2) use a general-purpose i/o line on the cpu to pull cs on the max1204 low. 3) transmit tb1 and simultaneously receive a byte and call it rb1. ignore rb1. 4) transmit a byte of all zeros ($00 hex) and simulta- neously receive byte rb2. 5) transmit a byte of all zeros ($00 hex) and simulta- neously receive byte rb3. 6) pull cs on the max1204 high. figure 6 shows the timing for this sequence. bytes rb2 and rb3 contain the result of the conversion padded with one leading zero, two trailing sub-bits (s1 and s0), and three trailing zeros. total conversion time is a func- tion of the serial clock frequency and the amount of idle time between 8-bit transfers. to avoid excessive t/h droop, make sure that the total conversion time does not exceed 120?. digital output in unipolar input mode, the output is straight binary (figure 15); for bipolar inputs, the output is two?- complement (figure 16). data is clocked out at sclk? falling edge in msb-first format. the digital output logic level is adjusted with the vl pin. this allows dout and sstrb to interface with 3v logic without the risk of overdrive. the max1204? digital inputs are designed to be compatible with 3v cmos logic as well as 5v logic. internal and external clock modes the max1204 can use either an external serial clock or the internal clock to perform the successive- approximation conversion. in both clock modes, the external clock shifts data in and out of the max1204. the t/h acquires the input signal as the last three bits of the control byte are clocked into din. bits pd1 and pd0 of the control byte program the clock mode. figures 7?0 show the timing characteristics common to both modes. external clock in external clock mode, the external clock not only shifts data in and out, but it also drives the a/d conversion steps. sstrb pulses high for one clock period after the last bit of the control byte. successive-approximation bit decisions are made and appear at dout on each of the next 12 sclk falling edges (figure 6). sstrb and dout go into a high-impedance state when cs goes high; after the next cs falling edge, sstrb outputs a logic low. figure 8 shows the sstrb timing in external clock mode. the conversion must complete in some minimum time or droop on the sample-and-hold can degrade conversion results. use internal clock mode if the clock period exceeds 10? or if serial-clock interruptions could cause the conversion interval to exceed 120?. internal clock in internal clock mode, the max1204 generates its own conversion clock. this frees the ? from running the sar conversion clock, and allows the conversion results to be read back at the processor? convenience, at any clock rate from zero to 2mhz. sstrb goes low at the start of the conversion, then goes high when the conversion is complete. sstrb is low for a maximum of 10?, during which time sclk should remain low for best noise performance. an internal register stores data while the conversion is in progress. sclk clocks the data out at this register at any time after the conversion is complete. after sstrb goes high, the next falling clock edge produces the msb of the conversion at dout, followed by the remaining bits in msb-first for- mat (figure 9). cs does not need to be held low once a conversion is started. pulling cs high prevents data from being clocked into the max1204 and three-states dout, but it does not adversely affect an internal clock-mode conversion already in progress. when internal clock mode is selected, sstrb does not go high impedance when cs goes high. figure 10 shows the sstrb timing in internal clock mode. data can be shifted in and out of the max1204 at clock rates up to 2.0mhz if the acquisition time, t acq , is kept above 1.5?.
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface ______________________________________________________________________________________ 13 figure 8. external clock-mode sstrb detailed timing t sdv t sstrb pd0 clocked in t str sstrb sclk cs t sstrb figure 7. detailed serial-interface timing cs sclk din dout t csh t css t cl t ds t dh t dv t ch t do t tr t csh figure 6. 24-bit external-clock-mode conversion timing (microwire/spi compatible) sstrb sclk din dout 14 8 12 16 20 24 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b9 msb b8 b7 b6 b5 b4 b3 b2 b1 b0 lsb s1 s0 1.5? (sclk = 2mhz) idle filled with zeros idle conversion t acq adc state cs rb1 rb2 rb3 acquisition
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface 14 ______________________________________________________________________________________ figure 9. internal clock mode timing sstrb cs sclk din dout 14 8 12 18 20 24 start sel2 sel1 sel0 uni/ dip sgl/ dif pd1 pd0 b9 msb b8 b7 b0 lsb s1 s0 acquisition 1.5? (sclk = 2mhz) idle filled with zeros idle conversion 10? max adc state 2 3 5 6 7 9 10 11 19 21 22 23 t conv data framing cs ? falling edge does not start a conversion on the max1204. the first logic high clocked into din is inter- preted as a start bit and defines the first bit of the control byte. a conversion starts on sclk? falling edge after the eighth bit of the control byte (the pd0 bit) is clocked into din. the start bit is defined as: the first high bit clocked into din with cs low any- time the converter is idle; (e.g., after v dd is applied). or the first high bit clocked into din after bit 3 (b3) of a conversion in progress appears at dout. if a falling edge on cs forces a start bit before b3 becomes available, the current conversion is termi- nated and a new one started. thus, the fastest the max1204 can run is 15 clocks/conversion. figure 11a shows the serial-interface timing necessary to perform a conversion every 15 sclk cycles in external clock mode. if cs is low and sclk is continuous, guarantee a start bit by first clocking in 16 zeros. most microcontrollers (?s) require that conversions occur in multiples of eight sclk clocks; 16 clocks per conversion is typically the fastest that a ? can drive the max1204. figure 11b shows the serial-interface timing necessary to perform a conversion every 16 sclk cycles in external clock mode. figure 10. internal clock mode sstrb detailed timing pd0 clock in t sstrb t csh t conv t sck sstrb sclk t css note: keep sclk low during conversion for best noise performance. cs
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface ______________________________________________________________________________________ 15 __________ applications information power-on reset when power is first applied and if shdn is not pulled low, internal power-on reset circuitry activates the max1204 in internal clock mode, ready to convert with sstrb = high. after the power supplies are stabilized, the internal reset time is 100?. no conversions should be performed during this phase. sstrb is high on power-up, and if cs is low, the first logical 1 on din is interpreted as a start bit. until a conversion takes place, dout shifts out zeros. reference-buffer compensation in addition to its shutdown function, shdn also selects internal or external compensation. the compensation affects both power-up time and maximum conversion speed. compensated or not, the minimum clock rate is 100khz due to droop on the sample-and-hold. float shdn to select external compensation. the typical operating circuit uses a 4.7? capacitor at ref. a value of 4.7? or greater ensures stability and allows converter operation at the 2mhz full clock speed. external com- pensation increases power-up time (see the section choosing power-down mode, and table 5). internal compensation requires no external capacitor at ref, and is selected by pulling shdn high. internal com- pensation allows for the shortest power-up times, but is only available using an external clock up to 400khz. power-down choosing power-down mode you can save power by placing the converter in a low-current shutdown state between conversions. select full power-down or fast power-down mode via bits 1 and 0 of the din control byte with shdn high or floating (tables 2 and 6). pull shdn low at any time to figure 11a. external clock mode, 15 clocks/conversion timing figure 11b. external clock mode, 16 clocks/conversion timing sclk din dout cs s control byte 0 control byte 1 s conversion result 0 conversion result 1 sstrb control byte 2 s 1 8181 15 15 b2 b3 b4 b5 b6 b7 b8 b9 b1 b0 s1 s0 b2 b3 b4 b5 b6 b7 b8 b9 b1 b0 s1 s0 cs sclk din dout s control byte 0 control byte 1 s conversion result 0 conversion result 1 b2 b3 b4 b5 b6 b7 b8 b9 b5 b6 b7 b8 b9 b1 b0 s1 s0
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface 16 ______________________________________________________________________________________ shut down the converter completely. shdn overrides bits 1 and 0 of the control byte. full power-down mode turns off all chip functions that draw quiescent current, reducing i dd and i ss typi- cally to 2?. fast power-down mode turns off all circuitry except the bandgap reference. with fast power-down mode, the supply current is 30?. power-up time can be shortened to 5? in internal compensation mode. the i dd shutdown current can increase if any digital input (din, sclk, cs ) is held high in either power-down mode. the actual shutdown current depends on the state of the digital inputs, the voltage applied to the digital inputs (v ih ), the supply voltage (v dd ), and the operating temper- ature. figure 12c shows the maximum i dd increase for each digital input held high in power-down mode for differ- ent operating conditions. this current is cumulative, so if all three digital inputs are held high, the additional shut- down current is three times the value shown in figure 12c. in both software power-down modes, the serial interface remains operational, but the adc does not convert. table 5 shows how the choice of reference-buffer com- pensation and power-down mode affects both power-up delay and maximum sample rate. in external compensation mode, power-up time is 20ms with a 4.7? compensation capacitor (200ms with a 33? capacitor) when the capacitor is initially fully discharged. from fast power-down, start-up time can be eliminated by using low-leakage capacitors that do not discharge more than 1/2lsb while shut down. in power-down, the capacitor has to supply the current into the reference (typically 1.5?) and the transient currents at power-up. figures 12a and 12b show the various power-down sequences in both external and internal clock modes. software power-down software power-down is activated using bits pd1 and pd0 of the control byte. as shown in table 6, pd1 and pd0 also specify clock mode. when software power- down is asserted, the adc continues to operate in the last specified clock mode until the conversion is com- plete. the adc then powers down into a low quiescent-current state. in internal clock mode, the interface remains active and conversion results can be clocked out even though the max1204 has already entered a software power-down. the first logical 1 on din is interpreted as a start bit and powers up the max1204. following the start bit, the control byte also determines clock and power-down modes. for example, if the control byte contains pd1 = 1, the chip remains powered up. if pd1 = 0, power-down resumes after one conversion. table 5. typical power-up delay times 133 2 full disabled 133 2 fast disabled 133 26 26 maximum sampling rate (ksps) see figure 14c 300 5 power-up delay (?) fast/full full fast power-down mode 4.7 reference capacitor (?) external enabled reference buffer internal enabled internal enabled reference-buffer compensation mode full power-down mode 0 0 fast power-down mode 1 0 pd1 internal clock mode 0 1 external clock mode 1 1 device mode pd0 n/a full power-down gnd shdn state external compensation enabled floating internal compensation enabled v dd reference-buffer compensation device mode table 6. software shutdown and clock mode table 7. hard-wired shutdown and compensation mode
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface ______________________________________________________________________________________ 17 hardware power-down the shdn pin places the converter into full power-down mode. unlike the software power-down modes, conversion is not completed; it stops coinci- dentally with shdn being brought low. there is no power-up delay if an external reference, which is not shut down, is used. shdn also selects internal or external reference compensation (table 7). power-down sequencing the max1204? automatic power-down modes can save considerable power when operating at less than maximum sample rates. the following sections discuss the various power-down sequences. lowest power at up to 500 conversions per channel per second figure 14a depicts max1204? power consumption for one or eight channel conversions using full power-down mode and internal reference compensation. a 0.01? bypass capacitor at refadj forms an rc filter with the internal 20k reference resistor, with a 0.2ms time constant. to achieve full 10-bit accuracy, 10 time constants (or 2ms in this example) are required for the reference buffer to settle. when exiting fullpd, waiting this 2ms in fastpd mode (instead of just exiting fullpd mode and returning to nor- mal operating mode) reduces power consumption by a factor of 10 or more (figure 13). figure 12b. timing diagram for power-down modes (internal clock) full power-down powered up powered up data valid data valid internal clock mode sx xxxx 10 s 00 xx x x x s mode dout din clock mode sets internal clock mode sets full power-down conversion conversion sstrb figure 12a. timing diagram for power-down modes (external clock) powered up full power- down powered up powered up data valid (10 + 2 data bits) data valid (10 + 2 data bits) data invalid external external internal sx xxxx 11 s 01 xx x x x xx xxx s11 fast power-down mode dout din clock mode shdn sets external clock mode sets external clock mode sets fast power-down mode
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface 18 ______________________________________________________________________________________ lowest power at higher throughputs figure 14b shows power consumption with external- reference compensation in fast power-down, with one and eight channels converted. the external 4.7? compensa- tion requires a 50? wait after power-up. this circuit com- bines fast multichannel conversion with the lowest power consumption possible. full power-down mode can increase power savings in applications where the max1204 is inactive for long periods of time, but where intermittent bursts of high-speed conversions are required. external and internal references the max1204 can be used with an internal or external reference. an external reference can be connected directly at the ref terminal or at the refadj pin. an internal buffer is designed to provide 4.096v at ref for the max1204. its internally trimmed 2.44v reference is buffered with a 1.68 nominal gain. internal reference the max1204? full-scale range with internal reference is 4.096v with unipolar inputs and ?.048v with bipolar inputs. the internal reference voltage is adjustable to ?.5% with the circuit of figure 17. external reference an external reference can be placed at either the input (refadj) or the output (ref) of the max1204? internal buffer amplifier. the refadj input impedance is typical- ly 20k . at ref, the input impedance is a minimum of 12k for dc currents. during conversion, an external reference at ref must deliver up to 350? dc load cur- rent and have an output impedance of 10 or less. if the reference has higher output impedance or is noisy, bypass it close to the ref pin with a 4.7? capacitor. using the buffered refadj input makes buffering of the external reference unnecessary. to use the direct ref input, disable the internal buffer by tying refadj to v dd . in power-down, the input bias current to refadj can be as much as 25? with refadj tied to v dd . pull refadj to gnd to minimize the input bias current in power-down. transfer function and gain adjust figure 15 depicts the nominal, unipolar input/output (i/o) transfer function, and figure 16 shows the bipolar i/o transfer function. code transitions occur halfway between successive integer lsb values. output coding is binary with 1 lsb = 4mv (4.096v/1024) for unipolar operation and 1 lsb = 4mv [(4.096v/2 - -4.096v/2)/1024] for bipolar operation. figure 13. max1204 fullpd/fastpd power-up sequence 100 din refadj ref 2.5v 0v 4v 0v 101 1 1 1100 101 fullpd fastpd nopd fullpd fastpd 2ms wait complete conversion sequence t buffen ? 15? t = rc = 20k w x c refadj (zeros) ch1 ch7 (zeros) figure 12c. additional i dd shutdown supply current vs. v ih for each digital input at a logic 1 0 -60 10 5 temperature (?) supply current per input ( m a) 100 25 20 15 -20 60 140 40 35 30 20 (v dd - v ih ) = 1.95v (v dd - v ih ) = 2.55v (v dd - v ih ) = 2.25v
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface ______________________________________________________________________________________ 19 figure 17, the reference-adjust circuit, shows how to adjust adc gain in applications that use the internal reference. the circuit provides ?.5% (?6lsbs) of gain-adjustment range. layout, grounding, bypassing for best performance, use printed circuit boards. wire-wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 18 shows the recommended system-ground con- nections. establish a single-point analog ground (star ground point) at gnd. connect all other analog grounds to this ground. no other digital system ground should be connected to this single-point analog ground. the ground return to the power supply should be low imped- ance and as short as possible for noise-free operation. high-frequency noise in the v dd power supply may affect the high-speed comparator in the adc. bypass these supplies to the single-point analog ground with 0.1? and 4.7? bypass capacitors close to the max1204. minimize capacitor lead lengths for best supply-noise rejection. if the +5v power supply is very noisy, a 10 resistor can be connected as a lowpass filter, as shown in figure 18. 3.0 2.5 2.0 1.5 1.0 0.5 0 0.0001 0.001 0.01 0.1 1 10 time in shutdown (sec) power-up delay (ms) figure 14c. typical power-up delay vs. time in shutdown figure 14a. max1204 supply current vs. sample rate/second, fullpd, 400khz clock 1000 1 0 100 300 500 full power-down 10 100 max186-14a conversions per channel per second 200 400 2ms fastpd wait 400khz external clock internal compensation 50 150 250 350 450 8 channels 1 channel average supply current (?) figure 14b. max1204 supply current vs. sample rate/second, fastpd, 2mhz clock 10,000 10 0 fast power-down 100 1000 conversions per channel per second 2k 8 channels 1 channel 4k 6k 8k 10k 12k 14k 16k 18k 2mhz external clock external compensation 50? wait average supply current (?)
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface 20 ______________________________________________________________________________________ +5v 510k 100k 24k 0.01? 12 refadj max1204 figure 17. reference-adjust circuit +5v -5v +3v gnd supplies dgnd +3v vl v ss gnd v dd digital circuitry max1204 r* = 10 w *optional figure 18. power-supply grounding connection figure 15. unipolar transfer function, 4.096v = full scale output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 123 0 fs fs - 3/2lsb fs = +4.096v 1lsb = fs 1024 input voltage (lsbs) figure 16. bipolar transfer function, ?.096v/2 = full scale 011 . . . 111 output code 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 -fs 0v input voltage (lsbs) +fs - 1lsb fs = +4.096v 2 1lsb = +4.096v 1024
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface ______________________________________________________________________________________ 21 tms320cl3x to max1204 interface figure 19 shows an application circuit to interface the max1204 to the tms320 in external clock mode. figure 20 is the timing diagram for this interface circuit. use the following steps to initiate a conversion in the max1204 and to read the results. 1) the tms320 should be configured with clkx (trans- mit clock) as an active-high output clock and clkr (tms320 receive clock) as an active-high input clock. the tms320? clkx and clkr are tied together with the max1204? sclk input. 2) the max1204? cs is driven low by the tms320? xf_ i/o port to enable data to be clocked into the max1204? din. 3) write an 8-bit word (1xxxxx11) to the max1204 to initiate a conversion and place the device into exter- nal clock mode. refer to table 2 to select the proper xxxxx bit values for your specific application. 4) the max1204? sstrb output is monitored via the tms320? fsr input. a falling edge on the sstrb output indicates that the conversion is in progress and data is ready to be received from the max1204. 5) the tms320 reads in one data bit on each of the next 16 rising edges of sclk. these data bits repre- sent the 10-bit conversion result followed by two sub-bits and four trailing bits, which should be ignored. 6) pull cs high to disable the max1204 until the next conversion is initiated. figure 19. max1204 to tms320 serial interface xf clkx clkr dx dr fsr cs sclk din dout sstrb tms320lc3x max1204 figure 20. tms320 serial-interface timing diagram cs sclk din sstrb dout start sel2 sel1 sel0 uni/bip sgl/dif pd1 pd0 msb lsb high impedance high impedance
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface 22 ______________________________________________________________________________________ _ordering information (continued) v dd i/o sck (sk) mosi (so) miso (si) v ss shdn sstrb dout din sclk cs v ss vl gnd v dd refadj ch7 c3 0.1? c4 0.1? ch0 +3v +5v c2 0.01? 0v to 4.096v analog inputs max1204 cpu c1 4.7? ref __________typical operating circuit ___________________chip information * contact factory for availability. ? ? ?/2 ? ?/2 inl (lsb) 20 cerdip* -55? to +125? max1204bmjp 20 ssop -40? to +85? max1204beap 20 ssop 20 plastic dip 20 plastic dip pin-package temp. range -40? to +85? -40? to +85? -40? to +85? MAX1204AEAP max1204bepp max1204aepp part transistor count: 2503 substrate connected to v ss
max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface ______________________________________________________________________________________ 23 ________________________________________________________package information l dim a a1 b c d e e h l a dim d d d d d min 0.068 0.002 0.010 0.004 0.205 0.301 0.025 0? min 0.239 0.239 0.278 0.317 0.397 max 0.078 0.008 0.015 0.008 0.209 0.311 0.037 8? max 0.249 0.249 0.289 0.328 0.407 min 1.73 0.05 0.25 0.09 5.20 7.65 0.63 0? min 6.07 6.07 7.07 8.07 10.07 max 1.99 0.21 0.38 0.20 5.38 7.90 0.95 8? pins 14 16 20 24 28 max 6.33 6.33 7.33 8.33 10.33 inches inches millimeters millimeters a ssop shrink small-outline package h e d a a1 c b 0.65 bsc 0.0256 bsc 21-0056a e see variations c a a2 e1 d e e a e b a3 b1 b dim a a1 a2 a3 b b1 c d d1 e e1 e e a e b l a min ? 0.015 0.125 0.055 0.016 0.050 0.008 1.015 0.040 0.300 0.240 ? 0.115 0? max 0.200 ? 0.150 0.080 0.022 0.065 0.012 1.045 0.070 0.325 0.280 0.400 0.150 15? min ? 0.38 3.18 1.40 0.41 1.27 0.20 25.78 1.02 7.62 6.10 ? 2.92 0? max 5.08 ? 3.81 2.03 0.56 1.65 0.30 26.54 1.78 8.26 7.11 10.16 3.81 15? inches millimeters 2.54 bsc 7.62 bsc 0.100 bsc 0.300 bsc a1 l d1 e 21-333a 20-pin plastic dual-in-line package a
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 1997 maxim integrated products printed usa is a registered trademark of maxim integrated products. max1204 5v, 8-channel, serial, 10-bit adc with 3v digital interface ___________________________________________package information (continued) c a e d e1 b1 b dim a b b1 c d e e1 e l l1 q s s1 a min ? 0.014 0.038 0.008 ? 0.220 0.290 0.125 0.150 0.015 ? 0.005 0? max 0.200 0.023 0.065 0.015 1.060 0.310 0.320 0.200 ? 0.070 0.080 15? min ? 0.36 0.97 0.20 ? 5.59 7.37 3.18 3.81 0.38 ? 0.13 0? max 5.08 0.58 1.65 0.38 26.92 7.87 8.13 5.08 ? 1.78 2.03 15? inches millimeters 2.54 bsc 0.100 bsc q l s1 e 21-335c 20-pin ceramic dual-in-line package a s l1

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