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november 2006 hys64t256022edl?[25f/2.5]?b hys64t256022edl?[3/3s]?b hys64t256022edl?3.7?b 200-pin dual die small-outline-ddr2-sdram modules ddr2 sdram so-dimm sdram rohs compliant internet data sheet rev. 1.0
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hys64t256022edl?[25f/2.5/3/3s/3.7]?b small outline ddr2 sdram modules qag_techdoc_rev400 / 3.2 qag / 2006-08-01 2 11172006-dxyk-2ppw hys64t256022edl?[25f/2.5]?b; hys64t25 6022edl?[3/3s]?b; hys64t256022edl?3.7?b revision history: 2006-11, rev. 1.0 page subjects (major chan ges since last revision) all adapted internet edition all initial document internet data sheet rev. 1.0, 2006-11 3 11172006-dxyk-2ppw hys64t256022edl?[25f/2.5/3/3s/3.7]?b small outline ddr2 sdram modules 1overview this chapter gives an overview of the 200-pin dual die small-outline-ddr2-sdram modules product family and describes its main characteristics. 1.1 features ? 200-pin pc2-6400, pc2?5300 and pc2-4200 ddr2 sdram memory modules. ? 256m 64 module organization, and 2 128m 8 chip organization ? standard double-data-rate-two synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply ? 2gb modules built with stacked 1gb ddr2 sdrams in pg-tfbga-71 chipsize packages ? all speed grades faster than ddr2-400 comply with ddr2-400 timing specifications. ? programmable cas latencies (3, 4, 5 and 6), burst length (8 & 4) and burst type ? burst refresh, distributed refresh and self refresh ? programmable self refres h rate via emrs2 setting ? programmable partial array refresh via emrs2 settings ? average refresh period 7.8 s at a t case lower than 85 c, 3.9 s between 85 c and 95 c. ? dcc enabling via emrs2 setting ? all inputs and outputs sstl_18 compatible ? off-chip driver impedance adjustment (ocd) and on-die termination (odt) ? serial presence detect with e 2 prom ? so-dimm dimensions (nominal): 30 mm high, 67.6 mm wide ? based on standard reference layouts raw card ?d? ? rohs compliant products 1) table 1 performance table 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product type speed code ?25f ?2.5 ?3 ?3s ?3.7 unit speed grade pc2?6400 5?5?5 pc2?6400 6?6?6 pc2?5300 4?4?4 pc2?5300 5?5?5 pc2?4200 4?4?4 ? max. clock frequency @cl6 f ck6 400400???mhz @cl5 f ck5 400 333 333 333 266 mhz @cl4 f ck4 266 266 333 266 266 mhz @cl3 f ck3 200 200 200 200 200 mhz min. ras-cas-delay t rcd 12.5 15 12 15 15 ns min. row precharge time t rp 12.5 15 12 15 15 ns min. row active time t ras 45 45 45 45 45 ns min. row cycle time t rc 57.5 60 57 60 60 ns internet data sheet rev. 1.0, 2006-11 4 11172006-dxyk-2ppw hys64t256022edl?[25f/2.5/3/3s/3.7]?b small outline ddr2 sdram modules 1.2 description the qimonda hys64t256022ed l?[25f/2.5/3/ 3s/3.7]?b module family are small outline modules ?so-dimms? with 30 mm height based on ddr2 technology. dimms are available as non-ecc modules in 256m 64 (2 gb) organization and density, intended for mounting into 200-pin connector sockets. the memory array is designed with stacked 1 gbit double- data-rate-two (ddr2) synchronous drams. decoupling capacitors are mounted on the pcb. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration da ta and are write protected; the second 128 bytes are available to the customer. table 2 ordering information for rohs compliant products table 3 address format table 4 components on modules product type 1) 1) all product type numbers end with a place code, designating the silicon die revision. example: hys64t256022edl?3.7?b, indicat ing rev. ?b? dies are used for ddr2 sdram components. for all qimonda ddr2 module and component nomenclature see chapter 6 of this data sheet. compliance code 2) 2) the compliance code is printed on the module label and describes the speed grade, for example ?pc2?4200s?444?12?d0?, where 4200s means so-dimm modules with 4.26 gb/sec module bandwidth and ?444?12? means column address strobe (cas) latency = 4, row column delay (rcd) latency = 4 and row precharge (rp) laten cy = 4 using the latest jedec spd revision 1.2 and produced on the raw card ?d?. description sdram technology pc2?6400 hys64t256022edl?25f?b 2gb 2r 8 pc2?6400s?555?12?d0 2 ranks, non-ecc 1 gbit ( 8) pc2?6400 hys64t256022edl?2.5?b 2gb 2r 8 pc2?6400s?666?12?d0 2 ranks, non-ecc 1 gbit ( 8) pc2?5300 hys64t256022edl?3?b 2gb 2r 8 pc2?5300s?444?12?d0 2 ranks, non-ecc 1 gbit ( 8) pc2?5300 hys64t256022edl?3s?b 2gb 2r 8 pc2?5300s?555?12?d0 2 ranks, non-ecc 1 gbit ( 8) pc2?4200 hys64t256022edl?3.7?b 2gb 2r 8 pc2?4200s?444?12?d0 2 ranks, non-ecc 1 gbit ( 8) dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/columns bits raw card 2 gbyte 256m 64 2 non-ecc 16 14/3/10 d product type 1) 1) green product dram components 1) dram density dram organisation note hys64t256022edl hyb18t2g802bf 2 1gbit 2 128m 8 2) 2) for a detailed description of all functionalities of the dram components on these modules see the component data sheet. internet data sheet rev. 1.0, 2006-11 5 11172006-dxyk-2ppw hys64t256022edl?[25f/2.5/3/3s/3.7]?b small outline ddr2 sdram modules 2 pin configuration the pin configuration of the small outline ddr2 sdram dimm is listed by function in table 5 (200 pins). the abbreviations used in columns pin and buffer type are explained in table 6 and table 7 respectively. the pin numbering is depicted in figure 1 table 5 pin configuration of so-dimm ball no. name pin type buffer type function clock signals 30 ck0 i sstl clock signals 2:0, comple ment clock signals 2:0 164 ck1 i sstl 32 ck0 i sstl 166 ck1 i sstl 79 cke0 i sstl clock enable rank 1:0 note: 2 ranks module 80 cke1 i sstl nc nc ? not connected note: 1-rank module control signals 110 s0 i sstl chip select rank 1:0 115 s1 i sstl nc nc ? not connected note: 1-rank module 108 ras i sstl row address strobe 113 cas i sstl column address strobe 109 we i sstl write enable address signals 107 ba0 i sstl bank address bus 2:0 106 ba1 i sstl 85 ba2 i sstl bank address bus 2 greater than 512mb ddr2 sdrams nc nc sstl less than 1gb ddr2 sdrams internet data sheet rev. 1.0, 2006-11 6 11172006-dxyk-2ppw hys64t256022edl?[25f/2.5/3/3s/3.7]?b small outline ddr2 sdram modules 102 a0 i sstl address bus 12:0 101 a1 i sstl 100 a2 i sstl 99 a3 i sstl 98 a4 i sstl 97 a5 i sstl 94 a6 i sstl 92 a7 i sstl 93 a8 i sstl 91 a9 i sstl 105 a10 i sstl ap i sstl 90 a11 i sstl 89 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies 116 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? not connected note: module based on 512 mbit or smaller dies data signals 5 dq0 i/o sstl data bus 63:0 note: data input/output pins 7 dq1 i/o sstl 17 dq2 i/o sstl 19 dq3 i/o sstl 4 dq4 i/o sstl 6 dq5 i/o sstl 14 dq6 i/o sstl 16 dq7 i/o sstl 23 dq8 i/o sstl 25 dq9 i/o sstl 35 dq10 i/o sstl 37 dq11 i/o sstl ball no. name pin type buffer type function internet data sheet rev. 1.0, 2006-11 7 11172006-dxyk-2ppw hys64t256022edl?[25f/2.5/3/3s/3.7]?b small outline ddr2 sdram modules 20 dq12 i/o sstl data bus 63:0 data input/output pins 22 dq13 i/o sstl 36 dq14 i/o sstl 38 dq15 i/o sstl 43 dq16 i/o sstl 45 dq17 i/o sstl 55 dq18 i/o sstl 57 dq19 i/o sstl 44 dq20 i/o sstl 46 dq21 i/o sstl 56 dq22 i/o sstl 58 dq23 i/o sstl 61 dq24 i/o sstl 63 dq25 i/o sstl 73 dq26 i/o sstl 75 dq27 i/o sstl 62 dq28 i/o sstl 64 dq29 i/o sstl 74 dq30 i/o sstl 76 dq31 i/o sstl 123 dq32 i/o sstl 125 dq33 i/o sstl 135 dq34 i/o sstl 137 dq35 i/o sstl 124 dq36 i/o sstl 126 dq37 i/o sstl 134 dq38 i/o sstl 136 dq39 i/o sstl 141 dq40 i/o sstl 143 dq41 i/o sstl 151 dq42 i/o sstl 153 dq43 i/o sstl 140 dq44 i/o sstl 142 dq45 i/o sstl 152 dq46 i/o sstl 154 dq47 i/o sstl 157 dq48 i/o sstl 159 dq49 i/o sstl 173 dq50 i/o sstl 175 dq51 i/o sstl ball no. name pin type buffer type function internet data sheet rev. 1.0, 2006-11 8 11172006-dxyk-2ppw hys64t256022edl?[25f/2.5/3/3s/3.7]?b small outline ddr2 sdram modules 158 dq52 i/o sstl data bus 63:0 160 dq53 i/o sstl 174 dq54 i/o sstl 176 dq55 i/o sstl 179 dq56 i/o sstl 181 dq57 i/o sstl 189 dq58 i/o sstl 191 dq59 i/o sstl 180 dq60 i/o sstl 182 dq61 i/o sstl 192 dq62 i/o sstl 194 dq63 i/o sstl data strobe signals 13 dqs0 i/o sstl data strobe bus 7:0 11 dqs0 i/o sstl 31 dqs1 i/o sstl 29 dqs1 i/o sstl 51 dqs2 i/o sstl 49 dqs2 i/o sstl 70 dqs3 i/o sstl 68 dqs3 i/o sstl 131 dqs4 i/o sstl 129 dqs4 i/o sstl 148 dqs5 i/o sstl 146 dqs5 i/o sstl 169 dqs6 i/o sstl 167 dqs6 i/o sstl 188 dqs7 i/o sstl 186 dqs7 i/o sstl data mask signals 10 dm0 i sstl data mask bus 7:0 26 dm1 i sstl 52 dm2 i sstl 67 dm3 i sstl 130 dm4 i sstl 147 dm5 i sstl 170 dm6 i sstl 185 dm7 i sstl ball no. name pin type buffer type function internet data sheet rev. 1.0, 2006-11 9 11172006-dxyk-2ppw hys64t256022edl?[25f/2.5/3/3s/3.7]?b small outline ddr2 sdram modules eeprom 197 scl i cmos serial bus clock 195 sda i/o od serial bus data 198 sa0 i cmos serial address select bus 2:0 200 sa1 i cmos power supplies 1 v ref ai ? i/o reference voltage 199 v ddspd pwr ? eeprom power supply 81,82,87,88,95 ,96,103,104, 111,112,117,118 v dd pwr ? power supply 2,3,8,9,12,15,18,21,24,27,28, 33,34,39,40,41, 42,47,48,53, 54,59,60,65,66, 71,72,77,78, 121,122,127,128, 132,133,138,13 9,144,145,149, 150,155,156,, 161,162,165,17 1,172,177, 178,183,184,18 7,190,193,196 v ss gnd ? ground plane other pins 114 odt0 i sstl on-die termination control 1:0 119 odt1 i sstl on-die termination control 1 note: 2 rank modules nc nc ? not connected note: 1 rank modules 50,69,83,84,120,163,168 nc nc ? not connected ball no. name pin type buffer type function internet data sheet rev. 1.0, 2006-11 10 11172006-dxyk-2ppw hys64t256022edl?[25f/2.5/3/3s/3.7]?b small outline ddr2 sdram modules table 6 abbreviations for pin type table 7 abbreviations for buffer type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. internet data sheet rev. 1.0, 2006-11 11 11172006-dxyk-2ppw hys64t256022edl?[25f/2.5/3/3s/3.7]?b small outline ddr2 sdram modules figure 1 pin configuration so-dimm (200 pin) 0 3 3 7 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 6 6 ' 4 ' 0 ' 4 9 6 6 ' 4 ' 0 & |