description features SY69753L final industrial temperature range (?0 c to +85 c) 3.3v power supply sonet/sdh/atm compatible clock and data recovery for 155mbps nrz data stream two on-chip plls: one for clock generation and another for clock recovery selectable reference frequencies differential pecl high-speed serial i/o line receiver input: no external buffering needed link fault indication 100k ecl compatible i/o esd protection > 2000v complies with bellcore, itu/ccitt and ansi specifications for oc-3 applications available in 32-pin epad-tqfp the SY69753L is a complete clock recovery and data retiming integrated circuit for oc-3/sts-3 applications at 155mbps nrz. the device is ideally suited for sonet/ sdh/atm applications and other high-speed data transmission systems. clock recovery and data retiming is performed by synchronizing the on-chip vco directly to the incoming data stream. the vco center frequency is controlled by the reference clock frequency and the selected divide ratio. on-chip clock generation is performed through the use of a frequency multiplier pll with a byte rate source as reference. the SY69753L also includes a link fault detection circuit. 3.3v 155mbps oc-3/sts-3 clock and data recovery applications sonet/sdh/atm oc-3 proprietary architectures at 135mbps to 180mbps block diagram phase detector phase/ frequency detector charge pump vco charge pump vco link fault detection divider by 8, 10, 16, 20 refclk (ttl) cd (pecl) rdinn rdinp pllr p/n clksel (ttl) rdoutp rclkp rclkn rdoutn plls p/n divsel 1/2 tclkp tclkn v cc v cca v cco gnd 1 0 0 1 phase/ frequency detector lfin (ttl) (pecl) (pecl) (pecl) (ttl) (pecl) 1 rev.: b amendment: /0 issue date: may 2002
SY69753L 2 micrel 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 nc rdinp rdinn nc refclk nc nc nc rdoutp rdoutn vcco rclkp rclkn vcco tclkp tclkn 9 10 11 12 13 14 15 16 clksel pllrp pllrn gnd gnd gnda pllsn pllsp 32 31 30 29 28 27 26 25 divsel2 cd vcc vcc vcca vcca lfin divsel1 top view epad-tqfp h32-1 package/ordering information ordering information package operating package part number type range marking SY69753Lhi h32-1 industrial SY69753Lhi SY69753Lhi* h32-1 industrial SY69753Lhi *tape and reel inputs rdinp, rdinn [serial data input] differential pecl these built-in line receiver inputs are connected to the differential receive serial data stream. an internal receive pll recovers the embedded clock (rclk) and data (rdout) information. refclk [reference clock] ttl input this input is used as the reference for the internal frequency synthesizer and the "training" frequency for the receiver pll to keep it centered in the absence of data coming in on the rdin inputs. cd [carrier detect] pecl input this input controls the recovery function of the receive pll and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. when this input is high the input data stream (rdin) is recovered normally by the receive pll. when this input is low the data on the inputs rdin will be internally forced to a constant low, the data outputs rdout will remain low, the link fault indicator output lfin forced low and the clock recovery pll forced to look onto the clock frequency generated from refclk. divsel1, divsel2 [divider select] ttl inputs these inputs select the ratio between the output clock frequency (rclk/tclk) and the refclk input frequency as shown in the ?eference frequency selection?table. clksel [clock select] ttl inputs this input is used to select either the recovered clock of the receiver pll (clksel = high) or the clock of the frequency synthesizer (clksel = low) to the tclk outputs. pin descriptions outputs lfin [link fault indicator] ttl output this output indicates the status of the input data stream rdin. active high signal is indicating when the internal clock recovery pll has locked onto the incoming data stream. lfin will go high if cd is high and rdin is within the frequency range of the receive pll (1000ppm). lfin is an asynchronous output. rdoutp, rdoutn [receive data output] differential pecl these ecl 100k outputs represent the recovered data from the input data stream (rdin). this recovered data is specified against the rising edge of rclk. rclkp, rclkn [clock output] differential pecl these ecl 100k outputs represent the recovered clock used to sample the recovered data (rdout). tclkp, tclkn [clock output] differential pecl these ecl 100k outputs represent either the recovered clock (clksel = high) used to sample the recovered data (rdout) or the transmit clock of the frequency synthesizer (clksel = low). pllsp, pllsn [clock synthesis pll loop filter] external loop filter pins for the clock synthesis pll. pllrp, pllrn [clock recovery pll loop filter] external loop filter pins for the receiver pll. power & ground vcc supply voltage(1) vcca analog supply voltage(1) vcco output supply voltage(1) gnd ground n/c no connect note: 1. vcc, vcca, vcco must be the same value.
SY69753L 3 micrel absolute maximum ratings (note 1) supply voltage (v cc ) .................................. ?.5v to +5.0v input voltage (v in ) .......................................... ?.5v tov cc output current (i out ) continuous ......................................................... 50ma surge ................................................................ 100ma storage temperature (t s ) ....................... ?5 c to +150 c operating ratings (note 2) supply voltage (v cc ) .............................. +3.15v to +3.45v ambient temperature (t a ) ..................... ?0 c to +85 c junction temperature (t j ) .................................. +125 c package thermal resistance (note 3) epad-tqfp ( ja ) still-air ............................................................. 28 c/w 500lfpm ............................................................ 20 c/w epad-tqfp ( jc ) ................................................. 4 c/w note 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operat ion is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximu m ratlng conditions for extended periods may affect device reliability. note 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. note 3. numbers valid with proper thermal design of pcb and exposed pad soldered to island on pcb. refer to figure on page 9. t a = ?0 c to +85 c symbol parameter condition min typ max units v cc power supply voltage 3.15 3.3 3.45 v i cc power supply current 170 230 ma dc electrical characteristics v cc = v cco = v cca = 3.3v 5%; t a = ?0 c to + 85 c symbol parameter condition min typ max units v ih input high voltage v cc ?1.165 v cc ?0.880 v v il input low voltage v cc ?1.810 v cc ?1.475 v i il input low current v in = v il (min.) 0.5 a v oh output high voltage 50 ? to v cc ?v v cc ?1.075 v cc ?0.830 v v ol output low voltage 50 ? to v cc ?v v cc ?1.860 v cc ?1.570 v v cc = v cco = v cca = 3.3v 5%; t a = ?0 c to + 85 c symbol parameter condition min typ max units v ih input high voltage 2.0 v cc v v il input low voltage 0.8 v i ih input high current v in = 2.7v, v cc = max. ?25 a v in = v cc , v cc = max. +100 a i il input low current v in = 0.5v, v cc = max. ?00 a v oh output high voltage i oh = ?.4ma 2.0 v v ol output low voltage i ol = 4ma 0.5 v i os output short circuit current v out = 0v (maximum 1sec) ?5 ?00 ma ttl dc electrical characteristics pecl 100k dc electrical characteristics
SY69753L 4 micrel v cc = v cco = v cca = 3.3v 5%; t a = ?0 c to + 85 c symbol parameter condition min typ max units f vco vco center frequency 800 1100 mhz ? f vco vco center frequency nominal 5 % tolerance t acq acquisition lock time 15 s t cpwh refclk pulse width high 4 ns t cpwl refclk pulse width low 4 ns t dv data valid 1/(2*f rclk ) ?200 ps t dh data hold 1/(2*f rclk ) ?200 ps t ir refclk input rise time 0.5 2 ns t odc output duty cycle (rclk/tclk) 45 55 % of ui t rskew recovered clock skew ?00 +200 ps t r , t f ecl output rise/fall time 50 ? to v cc ?v 100 500 ps (20% to 80%) ac electrical characteristics
SY69753L 5 micrel functional description and characteristics clock recovery clock recovery, as shown in the block diagram generates a clock that is at the same frequency as the incoming data bit rate at the serial data input. the clock is phase aligned by a pll so that it samples the data in the center of the data eye pattern. the phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. output pulses from the detector indicate the required direction of phase correction. these pulses are smoothed by an integral loop filter. the output of the loop filter controls the frequency of the voltage controlled oscillator (vco), which generates the recovered clock. frequency stability without incoming data is guaranteed by an alternate reference input (refclk) that the pll locks onto when data is lost. if the frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the pll will be declared out of lock, and the pll will lock to the reference clock. the loop filter transfer function is optimized to enable the pll to track the jitter, yet tolerate the minimum transition density expected in a received sonet data signal. this transfer function yields a 30 s data stream of continuous 1's or 0's for random incoming nrz data. the total loop dynamics of the clock recovery pll provides jitter tolerance which is better than the specified tolerance in gr-253-core. lock detect the SY69753L contains a link fault indication circuit which monitors the integrity of the serial data inputs. if the received serial data fails the frequency test, the pll will be forced to lock to the local reference clock. this will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. if the recovered clock frequency deviates from the local reference clock frequency by more than approximately 1000ppm, the pll will be declared out of lock. the lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. if the recovered clock frequency is determined to be within approximately 1000ppm, the pll will be declared in lock and the lock detect output will go active. performance the SY69753L pll complies with the jitter specifications proposed for sonet/sdh equipment defined by the bellcore specifications: gr-253-core, issue 2, december 1995 and itu- t recommendations: g.958 document, when used with differential inputs and outputs. input jitter tolerance input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1db optical/electrical power penalty. sonet input jitter tolerance requirement condition is the input jitter amplitude which causes an equivalent of 1db power penalty. figure 1. input jitter tolerance oc/sts-n f0 f1 f2 f3 ft level (hz) (hz) (hz) (khz) (khz) 3 10 30 300 6.5 65 15 1.5 0.40 f0 f1 f2 f4 ft sinusoidal input jitter amplitude (ui p-p) frequency -20db/decade -20db/decade a jitter transfer jitter transfer function is defined as the ratio of jitter on the output oc-n/sts-n signal to the jitter applied on the input oc-n/ sts-n signal versus frequency. jitter transfer requirements are shown in figure 2. jitter generation the jitter of the serial clock and serial data outputs shall not exceed .01 u.i. rms when a serial data input with no jitter is presented to the serial data inputs. 0.1 -20 fc jitter transfer (db) fre q uenc y -20db/decade acceptable range figure 2. jitter transfer oc/sts-n fc p level (khz) (db) 3 500 0.1
SY69753L 6 micrel reference frequency selection divsel1 divsel2 f rclk /f refclk 00 8 01 10 10 16 11 20 loop filter components (1) r 1 = 80 ? c 1 = 1.5 f (x7r dielectric) r 1 c 1 pllsp pllsn r 2 = 50 ? c 2 = 1.0 f (x7r dielectric) r 2 c 2 pllrp pllrn note: 1. suggested values. values may vary for different applications. timing waveforms t cpwl t cpwh rdout rclk refclk t odc t odc t skew t dv t dh
SY69753L 7 micrel application example 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 nc rdinp rdinn nc rdoutp rdoutn vcco rclkp rclkn vcco tclkp tclkn 9 10 11 12 13 14 15 16 clksel pllrp pllrn vee vee veea pllsn pllsp 32 31 30 29 28 27 26 25 divsel2 cd vcc vcc vcca vcca lfin divsel1 sw1 1 2 3 4 5 6 vcc r12 q1 2n2222a led d2 vee r1 c1 1.5 f 7 diode d1 1n4148 r10 r6 r7 r8 r9 r2 c2 1.0 f r11 1k ? cd divsel2 divsel1 clksel vee r13 vcc vcc ferrite bead blm21a102 l3 c5 22 f c6 0.1 f c7 6.8 f c8 6.8 f c9 6.8 f gnd l2 l1 vcco (+2v) c11 0.1 f c13 0.1 f c15 0.1 f c12 0.01 f c14 0.01 f c16 0.01 f c10 6.8 f c17 0.1 f c18 0.01 f vee c19 1.0 f c20 0.1 f c21 0.01 f vcc (+2v) vcca (+2v) vee ( 1.3v) veea ( 3v) gnd nc nc nc nc c1 = 1.5 f c2 = 1.0 f r1 = 80 ? r2 = 50 ? r3 through r10 = 5k ? r12 = 12k ? r13 = 130 ? note: c3, c4 are optional
SY69753L 8 micrel bill of materials item part number manufacturer description qty. c1 ecu-v1h104kbw panasonic 1.5 f ceramic capacitor, size 1206 1 x7r dielectric, loop filter, critical c2 ecu-v1h104kbw panasonic 1.0 f ceramic capacitor, size 1206 1 x7r dielectric, loop filter, critical c3, c4 ecu-v1h104kbw panasonic 0.47 f ceramic capacitor, size 1206 2 x7r dielectric, loop filter, optional c5 ecs-t1ed226r panasonic 22 f tantalum electrolytic capacitor, size d 1 c6 ecu-v1h104kbw panasonic 0.1 f ceramic capacitor, size 1206 1 x7r dielectric, power supply decoupling c7, c8, c9, c10 ecs-t1ec685r panasonic 6.8 f tantalum electrolytic capacitor, size c 4 c19 ecj-3yb1e105k panasonic 1.0 f ceramic capacitor, size 1206 1 x7r dielectric, veea decoupling c11, c13 ecu-v1h104kbw panasonic 0.1 f ceramic capacitor, size 1206 1 x7r dielectric, vcco/vcc decoupling c15, c17 ecu-v1h104kbw panasonic 0.1 f ceramic capacitor, size 1206 1 x7r dielectric, vcca/veea decoupling c20 ecu-v1h104kbw panasonic 0.1 f ceramic capacitor, size 1206 1 x7r dielectric, veea decoupling c12, c14 ecu-v1h103kbw panasonic 0.01 f ceramic capacitor, size 1206 1 x7r dielectric, vcco/vcc decoupling c16, c18 ecu-v1h103kbw panasonic 0.01 f ceramic capacitor, size 1206 1 x7r dielectric, vcca/veea decoupling c21 ecu-v1h103kbw panasonic 0.01 f ceramic capacitor, size 1206 1 x7r dielectric, veea decoupling d1 1n4148 diode 1 d2 p300-nd/p301-nd panasonic t-1 3/4 red led 1 j1, j2, j3, j4, j5 142-0701-851 johnson gold plated, jack, sma, pcb mount 12 j6, j7, j8, j9, components j10, j11, j12 l1, l2, l3 blm21a102f murata ferrite beads, power noise suppression 3 q1 nte123a nte 2n2222a buffer/driver transistor, npn 1 r1 80 ? resistor, 2%, size 1206 1 loop filter component, critical r2 50 ? resistor, 2%, size 1206 1 loop filter component, critical r3, r4, r5, r6 5k ? pullup resistors, 2%, size 1206 8 r7, r8, r9, r10 r11 1k ? pulldown resistor, 2%, size 1206 1 r12 12k ? resistor, 2%, size 1206 1 r13 130 ? pullup resistor, 2%, size 1206 1 sw1 206-7 cts spst, gold finish, sealed dip switch 1
SY69753L 9 micrel micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2002 micrel incorporated 32 lead epad-tqfp (die up) (h32-1) rev. 01 package ep- exposed pad die compside island heat dissipation heavy copper plane heavy copper plane v ee v ee heat dissipation pcb thermal consideration for 32-pin epad-tqfp package
|
